WO2018171547A9

WO2018171547A9 - Wafer-level chip encapsulating structure and manufacturing method therefor

Info

Publication number: WO2018171547A9
Application number: PCT/CN2018/079447
Authority: WO
Inventors: 蒋舟; 李扬渊
Original assignee: 苏州迈瑞微电子有限公司
Priority date: 2017-03-21
Filing date: 2018-03-19
Publication date: 2019-01-10
Also published as: WO2018171547A1; TWI669798B; TW201901910A; CN107068652A

Abstract

The present invention relates to a wafer-level chip encapsulating structure and a manufacturing method therefor, comprising a chip unit having a first surface and a second surface arranged opposite to one another, and at least one solder window for electrical coupling being disposed on the first surface; the second surface is provided with a TSV structure connected to the solder window, the TSV structure comprising a through hole penetrating through the first surface and the second surface, and a slot arranged on the second surface, the distance of the edges of the slot to the edges of the second surface being greater than 10 µm. The obtained progress compared to the prior art improves the structural strength of the chip.

Description

Wafer level chip package structure and manufacturing method

The application claims the priority of the Chinese patent application entitled "Wafer-Level Chip Package Structure and Manufacturing Method" on March 21, 2017, the application number is 201710171067.5, the entire contents of which are incorporated herein by reference. .

Technical field

The invention relates to the field of semiconductor technologies, and in particular to a wafer level chip package structure and a packaging method thereof.

Background technique

TSV (Through Silicon Vias) package structure is one of the IC package methods, which can be divided into memory package and wafer level package for chip devices. The wafer level package is applied to an optical image sensor (please refer to FIG. 1). In this case, the optical image sensor 2 has a glass substrate 3 supporting the TSV structure 4 to maintain structural strength, the TSV opening 41, the slot 22, the wiring 23, and A Z-axis connection structure such as a solder window 24 is provided at the edge 21 of the image sensor chip to facilitate fabrication.

In order to reduce the thickness of the package, some chips (such as capacitive fingerprint sensor chips) require a TSV package but no glass plate as a support. If the optical image sensor TSV package process continues to be used (for example, the TSV package disclosed in the patent CN201510305840.3) Structure) will result in technical defects in the edge strength of the chip, which will bring risks in subsequent processing. For example, when cutting a wafer, the risk of chip fragmentation due to stress is increased, and there is also a risk in the post-laying and assembly stages.

Therefore, there is a need to improve the TSV structure and manufacturing method to improve the structural strength of the chip to solve the above problems.

Summary of the invention

The purpose of the technical solution is to ensure the overall thickness of the chip chip and thereby improve the structural strength of the chip. To this end, the slot of the TSV is disposed inside the chip so that the slot is kept at a certain safe distance from the edge of the chip, for example, greater than 10 um. Since the TSV slot is disposed inside the chip, the thickness of the chip outside the TSV slot is the same as the thickness of the inside of the slot.

The technical solution of the present invention includes the following specific contents:

a wafer level chip package structure, comprising: a chip unit having oppositely disposed first surfaces and second surfaces, the first surface arranging at least one solder window for electrical connection; the second surface setting A TSV structure coupled to the solder window, the TSV structure including a through hole extending through the first surface and the second surface and a groove disposed on the second surface, the boundary of the groove being greater than 10 um from the edge of the second surface.

Preferably, the distance L between the boundary of the solder window and the edge of the first surface satisfies the relationship

Preferably, at least one pad is disposed on the second surface of the chip unit, and the soldering window and the pad are electrically connected through the wiring formed on the through hole wall, the slotted bottom wall, the slotted sidewall and the second surface .

In order to better solve the above technical problems, the present invention also provides a method for fabricating a wafer level chip package structure, including the steps of:

S1: arranging a soldering window on the first surface of the chip unit such that the distance L between the soldering window and the edge of the first surface satisfies a relationship

S2: forming a trapezoidal groove on the second surface of the chip unit, the projection of the bottom wall of the groove on the first surface covers the welding window, the boundary of the groove is greater than 10 um from the edge of the second surface;

S3: forming a through hole through the soldering window and the bottom wall of the slot in the slot, such that the through hole is connected to the soldering window;

S4: forming a wiring on the through hole wall, the grooved bottom wall, the grooved side wall, and the second surface, the wiring electrically communicating with the solder window and the pad.

Preferably, the aspect ratio k of the slotted sidewall is approximately equal to 2.75.

Preferably, the trapezoidal groove is a one-stage or multi-stage trapezoidal groove.

In order to move the TSV to the inside of the chip by slotting the TSV, the height of the chip outside the TSV slot is the same as the height of the chip inside, which improves the strength of the edge of the chip, and avoids the design of the left and right symmetrical solder window structure, thereby avoiding This design has an impact on the circuit design.

DRAWINGS

1 is a schematic cross-sectional structural view of a prior art image sensor TSV package structure.

2a is a perspective view of a TSV package structure of the present invention.

2b is a perspective view of a TSV package structure of the present invention.

3 is a schematic view of a second surface pad array of the present invention.

4a is a schematic cross-sectional view of the present invention in the TSV manufacturing step S1.

Fig. 4b is a schematic cross-sectional view showing the TSV manufacturing step S2 of the present invention.

Figure 4c is a schematic cross-sectional view of the TSV manufacturing step S3 of the present invention.

Figure 4d is a schematic cross-sectional view of the TSV manufacturing step S4 of the present invention.

4e is a schematic view of another embodiment of the TSV structure of the present invention.

Figure 5 is a schematic view showing the functional structure of the welding window of the present invention.

6a-6d are schematic views of four kinds of welding window components of the welding window layout of the fifth embodiment of the present invention;

Detailed ways

In order to make those skilled in the art better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. The embodiments are only a part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of the present invention.

As shown in FIG. 2a, the wafer level chip package structure of the present invention comprises a chip unit 1 having a first surface 115 and a second surface 116 disposed opposite each other. In the present invention, a fingerprint sensing chip is taken as an example. The first surface 115 is provided with

functional circuits

132 and 131 and a capacitor unit array (not shown) for sensing a fingerprint image, and the functional circuit is electrically connected to the soldering window. . The second surface 116 is provided with a pad 12 and a TSV structure electrically connected to the soldering window, the TSV structure including a through hole 112 penetrating the first surface 115 or the soldering window 13 and the second surface 116, and the through hole 112 The connected slot 11 has a

grooved boundary distance

110, 111 and the edge 117 of the second surface is greater than 10 um.

In the present embodiment, the grooved boundary 110 is greater than 10 um from the edge 117 of the second surface 116 such that the thickness d1 outside the chip slot 11 is the same as the thickness d2 inside the chip (refer to FIG. 3c), thereby ensuring the chip from the crystal. It can withstand the stress generated during cutting when cutting on a circle to avoid the risk of chip edge cracking.

In the present embodiment, the boundary of the slot 11 includes a longitudinally extending boundary 110 and a laterally extending boundary 111; the boundary of the soldering window of the present invention is greater than 10 um from the edge of the second surface, and refers to any boundary. The edge of the welded window is greater than 10um. Thus the distance from the weld window boundary 110 closest to the second surface edge 117 is at least greater than 10 um

In order to obtain the above TSV package structure, the present invention provides the following manufacturing method:

S1: arranging a soldering window on the first surface of the chip unit such that the distance L between the soldering window and the edge of the first surface satisfies

The above steps are described in detail below:

Referring to FIGS. 4a and 4b, a soldering window 13 is disposed on the first surface 115 of the chip in step S1 such that the soldering window 12 is away from the edge 118 of the first surface 115, and the soldering window 13 is away from the first surface edge 118 in order to The boundary 133 of the weld window 13 is maintained at a distance L from the first edge 118 that is set such that the boundary 110 of the slot 11 is greater than 10 um from the edge of the second surface 116. In order to achieve the above purpose, the distance L satisfies the relationship

In the present embodiment, the first surface edge 118 should understand the outermost side of the first surface 115, and the boundary of the solder window 113 should be understood as the boundary line between the solder window and the chip; the distance L should be understood as the boundary 113. The minimum distance that can be achieved with the first surface edge 118.

In this step, in order to open the through hole 112, the central axis x of the soldering window 13 coincides with the central axis of the slot 11 and the corresponding slot 11 is changed when the position of the soldering window 13 on the chip unit changes. The same position change also occurs in the position.

In this step, the

function circuits

131, 132 and the fingerprint sensing array are arranged simultaneously with the solder window 13.

In this step, the shape and number of the weld windows 13 are designed differently as needed.

In this step, a plurality of soldering windows 13 may be disposed, and the soldering windows 13 are spaced apart from each other such that the through holes 112 corresponding to the different pads 13 do not interfere with each other when the through holes 112 are prepared.

Referring to FIG. 4b, a slot 11 is formed on the second surface 116 of the chip unit 1 by air/chemical etching or the like in step S2. The slot 11 is disposed under the solder window 13, and the thickness of the chip 11 can be thinned. The preparation of the subsequent vias 112 is facilitated.

In this step, the etching method determines the aspect ratio of the sidewall of the groove, and the angle between the side wall of the groove formed by the air etching and the vertical direction is approximately 20°, and the width h of the grooved sidewall is greater than k.

In this step, the bottomed wall 1122 of the groove covers the soldering window 13 on the projection area S on the first surface (see also FIG. 1) to facilitate the preparation of the subsequent via 112. The slot 11 is a trapezoidal structure whose central axis x coincides with the central axis of the slot, and the left boundary 110 of the slot is maintained larger than the left edge of the second surface 116 of the chip by more than 10 um while preparing the slot 11 while maintaining The upper and lower boundaries 110 at both ends of the slot 11 are larger than 10 μm from the upper and lower edges of the second surface of the chip (refer to FIG. 1 or FIG. 5b).

In the present embodiment, the second surface edge 117 should understand the outermost side of the second surface 116, and the grooved boundary 110 should be understood as the boundary line between the slot 11 and the second surface; the boundary 110 and the second surface The distance of the edge 117 should be understood as the minimum distance that the boundary 110 can reach between the second surface edge 118.

Referring to FIG. 4c, etching is performed between the slot 11 and the soldering window 13 in step S3 to form a through hole 112 penetrating the first surface 115 or the soldering window 13 and the second surface 116. In this embodiment, the through hole 112 The shape is a hollow truncated cone shape, and may be a columnar shape or the like in other embodiments.

Referring to FIG. 4d, a circular pad 12 is formed on the second surface 116 of the chip unit and on the periphery of the slot 11, and then electrically connected by the wiring 121 between the pad 12 and the solder window 13, so that The functional circuit is electrically coupled to the pad 12.

In the present embodiment, the wiring is formed in the through hole 1121 wall, the grooved bottom wall 1122, the grooved side wall 1123, and the second surface 116.

Referring to FIG. 4e, in the embodiment, a plurality of stages of slots 11 may be provided, that is, the overlapping trapezoidal slots 113 extend along the trapezoidal shape of the

trapezoidal slots

11, 113, and the boundary 110 of the multi-stage trapezoidal slots 11 The distance from the second surface edge 117 is greater than 10 um, that is, at least the boundary distance 117 of the first-stage trapezoidal groove of the multi-stage trapezoidal groove is greater than 10 um when the trapezoidal groove is prepared.

Referring to FIG. 5 and FIG. 6a, the soldering window and the functional circuit arranged in the above step S1 are logical operation circuit 132, ESD protection circuit 131, solder window 13, solder window 13 and logic in order from top to bottom in the figure. The arithmetic circuit 131 and the ESD protection circuit 132 form a circuit arrangement unit 14 in which a plurality of the circuit arrangement units 14 are juxtaposed on the first surface 115 of the chip 1, the solder window 13 being disposed on the side close to the first surface edge 118 The logical operation circuit 132 and the ESD protection circuit 131 are disposed on a side away from the first surface edge 118. Therefore, the relative positional relationship between the soldering window 13 and the logic operation circuit 132 and the ESD protection circuit 131 is the same as that of the prior art, and the slot of the slot 11 is slotted from the second surface edge 117 in order to satisfy the slotting in step S2. More than 10um, the position of the arrangement unit is moved away from the edge of the first surface as a whole, that is, moving upwards and to the right (referred to as a paper surface).

Referring to the second arrangement of the weld window shown in Figure 6b, the arrangement of the weld window in Figure 6a differs in that a plurality of arrangement units 14 are added to the left side of the first surface 115. The increased placement unit 14 position moves generally away from the first surface edge 118 relative to the prior art, i.e., downwards and to the left (referenced to the paper surface).

Referring to the third arrangement of the welding window shown in FIG. 6c, the arrangement of the welding window 13 in FIG. 6a is different in that the position of the arrangement unit 14 is reversed, that is, the logic operation circuit 132, and the ESD protection circuit 131 is arranged close to The position of the first surface edge 118, the weld window 13 is disposed in a direction away from the first surface edge 118. An advantage over the weld window arrangement of Figure 6a is that the circuit is disposed in the lower weld window 13 and the circuit arrangement requires a certain distance. The weld window 13 is naturally remote from the edge 118 of the first surface and can be slotted in step S2. A sufficient distance is reserved so that the boundary 110 of the slot 11 is larger than 10 um from the second surface, and the circuit fully utilizes the area of the chip, and the partial chip area waste in FIG. 5a does not occur.

It is apparent to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the invention is defined by the appended claims instead All changes in the meaning and scope of equivalent elements are included in the present invention. Any reference signs in the claims should not be construed as limiting the claim.

In addition, it should be understood that although the description is described in terms of embodiments, not every embodiment includes only one independent technical solution. The description of the specification is merely for the sake of clarity, and those skilled in the art should The technical solutions in the respective embodiments may also be combined as appropriate to form other embodiments that can be understood by those skilled in the art.

Claims

a wafer level chip package structure, comprising: a chip unit having oppositely disposed first surfaces and second surfaces, the first surface arranging at least one solder window for electrical connection; the second surface setting A TSV structure coupled to the solder window, the TSV structure including a through hole extending through the first surface and the second surface and a groove disposed on the second surface, the boundary of the groove being greater than 10 um from the edge of the second surface.
The wafer level chip package structure according to claim 1, wherein a distance L between a boundary of the solder window and a first surface edge satisfies a relationship
The wafer level chip package structure according to claim 1 , wherein at least one pad is disposed on the second surface of the chip unit, and the soldering window and the pad are formed in the through hole wall and slotted The wiring of the bottom wall, the slotted side wall, and the second surface is electrically conductive.
The wafer level chip package structure according to claim 1, wherein the groove is a one-stage or multi-stage trapezoidal groove.
The method of fabricating a wafer level chip package structure according to claim 1, comprising the steps of:

S1: arranging a soldering window on the first surface of the chip unit such that the distance L between the soldering window and the edge of the first surface satisfies a relationship

S2: forming a trapezoidal groove on the second surface of the chip unit, the projection of the bottom wall of the groove on the first surface covers the welding window, the boundary of the groove is greater than 10 um from the edge of the second surface;

S3: forming a through hole through the soldering window and the bottom wall of the slot in the slot, such that the through hole is connected to the soldering window;

S4: forming a wiring on the through hole wall, the grooved bottom wall, the grooved side wall, and the second surface, the wiring electrically communicating with the solder window and the pad.
The method of fabricating a wafer level chip package structure according to claim 5, wherein the aspect ratio k of the grooved sidewall is approximately equal to 2.75.
The method of fabricating a wafer level chip package structure according to claim 5, wherein the trapezoidal groove is a one-stage or multi-stage trapezoidal groove.