CN206650071U - Wafer stage chip encapsulating structure - Google Patents
Wafer stage chip encapsulating structure Download PDFInfo
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- CN206650071U CN206650071U CN201720278291.XU CN201720278291U CN206650071U CN 206650071 U CN206650071 U CN 206650071U CN 201720278291 U CN201720278291 U CN 201720278291U CN 206650071 U CN206650071 U CN 206650071U
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Abstract
Wafer stage chip encapsulating structure, including chip unit are the utility model is related to, it has the first surface and second surface being oppositely arranged, and the first surface arranges at least one weldering window for electrically connecting；The second surface sets the TSV structure being connected with weldering window, and the TSV structure includes the through hole through first surface and second surface and the fluting set in second surface, and the edge of the frontier distance second surface of fluting is more than 10um.The progress obtained compared with the prior art is to improve the structural strength of chip.
Description
Technical field
It the utility model is related to technical field of semiconductors, more particularly to a kind of wafer stage chip encapsulating structure.
Background technology
TSV (Through Silicon Vias pass through silicon chip passage) encapsulating structure is one kind of IC package mode, can be divided
To be encapsulated and for surface-mounted device wafer-level packaging for memory.Wafer-level packaging is applied on optical image sensor (please
Reference picture 1), optical image sensor 2 has glass substrate 3 to support TSV structure 4 to maintain structural strength under this situation, and TSV's opens
Made with facilitating at the edge 21 that the Z axis attachment structures such as hole 41, fluting 22, wiring 23 and weldering window 24 are arranged on image sensor chip
Make.
And some chips (such as capacitive fingerprint sensing device chip) in order to package thickness is thinned, it is necessary to TSV encapsulation but
There is no glass plate as support, if continuing to adopt optical image sensor TSV packaging technologies (such as patent
The TSV encapsulating structures disclosed in CN201510305840.3), the technological deficiency of chip edge insufficient strength will be produced, so that
Risk can be brought in following process by obtaining.Such as stress is increased when being cut to chip cause the wind of chip cracks
Danger, also can bring risk in later stage paster and assembling stage.
Therefore the structural strength for needing to improve TSV structure and manufacture method raising chip solves the above problems.
Utility model content
The purpose of the technical program be ensure microarray biochip integral thickness so as to improve chip structure intensity, for this general
The inside that TSV fluting is arranged on chip causes fluting to keep certain safe distance with chip edge, is greater than 10um.By
The inside of chip is arranged in TSV flutings so that the chip thickness in TSV flutings outside structure identical with the thickness of fluting inner side is strong
Degree is lifted.
Technical solutions of the utility model include content in detail below：
Wafer stage chip encapsulating structure, it is characterised in that including chip unit, its have the first surface that is oppositely arranged and
Second surface, at least one weldering window for being used to electrically connect of first surface arrangement；The second surface is set to be connected with weldering window
TSV structure, the TSV structure includes the through hole and the fluting that is set in second surface through first surface and second surface,
The edge of the frontier distance second surface of fluting is more than 10um.
Preferably, the distance L on the border and first surface edge of welding window meets relational expression
Preferably, the second surface of chip unit is provided with least one pad, welds window and pad by being formed described
The wiring of through-hole wall, slot bottom wall, slotted wall and second surface electrically conducts.
A kind of manufacture of wafer stage chip encapsulating structure is also disclosed preferably to solve above-mentioned technical problem the utility model
Method, including step：
S1：In the first surface arrangement weldering window of chip unit so that the distance L of the weldering window and first surface edge meets
Relational expression
S2：Dovetail groove, the projection covering institute of the bottom wall of fluting on the first surface are formed in the second surface of chip unit
Weldering window is stated, the frontier distance second surface edge of fluting is more than 10um；
S3：The through hole of insertion weldering window and bottom wall of slotting is formed in the fluting so that the through hole connection weldering window；
S4：Wiring, wiring electrical communication weldering are formed in the through-hole wall, fluting bottom wall, slotted wall and second surface
Window and pad.
Preferably, the depth-width ratio k of slotted wall is approximately equal to 2.75.
Preferably, dovetail groove is one or more levels dovetail groove.
The utility model in order to by by TSV slot to chip internal move so that the chip height of TSV grooved exteriors with
The height of chip internal is identical, improves the intensity of chip edge, while avoids the symmetrical weldering window construction of design, also
Avoid this design and bring influence to circuit design.
Brief description of the drawings
, below will be to embodiment in order to illustrate more clearly of the utility model embodiment or technical scheme of the prior art
Or the required accompanying drawing used is briefly described in description of the prior art, it should be apparent that, drawings in the following description are only
It is some embodiments described in the utility model, for those of ordinary skill in the art, is not paying creative work
On the premise of, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is prior art image sensor TSV encapsulating structure cross-sectional views.
Fig. 2 a are the schematic perspective view of the utility model TSV encapsulating structures.
Fig. 2 b are the schematic perspective view of the utility model TSV encapsulating structures.
Fig. 3 is the utility model second surface pad array schematic diagram.
Fig. 4 a are the utility model cross-sectional view in TSV manufacturing step S1.
Fig. 4 b are the utility model cross-sectional view in TSV manufacturing step S2.
Fig. 4 c are the utility model cross-sectional view in TSV manufacturing step S3.
Fig. 4 d are the utility model cross-sectional view in TSV manufacturing step S4.
Fig. 4 e are the utility model in another embodiment schematic diagram of TSV structure.
Fig. 5 is that the utility model welds window function structural representation.
Fig. 6 a-6c are to weld window in the utility model 5 to be laid out 4 kinds of weldering window component schematic diagrames.
Embodiment
In order that those skilled in the art more fully understand the technical scheme in the utility model, below in conjunction with this reality
With the accompanying drawing in new embodiment, the technical scheme in the embodiment of the utility model is clearly and completely described, it is clear that
Described embodiment is only the utility model part of the embodiment, rather than whole embodiments.Based on the utility model
In embodiment, the every other implementation that those of ordinary skill in the art are obtained under the premise of creative work is not made
Example, it should all belong to the scope of the utility model protection.
As shown in Figure 2 a, the utility model wafer stage chip encapsulating structure, including chip unit 1, chip unit has phase
To the first surface 115 and second surface 116 of setting.In the utility model by taking fingerprint sensor as an example, the first surface
115 set functional circuits 132,131 and the capacitor cell array (not shown) for sensing fingerprint image, functional circuit with
Weld the electric 13 property connection of window.The second surface 116 sets pad 12 and the TSV structure being electrically connected with weldering window, the TSV structure
Including through first surface 115 or the through hole 112 of weldering window 13 and second surface 116, and the fluting 11 being connected with through hole 112, opening
The frontier distance 110 of groove, the edge 117 of 111 second surfaces are more than 10um.
In the present embodiment, the border 110 of fluting causes apart from the edge 117 of the second surface 116 more than 10um
The thickness d 1 in the outside of chip fluting 11 and the thickness d 2 identical (reference picture 4c) of chip internal, so as to ensure that chip is cut from wafer
The risk that stress caused by cutting avoids chip edge fragmentation can be born when cutting.
In the present embodiment, the border that the border of the fluting 11 includes the border 110 of Longitudinal extending and extended laterally
111；The distance at the frontier distance second surface edge of weldering window described in the utility model is more than 10um, refers to any one border
The edge of distance weldering window is all higher than 10um.Therefore near the weldering window border 110 at second surface edge 117 distance at least above
10um
Following manufacture method is provided in order to obtain above-mentioned TSV encapsulating structures the utility model:
S1：In the first surface arrangement weldering window of chip unit so that the distance L of the weldering window and first surface edge meets
Relational expression
S2：Dovetail groove, the projection covering institute of the bottom wall of fluting on the first surface are formed in the second surface of chip unit
Weldering window is stated, the frontier distance second surface edge of fluting is more than 10um；
S3：The through hole of insertion weldering window and bottom wall of slotting is formed in the fluting so that the through hole connection weldering window；
S4：Wiring, wiring electrical communication weldering are formed in the through-hole wall, fluting bottom wall, slotted wall and second surface
Window and pad.
Above-mentioned step is described in detail below：
Fig. 4 a and Fig. 4 b are refer in step sl in the arrangement weldering window 13 of first surface 115 of chip so that the weldering window 12
Edge 118 away from first surface 115, weldering window 13 away from first surface edge 118 be in order that must weld the border 133 of window 13 with
First edge 118 maintains a certain distance L, and distance L is provided so that the border 110 of the fluting 11 apart from second surface
116 edge is more than 10um.Distance L meets relational expression in order to achieve the above object
In the present embodiment, the first surface edge 118 is it should be understood that the outermost of first surface 115, the weldering window
113 border should be understood to weld the boundary line of window and chip；The distance L should be understood to that border 113 can reach with
Minimum range between first surface edge 118.
In this step, in order to open up central shaft x and fluting 11 that window 13 is welded described in through hole 112 center overlapping of axles x, when
Same change in location also occurs for the weldering window 13 position of corresponding fluting 11 when the position on chip unit changes.
In this step, functional circuit 131,132 and fingerprint sensing array are included with what the weldering window 13 was arranged simultaneously.
In this step, weld the shape of window 13 and quantity carries out different designs as needed.
In this step, multiple weldering windows 13 can be set, keep certain spacing between weldering window 13, the spacing preparing
During through hole 112, do not interfered between through hole 112 corresponding to different pads 13.
Fig. 4 b be refer in step s 2 on the second surface 116 of chip unit 1 by air/chemical etching the methods of
Fluting 11 is prepared, fluting 11 is arranged at the lower section of weldering window 13, with the thickness of thinned die 11, can facilitate the system of follow-up through hole 112
It is standby.
The ratio of width to height of slotted wall is determined in this step lithographic method, air etches the slotted wall to be formed and vertical side
It is than k to angle a substantially 20 ° of wide w of the high h of slotted wall
In this step, described in view field S (referring concurrently to Fig. 1) coverings of the bottom wall 1122 of fluting on the first surface
Window 13 is welded, to facilitate the preparation of follow-up through hole 112.The fluting 11 is trapezium structure central shaft x and fluting central shaft weight
Close, keep the left margin 110 of the groove to be more than apart from the left hand edge of the chip second surface 116 when preparing fluting 11
10um, while keep the up-and-down boundary 110 at 11 both ends of fluting to be more than 10um (ginsengs apart from the lower edges of the chip second surface
According to Fig. 1 or Fig. 6 b).
In the present embodiment, the second surface edge 117 is it should be understood that the outermost of second surface 116, the fluting
Border 110 should be understood to fluting 11 and the boundary lines of second surface；The distance at border 110 and second surface edge 117 should
When the minimum range between second surface edge 118 that is interpreted as border 110 and can reach.
Fig. 4 c are refer to, are performed etching in step s3 between fluting 11 and weldering window 13, formation runs through first surface 115
Or the through hole 112 of weldering window 13 and second surface 116, in the present embodiment through hole 112 be shaped as it is hollow round table-like, in other realities
It can also be cylindric etc. to apply a mode.
It refer to shown in Fig. 4 d, circle formed on the second surface 116 of chip unit and positioned at the periphery of fluting 11
Pad 12, then it is electrically connected between pad 12 and weldering window 13 using wiring 121 so that the functional circuit produces and institute
Pad 12 is stated to electrically conduct.
The wiring in the present embodiment is formed in the wall of through hole 1121, fluting bottom wall 1122, the and of slotted wall 1123
Second surface 116.
Refer to Fig. 4 e can also set the fluting 11 of multistage in the present embodiment, i.e., described in overlapping dovetail groove 113
Trapezoidal extension of the wiring 121 along dovetail groove 11,113, the border 110 of the multistage dovetail groove 11 is apart from second surface edge
117 distance is more than 10um, i.e., at least ensures the first order dovetail groove of the multistage dovetail groove when preparing the dovetail groove
The edge 117 of the second surface of frontier distance 110 is more than 10um.
Fig. 5 and Fig. 6 a are refer to, the weldering window and functional circuit arranged in above-mentioned steps S1, according to suitable from top to bottom in figure
Sequence is logical operation circuit 132 successively, esd protection circuit 131, welds window 13；Weld window 13 and logical operation circuit 131 and ESD is protected
Protection circuit 132 forms a circuit arrangement unit 14, and multiple circuit arrangement units 14 are disposed in parallel in the first table of chip 1
On face 115, the weldering window 13 is disposed adjacent to the position of the side of first surface edge 118, the He of logical operation circuit 132
Esd protection circuit 131 is arranged in the side away from first surface edge 118.Therefore, window 13 and logical operation circuit 132 are welded,
The relative position relation of esd protection circuit 131 is same as the prior art, fluting during in order to meet to slot in step s 2
11 fluting of frontier distance second surface edge 117 is more than 10um, and arrangement unit position is overall to remote the compared with the prior art
One marginal surface direction is moved, i.e., upwards, moves right (using paper as reference).
Second of arrangement of the weldering window of Fig. 6 b displayings is refer to, the arrangement difference with welding window in Fig. 6 a is first
The left side on surface 115 adds multiple arrangement units 14.The increased position of arrangement unit 14 is overall to remote compared with the prior art
The direction of first surface edge 118 is moved, i.e., downwards, is moved to the left (using paper as reference).
The third arrangement of the weldering window of Fig. 6 c displayings is refer to, the arrangement difference with welding window 13 in Fig. 6 a is described
The position of arrangement unit 14 is overturned, i.e. logical operation circuit 132, and esd protection circuit 131 is disposed adjacent to first surface
The position at edge 118, weldering window 13 are arranged in the direction away from the first surface edge 118.It is relative to be arranged with welding window in Fig. 6 a
The advantage of mode is, circuit arrangement is welded into window 13 in lower section and circuit arrangement needs to take a certain distance, and weldering window 13 is natural
Edge 118 away from first surface, can be that fluting 11 reserves the border 110 that enough distances cause fluting 11 in step S2
It is more than 10um apart from second surface fluting, while circuit takes full advantage of the area of chip, and segment chip in Fig. 6 a will not occur
The situation of area loss.
It is obvious to a person skilled in the art that the utility model is not limited to the details of above-mentioned one exemplary embodiment, and
And in the case of without departing substantially from spirit or essential attributes of the present utility model, it can realize that this practicality is new in other specific forms
Type.Therefore, no matter from the point of view of which point, embodiment all should be regarded as exemplary, and is nonrestrictive, this practicality is new
The scope of type limits by appended claims rather than described above, it is intended that the equivalency fallen in claim is contained
All changes in justice and scope are included in the utility model.Any reference in claim should not be considered as limitation
Involved claim.
Moreover, it will be appreciated that although the present specification is described in terms of embodiments, not each embodiment is only wrapped
Containing an independent technical scheme, this narrating mode of specification is only that those skilled in the art should for clarity
Using specification as an entirety, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the art
It is appreciated that other embodiment.
Claims (5)
1. wafer stage chip encapsulating structure, it is characterised in that including chip unit, it has the first surface that is oppositely arranged and the
Two surfaces, at least one weldering window for being used to electrically connect of first surface arrangement；The second surface sets what is be connected with weldering window
TSV structure, the TSV structure include the through hole through first surface and second surface and the fluting set in second surface, opened
The edge of the frontier distance second surface of groove is more than 10um.
2. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the border of the weldering window and the first table
The distance L at face edge meets relational expression
3. wafer stage chip encapsulating structure according to claim 2, it is characterised in that the depth-width ratio k of the slotted wall
It is approximately equal to 2.75.
4. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the second surface of the chip unit
At least one pad is provided with, welds window and pad by being formed in the through-hole wall, fluting bottom wall, slotted wall and second surface
Wiring electrically conduct.
5. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the fluting is one or more levels ladder
Shape groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720278291.XU CN206650071U (en) | 2017-03-21 | 2017-03-21 | Wafer stage chip encapsulating structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720278291.XU CN206650071U (en) | 2017-03-21 | 2017-03-21 | Wafer stage chip encapsulating structure |
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| Publication Number | Publication Date |
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| CN206650071U true CN206650071U (en) | 2017-11-17 |
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| CN201720278291.XU Active CN206650071U (en) | 2017-03-21 | 2017-03-21 | Wafer stage chip encapsulating structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107068652A (en) * | 2017-03-21 | 2017-08-18 | 苏州迈瑞微电子有限公司 | Wafer stage chip encapsulating structure and method for packing |
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2017
- 2017-03-21 CN CN201720278291.XU patent/CN206650071U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107068652A (en) * | 2017-03-21 | 2017-08-18 | 苏州迈瑞微电子有限公司 | Wafer stage chip encapsulating structure and method for packing |
| WO2018171547A1 (en) * | 2017-03-21 | 2018-09-27 | 苏州迈瑞微电子有限公司 | Wafer-level chip encapsulating structure and manufacturing method therefor |
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