CN103547088B - There is multilayer circuit board structure and the manufacture method of embedded element - Google Patents
There is multilayer circuit board structure and the manufacture method of embedded element Download PDFInfo
- Publication number
- CN103547088B CN103547088B CN201210242976.0A CN201210242976A CN103547088B CN 103547088 B CN103547088 B CN 103547088B CN 201210242976 A CN201210242976 A CN 201210242976A CN 103547088 B CN103547088 B CN 103547088B
- Authority
- CN
- China
- Prior art keywords
- semiconductor element
- circuit board
- wire
- multilayer circuit
- vias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The present invention discloses a kind of multilayer circuit board structure and manufacture method with embedded element. Manufacture method comprises: the substrate with first surface and the first alignment mark is provided. Semiconductor element is set on substrate. Form dielectric layer on substrate, dielectric layer covers semiconductor element and has second surface and the second alignment mark. The corresponding each semiconductor element setting of each the second alignment mark. Do contraposition reference with first and second alignment mark respectively and form first and second via group, the first via group comprises multiple the first vias that extended to first surface by second surface. The second via group comprises and multiplely extends to multiple the second vias on semiconductor element by second surface. Form wire group on second surface. Two the stage patterning wire group to form respectively first and second wire group connected to one another.
Description
Technical field
The present invention relates to a kind of circuit board structure and manufacture method, and particularly relate to a kind of multilayer circuit board structure and manufacture method thereof with embedded element.
Background technology
In semiconductor industry, the object of chip packaging is to prevent that bare chip is subject to the impact of moisture, heat and noise, and the medium being electrically connected between bare chip and external circuit is provided. In recent years, along with making rapid progress and continuous integration and the innovation of high-tech electronic product of electronic technology, conventional semiconductors structure packing technique cannot meet product function and cost demand. At present, semi-conductor packaging technology strides forward towards the trend that chip is integrated in circuit base plate, so that whole structure dress area and volume significantly dwindle, reaches the demand of compactization of electronic product, multifunction, high speed and densification.
The technology of existing embedded element wiring board can be arranged on embedded element on support plate (carrier) in advance, again by after the dielectric layer contraposition of embedded element, its support plate depending on and joint use, carry out conductive through hole (conductivevia) manufacture craft with laser, be electrically connected these embedded elements to produce the conductive through hole that multiple degree of depth are identical, so repeat to make multilayer line layer, finally remove again support plate, make the active surperficial copline of embedded element and dielectric layer. So not only step is complicated for manufacture craft, and, easily cause the error laser offset or contraposition from the surface of wiring board with laser drill. Especially,, when the embedded element in wiring board or the circuit number of plies are when more, the contraposition effect of conductive through hole is more undesirable, has therefore reduced the making yield of wiring board. Therefore,, how by being embedded in wiring board in element and the variety of problems that can avoid prior art to produce, become current key technology.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of the multilayer circuit board structure with embedded element, it can simplify manufacture craft, and can promote the contraposition precision of via and improve and produce yield.
A further object of the present invention provides a kind of multilayer circuit board structure with embedded element, and its manufacture craft is comparatively simple, and the contraposition precision of its via is higher, has more higher production yield.
For reaching above-mentioned purpose, the present invention proposes a kind of manufacture method of the multilayer circuit board structure with embedded element, and it comprises the following steps. One substrate is provided, and substrate has a first surface and is positioned at least one the first alignment mark on first surface. At least one semiconductor element is set on substrate. Form one first dielectric layer on substrate, wherein the first dielectric layer covers semiconductor element and has a second surface and be positioned at least one second alignment mark of second surface. The corresponding each semiconductor element setting in position of each the second alignment mark. Do contraposition reference with the first alignment mark and form at least one the first via group. The first via group comprises multiple the first vias, and each the first via extends to first surface by second surface. Do contraposition reference with the second alignment mark and form at least one the second via group. The second via group comprises multiple the second vias, and each the second via is extended to a upper surface of semiconductor element by second surface. Form a wire group on second surface. Two the stage patterning wire group to form respectively one first wire group connected to one another and one second wire group.
The present invention also proposes a kind of multilayer circuit board structure with embedded element, and it comprises a substrate, at least one semiconductor element, one first dielectric layer, at least one the first via group, at least one the second via group and a patterning wire group. Substrate has a first surface and is positioned at least one the first alignment mark on first surface. Semiconductor element is arranged on substrate. The first dielectric layer is formed on substrate and covers semiconductor element. The first dielectric layer has a second surface and is positioned at least one second alignment mark of second surface, or at least one the second alignment mark on semiconductor element can be had an X-rayed by the first dielectric layer. The corresponding each semiconductor element setting in position of each the second alignment mark. Corresponding the first alignment mark setting of the first via group. The first via group comprises multiple the first vias. Each the first via extends to first surface by second surface. Corresponding the second alignment mark setting of the second via group. The second via group comprises multiple the second vias. Each the second via is extended to a upper surface of semiconductor element by second surface. Patterning wire group connect another patterning wire group and the first via at least one of them and the second via at least one of them.
In one embodiment of this invention, the first surface of above-mentioned substrate has multiple the first connection pads, and the first via connects the first corresponding connection pad.
In one embodiment of this invention, the upper surface of above-mentioned semiconductor element has multiple the second connection pads, and the second via connects the second corresponding connection pad.
In one embodiment of this invention, above-mentioned each the first via has one first height, the height of the height of each the first via etc. or each second via such as not.
In one embodiment of this invention, above-mentioned two the stage patterning wire group comprise with the step that forms respectively the first wire group connected to one another and the second wire group: do contraposition reference exposure wire group with the first alignment mark, with form one first exposure wire pattern, first exposure wire pattern one end connect the first via at least one of them. Do contraposition reference exposure wire pattern to form one second exposure wire pattern with the second alignment mark. Second exposure wire pattern one end connect the second via at least one of them, and first and second exposure wire pattern be connected to each other. Development wire group is to form the first wire group and the second wire group.
In one embodiment of this invention, the first above-mentioned wire group comprises at least one the first end points connection pad and at least one the first wire. The first wire connect the first end points connection pad and the first via at least one of them. The second wire group comprises at least one the second end points connection pad and at least one the second wire. The second wire connect the second end points connection pad and the second via at least one of them. The first end points connection pad overlaps at least partly with the second end points connection pad.
In one embodiment of this invention, above-mentioned semiconductor element comprises active component, passive element, chip size packages element (ChipScalePackage, CSP), circuit board or its arbitrary combination.
In one embodiment of this invention, above-mentioned formation the first via group and the mode of the second via group comprise laser drill.
In one embodiment of this invention, the quantity of the second alignment mark of above-mentioned semiconductor element and correspondence is all multiple, semiconductor element comprises one first semiconductor element and one second semiconductor element, height of the first semiconductor element etc. or be not equal to the height of the second semiconductor element.
In one embodiment of this invention, the second via of above-mentioned part is extended to the upper surface of the first semiconductor element by second surface, and the second via of part is extended to the upper surface of the second semiconductor element by second surface.
In one embodiment of this invention, the above-mentioned step of semiconductor element on substrate that arrange comprises: electrically configure the first semiconductor element on the first surface of substrate. Form one second dielectric layer on first surface, and coated this first semiconductor element at least partly of the second dielectric layer. Electrically configuration the second semiconductor element is on the second dielectric layer.
In one embodiment of this invention, above-mentioned patterning wire group comprises one first wire group and one second wire group. The first wire group comprises at least one the first end points connection pad and at least one the first wire. The first wire connect the first end points connection pad and the first via at least one of them. The second wire group comprises at least one the second end points connection pad and at least one the second wire. The second wire connect the second end points connection pad and the second via at least one of them, wherein the first end points connection pad overlaps at least partly with the second end points connection pad.
Based on above-mentioned, the present invention will have multiple vias on the multilayer circuit board structure of embedded element highly to do and to classify, and multiple vias of same group are once formed with laser drill. So, can the multilayer circuit board structure with embedded element is stacking complete after, form together the via group of multiple differing heights, saved existing complicated manufacturing process steps.
In addition, each via group also does contraposition reference with alignment mark separately respectively and carries out contraposition. And in the mode of two stage patternings, do contraposition reference with corresponding alignment mark respectively and form two wire connected to one another groups, and two wire groups all have end points connection pad, make two-end-point connection pad only need to partially overlap, can reach effect of the two wire groups that electrically conduct, the bit errors tolerance of via and wire is improved. Therefore, the present invention has not only simplified the production process of the multilayer circuit board structure with embedded element, has more increased the contraposition precision of via and wire group, with and manufacture craft yield.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended accompanying drawing to be described in detail below.
Brief description of the drawings
Figure 1A to Fig. 1 G is the manufacturing process schematic top plan view of a kind of multilayer circuit board structure with embedded element of one embodiment of the invention;
Fig. 2 A to 2C is the generalized section of the manufacturing process of a kind of multilayer circuit board structure with embedded element of another embodiment of the present invention;
Fig. 3 A to Fig. 3 D is the generalized section of the manufacturing process of a kind of multilayer circuit board structure with embedded element of another embodiment of the present invention.
Main element symbol description
100,200,300: the multilayer circuit board structure with embedded element
110: substrate
112: first surface
114: the first alignment marks
116: the first connection pads
120,120a, 120b: semiconductor element
122: upper surface
124: the second connection pads
130: the first dielectric layers
132: second surface
134: the second alignment marks
140: the first via groups
142: the first vias
150,150a, 150b: the second via group
152,152a, 152b: the second via
162: the first exposure wire patterns
163: the first wire groups
163a: the first end points connection pad
163b: the first wire
164: the second exposure wire patterns
165: the second wire groups
165a: the second end points connection pad
165b: the second wire
170: the second dielectric layers
Detailed description of the invention
Figure 1A to Fig. 1 G is the manufacturing process schematic top plan view according to a kind of multilayer circuit board structure with embedded element of one embodiment of the invention. According to the preparation method of the multilayer circuit board structure with embedded element of the present embodiment, first, please refer to Figure 1A, one substrate 110 is provided, substrate 110 has a first surface 112 and is positioned at least one the first alignment mark 114 on first surface 112, wherein, the first surface 112 of substrate 110 also has multiple the first connection pads 116. Then, please refer to Figure 1B, arranging that at least one semiconductor element 120(illustrates is one) on substrate 110, wherein, the upper surface 122 of semiconductor element 120 has multiple the second connection pads 124. In the present embodiment, semiconductor element 120 can be active component, passive element, chip size packages element (ChipScalePackage, CSP), circuit board or any combination wherein. Then, please refer to Fig. 1 C, form one first dielectric layer 130 on substrate 110, wherein, the first dielectric layer 130 covers semiconductor element 120 and has a second surface 132 and be positioned at least one second alignment mark 134 of second surface 132, or at least one the second alignment mark 134 on semiconductor element 120 can be had an X-rayed by the first dielectric layer 130. The corresponding each semiconductor element 120 in the position of each the second alignment mark 134 arranges, and for example, with the edge of the each semiconductor element 120 of the second alignment mark 134 mark, but the present invention is not as limit. At this, based on the relation at visual angle, Fig. 1 C does not illustrate substrate 110, and the element (such as semiconductor element 120 and connection pad 116,124 etc.) on substrate 110 is illustrated on the first dielectric layer 130 with dotted line.
Hold above-mentioned, then, please refer to Fig. 1 D, do contraposition reference with the first alignment mark 114 and form at least one the first via group 140, and, do contraposition reference with the second alignment mark 134 and form at least one the second via group 150, wherein, the quantity of the quantity of the second via group 150 and corresponding semiconductor element 120. In the present embodiment, the mode that forms the first via group 140 and the second via group 150 comprises laser drill, but the present invention is not as limit. In addition, the present invention does not limit the order that forms the first via group 140 and the second via group 150 yet, has and conventionally know that the knowledgeable all can set the formation order of via group voluntarily according to actual design demand in any affiliated technical field. Actual, the first via group 140 comprises multiple the first vias 142, and each the first via 142 extends to first surface 112 by second surface 132. The first via 142 connects the first corresponding connection pad 116. The second via group 150 comprises respectively multiple the second vias 152, each the second via 152 is extended to the upper surface 122 of semiconductor element 120 by second surface 132, and the second via 152 connects the second corresponding connection pad 124, and the height of each the first via 142 etc. or be not equal to the height of each the second via 152.
Referring to Fig. 1 E to Fig. 1 G, then, form a wire group (not illustrating) on second surface 132, the more above-mentioned wire group of two stage patternings is to form respectively the first wire group 163 connected to one another and the second wire group 165 as shown in Figure 1 G. Specifically, the step of the above-mentioned wire group of two stage patternings comprises: do contraposition reference exposure wire group with the first alignment mark 114, to form the first exposure wire pattern 162 as shown in Fig. 1 E, wherein, first exposure wire pattern 162 one end connect the first via 142 at least one of them. And, do contraposition reference exposure wire group to form the second exposure wire pattern 164 as shown in Figure 1 F with the second alignment mark 134. Wherein, second exposure wire pattern 164 one end connect the second via 152 at least one of them, and first and second exposure wire pattern 162,164 be connected to each other. Then, develop first and second exposure wire pattern 162,164 to form the first wire group 163 and the second wire group 165 as shown in Figure 1 G. At this, the present invention does not limit the order that forms the first wire group 163 and the second wire group 165, has and conventionally know that the knowledgeable all can set the formation order of wire group voluntarily according to actual design demand in any affiliated technical field.
Actual, as shown in Figure 1 G, the first wire group 163 also comprises at least one the first end points connection pad 163a and at least one the first wire 163b, and the first wire 163b connect the first end points connection pad 163a and the first via 142 at least one of them. The second wire group 165 also comprises at least one the second end points connection pad 165a and at least one the second wire 165b, and the second wire 165b connect the second end points connection pad 165a and the second via 152 at least one of them. In the present embodiment, the first end points connection pad 163a is with the second end points connection pad 165a the state overlapping completely, with the first wire 163a and the second wire 165a of electrically conducting. But in the embodiment not illustrating at other, the first end points connection pad 163a can only partially overlap with the second end points connection pad 165a, can reach effect of electrically conduct the first wire 163a and the second wire 165a. So design, can make the bit errors tolerance of via 142,152 and wire 163,165 improve, and then promote the yield of manufacture craft.
Manufacturing process described above, completes the manufacture craft of the multilayer circuit board structure with embedded element 100 of one embodiment of the invention. So design, by the numerous vias on multilayer circuit board structure 100 142,152 highly to do and to classify, this means, will extend to the via 142/152 Fen Zuoyige group 140/150 of same layer, and multiple vias 142/152 of same group 140/150 are once formed with laser drill. So, can form together the via group 140,150 of multiple differing heights after completing multilayer circuit board structure 100 is stacking, save complicated manufacturing process steps. In addition, each via group 140/150 does contraposition reference with alignment mark 114/134 separately respectively and carries out contraposition, has more increased the contraposition precision of via 142,152, and then promotes the manufacture craft yield of multilayer circuit board structure 100.
Fig. 2 A to 2C is the generalized section according to the manufacturing process of a kind of multilayer circuit board structure with embedded element of another embodiment of the present invention. The present embodiment is continued to use element numbers and the partial content of previous embodiment, wherein adopts identical label to represent identical or approximate element, and has omitted the explanation of constructed content. Explanation about clipped can be with reference to previous embodiment, and it is no longer repeated for the present embodiment. In addition, the present embodiment presents the manufacturing process of the multilayer circuit board structure with embedded element with generalized section, to know the height of formation that presents via.
The multilayer circuit board structure with embedded element 200 of the present embodiment can adopt the production method roughly the same with the making flow process of the multilayer circuit board structure with embedded element 100 of previous embodiment, after a substrate 110 is provided, semiconductor element 120 is set on substrate 110, only in the present embodiment, the quantity of second alignment mark (not illustrating) of semiconductor element 120 and correspondence is all multiple. As shown in Figure 2 A, semiconductor element 120 comprises one first semiconductor element 120a and one second semiconductor element 120b, wherein, and the height of the first semiconductor element 120a etc. or be not equal to the height of the second semiconductor element 120b.
Then, form as in the foregoing embodiment the first dielectric layer 130 on substrate 110, then do contraposition reference with the first alignment mark (the first alignment mark 114 as shown in Figure 1A) as shown in Figure 2 B and form the first via group 140. And as shown in Figure 2 C, do contraposition reference with the second alignment mark of corresponding semiconductor element 120a, 120b respectively and form the second 150a of via group, 150b, the second via 152a is extended to the upper surface of the first semiconductor element 120a by second surface 132, the second via 150b is extended to the upper surface of the second semiconductor element 120b by second surface 132. From Fig. 2 C, the height of the first via group 140 and the second 150a of via group, 150b is neither identical. Then, more as in the foregoing embodiment two the stage patterning wire group to form respectively the first wire connected to one another and the second wire group, complete the manufacture craft of the multilayer circuit board structure with embedded element 200 of one embodiment of the invention. At this, the present invention does not limit the order that forms the first via group 140 and the second 150a of via group, 150b, has and conventionally know that the knowledgeable all can set the formation order of via voluntarily according to actual design demand in any affiliated technical field.
Fig. 3 A to Fig. 3 D is the generalized section according to the manufacturing process of a kind of multilayer circuit board structure with embedded element of another embodiment of the present invention. The present embodiment is continued to use element numbers and the partial content of previous embodiment, wherein adopts identical label to represent identical or approximate element, and has omitted the explanation of constructed content. Explanation about clipped can be with reference to previous embodiment, and it is no longer repeated for the present embodiment. In addition, the present embodiment presents the manufacturing process of the multilayer circuit board structure with embedded element with generalized section, to know the height of formation that presents via.
The multilayer circuit board structure with embedded element 300 of the present embodiment can adopt the production method roughly the same with the making flow process of the multilayer circuit board structure with embedded element 200 of previous embodiment, only in the present embodiment, after a substrate 110 is provided, as shown in Figure 3A, first electrically configure the first semiconductor element 120a on the first surface 112 of substrate 110, then, again as shown in Figure 3 B, form one second dielectric layer 170 on first surface 112, and coated at least part of the first semiconductor element 120a of the second dielectric layer 170. Then,, as described in Fig. 3 C, electrically configure the second semiconductor element 120b on the second dielectric layer 170. So, copline not of the bottom surface of the first semiconductor element 120a and the second semiconductor element 120b. Then form as in the foregoing embodiment again the first via group 140. And form the second 150a of via group, 150b, wherein, the second via 152a is extended to the upper surface of the first semiconductor element 120a by second surface 132, the second via 150b is extended to the upper surface of the second semiconductor element 120b by second surface 132. From Fig. 2 C, the not copline of bottom surface of the first semiconductor element 120a and the second semiconductor element 120b, and the height of the first via group 140 and the second 150a of via group, 150b is neither identical. Then, more as in the foregoing embodiment two the stage patterning wire group to form respectively the first wire connected to one another and the second wire group, complete the manufacture craft of the multilayer circuit board structure with embedded element 300 of one embodiment of the invention. The present invention does not limit the order that forms the first via group 140 and the second 150a of via group, 150b, has and conventionally know that the knowledgeable all can set the formation order of via voluntarily according to actual design demand in any affiliated technical field.
In sum, the present invention will have multiple vias on the multilayer circuit board structure of embedded element highly to do and to classify, and multiple vias of same group are once formed with laser drill. So, can the multilayer circuit board structure with embedded element is stacking complete after, form together the via group of multiple differing heights, saved existing complicated manufacturing process steps.
In addition, each via group does contraposition reference with alignment mark separately more respectively and carries out contraposition. And in the mode of two stage patternings, do contraposition reference with corresponding alignment mark respectively and form two wire connected to one another groups, and two wire groups all have end points connection pad, make two-end-point connection pad only need to partially overlap, can reach effect of the two wire groups that electrically conduct, the bit errors tolerance of via and wire is improved. Therefore, the present invention has not only simplified the production process of the multilayer circuit board structure with embedded element, has more increased the contraposition precision of via and wire group, with and manufacture craft yield.
Although disclosed the present invention in conjunction with above embodiment; but it is not in order to limit the present invention; under any, in technical field, be familiar with this operator; without departing from the spirit and scope of the present invention; can do a little change and retouching, thus protection scope of the present invention should with enclose claim was defined is as the criterion.
Claims (20)
1. a manufacture method with the multilayer circuit board structure of embedded element, comprising:
One substrate is provided, and this substrate has first surface and is positioned at least one first pair on this first surfacePosition mark;
At least one semiconductor element is set on this substrate;
Form one first dielectric layer on this substrate, wherein this first dielectric layer cover this semiconductor element andThere is a second surface and be positioned at least one second alignment mark of this second surface, respectively this second register guideThe position correspondence of note respectively this semiconductor element arranges;
Do contraposition reference with this first alignment mark and form at least one the first via group, this first conductingHole group comprises multiple the first vias, and respectively this first via extends to this first table by this second surfaceFace;
Do contraposition reference with this second alignment mark and form at least one the second via group, this second conductingHole group comprises multiple the second vias, and respectively this second via extends to this semiconductor by this second surfaceOne upper surface of element;
Form a wire group on this second surface; And
This wire group of two stage patternings is to form respectively one first wire group connected to one another and oneThe second wire group.
2. the manufacture method of the multilayer circuit board structure with embedded element as claimed in claim 1, itsIn this first surface of this substrate there are multiple the first connection pads, those first vias connect corresponding thoseThe first connection pad.
3. the manufacture method of the multilayer circuit board structure with embedded element as claimed in claim 1, itsIn this upper surface of this semiconductor element there are multiple the second connection pads, those second vias connect correspondingThose second connection pads.
4. the manufacture method of the multilayer circuit board structure with embedded element as claimed in claim 1, itsIn respectively this first via height etc. or be not equal to the respectively height of this second via.
5. the manufacture method of the multilayer circuit board structure with embedded element as claimed in claim 1, itsIn this wire group of two stage patternings to form respectively this first wire group connected to one another and thisThe step of two wire groups comprises:
Do contraposition reference this wire group that exposes with this first alignment mark, to form one first exposure wirePattern, this first exposure wire pattern one end connect those the first vias at least one of them;
Do contraposition reference with this second alignment mark and expose this wire group to form one second exposure wirePattern, this second exposure wire pattern one end connect those the second vias at least one of them, andThis first and second exposure wire pattern is connected to each other; And
Develop this first and second exposure wire pattern to form this first wire group and this second wireGroup.
6. the manufacture method of the multilayer circuit board structure with embedded element as claimed in claim 1, itsIn this first wire group comprise at least one the first end points connection pad and at least one the first wire, this first wireConnect this first end points connection pad and those the first vias at least one of them, this second wire group bagDraw together at least one the second end points connection pad and at least one the second wire, this second wire connects this second end points connection padAnd those the second vias at least one of them, wherein this first end points connection pad and this second end points connection padOverlap at least partly.
7. the manufacture method of the multilayer circuit board structure with embedded element as claimed in claim 1, itsIn this at least one semiconductor element comprise active component, passive element, chip size packages element (ChipScalePackage, CSP), circuit board or its any combination.
8. the manufacture method of the multilayer circuit board structure with embedded element as claimed in claim 1, itsIn the mode of this first via group of this formation and this second via group comprise laser drill.
9. the manufacture method of the multilayer circuit board structure with embedded element as claimed in claim 1, itsIn the quantity of this at least one semiconductor element and corresponding this at least one the second alignment mark be all multiple, shouldA little semiconductor elements comprise the first semiconductor element and the second semiconductor element, this first semiconductor elementHighly wait or be not equal to the height of this second semiconductor element.
10. the manufacture method of the multilayer circuit board structure with embedded element as claimed in claim 9,Some of those second vias are extended to the upper table of this first semiconductor element by this second surfaceFace, those second vias of part are extended to the upper table of this second semiconductor element by this second surfaceFace.
The manufacture method of 11. multilayer circuit board structures with embedded element as claimed in claim 9,The step of this at least one semiconductor element on this substrate is wherein set to be comprised:
Electrically this first semiconductor element of configuration is on this first surface of this substrate;
Form one second dielectric layer on this first surface, and this second dielectric layer coated at least partly thisSemiconductor element; And
Electrically this second semiconductor element of configuration is on this second dielectric layer.
12. 1 kinds have the multilayer circuit board structure of embedded element, comprising:
Substrate, has first surface and is positioned at least one the first alignment mark on this first surface;
At least one semiconductor element, is arranged on this substrate;
The first dielectric layer, is arranged on this substrate and covers this semiconductor element, and this first dielectric layer hasOne second surface and be positioned at least one second alignment mark of this second surface, respectively this second alignment markPosition correspondence respectively this semiconductor element arranges;
At least one the first via group, its position is to should the first alignment mark setting, this first conductingHole group comprises multiple the first vias, and respectively this first via extends to this first table by this second surfaceFace;
At least one the second via group, its position is to should the second alignment mark setting, this second conductingHole group comprises multiple the second vias, and respectively this second via extends to this semiconductor by this second surfaceOne upper surface of element;
Wire group, connects at least one of them and those second vias of those the first vias extremelyLack one of them.
13. multilayer circuit board structure with embedded element as claimed in claim 12, wherein these substratesThis first surface there are multiple the first connection pads, those first vias connect corresponding those first and connectPad.
14. multilayer circuit board structures with embedded element as claimed in claim 12, wherein this is partly ledThis upper surface of body member has multiple the second connection pads, and those second vias connect corresponding those secondConnection pad.
15. multilayer circuit board structures with embedded element as claimed in claim 12, wherein respectively thisHeight of one via etc. or be not equal to the respectively height of this second via.
16. multilayer circuit board structure with embedded element as claimed in claim 12, wherein these wiresGroup comprises the first wire group and the second wire group, and this first wire group comprises at least one first endPoint connection pad and at least one the first wire, this first wire connects this first end points connection pad and those the first conductingsHole at least one of them, this second wire group comprises at least one the second end points connection pad and at least one secondWire, this second wire connect this second end points connection pad and those the second vias at least one of them,Wherein this first end points connection pad overlaps at least partly with this second end points connection pad.
17. multilayer circuit board structures with embedded element as claimed in claim 12, wherein this is at leastSemiconductor element comprises active component, passive element, chip size packages element (ChipScalePackage, CSP), circuit board or its any combination.
18. multilayer circuit board structures with embedded element as claimed in claim 12, wherein this is at leastThe quantity of this at least one the second alignment mark of semiconductor element and correspondence is all multiple, those semiconductorsElement comprises the first semiconductor element and the second semiconductor element, the height of this first semiconductor element etc. orBe not equal to the height of this second semiconductor element.
19. multilayer circuit board structures with embedded element as claimed in claim 18, some ofThose second vias are extended to the upper surface of this first semiconductor element by this second surface, this of partA little the second vias are extended to the upper surface of this second semiconductor element by this second surface.
20. multilayer circuit board structures with embedded element as claimed in claim 18, also comprise secondDielectric layer, is arranged on this first surface, and this first semiconductor element is arranged on this first surface, andCoated this first semiconductor element at least partly of this second dielectric layer, this second semiconductor element is arranged at thisOn the second dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210242976.0A CN103547088B (en) | 2012-07-13 | 2012-07-13 | There is multilayer circuit board structure and the manufacture method of embedded element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210242976.0A CN103547088B (en) | 2012-07-13 | 2012-07-13 | There is multilayer circuit board structure and the manufacture method of embedded element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103547088A CN103547088A (en) | 2014-01-29 |
| CN103547088B true CN103547088B (en) | 2016-05-18 |
Family
ID=49970023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210242976.0A Active CN103547088B (en) | 2012-07-13 | 2012-07-13 | There is multilayer circuit board structure and the manufacture method of embedded element |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103547088B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106793555B (en) * | 2015-11-23 | 2019-02-12 | 健鼎（无锡）电子有限公司 | Circuit board package structure and its manufacturing method |
| CN111885828A (en) * | 2020-06-16 | 2020-11-03 | 惠州美锐电子科技有限公司 | Method for manufacturing PCB circuit with through holes and blind holes |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101339893A (en) * | 2007-07-03 | 2009-01-07 | 台湾积体电路制造股份有限公司 | Method for judging wafer thinning, device structure and device and its manufacture method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6898846B2 (en) * | 2002-08-21 | 2005-05-31 | Potomac Photonics, Inc. | Method and components for manufacturing multi-layer modular electrical circuits |
-
2012
- 2012-07-13 CN CN201210242976.0A patent/CN103547088B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101339893A (en) * | 2007-07-03 | 2009-01-07 | 台湾积体电路制造股份有限公司 | Method for judging wafer thinning, device structure and device and its manufacture method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103547088A (en) | 2014-01-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8456018B2 (en) | Semiconductor packages | |
| CN103258807B (en) | Circuit substrate, semiconductor packaging structure and circuit substrate manufacturing process | |
| US8064215B2 (en) | Semiconductor chip package and printed circuit board | |
| CN104347536B (en) | Wafer encapsulation body and its manufacturing method | |
| US9583436B2 (en) | Package apparatus and manufacturing method thereof | |
| TWI612860B (en) | Electronic circuit module | |
| CN105789058A (en) | Wiring board with embedded interposer integrated with stiffener and method of making the same | |
| KR20090034081A (en) | Stack-type semiconductor package apparatus and manufacturing method the same | |
| CN104465473A (en) | Integrated Circuit Packaging System With Heat Spreader And Method Of Manufacture Thereof | |
| US20230146783A1 (en) | Die Interconnect Substrate, an Electrical Device and a Method for Forming a Die Interconnect Substrate | |
| CN103151330B (en) | Circuit substrate and circuit substrate manufacturing process | |
| US20080223612A1 (en) | Wiring substrate and manufacturing method thereof | |
| TW200612526A (en) | Chip package structure, package substrate and manufacturing method thereof | |
| CN107665876A (en) | Packaging body substrate, its manufacture method and packaging body | |
| CN103547088B (en) | There is multilayer circuit board structure and the manufacture method of embedded element | |
| CN102738064B (en) | Method for fabricating metal redistribution layer | |
| CN103545286A (en) | Circuit substrate, semiconductor packaging structure and circuit substrate manufacturing process | |
| JP2014183085A (en) | Board for multichip modules, multilayer wiring board for multichip modules, multichip module, and multichip multilayer wiring module | |
| CN105023915B (en) | Method for manufacturing stack type packaging piece | |
| CN101211792A (en) | Semi-conductor package and its manufacture method and stacking structure | |
| US8772644B2 (en) | Carrier with three-dimensional capacitor | |
| CN102655715A (en) | Flexible printed circuit board (PCB) and manufacturing method thereof | |
| CN205723510U (en) | Semiconductor device | |
| CN105097761B (en) | Chip packaging structure | |
| CN103855099A (en) | Substrate structure with component arrangement area and manufacturing technology thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |