CN207738446U

CN207738446U - A kind of encapsulating structure of MEMS chip and asic chip

Info

Publication number: CN207738446U
Application number: CN201720814617.6U
Authority: CN
Inventors: 王之奇
Original assignee: China Wafer Level CSP Co Ltd
Current assignee: China Wafer Level CSP Co Ltd
Priority date: 2017-07-06
Filing date: 2017-07-06
Publication date: 2018-08-17
Anticipated expiration: 2027-07-06

Abstract

The utility model discloses the encapsulating structure of a kind of MEMS chip and asic chip integration packaging, the encapsulating structure includes：MEMS chip, the MEMS chip have front and the back side relatively；Asic chip, the asic chip have front and the back side relatively；The front of the asic chip is bonded fixation with the back side of the MEMS chip, and the asic chip is electrically connected with the MEMS chip；The asic chip is provided with the first solder-bump away from the side of the MEMS chip, and first solder-bump with external circuit for connecting；There is cover board host cavity, the cover board to be set on the asic chip, and the MEMS chip is located in the host cavity, and the cover board is tightly connected with the asic chip.The encapsulating structure of MEMS chip and asic chip that technical solutions of the utility model provide is simple, and low manufacture cost.

Description

A kind of encapsulating structure of MEMS chip and asic chip

Technical field

The utility model is related to technical field of semiconductor device, more specifically, being related to a kind of encapsulating structure.

Background technology

MEMS (Micro-Electro-Mechanical Systems, abbreviation MEMS) be by microelectric technique with A kind of industrial technology that mechanical engineering is fused together, its opereating specification is in micron range.MEMS be it is a kind of it is completely new must The research and development field that must consider a variety of physical field immixtures simultaneously, relative to traditional machinery, they smaller is maximum No more than one centimetre, or even only several microns, thickness are just more small.Application-specific integrated circuit (Application Specific Integrated Circuit, abbreviation ASIC), it is considered as that one kind sets for special purpose in integrated circuit circle The integrated circuit of meter.The characteristics of ASIC is the demand towards specific user, ASIC in batch production with universal integrated circuit phase Than having many advantages, such as that volume smaller, power consumption are lower, reliability improves, performance improves, confidentiality enhances, cost reduction.

The generation technique similar with integrated circuit may be used in MEMS and ASIC, can largely utilize integrated circuit at Cooking technique and technique carry out the production of high-volume, low cost, generate high performance MEMS chips and asic chip.MEMS The encapsulating structure of the integral packaging of chip and asic chip opens a completely new technical field and industry, is based on the encapsulation Microsensor, microactrator, micro parts, Micromechanical Optics device, vacuum microelectronic device, the power electronics device of structure fabrication Part etc. in Aeronautics and Astronautics, automobile, biomedicine, environmental monitoring, military affairs and all spectra that almost people are touched all There is very wide application prospect.

In the prior art, the encapsulating structure of general MEMS chip and asic chip is complex, and cost of manufacture is higher. Therefore, how the encapsulating structure and envelope of the lower MEMS chip of a kind of simple in structure and cost of manufacture and asic chip are provided Dress method is one urgent problem to be solved of field of semiconductor devices.

Utility model content

To solve the above-mentioned problems, the utility model provides a kind of encapsulating structure so that MEMS chip and asic chip Encapsulating structure it is simple, and low manufacture cost.

To achieve the goals above, the utility model provides the following technical solutions：

A kind of encapsulating structure of MEMS chip and asic chip integration packaging, the encapsulating structure include：

MEMS chip, the MEMS chip have front and the back side relatively；

Asic chip, the asic chip have front and the back side relatively；The asic chip front with it is described The back side fitting of MEMS chip is fixed, and the asic chip is electrically connected with the MEMS chip；

The asic chip is provided with the first solder-bump, first solder-bump away from the side of the MEMS chip For being connect with external circuit；

There is cover board host cavity, the cover board to be set on the asic chip, and the MEMS chip is located at the receiving Intracavitary, and the cover board is tightly connected with the asic chip.

Preferably, in above-mentioned encapsulating structure, the back side of the MEMS chip has the second solder-bump, the MEMS cores There is the first weld pad, first weld pad to be electrically connected with second solder-bump in the front of piece；

The asic chip has termination power, and the termination power is for being electrically connected second solder-bump.

Preferably, in above-mentioned encapsulating structure, the MEMS chip back side has the first mistake through the MEMS chips Hole, for exposing first weld pad；The first electric connection structure, first electric connection structure are formed in first via It is electrically connected respectively with first weld pad and second solder-bump.

Preferably, in above-mentioned encapsulating structure, first electric connection structure is the first conductive plunger.

Preferably, in above-mentioned encapsulating structure, first electric connection structure includes being arranged in first via First wiring layer again.

Preferably, in above-mentioned encapsulating structure, the aperture of first via by the MEMS chip described in being directed toward It is constant on the direction of asic chip；

Or, the aperture of first via gradually increases being directed toward on the direction of the asic chip by the MEMS chip Greatly；

Or, first via includes：Groove at the MEMS chip back side is set, and the depth of groove is less than described The thickness of MEMS chip；In the groove, and through the through-hole of the MEMS chip.

Preferably, in above-mentioned encapsulating structure, the asic chip front has the second weld pad, and the back side, which has, runs through institute The second via for stating asic chip, for exposing second weld pad；The second connection structure, institute are formed in second via The second connection structure is stated to be electrically connected with second weld pad and first solder-bump respectively.

Preferably, in above-mentioned encapsulating structure, second connection structure is the second conductive plunger.

Preferably, in above-mentioned encapsulating structure, second conductive plunger is directly electrically connected with first solder-bump, Or the printed circuit by being arranged at the asic chip back side is electrically connected with first solder-bump.

Preferably, in above-mentioned encapsulating structure, second connection structure includes be arranged in second via Two wiring layers again.

Preferably, in above-mentioned encapsulating structure, the aperture of second via by the MEMS chip described in being directed toward It is constant on the direction of asic chip；

Or, the aperture of second via gradually increases being directed toward on the direction of the asic chip by the MEMS chip Greatly；

Or, second via includes：Groove at the MEMS chip back side is set, and the depth of groove is less than described The thickness of asic chip；In the groove, and through the through-hole of the asic chip.

Preferably, in above-mentioned encapsulating structure, perpendicular to the direction of the MEMS chip and the ASIC chips On, the MEMS chip is less than the asic chip.

Preferably, in above-mentioned encapsulating structure, reduction processing, and the asic chip are passed through in the back side for stating asic chip The back side after reduction processing is provided with enhancement layer.

By foregoing description it is found that in encapsulating structure and chip packaging method that technical solutions of the utility model provide, MEMS chip is connect in first solder-bump of the asic chip away from MEMS chip side with external circuit by being arranged, and is passed through Protection is sealed to MEMS chip with cover board, the encapsulating structure of MEMS chip and asic chip is simple, and low manufacture cost.

Description of the drawings

In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only It is the embodiments of the present invention, for those of ordinary skill in the art, without creative efforts, also Other attached drawings can be obtained according to the attached drawing of offer.

Fig. 1 is the structural representation of the encapsulating structure of a kind of MEMS chip that the utility model embodiment provides and asic chip Figure；

Fig. 2 is a kind of structural schematic diagram for MEMS chip that the utility model embodiment provides；

Fig. 3 is the structural schematic diagram for another MEMS chip that the utility model embodiment provides；

Fig. 4 is the structural schematic diagram for another MEMS chip that the utility model embodiment provides；

Fig. 5 is the structural schematic diagram for another MEMS chip that the utility model embodiment provides；

Fig. 6 is a kind of flow diagram for chip packaging method that the utility model embodiment provides；

Fig. 7-Figure 16 is a kind of principle schematic for chip packaging method that the utility model embodiment provides；

Figure 17 is the flow diagram for another chip packaging method that the utility model embodiment provides.

Specific implementation mode

The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work The every other embodiment obtained, shall fall within the protection scope of the present invention.

To keep the above objects, features, and advantages of the utility model more obvious and easy to understand, below in conjunction with the accompanying drawings and have Body embodiment is described in further detail the utility model.

With reference to figure 1, Fig. 1 is the encapsulating structure of a kind of MEMS chip and asic chip that the utility model embodiment provides Structural schematic diagram, the encapsulating structure include MEMS chip 11, asic chip 12 and cover board 14.The MEMS chip 11 has There are front and the back side relatively.The asic chip 12 has front and the back side relatively.The asic chip 12 front with The back side fitting of the MEMS chip 11 is fixed, and the asic chip 12 is electrically connected with the MEMS chip 11.The ASIC Chip 12 is provided with the first solder-bump 13 away from the side of the MEMS chip 11, first solder-bump 13 be used for it is outer Portion's circuit connection.The cover board 14 has host cavity 19, and the cover board 14 is set on the asic chip 12, and the cover board 14 are tightly connected with the asic chip 12, and the cover board 14 is for being sealed the MEMS chip 11.

In encapsulating structure described in the utility model embodiment, the MEMS chip 11 is by being arranged in the asic chip 12 connect away from the first solder-bumps 13 of 11 side of MEMS chip with external circuit, and by with cover board 14 to MEMS chip 11 It is sealed protection, MEMS chip 11 and the encapsulating structure of asic chip 12 are simple, and low manufacture cost.

Optionally, first solder-bump 13 can be pad or tin ball.In Fig. 1 illustrated embodiments, described One solder-bump 13 is tin ball.The MEMS chip 11 can be deviated from the ASIC chips 12 by TSV (silicon hole) techniques Side form first solder-bump 13.

As shown in Figure 1, being electrically connected for the ease of the MEMS chip 11 and the asic chip 12, the MEMS chip 11 back side has the second solder-bump 15；The asic chip 12 has termination power, and the termination power is for being electrically connected Second solder-bump 15.

It again may be by TSV techniques and form described towards the side of the asic chip 12 in the MEMS chip 11 Two solder-bumps 15.

Optionally, the front of the MEMS chip 11 has the first weld pad；First weld pad and second welding are convex Play 15 electrical connections.The weld pad is not shown in Fig. 1.

In order to enable first weld pad is electrically connected with second solder-bump 15, it can be in the MEMS chip 11 The back side setting through the MEMS chip 11 the first via, for expose the first weld pad, be arranged in first via First electric connection structure is electrically connected first weld pad and second solder-bump 15.First electric connection structure can be setting The first conductive plunger in first via or the first wiring layer again

Specifically, the aperture of first via is being directed toward by the MEMS chip 11 on the direction of the asic chip 12 It is constant.First via is straight hole at this time for definition.First via can be circular hole, square hole or tri-angle-holed etc..

Or, the aperture of first via by the MEMS chip 11 be directed toward on the direction of the asic chip 12 by It is cumulative big.First via is trapezoidal via at this time for definition.The trapezoidal hole can be truncation centrum or terrace with edge.

Or, first via includes：Groove at 11 back side of the MEMS chip is set, and the depth of groove is less than institute State the thickness of MEMS chip 11；In the groove, and through the through-hole of the MEMS chip 11.Define described at this time the One via is bilayer step hole.

With reference to figure 2, Fig. 2 is a kind of structural schematic diagram for MEMS chip that the utility model embodiment provides, shown in Fig. 2 In MEMS chip 11, the MEMS chip 11 has the first via 20 through the MEMS chips 11.First via 20 It is inside provided with the first conductive plunger 22, first conductive plunger 22 is for being electrically connected second solder-bump 15 and first Weld pad 21.There is insulating layer 23 between first conductive plunger 22 and the MEMS chip 11.The MEMS chip 11 deviates from There is solder mask 24, the position that solder mask 24 corresponds to the first conductive plunger 22 to have opening, use for one side surface of the first weld pad 21 In the second solder-bump 15 of setting.At this point, second solder-bump 15 passes through first conductive plunger 22 and the weld pad 21 electrical connections, and then realize and be electrically connected with the 21 of first weld pad.Wherein, the first weld pad 21 can be with first conduction Plug 22 is directly electrically connected, or by being arranged in 11 positive printed wire of the MEMS chip and first conductive plunger 22 connections.Second solder-bump 15 can be directly electrically connected with first conductive plunger 22, or by being arranged in institute The printed wire for stating 11 back side of MEMS chip is connect with first conductive plunger 22.

11 front of the MEMS chip has multiple first weld pads 21.The optional weld pad can be divided into the setting of two row and exist The positive opposite two sides of the MEMS chip 11.In the exemplary embodiment illustrated in fig. 2, the aperture of first via 20 by The MEMS chip 11 is directed toward constant on the direction of the asic chip 12, as straight hole.When using 22 electricity of the first conductive plunger When connecting the first weld pad 21 and the second solder-bump 15, the first via 20 can also be above-mentioned trapezoidal hole or bilayer step Hole needs to set matched first conductive plunger 22 according to the shape of the first via 20 at this time.

With reference to figure 3, Fig. 3 is the structural schematic diagram for another MEMS chip that the utility model embodiment provides, described MEMS chip 11 has the first via 20 through the MEMS chip 11.MEMS chip 11 shown in Fig. 3 and MEMS shown in Fig. 2 11 difference of chip is that the first via 20 described in Fig. 3 is bilayer step hole.The bilayer step hole includes not running through described The groove K1 of the MEMS chip 11 and through-hole K2 for running through the MEMS chip 11 on the basis of the groove K1.

When in weld pad multiple first weld pads 21 be divided to for two row setting when, the MEMS chip 11 the back side setting with two row First weld pad 21 opposite two groove K1 respectively are arranged multiple with 21 one-to-one through-hole of the first weld pad in groove K1 K2, for exposing the first weld pad 21.It is provided with the first wiring layer 31 again in first via 20, the described first wiring layer 31 again For being electrically connected first weld pad 21 and second solder-bump 15, specifically, second solder-bump 15 passes through Described first again wiring layer 31 be electrically connected with the first weld pad 21.

With reference to figure 4, Fig. 4 is the structural schematic diagram for another MEMS chip that the utility model embodiment provides, shown in Fig. 4 In MEMS chip 11, the MEMS chip 11 has the first via 20 through the MEMS chips 11.Embodiment party shown in Fig. 4 Embodiment difference is formula as shown in figure 3, and first via 20 is straight hole.Equally, in Fig. 4 weld pad by be arranged first In via 20 first again wiring layer 31 be electrically connected first weld pad 21 and second solder-bump 15.

With reference to figure 5, Fig. 5 is the structural schematic diagram for another MEMS chip that the utility model embodiment provides, shown in Fig. 5 In MEMS chip 11, the MEMS chip 11 has the first via 20 through the MEMS chips 11.Embodiment party shown in Fig. 5 Embodiment difference is formula as shown in figure 3, and first via 20 is trapezoidal hole.Equally, Fig. 5 embodiments are existed by setting In first via 20 first again wiring layer 31 be electrically connected the first weld pad 21 and second solder-bump 15.

As shown in Figure 1, in the encapsulating structure described in the utility model embodiment, the back side of the asic chip 12 has Through the second via 18 of the asic chip 12, in order to make the second solder-bump 15 and the first solder-bump 13 be electrically connected It connects.Specifically, the front of the asic chip 12 has the second weld pad 17, the first solder-bump 13 is by being arranged described second The second connection structure in via 18 is electrically connected with the weld pad 17, and then is realized and be electrically connected with second solder-bump 15. Second connection structure is electrically connected with second weld pad 17 and first solder-bump 13 respectively.Second connection structure It is the second conductive plunger being arranged in second via 18 or the second wiring layer again.

Second via 18 is identical with the realization method of above-mentioned first via 20.Equally, second via 18 can be with It is straight hole trapezoidal hole or bilayer step hole.

When second via 18 is straight hole, the aperture of second via 18 is directed toward by the MEMS chips 11 It is constant on the direction of the asic chip 12.

When second via 18 is trapezoidal hole, the aperture of second via 18 refers to by the MEMS chips 11 Gradually increase on the direction of the asic chip 12.

When second via 18 is bilayer step hole, second via 18 includes：It is arranged in the asic chip The groove Q1 at 12 back sides, the groove Q1 depth are less than the thickness of the asic chip 12；In the groove Q1, and run through The through-hole Q2 of the asic chip 12.

In Fig. 1 illustrated embodiments, the asic chip 12 is provided through the second via of the asic chip 12 18.Be provided with the described second wiring layer 111 again in second via 18, described second again wiring layer 111 for being electrically connected institute State the second weld pad 17 and first solder-bump 13.At this point, the institute of the backside structure of the asic chip 12 as shown in figure 3 The backside structure for stating MEMS chip 11 is identical, and insulation is equipped between wiring layer 111 and the asic chip 12 again described second Layer 112, described second again 111 surface of wiring layer be covered with solder mask 113, the first solder-bump 13 is by being located at solder mask 113 opening with described second again wiring layer 111 be electrically connected, and then connect with weld pad 17, pass through the second weld pad 17 and second and weld Protrusion 15 is connect to be electrically connected.The back side of the asic chip 12 is the side that the asic chip 12 deviates from the MEMS chip 11 Surface.The back side of the MEMS chip 11 is the MEMS chip 11 towards the side surface for stating asic chip 12.

In Fig. 1 illustrated embodiments, second via 18 is bilayer step hole, has and does not run through the asic chip The 12 groove Q1 and through-hole Q2 for running through the asic chip 12 on the basis of groove Q1.

In other embodiments, the second conductive plunger of setting connection 17 He of weld pad in the second through-hole 18 can also be passed through First solder-bump 13, so that the first solder-bump 13 and the electrical connection of the second solder-bump 15.

Second conductive plunger is by being arranged printed circuit and first welding at 12 back side of the asic chip Protrusion 13 is electrically connected.Or second conductive plunger can also be directly electrically connected with first solder-bump 13.At this point, institute The backside structure for stating asic chip 12 is identical as the backside structure of the MEMS chips 11 shown in Fig. 2, and no longer diagram is said herein It is bright.When being provided with the second conductive plunger in second via 18, the second via can also be trapezoidal hole or double layers table The second conductive plunger of different shapes is arranged in rank hole, the second via 18 of different shapes.

In other embodiments, when second via 18 is straight hole, first solder-bump 13 can pass through Be arranged second in second via 18 again wiring layer be electrically connected with the weld pad 17, and then with the electricity of the second solder-bump 15 Connection.At this point, the backside structure of the asic chip 12 is identical as the backside structure of the MEMS chip 11 shown in Fig. 4, This is no longer illustrated.

In other embodiments, second via 18 can also be trapezoidal hole；The setting of second via 18 is State the second wiring layer again, described second again wiring layer for being electrically connected second solder-bump 15 and first welding Protrusion 13, specific first solder-bump 13 by second again wiring layer be electrically connected with second weld pad 17, and then with second Solder-bump 15 is electrically connected.At this point, the back side knot of MEMS chip 11 shown in the backside structure and Fig. 5 of the ASIC chips 12 Structure is identical, no longer illustrates herein.

In the encapsulating structure described in the utility model embodiment, perpendicular to the MEMS chip 11 and the ASIC cores On the direction of piece 12, the MEMS chip 11 is less than the asic chip 12, that is to say, that the MEMS chip 11 is described Upright projection on asic chip 12 is fully located in the asic chip 12.In this way, the size of MEMS chip 11 is reduced, it can Its integrated level is improved, cost of manufacture is reduced.

In the encapsulating structure described in the utility model embodiment, the cover board 14 has towards the side of the MEMS chip 11 There are host cavity 19, the MEMS chip 11 to be located in the host cavity 19.The host cavity 19 is the host cavity of vacuumize process, Alternatively, being filled with fluid sealant in the host cavity 19.When the host cavity 19 is the host cavity of vacuumize process, the receiving The inner wall of chamber 19 is provided with drier, to increase service life.The drier is not shown in Fig. 1.In order to ensure the MEMS The stability of chip 11 and the asic chip 12 also has insulation between the MEMS chip 11 and the asic chip 12 Glue-line.Insulated glue-line is not shown in Fig. 1.Optionally, the cover board 14 be PCB substrate or glass substrate or metal substrate or Semiconductor substrate or polymer flexibility substrate.

When the prior art is packaged chip, the encapsulating structure of lower thickness, needs to subtract chip in order to obtain Thin processing, specifically, reduction processing can be carried out to chip by modes such as mechanical lapping or chemical etchings.But pass through The mechanical strength of chip after reduction processing is weaker.

In the utility model embodiment, in order to ensure the thinner thickness of encapsulating structure and mechanical strength is larger simultaneously, setting Reduction processing is passed through at 12 back side of the asic chip, and the back side of the asic chip 12 after reduction processing is provided with reinforcement Layer.The mechanical strength of the enhancement layer is more than the mechanical strength of the asic chip 12.In this way, can be right in the prior art The asic chip 12 carries out reduction processing by a larger margin, and deviates from the MEMS cores in the asic chip 12 by setting The enhancement layer of the side of piece 11 increases mechanical strength, ensures encapsulation knot while 12 thickness of asic chip is greatly lowered Structure has preferable mechanical strength.

That is, encapsulating structure described in the utility model embodiment, compared with the existing technology in encapsulating structure, can be with Further increasing reduction processing reduces the thickness of the asic chip 12 so that the ASIC chips 12 it is thinner, pass through Mechanical strength after the better enhancement layer compensation reduction processing of mechanical strength, may be implemented the lightening of encapsulating structure.Optionally, The enhancement layer can be capsulation material.The enhancement layer has opening, for first solder-bump 13 to be arranged, in order to First solder-bump 13 is electrically connected with the termination power.

Similarly, in order to further decrease the thickness of encapsulating structure, while ensureing its mechanical strength, the MEMS chip is set Reduction processing is passed through at 11 back side, and the back side of the MEMS chip 11 after reduction processing is provided with enhancement layer.It is described to add The mechanical strength of strong layer is more than the mechanical strength of the MEMS chip 11.

In encapsulating structure described in the utility model embodiment, the MEMS chip 11 is by being arranged in the asic chip 12 The first solder-bump 13 away from 11 side of the MEMS chip is connect with external circuit, and by with cover board 14 to MEMS chip 11 are sealed protection, and MEMS chip 11 and the encapsulating structure of asic chip 12 are simple, and low manufacture cost.

Moreover, in encapsulating structure described in the utility model embodiment, the MEMS chip 11 by TSV techniques overleaf The second solder-bump 15 is formed, the asic chip 12 overleaf forms the first solder-bump 13, the MEMS by TSV techniques Chip 11 directly opposite can be welded to be that reality is electrically coupled with the asic chip 12, without structures such as welding leads, be reduced The size of the MEMS chip 11 and the asic chip 12, improves integrated level.

Based on above-mentioned encapsulating structure embodiment, another embodiment of the utility model additionally provides a kind of chip packaging method, It is used to prepare above-mentioned encapsulating structure, the packaging method is as shown in Figure 6.

With reference to figure 6, Fig. 6 is a kind of flow diagram for chip packaging method that the utility model embodiment provides, described Chip packaging method includes：

Step S11：Shown in as shown in Figure 7 and Figure 8, a wafer 40 is provided, Fig. 7 is the vertical view of wafer 40, and Fig. 8 is figure 7 the directions AA ' sectional drawing.

The wafer 40 includes the asic chip 12 of multiple array arrangements, has between two neighboring asic chip 12 and cuts Cut raceway groove 41；The asic chip 12 has front and the back side.The front of the asic chip 12 has the second weld pad 17.

Step S12：As shown in figure 9, a MEMS chips 11 are fixed in fitting in the front of the asic chip 12.

The MEMS chip 11 has front and the back side relatively.Front and the MEMS chip of the asic chip 12 11 back side fitting is fixed, and the asic chip 12 is electrically connected with the MEMS chips 11.11 back side of the MEMS chip has There are the second solder-bump 15, second solder-bump 15 to be electrically connected with second weld pad 17.The MEMS chip 11 is passed through TSV techniques overleaf form second solder-bump 15.

Step S13：As shown in Figure 10, it is arranged and is bonded fixed substrate 51 with the wafer 40.

There is in the region opposite with each MEMS chip 11 of substrate 51 host cavity 19, the MEMS chips 11 to be located at In the host cavity 19.

Step S14：As shown in Figure 11-Figure 16, the first solder-bump 13, institute are respectively formed at the back side of the asic chip 12 The first solder-bump 13 is stated for being connect with external circuit.

First, as shown in figure 11, the asic chip is inverted, the wafer 40 is the protection of bottom with the substrate 51 Substrate carries out subsequent TSV techniques, is not necessarily to individual protective substrate.

Then, as shown in figure 12, the second via 18 through the asic chip 12 is formed.Formed the second via 18 it Before, can reduction processing first be carried out to the back side of the wafer 40.Enhancement layer can be arranged by subsequent technique in the utility model Method so as to wafer 40 carry out reduction processing when, largely wafer 40 is thinned, reduce wafer 40 Ensure the mechanical strength of wafer 40 while thickness.It is illustrated so that the second via 18 is double step via as an example, first choice is formed Do not run through the groove Q1 of ASIC chips, the through-hole Q2 through asic chip is then formed on the basis of groove Q1, described in exposing Second weld pad 17 of the asic chip other side.

Further, as shown in figure 13, the insulating layer 112 at 40 back side of covering institute wafer is formed, the covering of insulating layer 112 the The side wall of two vias 18, and there is opening in the bottom of the second via 18, to expose weld pad 17.

Further, as shown in the figure 14, form the second wiring layer 111 again on 112 surface of the insulating layer.Second connects up again Layer 111 covers the bottom of the second via 18, and extends to the outside of the second via 18.

Further, as shown in figure 15, described second again wiring layer 111 surface formed solder mask 113.Solder mask 113 surfaces have opening.

Finally, as shown in figure 16, first solder-bump 13 is set in the opening of solder mask 113.

Step S15：It is cut along the cutting raceway groove 41, forms multiple encapsulating structures.

Wherein, after cutting, the encapsulating structure of formation is as shown in Figure 1, the substrate 51 divides for multiple cover boards 14.Each institute Stating encapsulating structure tool, there are one the cover boards 14.In the encapsulating structure, the periphery of the cover board 14 and the asic chip 12 periphery fitting is fixed, and the cover board 14 is for being sealed the MEMS chip 11.

In Figure 16 illustrated embodiments, the first solder-bump 13 passes through positioned at the second mistake through the asic chip 12 In hole 18 second again wiring layer 111 connect with second weld pad 17, and then connect with the second solder-bump 15.At this point, institute The fitting in the front of the asic chip 12 is stated to fix a MEMS chip 11 and include：11 back side of the MEMS chip has the Two solder-bumps 15, and the asic chip 12 has termination power；It is electrically connected second welding by the termination power Protrusion 15 and first solder-bump 13.The termination power includes above-mentioned second electric connection structure.Specifically, described There is the first weld pad, the back side to have the second solder-bump 15 being electrically connected with first weld pad in MEMS chip 11 front；Institute Stating 11 front of asic chip has the second weld pad 17 being electrically connected with first solder-bump 13；By welding second weldering Protrusion 15 and second weld pad 17 are connect, a MEMS chip 11 is fixed in the front fitting of the asic chip 12.

For Figure 16 illustrated embodiments, the termination power includes the described second wiring layer 111 again.At this point, it is described The back side of the asic chip 12 is respectively formed the first solder-bump 13：It is formed at 12 back side of the asic chip and runs through institute The second via 18 for stating asic chip 12, to expose its positive second weld pad 17；Second is formed in second via 18 Electric connection structure；First welding that formation is electrically connected with second electric connection structure at 11 back side of the asic chip is convex Play 13.

In Figure 16 illustrated embodiments, second via 18 is bilayer step hole.Second electric connection structure includes Described second be arranged in second via 18 wiring layer 111 again.By described second again wiring layer 111 be electrically connected it is described Second weld pad 17 and first solder-bump 13.

In other embodiments, described to be respectively formed the first solder-bump 13 at the back side of the asic chip 12 and include： It is provided with the second conductive plunger electrical connection second weld pad 17 and described first by being arranged in second via 18 Solder-bump 13.

As above-mentioned, second via 18 can be straight hole or trapezoidal hole or bilayer step hole.

As above-mentioned, in order to prepare the preferable encapsulating structure of thinner and mechanical strength, said chip packaging method is also wrapped It includes：Reduction processing is carried out away from the surface of 11 side of the MEMS chip to the wafer 40.After carrying out reduction processing, also Including：In the wafer 40 enhancement layer is formed away from the side of the MEMS chip 11.Can prepare it is described first welding it is convex The enhancement layer is formed before playing 13.Enhancement layer is in asic chip 12 away from the specific level position of the side of the MEMS chip 11 It sets and does not limit, the relative position of itself and other hierarchical structures at 12 back side of asic chip can be set according to demand.

Said chip packaging method forms the MEMS chip 11 and the asic chip 12 using wafer-level packaging technique Encapsulating structure, simple process and low cost, and the thinner thickness of encapsulating structure, mechanical strength is preferable, and integrated level is higher.

Another kind is additionally provided based on above-mentioned encapsulating structure and chip packaging method embodiment, the utility model embodiment Chip packaging method, the chip packaging method is as shown in figure 17, and Figure 17 is another core that the utility model embodiment provides The flow diagram of piece packaging method, the chip packaging method are used to prepare above-mentioned encapsulating structure, the chip packaging method Including：

Step S21：A wafer is provided, the wafer includes the asic chip of multiple array arrangements, two neighboring ASIC cores There is cutting raceway groove between piece；The asic chip has front and the back side.

Step S22：In the front of the asic chip, a MEMS chip is fixed in fitting.

The MEMS chip has front and the back side relatively.The front of the asic chip and the MEMS chip Back side fitting is fixed, and the asic chip is electrically connected with the MEMS chip.

Step S23：One cover board is set away from the side of the asic chip in the MEMS chip.

The periphery of the cover board is bonded fixation with the periphery of the asic chip, and the cover board is used for the MEMS cores Piece is sealed.

Step S24：Be respectively formed the first solder-bump at the back side of the asic chip, first solder-bump be used for External circuit connects.

Step S25：It is cut along the cutting raceway groove, forms multiple encapsulating structures.

Chip packaging method shown in Figure 17 is with chip packaging method difference shown in Fig. 6, is directly each MEMS chip The fixed cover board being separately separated of fitting.

Equally, in the chip packaging method shown in Figure 17, the fitting in the front of the asic chip fixes one MEMS chip includes：The back side of the MEMS chip has the second solder-bump, and the asic chip has termination power；It is logical It crosses the termination power and is electrically connected second solder-bump and first solder-bump.

Equally, described to be respectively formed the first welding at the back side of the asic chip in the chip packaging method shown in Figure 17 Protrusion includes：The asic chip has the second via through the asic chip；By being arranged in second via It is provided with the second conductive plunger and is electrically connected second solder-bump and first solder-bump.

Equally, described to be respectively formed the first welding at the back side of the asic chip in the chip packaging method shown in Figure 17 Protrusion includes：The asic chip back side formed through the asic chip the second via, with expose its positive second Weld pad 17；The second electric connection structure is formed in second via 18；It is formed and described the at 11 back side of the asic chip First solder-bump 13 of two electric connection structures electrical connection.

Equally, second via is straight hole, bilayer step hole or trapezoidal hole.

Equally, in the chip packaging method shown in Figure 17, further include：The MEMS chip-sides are deviated to the wafer Surface carry out reduction processing.In the chip packaging method shown in Figure 17, further include：Deviate from the MEMS chip in the wafer Side formed enhancement layer.

Equally, the chip packaging method forms the MEMS chip and the asic chip using wafer-level packaging technique Encapsulating structure, simple process and low cost, and the thinner thickness of encapsulating structure, mechanical strength is preferable, and integrated level is higher.

It should be noted that each embodiment is described by the way of progressive in this specification, each embodiment emphasis is said Bright is all difference from other examples, and just to refer each other for identical similar portion between each embodiment.For reality For applying chip packaging method disclosed in example, since it is corresponding with encapsulating structure disclosed in embodiment, so the comparison of description is simple Single, related place illustrates referring to encapsulating structure corresponding part.

The foregoing description of the disclosed embodiments enables professional and technical personnel in the field to realize or use this practicality new Type.Various modifications to these embodiments will be apparent to those skilled in the art, and determine herein The General Principle of justice can be realized in other embodiments without departing from the spirit or scope of the present utility model.Cause This, the utility model is not intended to be limited to the embodiments shown herein, and is to fit to and principles disclosed herein The widest range consistent with features of novelty.

Claims

1. the encapsulating structure of a kind of MEMS chip and asic chip, which is characterized in that including：

MEMS chip, the MEMS chip have front and the back side relatively；

Asic chip, the asic chip have front and the back side relatively；Front and the MEMS cores of the asic chip The back side fitting of piece is fixed, and the asic chip is electrically connected with the MEMS chip；

The asic chip is provided with the first solder-bump away from the side of the MEMS chip, and first solder-bump is used for It is connect with external circuit；

There is cover board host cavity, the cover board to be set on the asic chip, and the MEMS chip is located at the host cavity It is interior, and the cover board is tightly connected with the asic chip.

2. encapsulating structure according to claim 1, which is characterized in that the back side of the MEMS chip has the second welding convex It rises, there is the first weld pad, first weld pad to be electrically connected with second solder-bump in the front of the MEMS chip；

3. encapsulating structure according to claim 2, which is characterized in that the MEMS chip back side, which has, runs through the MEMS First via of chip, for exposing first weld pad；It is formed with the first electric connection structure in first via, described One electric connection structure is electrically connected with first weld pad and second solder-bump respectively.

4. encapsulating structure according to claim 3, which is characterized in that first electric connection structure is first conductive slotting Plug.

5. encapsulating structure according to claim 3, which is characterized in that first electric connection structure includes being arranged described The first wiring layer again in first via.

6. encapsulating structure according to claim 3, which is characterized in that the aperture of first via is by the MEMS cores Piece is directed toward constant on the direction of the asic chip；

Or, the aperture of first via gradually increases being directed toward on the direction of the asic chip by the MEMS chip；

Or, first via includes：Groove at the MEMS chip back side is set, and the depth of groove is less than the MEMS The thickness of chip；In the groove, and through the through-hole of the MEMS chip.

7. encapsulating structure according to claim 1, which is characterized in that the asic chip front has the second weld pad, The back side has the second via through the asic chip, for exposing second weld pad；It is formed in second via Second connection structure, second connection structure are electrically connected with second weld pad and first solder-bump respectively.

8. encapsulating structure according to claim 7, which is characterized in that second connection structure is the second conductive plunger.

9. encapsulating structure according to claim 8, which is characterized in that second conductive plunger is directly welded with described first Connect raised electrical connection, or the printed circuit by being arranged at the asic chip back side is electrically connected with first solder-bump It connects.

10. encapsulating structure according to claim 7, which is characterized in that second connection structure includes being arranged described The second wiring layer again in second via.

11. encapsulating structure according to claim 7, which is characterized in that the aperture of second via is by the MEMS Chip is directed toward constant on the direction of the asic chip；

Or, the aperture of second via gradually increases being directed toward on the direction of the asic chip by the MEMS chip；

Or, second via includes：Groove at the MEMS chip back side is set, and the depth of groove is less than the ASIC The thickness of chip；In the groove, and through the through-hole of the asic chip.

12. encapsulating structure according to claim 1, which is characterized in that perpendicular to the MEMS chip and described On the direction of asic chip, the MEMS chip is less than the asic chip.

13. according to claim 1-12 any one of them encapsulating structures, which is characterized in that the back side of the asic chip is passed through Reduction processing, and the back side of the asic chip after reduction processing is provided with enhancement layer.