CN107068652A - Wafer stage chip encapsulating structure and method for packing - Google Patents
Wafer stage chip encapsulating structure and method for packing Download PDFInfo
- Publication number
- CN107068652A CN107068652A CN201710171067.5A CN201710171067A CN107068652A CN 107068652 A CN107068652 A CN 107068652A CN 201710171067 A CN201710171067 A CN 201710171067A CN 107068652 A CN107068652 A CN 107068652A
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- fluting
- window
- weldering window
- weldering
- wafer stage
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- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000012856 packing Methods 0.000 title description 3
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000004891 communication Methods 0.000 claims description 3
- 238000003780 insertion Methods 0.000 claims description 3
- 230000037431 insertion Effects 0.000 claims description 3
- 238000013461 design Methods 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 238000000018 DNA microarray Methods 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 241000826860 Trapezium Species 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 238000002493 microarray Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
Abstract
The present invention relates to wafer stage chip encapsulating structure and manufacture method, including chip unit, it has the first surface and second surface being oppositely arranged, and the first surface arranges at least one weldering window for being used to electrically connect；The second surface sets the TSV structure being connected with weldering window, and the TSV structure includes the through hole through first surface and second surface and the fluting set in second surface, and the edge of the frontier distance second surface of fluting is more than 10um.The progress obtained compared with the prior art is the structural strength for improving chip.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of wafer stage chip encapsulating structure and its method for packing.
Background technology
TSV (Through Silicon Vias pass through silicon chip passage) encapsulating structure is one kind of IC package mode, can be divided
To be encapsulated and for surface-mounted device wafer-level packaging for memory.Wafer-level packaging is applied on optical image sensor (please
Reference picture 1), optical image sensor 2 has glass substrate 3 to support TSV structure 4 to maintain structural strength under this situation, and TSV's opens
The Z axis attachment structures such as hole 41, fluting 22, wiring 23 and weldering window 24 are arranged on the edge 21 of image sensor chip to facilitate system
Make.
And some chips (such as capacitive fingerprint sensing device chip) in order to package thickness is thinned, it is necessary to TSV encapsulation but
There is no glass plate as support, if continuing to adopt optical image sensor TSV packaging technology (such as patents
The TSV encapsulating structures disclosed in CN201510305840.3), the technological deficiency of chip edge insufficient strength will be produced, so that
Risk can be brought in following process by obtaining.Stress is for example increased when being cut to chip causes the wind of chip cracks
Danger, also can bring risk in later stage paster and assembling stage.
Therefore the structural strength for improving TSV structure and manufacture method raising chip is needed to solve the above problems.
The content of the invention
The purpose of the technical program is to ensure the integral thickness of microarray biochip to improve chip structure intensity, will for this
The inside that TSV fluting is arranged on chip causes fluting to keep certain safe distance with chip edge, is greater than 10um.By
Slotted in TSV and be arranged on the inside of chip so that the chip thickness structure identical with the thickness on the inside of fluting on the outside of TSV flutings is strong
Degree is lifted.
Technical solution of the present invention includes content in detail below：
Wafer stage chip encapsulating structure, it is characterised in that including chip unit, it has the first surface being oppositely arranged
And second surface, the first surface arrange at least one be used for electrically connect weldering window；The second surface is set to be connected with weldering window
The TSV structure connect, the TSV structure includes the through hole through first surface and second surface and opening in second surface setting
Groove, the edge of the frontier distance second surface of fluting is more than 10um.
Preferably, border and the first surface edge of weldering window meet relational expression apart from L
Preferably, the second surface of chip unit is provided with least one pad, and weldering window and pad are by forming described
Through-hole wall, fluting bottom wall, the wiring of slotted wall and second surface electrically conduct.
A kind of manufacture method of wafer stage chip encapsulating structure is also provided preferably to solve the above-mentioned technical problem present invention,
Including step：
S1：In the first surface arrangement weldering window of chip unit so that the weldering window is met with first surface edge apart from L
Relational expression
S2：In the second surface formation dovetail groove of chip unit, the projection covering institute of the bottom wall of fluting on the first surface
Weldering window is stated, the frontier distance second surface edge of fluting is more than 10um；
S3：The through hole of insertion weldering window and fluting bottom wall is formed in the fluting so that the through hole connection weldering window；
S4：In the through-hole wall, fluting bottom wall, slotted wall and second surface formation wiring, wiring electrical communication weldering
Window and pad.
Preferably, the depth-width ratio k of slotted wall is approximately equal to 2.75.
Preferably, dovetail groove is one or more levels dovetail groove.
The present invention by the way that TSV is slotted to chip internal in order to be moved so that the chip height and chip of TSV grooved exteriors
Internal height is identical, improves the intensity of chip edge, while avoid the symmetrical weldering window construction of design, also it is avoided that
This design brings influence to circuit design.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments described in invention, for those of ordinary skill in the art, on the premise of not paying creative work,
Other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is prior art image sensor TSV encapsulating structure cross-sectional views.
Fig. 2 a are the schematic perspective view of TSV encapsulating structures of the present invention.
Fig. 2 b are the schematic perspective view of TSV encapsulating structures of the present invention.
Fig. 3 is second surface pad array schematic diagram of the present invention.
Fig. 4 a cross-sectional views in TSV manufacturing step S1 for the present invention.
Fig. 4 b cross-sectional views in TSV manufacturing step S2 for the present invention.
Fig. 4 c cross-sectional views in TSV manufacturing step S3 for the present invention.
Fig. 4 d cross-sectional views in TSV manufacturing step S4 for the present invention.
Fig. 4 e are the present invention in another embodiment schematic diagram of TSV structure.
Fig. 5 is present invention weldering window function structural representation.
Fig. 6 a-6c are laid out 4 kinds of weldering window component schematic diagrames for weldering window in the present invention 5.
Embodiment
In order that those skilled in the art more fully understand the technical scheme in the present invention, below in conjunction with of the invention real
The accompanying drawing in example is applied, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described implementation
Example only a part of embodiment of the invention, rather than whole embodiments.Based on the embodiment in the present invention, this area is common
The every other embodiment that technical staff is obtained under the premise of creative work is not made, should all belong to protection of the present invention
Scope.
As shown in Figure 2 a, wafer stage chip encapsulating structure of the present invention, including chip unit 1, chip unit have relative set
The first surface 115 and second surface 116 put.In the present invention by taking fingerprint sensor as an example, the first surface 115 sets work(
Energy circuit 132,131 and the capacitor cell array (not shown) for sensing fingerprint image, functional circuit and weldering window electricity 13
Property connection.The second surface 116 sets pad 12 and the TSV structure being electrically connected with weldering window, and the TSV structure includes running through
The through hole 112 of first surface 115 or weldering window 13 and second surface 116, and the fluting 11 being connected with through hole 112, the border of fluting
The edge 117 of second surface described in distance 110,111 is more than 10um.
In the present embodiment, the border 110 of fluting causes apart from the edge 117 of the second surface 116 more than 10um
The thickness d 1 in the outside of chip fluting 11 and the thickness d 2 identical (reference picture 4c) of chip internal, so as to ensure that chip is cut from wafer
The stress that produces avoids the risk of chip edge fragmentation when cutting can be born when cutting.
In the present embodiment, the border that the border of the fluting 11 includes the border 110 of Longitudinal extending and extended laterally
111；The distance at the frontier distance second surface edge of weldering window of the present invention is more than 10um, refers to any one frontier distance
The edge of weldering window is all higher than 10um.Therefore the distance for welding window border 110 near second surface edge 117 is at least above 10um
In order to obtain above-mentioned TSV encapsulating structures, the invention provides following manufacture method:
S1：In the first surface arrangement weldering window of chip unit so that the weldering window is met with first surface edge apart from L
Relational expression
S2：In the second surface formation dovetail groove of chip unit, the projection covering institute of the bottom wall of fluting on the first surface
Weldering window is stated, the frontier distance second surface edge of fluting is more than 10um；
S3：The through hole of insertion weldering window and fluting bottom wall is formed in the fluting so that the through hole connection weldering window；
S4：In the through-hole wall, fluting bottom wall, slotted wall and second surface formation wiring, wiring electrical communication weldering
Window and pad.
Above-mentioned step is described in detail below：
Fig. 4 a and Fig. 4 b are refer in step sl in the arrangement weldering window 13 of first surface 115 of chip so that the weldering window
12 edges 118 away from first surface 115, weldering window 13 is in order that the border 133 of window 13 must be welded away from first surface edge 118
L is maintained a certain distance with first edge 118, this is provided so that the second table of distance of border 110 of the fluting 11 apart from L
The edge in face 116 is more than 10um.This meets relational expression apart from L in order to achieve the above object
In the present embodiment, the first surface edge 118 is it should be understood that the outermost of first surface 115, the weldering window
113 border should be understood to weld the boundary line of window and chip；It is described it is should be understood to that border 113 can reach apart from L with
Minimum range between first surface edge 118.
In this step, in order to open up described in through hole 112 weld window 13 central shaft x with fluting 11 center overlapping of axles x, when
Same change in location also occurs for the position of corresponding fluting 11 when position of the weldering window 13 on chip unit changes.
In this step, with the weldering window 13 while that arranges includes functional circuit 131,132 and fingerprint sensing array.
In this step, the shape and quantity of weldering window 13 carry out different designs as needed.
In this step, it can be set and keep certain spacing between multiple weldering windows 13, weldering window 13, the spacing preparing
During through hole 112, do not interfered between the corresponding through hole 112 of different pads 13.
Fig. 4 b be refer in step s 2 on the second surface 116 of chip unit 1 by methods such as air/chemical etchings
Fluting 11 is prepared, fluting 11 is arranged at the lower section of weldering window 13, with the thickness of thinned die 11, can facilitate the system of follow-up through hole 112
It is standby.
The ratio of width to height of slotted wall is determined in this step lithographic method, air etches the slotted wall to be formed and vertical side
It is than k to substantially 20 ° wide w of the high h of slotted wall of angle a
In this step, view field S (referring concurrently to Fig. 1) coverings of the bottom wall 1122 of fluting on the first surface are described
Window 13 is welded, to facilitate the preparation of follow-up through hole 112.The fluting 11 is trapezium structure central shaft x and fluting central shaft weight
Close, keep the left margin 110 of the groove to be more than apart from the left hand edge of the chip second surface 116 when preparing fluting 11
10um, while keeping the up-and-down boundary 110 at 11 two ends of fluting to be more than 10um (ginsengs apart from the lower edges of the chip second surface
According to Fig. 1 or Fig. 6 b).
In the present embodiment, the second surface edge 117 is it should be understood that the outermost of second surface 116, the fluting
Border 110 should be understood to fluting 11 and the boundary line of second surface；The distance at border 110 and second surface edge 117 should
When being interpreted as the minimum range between second surface edge 118 that border 110 can reach.
Fig. 4 c are refer to, is performed etching in step s3 between fluting 11 and weldering window 13, is formed and run through first surface 115
Or the through hole 112 of weldering window 13 and second surface 116, in the present embodiment through hole 112 be shaped as it is hollow round table-like, in other realities
It can also be cylindric etc. to apply a mode.
It refer to shown in Fig. 4 d, circle formed on the second surface 116 of chip unit and positioned at the periphery of fluting 11
Pad 12, is then electrically connected so that the functional circuit is produced and institute between pad 12 and weldering window 13 using wiring 121
Pad 12 is stated to electrically conduct.
The wiring in the present embodiment is formed in the wall of through hole 1121, fluting bottom wall 1122, the and of slotted wall 1123
Second surface 116.
Refer to Fig. 4 e can also set the fluting 11 of multistage in the present embodiment, i.e., described in overlapping dovetail groove 113
Trapezoidal extension of the wiring 121 along dovetail groove 11,113, the border 110 of the multistage dovetail groove 11 is apart from second surface edge
117 distance is more than 10um, i.e., at least ensure the first order dovetail groove of the multistage dovetail groove when preparing the dovetail groove
The edge 117 of the second surface of frontier distance 110 is more than 10um.
Fig. 5 and Fig. 6 a are refer to, the weldering window and functional circuit arranged in above-mentioned steps S1, according to suitable from top to bottom in figure
Sequence is logical operation circuit 132 successively, and esd protection circuit 131 welds window 13；Weld window 13 and logical operation circuit 131 and ESD is protected
The one circuit arrangement unit 14 of formation of protection circuit 132, multiple circuit arrangement units 14 are disposed in parallel in the first table of chip 1
On face 115, the weldering window 13 is disposed adjacent to the position of the side of first surface edge 118, the He of logical operation circuit 132
Esd protection circuit 131 is arranged in the side away from first surface edge 118.Therefore, weldering window 13 and logical operation circuit 132,
The relative position relation of esd protection circuit 131 is same as the prior art, fluting during in order to meet fluting in step s 2
11 fluting of frontier distance second surface edge 117 is more than 10um, and arrangement unit position is overall to away from the compared with the prior art
One marginal surface direction is moved, i.e., upwards, move right (using paper as reference).
Second of arrangement of the weldering window of Fig. 6 b displayings is refer to, is with welding the arrangement of window in Fig. 6 a and distinguishing first
The left side on surface 115 adds multiple arrangement units 14.The increased position of arrangement unit 14 is overall to remote compared with the prior art
The direction of first surface edge 118 is moved, i.e., downwards, be moved to the left (using paper as reference).
The third arrangement of the weldering window of Fig. 6 c displayings is refer to, the arrangement difference with welding window 13 in Fig. 6 a is described
The position of arrangement unit 14 there occurs reverse, i.e. logical operation circuit 132, and esd protection circuit 131 is disposed adjacent to first surface
The position at edge 118, weldering window 13 is arranged in the direction away from the first surface edge 118.It is relative to be arranged with welding window in Fig. 6 a
The advantage of mode is that circuit arrangement needs to take a certain distance in lower section weldering window 13 by circuit arrangement, and weldering window 13 is natural
Edge 118 away from first surface, can reserve the border 110 that enough distances cause fluting 11 for fluting 11 in step S2
It is more than 10um apart from second surface fluting, while circuit takes full advantage of the area of chip, will not occurs segment chip in Fig. 6 a
The situation of area loss.
It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, Er Qie
In the case of without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
From the point of view of which point, embodiment all should be regarded as exemplary, and be nonrestrictive, the scope of the present invention is by appended power
Profit is required rather than described above is limited, it is intended that all in the implication and scope of the equivalency of claim by falling
Change is included in the present invention.Any reference in claim should not be considered as to the claim involved by limitation.
Moreover, it will be appreciated that although the present specification is described in terms of embodiments, not each embodiment is only wrapped
Containing an independent technical scheme, this narrating mode of specification is only that for clarity, those skilled in the art should
Using specification as an entirety, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the art
It may be appreciated other embodiment.
Claims (7)
1. wafer stage chip encapsulating structure, it is characterised in that including chip unit, it has the first surface that is oppositely arranged and the
Two surfaces, the first surface arrange at least one be used for electrically connect weldering window；The second surface sets what is be connected with weldering window
TSV structure, the TSV structure includes the through hole through first surface and second surface and the fluting set in second surface, opens
The edge of the frontier distance second surface of groove is more than 10um.
2. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the border of the weldering window and the first table
Face edge meets relational expression apart from L
3. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the second surface of the chip unit
At least one pad is provided with, weldering window and pad are by forming in the through-hole wall, fluting bottom wall, slotted wall and second surface
Wiring electrically conduct.
4. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the fluting is one or more levels ladder
Shape groove.
5. the manufacture method of wafer stage chip encapsulating structure as claimed in claim 1, it is characterised in that including step：
S1：In the first surface arrangement weldering window of chip unit so that the weldering window meets relation with first surface edge apart from L
Formula
S2：In the second surface formation dovetail groove of chip unit, the projection of the bottom wall of fluting on the first surface covers the weldering
Window, the frontier distance second surface edge of fluting is more than 10um；
S3：The through hole of insertion weldering window and fluting bottom wall is formed in the fluting so that the through hole connection weldering window；
S4：The through-hole wall, fluting bottom wall, slotted wall and second surface formation wiring, the wiring electrical communication weldering window and
Pad.
6. the manufacture method of wafer stage chip encapsulating structure according to claim 5, it is characterised in that the slotted wall
Depth-width ratio k be approximately equal to 2.75.
7. the manufacture method of wafer stage chip encapsulating structure according to claim 5, it is characterised in that the dovetail groove is one
Level or multistage dovetail groove.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710171067.5A CN107068652A (en) | 2017-03-21 | 2017-03-21 | Wafer stage chip encapsulating structure and method for packing |
| PCT/CN2018/079447 WO2018171547A1 (en) | 2017-03-21 | 2018-03-19 | Wafer-level chip encapsulating structure and manufacturing method therefor |
| TW107109749A TWI669798B (en) | 2017-03-21 | 2018-03-20 | Wafer level chip size package and method of making the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710171067.5A CN107068652A (en) | 2017-03-21 | 2017-03-21 | Wafer stage chip encapsulating structure and method for packing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107068652A true CN107068652A (en) | 2017-08-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710171067.5A Pending CN107068652A (en) | 2017-03-21 | 2017-03-21 | Wafer stage chip encapsulating structure and method for packing |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN107068652A (en) |
| TW (1) | TWI669798B (en) |
| WO (1) | WO2018171547A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018171547A1 (en) * | 2017-03-21 | 2018-09-27 | 苏州迈瑞微电子有限公司 | Wafer-level chip encapsulating structure and manufacturing method therefor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104900607A (en) * | 2014-03-07 | 2015-09-09 | 精材科技股份有限公司 | Chip package and method of fabricating the same |
| CN105047628A (en) * | 2015-06-05 | 2015-11-11 | 苏州迈瑞微电子有限公司 | Wafer-level chip TSV packaging structure and packaging method thereof |
| CN206650071U (en) * | 2017-03-21 | 2017-11-17 | 苏州迈瑞微电子有限公司 | Wafer stage chip encapsulating structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009140798A1 (en) * | 2008-05-21 | 2009-11-26 | 精材科技股份有限公司 | Electronic component package body and its packaging method |
| JP5356742B2 (en) * | 2008-07-10 | 2013-12-04 | ラピスセミコンダクタ株式会社 | Semiconductor device, semiconductor device manufacturing method, and semiconductor package manufacturing method |
| CN103400808B (en) * | 2013-08-23 | 2016-04-13 | 苏州晶方半导体科技股份有限公司 | The wafer level packaging structure of image sensor and method for packing |
| CN103474365B (en) * | 2013-09-04 | 2017-01-18 | 惠州硕贝德无线科技股份有限公司 | Method for packaging semiconductor |
| WO2017022450A1 (en) * | 2015-07-31 | 2017-02-09 | ソニー株式会社 | Pinhole camera, electronic apparatus, and manufacturing method |
| CN107068652A (en) * | 2017-03-21 | 2017-08-18 | 苏州迈瑞微电子有限公司 | Wafer stage chip encapsulating structure and method for packing |
-
2017
- 2017-03-21 CN CN201710171067.5A patent/CN107068652A/en active Pending
-
2018
- 2018-03-19 WO PCT/CN2018/079447 patent/WO2018171547A1/en active Application Filing
- 2018-03-20 TW TW107109749A patent/TWI669798B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104900607A (en) * | 2014-03-07 | 2015-09-09 | 精材科技股份有限公司 | Chip package and method of fabricating the same |
| CN105047628A (en) * | 2015-06-05 | 2015-11-11 | 苏州迈瑞微电子有限公司 | Wafer-level chip TSV packaging structure and packaging method thereof |
| CN206650071U (en) * | 2017-03-21 | 2017-11-17 | 苏州迈瑞微电子有限公司 | Wafer stage chip encapsulating structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018171547A1 (en) * | 2017-03-21 | 2018-09-27 | 苏州迈瑞微电子有限公司 | Wafer-level chip encapsulating structure and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2018171547A1 (en) | 2018-09-27 |
| WO2018171547A9 (en) | 2019-01-10 |
| TW201901910A (en) | 2019-01-01 |
| TWI669798B (en) | 2019-08-21 |
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