TW201901910A - Wafer level chip size package and method of making the same - Google Patents

Abstract

The utility provides a kind of wafer level chip size package and method of packaging the same. The wafer level chip size package includes a chip unit having a first surface and a second surface disposed oppositely. The chip unit has at least a pad located at the first surface and at least a TVS structure connected with the pad and located at the second surface. The TVS structure has a hole extending through the first surface and the second surface and a groove located at the second surface. A border of the groove defines a distance which is longer than 10 um corresponding to an edge of the second surface.

Description

 Wafer level chip package structure and manufacturing method thereof  

The present invention relates to the field of semiconductor technologies, and in particular, to a wafer level chip package structure and a method of fabricating the same.

The TSV (Through Silicon Vias) package structure is a type of wafer (IC) package that can be divided into memory packages and wafer level packages for chip devices. The wafer level package is applied to the optical image sensor (please refer to the first figure). In this case, the optical image sensor 2 has the glass substrate 3 supporting the TSV structure 4 to maintain the structural strength, the TSV opening 41, A Z-axis connection structure such as the slit 22, the wiring 23, and the solder window 24 is provided at the edge 21 of the image sensor wafer to facilitate fabrication. In order to reduce the thickness of the package, some wafers (such as capacitive fingerprint sensor wafers) require a TSV package but no glass plate as a support. If the optical image sensor TSV packaging process continues to be used (for example, patent CN201510305840.3) The TSV package structure disclosed in the present invention will result in technical defects in insufficient wafer edge strength, which may cause risks in subsequent processing. For example, when cutting a wafer, the risk of wafer fragmentation due to stress is increased, and there is also a risk in the post-laying and assembly stages.

The object of the present invention is to ensure the overall thickness of the wafer to increase the structural strength of the wafer. To this end, the slot of the TSV is placed inside the wafer such that the slot maintains a certain safe distance from the edge of the wafer, for example greater than 10 um. Since the TSV slot is disposed inside the wafer, the thickness of the wafer outside the TSV slot is the same as the thickness of the inside of the slot.

To achieve the above object, the present invention provides a wafer level wafer package structure including a wafer unit having oppositely disposed first and second surfaces, the first surface being disposed with at least one soldering window for electrical connection; The second surface is provided with a TSV structure connected to the solder window, the TSV structure including a through hole penetrating the first surface and the second surface and a groove provided on the second surface, the boundary of the groove being larger than the edge of the second surface 10um.

Preferably, the distance L between the boundary of the solder window and the edge of the first surface satisfies the relationship L> +10 um .

Preferably, at least one pad is disposed on the second surface of the wafer unit, and the soldering window and the pad are electrically connected by wiring formed on the through hole wall, the grooved bottom wall, the grooved side wall, and the second surface.

In order to solve the above technical problem, the present invention further provides a method for fabricating a wafer level chip package structure, comprising the steps of: S1: arranging a solder window on a first surface of the wafer unit such that the solder window and the first surface edge The distance L satisfies the relationship L> +10 um ; S2: forming a trapezoidal groove on the second surface of the wafer unit, the projection of the grooved bottom wall on the first surface covering the solder window, the boundary of the groove being greater than 10 um from the edge of the second surface; S3: a through hole penetrating through the soldering window and the bottom wall of the slot is formed in the slot, so that the through hole is connected to the soldering window; S4: forming a wiring on the through hole wall, the slotted bottom wall, the slotted sidewall and the second surface The wiring electrically communicates with the soldering window and the pad.

Preferably, the aspect ratio k of the slotted sidewall is approximately equal to 2.75.

Preferably, the trapezoidal groove is a one-stage or multi-stage trapezoidal groove.

The invention moves the TSV to the inside of the wafer by slotting, so that the height of the wafer outside the TSV slot is the same as the height of the inside of the wafer, thereby improving the strength of the edge of the wafer, and avoiding the design of the left and right symmetrical solder window structure, thereby avoiding this. The design has an impact on the circuit design.

1‧‧‧ wafer unit

11‧‧‧ slotting

110, 111‧‧‧ border

112‧‧‧through hole

1121‧‧‧through hole wall

1122‧‧‧Slotted bottom wall

1123‧‧‧Slotted side wall

113‧‧‧Trapezoidal slot

115‧‧‧ first surface

116‧‧‧ second surface

117‧‧‧second surface edge

118‧‧‧First surface edge

12‧‧‧ pads

121‧‧‧Wiring

13‧‧‧weld window

131‧‧‧Logical Operation Circuit

132‧‧‧ESD protection circuit

14‧‧‧ Arrangement unit

1 is a schematic cross-sectional structural view of a prior art image sensor TSV package structure.

2a is a perspective view of a TSV package structure of the present invention.

2b is a perspective view of a TSV package structure of the present invention.

3 is a schematic view of a second surface pad array of the present invention.

4a is a schematic cross-sectional view of the present invention in the TSV manufacturing step S1.

Fig. 4b is a schematic cross-sectional view showing the TSV manufacturing step S2 of the present invention.

Figure 4c is a schematic cross-sectional view of the TSV manufacturing step S3 of the present invention.

Figure 4d is a schematic cross-sectional view of the TSV manufacturing step S4 of the present invention.

4e is a schematic view of another embodiment of the TSV structure of the present invention.

Figure 5 is a schematic view showing the functional structure of the welding window of the present invention.

6a-6c are schematic views of four kinds of welded window components of the welding window layout of Fig. 5 of the present invention.

As shown in FIG. 2a, the wafer level wafer package structure of the present invention comprises a wafer unit 1 having a first surface 115 and a second surface 116 disposed opposite each other. In the present invention, a fingerprint sensing chip is taken as an example. The first surface 115 is provided with functional circuits 132 and 131 and a capacitor unit array (not shown) for sensing a fingerprint image, and the functional circuit and the soldering window 13 are electrically connected. connection. The second surface 116 is provided with a pad 12 and a TSV structure electrically connected to the soldering window, the TSV structure including a through hole 112 penetrating the first surface 115 or the soldering window 13 and the second surface 116, and the through hole 112 The connected slot 11 has a grooved boundary distance 110, 111 and the edge 117 of the second surface is greater than 10 um.

In the present embodiment, the grooved boundary 110 is larger than 10 um from the edge 117 of the second surface 116 such that the thickness d1 outside the wafer slot 11 is the same as the thickness d2 inside the wafer (refer to FIG. 3), thereby ensuring the wafer from the crystal. It can withstand the stress generated during cutting when cutting on a circle to avoid the risk of chip edge cracking.

In the present embodiment, the boundary of the slot 11 includes a longitudinally extending boundary 110 and a laterally extending boundary 111; the boundary of the soldering window of the present invention is greater than 10 um from the edge of the second surface, and refers to any boundary. The edge of the welded window is greater than 10um. Thus the distance from the weld window boundary 110 closest to the second surface edge 117 is at least greater than 10 um.

S1: arranging a soldering window on the first surface of the wafer unit such that the distance L between the soldering window and the edge of the first surface satisfies the relationship L> +10 um .

S2: forming a trapezoidal groove on the second surface of the wafer unit, the projection of the grooved bottom wall on the first surface covering the solder window, the boundary of the groove being greater than 10 um from the edge of the second surface.

S3: forming a through hole penetrating through the soldering window and the bottom wall of the groove in the slot, such that the through hole is connected to the soldering window.

S4: forming a wiring on the through hole wall, the grooved bottom wall, the grooved side wall, and the second surface, the wiring electrically communicating with the solder window and the pad.

The above steps are described in detail below. Please refer to FIG. 4a and FIG. 4b to arrange the soldering window 13 on the first surface 115 of the wafer in step S1 such that the soldering window 12 is away from the first surface edge 118 of the first surface 115, The weld window 13 is remote from the first surface edge 118 in order to maintain the boundary 133 of the weld window 13 at a certain distance L from the first surface edge 118, the distance L being set such that the boundary 110 of the slot 11 is away from the second surface 116 The edge is greater than 10um. In order to achieve the above purpose, the distance L satisfies the relationship L> +10 um .

In the present embodiment, the first surface edge 118 should be understood as the outermost side of the first surface 115, and the boundary of the solder window 113 should be understood as the boundary line between the solder window and the wafer; the distance L should be understood as a boundary. 113 is the minimum distance that can be achieved with the first surface edge 118.

In this step, in order to open the through hole 112, the central axis x of the soldering window 13 coincides with the central axis of the slot 11, and the corresponding slot 11 is changed when the position of the soldering window 13 on the wafer unit changes. The same position change also occurs in the position.

In this step, the function circuits 131, 132 and the fingerprint sensing array are arranged simultaneously with the solder window 13.

In this step, the shape and number of the weld windows 13 are designed differently as needed.

In this step, a plurality of soldering windows 13 may be disposed, and the soldering windows 13 are spaced apart from each other such that the through holes 112 corresponding to the different pads 13 do not interfere with each other when the through holes 112 are prepared.

Referring to FIG. 4b, in step S2, a groove 11 is formed on the second surface 116 of the wafer unit 1 by air/chemical etching or the like, and the groove 11 is disposed under the solder window 13.

In this step, the etching method determines the width and height of the sidewall of the trench, and the thickness of the wafer 11 can be thinned to facilitate the preparation of the subsequent via 112. The angle between the side wall of the groove formed by the air etching and the vertical direction is approximately 20°, and the height h of the grooved side wall is k ratio 2.75.

In this step, the bottomed wall 1122 of the groove covers the soldering window 13 on the projection area S on the first surface (see also FIG. 1) to facilitate the preparation of the subsequent via 112. The slot 11 is a trapezoidal structure whose central axis x coincides with the central axis of the slot, and the left boundary 110 of the slot is maintained greater than 10 um from the left edge of the second surface 116 of the wafer while the slot 11 is being prepared, while maintaining The upper and lower boundaries 110 at both ends of the slot 11 are larger than 10 μm from the upper and lower edges of the second surface of the wafer (refer to FIG. 1 or FIG. 4b).

In the present embodiment, the second surface edge 117 should understand the outermost side of the second surface 116, and the grooved boundary 110 should be understood as the boundary line between the slot 11 and the second surface; the boundary 110 and the second surface The distance of the edge 117 should be understood as the minimum distance that the boundary 110 can reach between the second surface edge 117.

Referring to FIG. 4c, etching is performed between the slot 11 and the soldering window 13 in step S3 to form a through hole 112 penetrating the first surface 115 or the soldering window 13 and the second surface 116. The through hole in this embodiment The shape of 112 is a hollow truncated cone shape, and may be a columnar shape or the like in other embodiments.

Referring to FIG. 4d, a circular pad 12 is formed on the second surface 116 of the wafer unit and at the periphery of the slot 11, and then electrically connected by the wiring 121 between the pad 12 and the solder window 13, The functional circuit is caused to be electrically connected to the pad 12.

In the present embodiment, the wiring is formed in the through hole wall 1121, the grooved bottom wall 1122, the grooved side wall 1123, and the second surface 116.

Referring to FIG. 4e, in the present embodiment, a plurality of stages of slots 11, that is, overlapping trapezoidal slots 113, may be provided. The wires 121 extend along a trapezoidal shape of the trapezoidal slots 113, and the boundary 110 of the plurality of trapezoidal slots 113 The distance from the second surface edge 117 is greater than 10 um, that is, at least the boundary 110 of the first-order trapezoidal groove of the multi-stage trapezoidal groove is ensured to be greater than 10 um from the second surface edge 117 when the trapezoidal groove 113 is prepared.

Referring to FIG. 5 and FIG. 6a, the soldering window and the functional circuit arranged in the above step S1 are logical operation circuit 132, ESD protection circuit 131, solder window 13, solder window 13 and logic in order from top to bottom in the figure. The arithmetic circuit 131 and the ESD protection circuit 132 form a circuit arrangement unit 14 in which a plurality of the circuit arrangement units 14 are juxtaposed on the first surface 115 of the wafer 1, the weld window 13 being disposed on the side close to the first surface edge 118 The logical operation circuit 132 and the ESD protection circuit 131 are disposed on a side away from the first surface edge 118. Therefore, the relative positional relationship between the welding window 13 and the logic operation circuit 132 and the ESD protection circuit 131 is the same as that of the prior art. In order to satisfy the boundary of the slot 11 when the slot is opened in step S2, the second surface edge 117 is slotted. Above 10um, the position of the arrangement unit is moved away from the edge of the first surface as a whole, that is, moving upwards and to the right (referenced to the paper surface).

Referring to the second arrangement of the weld window shown in Figure 6b, the arrangement of the weld window in Figure 6a differs in that a plurality of arrangement units 14 are added to the left side of the first surface 115. The increased placement unit 14 position moves generally away from the first surface edge 118 relative to the prior art, i.e., downwards and to the left (referenced to the paper surface).

Referring to the third arrangement of the welding window shown in FIG. 6c, the arrangement of the welding window 13 in FIG. 6a is different in that the position of the arrangement unit 14 is reversed, that is, the logic operation circuit 132, and the ESD protection circuit 131 is arranged close to The position of the first surface edge 118, the weld window 13 is disposed in a direction away from the first surface edge 118. An advantage over the weld window arrangement of Figure 6a is that the circuit is disposed in the lower weld window 13 and the circuit arrangement requires a certain distance. The weld window 13 is naturally remote from the edge 118 of the first surface 115 and can be slotted in step S2. 11 is reserved for a sufficient distance such that the boundary 110 of the slot 11 is slotted from the second surface by more than 10 um, and the circuit makes full use of the area of the wafer, and the partial wafer area waste in FIG. 5 does not occur.

The present invention is described in the above embodiments, but the present invention is not limited to the embodiments disclosed above, and various modifications and changes in accordance with the nature of the present invention are intended to fall within the scope of the present invention.

Claims (7)

 A wafer level wafer package structure comprising a wafer unit having oppositely disposed first surfaces and second surfaces, the first surface arranging at least one solder window for electrical connection; the second surface being disposed and soldered A connected TSV structure, the TSV structure including a through hole penetrating the first surface and the second surface and a groove disposed on the second surface, the boundary of the groove being greater than 10 um from the edge of the second surface.   The wafer level chip package structure according to claim 1, wherein a distance L between the boundary of the solder window and the edge of the first surface satisfies a relationship L> +10 um .  The wafer-level chip package structure according to claim 1, wherein at least one pad is disposed on the second surface of the wafer unit, and the soldering window and the pad are formed in the through-hole wall and slotted. The wiring of the bottom wall, the slotted side wall, and the second surface is electrically conductive.    The wafer level chip package structure of claim 1, wherein the groove is a one-stage or multi-stage trapezoidal groove.   The method for manufacturing a wafer level chip package structure according to claim 1, comprising the steps of: S1: arranging a soldering window on the first surface of the wafer unit such that a distance L between the solder window and the first surface edge is satisfied. Relation L> +10 um ; S2: forming a trapezoidal groove on the second surface of the wafer unit, the projection of the grooved bottom wall on the first surface covering the solder window, the boundary of the groove being greater than 10 um from the edge of the second surface; S3: a through hole penetrating through the soldering window and the bottom wall of the groove is formed in the groove, so that the through hole is connected to the welding window; and S4: forming on the through hole wall, the groove bottom wall, the grooved side wall and the second surface Wiring, which electrically connects the solder window and the pad.  The method of fabricating a wafer level chip package structure according to claim 5, wherein the aspect ratio k of the sidewall of the trench is approximately equal to 2.75.    The method of fabricating a wafer level chip package structure according to claim 5, wherein the trapezoidal groove is a one-stage or multi-stage trapezoidal groove.