WO2018171389A1 - 一种光收发芯片的自动测试装置及方法 - Google Patents

一种光收发芯片的自动测试装置及方法 Download PDF

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Publication number
WO2018171389A1
WO2018171389A1 PCT/CN2018/077365 CN2018077365W WO2018171389A1 WO 2018171389 A1 WO2018171389 A1 WO 2018171389A1 CN 2018077365 W CN2018077365 W CN 2018077365W WO 2018171389 A1 WO2018171389 A1 WO 2018171389A1
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test
module
optical transceiver
transceiver chip
relay switch
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PCT/CN2018/077365
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English (en)
French (fr)
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黄秋伟
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厦门优迅高速芯片有限公司
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Publication of WO2018171389A1 publication Critical patent/WO2018171389A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
    • H04B10/073—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an out-of-service signal
    • H04B10/0731—Testing or characterisation of optical devices, e.g. amplifiers

Definitions

  • the invention relates to the technical field of optical transceiver chip testing, and in particular relates to an automatic testing device and method for an optical transceiver chip.
  • the optical module in optical communication has an indispensable important position.
  • the optical transceiver chip is an integrated circuit in the optical transceiver module, which refers to the main basic chip of the physical layer of the optical broadband network, including a transimpedance amplifier (TIA) and a limiting amplifier ( LA), laser driver (LDD) three. They are used in the front end of fiber optic transmission to achieve opto-electronic, electro-optic conversion of high-speed transmission signals, which are integrated into the fiber-optic transceiver module.
  • the optical transceiver chip is an important chip of the physical layer of the optical fiber broadband network, and relates to the transmission quality of the optical signal. Therefore, optical network equipment and optical transceiver modules impose stringent requirements on these IC chips.
  • the object of the present invention is to overcome the deficiencies of the prior art, and provide an automatic testing device and method for an optical transceiver chip, which are mainly used for testing an integrated optical transceiver module, that is, a limiting amplifier (LA) and a laser driver (LDD).
  • the chip can automatically and accurately test the optical transceiver chip by combining the hardware circuit with the host computer test software, and visually display the test result and store the test result.
  • An automatic test device for an optical transceiver chip comprising: a host computer test module, a USB to I2C module, an MCU control module, a relay switch, an EEPROM module, a regulated power supply module, and a signal generator; the MCU control module and the light
  • the transceiver chip is connected;
  • the USB to I2C module is connected between the upper computer test module and the MCU control module for implementing communication between the USB bus of the upper computer test module and the I2C bus of the MCU control module;
  • the test module is used for performing a reset test and a RAM test of the optical transceiver chip, and performing data initialization on the optical transceiver chip and importing a test data configuration table, and controlling the relay switch to realize high and low level switching by the MCU control module, and performing register address Detecting and judging, after the detection is correct, the preset parameter test is entered, and the test completes the output test result;
  • the EEPROM module is connected to the optical transceiver chip for normally
  • the upper computer test module is connected to the regulated power supply module for monitoring voltage regulation a DC voltage value output by the source module;
  • the regulated power supply module is respectively connected to the optical transceiver chip and the relay switch for providing a regulated DC power source; and the relay switch is configured to control an output signal of the signal generator Whether it is connected to the light transceiver chip.
  • the regulated power supply module is connected to the optical transceiver chip for providing a +3.3V power supply.
  • the regulated power supply module is connected to the relay switch for providing a +5V power supply.
  • the USB to I2C module includes a USB interface and a CH341T chip, and the USB interface communicates with the host computer test module through a USB data line and is electrically connected to the CH341T chip; the CH341T chip is introduced by its SDA The pin and SCL pin are connected to the MCU control module.
  • the MCU control module includes an F330 chip, and the P0.4 pin of the F330 chip is connected to the input of the relay switch K1; the P0.1 pin is connected to the input of the relay switch K2; The foot is connected to the input of the relay switch K3.
  • the optical transceiver chip comprises pins RESET, SDA, SCL, TX_DISABLE, BIAS_P, TSENSE, MD, TX_FAULT, IROP, RREF and LOS_SD connected to the MCU control module; and further comprises an output connected to the relay switch K1.
  • the LAIN pin and the LAIP pin connected to the output of the relay switch K2; the output of the relay switch K3 is connected to the IROP pin.
  • the upper computer test module comprises a reset test unit, a RAM test unit, an OMA (optical modulation amplitude) alarm test unit, a ROP alarm test unit, an ADC test unit, a TX_FAULT (transmit alarm) test unit, and a LOW POWER. (low voltage/power off) test unit, analog test unit, TX_DISABLE test unit and limiting amplifier LA offset test unit; the analog test unit is used for RREF, TX_FAULT, MD, BIAS_P, The output voltages of the TSENSE, LOS_SD, and IROP pins are tested and used to test the output amplitude of the limiting amplifier LA and the laser driver LDD.
  • the EEPROM module comprises an AT24C08 chip, and the WA pin of the AT24C08 chip is used for receiving high and low level switching, so that data can be read or protected, and the data of the EEPROM is passed through the SDA pin when the data is initialized.
  • the SCL pin is normally introduced into the optical transceiver chip.
  • the automatic testing device further includes an oscilloscope, and the oscilloscope is connected to the optical transceiver chip for outputting a detection waveform.
  • An automatic test method for an optical transceiver chip comprising:
  • regulated power supply module Use the regulated power supply module to provide +3.3V power for the optical transceiver chip, and provide +5V power for each relay switch;
  • the upper computer test module sequentially performs the reset test and the RAM test of the optical transceiver chip, and performs data initialization and import test data configuration table of the optical transceiver chip, and controls the relay switch through the MCU control module to realize high and low level switching, and detects and judges the register address.
  • the preset parameter test is entered, and the test completes the output test result;
  • the preset parameter test includes the OMA alarm test, the ROP alarm test, the ADC test, the TX_FAULT test, the low voltage test, the analog test, the TX_DISABLE test, and the limiting amplifier.
  • LA offset test includes testing the output voltages of the RREF, TX_FAULT, MD, BIAS_P, TSENSE, LOS_SD, and IROP pins of the optical transceiver chip, and also including the output amplitudes of the limiting amplifier LA and the laser driver LDD. carry out testing.
  • An automatic testing device and method for an optical transceiver chip comprising: a host computer test module, a USB to I2C module, an MCU control module, a relay switch, an EEPROM module, a regulated power supply module, and a signal generator, wherein the upper computer
  • the test module is implemented by software, and the USB to I2C module, the MCU control module, the relay switch, the EEPROM module and the regulated power supply module are realized by a hardware circuit, and the hardware circuit is controlled and tested by the upper computer test module to realize fast and accurate pairing.
  • the optical transceiver chip performs automated testing and visually displays the test results and stores the test results.
  • FIG. 1 is an overall frame view of an automatic test device for an optical transceiver chip of the present invention
  • FIG. 2 is a circuit diagram of a regulated power supply module according to an embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a USB to I2C module according to an embodiment of the present invention.
  • FIG. 4 is a circuit diagram of an MCU control module according to an embodiment of the present invention.
  • FIG. 5 is a circuit diagram of an optical transceiver chip to be tested according to an embodiment of the present invention.
  • FIG. 6 is a circuit diagram of an EEPROM module according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of software testing according to an embodiment of the present invention.
  • FIG. 8 is an interface diagram of a host computer test module according to an embodiment of the present invention.
  • an automatic test device for an optical transceiver chip is used for testing an optical transceiver chip 7 , which is an integrated integrated chip of a limiting amplifier (LA) and a laser driver (LDD).
  • the automatic test device comprises: a host computer test module 1, a USB to I2C module 2, an MCU control module 3, a relay switch 4, an EEPROM module 5, a regulated power supply module 6 and a signal generator 8; the MCU control module 3 and the The optical transceiver chip 7 is connected; the USB to I2C module 2 is connected between the upper computer test module 1 and the MCU control module 3 for realizing the USB bus of the upper computer test module 1 and the I2C bus of the MCU control module 3
  • the upper computer test module 1 is configured to perform a reset test and a RAM test of the optical transceiver chip 7, and perform data initialization and import test data configuration table on the optical transceiver chip 7, and control the relay through the MCU control module 3.
  • the switch 4 realizes high and low level switching, detects and judges the register address of the IIC, and enters the preset parameter test after the detection is correct, and the test completes the output test result; the EEPROM module 5 and the optical transceiver
  • the chip 7 is connected for the data of the EEPROM to be normally introduced into the optical transceiver chip through the data line and the clock line during data initialization; the upper computer test module 1 is connected to the regulated power supply module 6 for monitoring the power supply module 6
  • the output DC voltage value; the regulated power supply module 6 and the optical transceiver chip 7 and the relay switch 4 are respectively connected to provide a regulated DC power supply; the relay switch 4 is used to control the signal generator 8 Whether the output signal is connected to the optical transceiver chip 7 is connected.
  • the upper computer test module 1 runs on a PC, and is implemented by software, specifically based on the software of the labview design; the USB to I2C module 2, the MCU control module 3, the relay switch 4, the EEPROM module 5, and The power supply module 6 is implemented by a hardware circuit.
  • the USB to I2C module 2, the MCU control module 3, the relay switch 4, the EEPROM module 5, and the regulated power supply module 6 are integrated on the test circuit board to form an integrated circuit.
  • the optical transceiver chip 7 to be tested is inserted on the test circuit board.
  • the upper computer test module 1 connects the PC to the stabilized power supply module 6 through the GPIB line to monitor the power supply size, that is, the value of the output voltage of the regulated power supply module 6 is filled in by the upper computer, and can also be manually controlled.
  • the voltage value is set directly on the regulated power supply module 6.
  • the upper computer test module 1 can also visually display the voltage setting value and perform a modification operation.
  • the regulated power supply module 6 provides a +3.3 V power supply to the optical transceiver chip through J2; the regulated power supply module 6 provides a +5 V power supply to the relay switch 4 through J1.
  • the USB to I2C module 2 includes a USB interface USB and a CH341T chip U1.
  • the USB interface communicates with the host computer test module 1 through a USB data line, and the CH341T chip U1. Electrical connection; the CH341T chip is connected to the MCU control module 3 through its SDA pin and SCL pin.
  • the MCU control module 3 includes an F330 chip, and the main function is to output a high level and a low level to control the relay as a switch, and collect the pin output voltage of the optical transceiver chip 7 and internal setting. The value is compared and judged. Specifically, the P0.4 pin of the F330 chip is connected to the input of the relay switch K1; the P0.1 pin is connected to the input of the relay switch K2; and the P0.2 pin is connected to the input of the relay switch K3.
  • the optical transceiver chip 7 includes pins RESET, SDA, SCL, TX_DISABLE, BIAS_P, TSENSE, MD, TX_FAULT, IROP, RREF, and LOS_SD connected to the MCU control module 3;
  • the LAIN pin connected to the output of the relay switch K1 and the LAIP pin connected to the output of the relay switch K2 are included; the output of the relay switch K3 is connected to the IROP pin.
  • Table 1 the pin description of the optical transceiver chip 7 is shown in Table 1 below.
  • VDDTX_3V3 power supply 3.3V transmitting part of the power supply 14
  • TSENSE Analog output Connect a thermistor to the ground for temperature detection 15 GNDTX Ground Part of the launch 16
  • LDON RF output Transmit signal reverse output 17
  • LDOP RF output Transmit signal output 18 GNDTXO Ground Ground of the output channel 19
  • MD Analog input Emission monitoring backlight current input twenty one
  • TX_FAULT Digital output Emission warning, external pull-up 4.7K ⁇ 10K resistor twenty two IROP Analog input Monitor ROSA input optical power twenty three RREF Analog output
  • VDDRX_3V3 power supply 3.3V limiting amplifier power supply 25
  • LAIN RF input Limiting amplifier signal reverse input 26
  • LAIP RF input Limiting amplifier signal input
  • GND Ground Limiting amplifier and ESD ground 28
  • the EEPROM module 5 includes an AT24C08 chip, and the WA pin of the AT24C08 chip is used to receive high and low level switching, so that data can be read or protected, and the data is initialized when the EEPROM is used.
  • the data is normally imported into the optical transceiver chip through its SDA pin and SCL pin.
  • the upper computer test module 1 includes a reset test unit, a RAM test unit, an OMA (optical modulation amplitude) alarm test unit, an ROP (received optical power) alarm test unit, and an ADC (analog digital conversion) test unit.
  • TX_FAULT transmit alarm
  • LOW POWER low voltage / power off
  • analog test unit TX_DISABLE (transmit not enabled) test unit and limiting amplifier LA offset test unit
  • the analog test unit Used to test the output voltages of the RREF, TX_FAULT, MD, BIAS_P, TSENSE, LOS_SD, and IROP pins, and to test the output amplitude of the limiting amplifier LA and the laser driver LDD.
  • the testing process of the upper computer software testing module of this embodiment is as follows:
  • write IIC A2 address register value is AA, read IIC A2 address register value, if the value is not AA, output error message, stop test; otherwise write IIC A2 address register The value is 55, the IIC A2 address register value is read. If the value is not 55, the error message is output, and the test is stopped; otherwise, the RAM test is passed, and the next test is entered;
  • IIC A2 address 00 register Set the eighth bit value of IIC A2 address 00 register to be high, read IIC current, judge whether it meets LOW Power (low voltage) current, if it does not match, output error message, stop test, if it is met, set IIC A2 address 00
  • the eighth bit value of the register is low, indicating that the LOW Power test is qualified, and the next test is entered;
  • FIG. 8 it is an interface diagram of the upper computer test module.
  • the test operation steps of this embodiment are as follows:
  • Step A connect the power cable and the related communication line, turn on the power switch, and after the power supply is completed, turn on the upper computer software test module;
  • Step B loading the chip required for testing on the fixture
  • Step C click Start to start the test, the test result is displayed in the Test Result, if the test is qualified, the corresponding indicator is green, otherwise it is red and flashing;
  • Step D the test is completed, the optical transceiver chip is taken out, a new chip to be tested is placed, and step C is repeated.
  • the signal generator 8 is connected to the SAM3 and the SAM4 of the optical transceiver chip 7.
  • the automatic test device further includes an oscilloscope 9 connected to the optical transceiver chip for outputting a detection waveform.
  • the oscilloscope 9 is connected to the SAM5 and SAM6 of the optical transceiver chip 7, or to the SAM7 and the SAM8.

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  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
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Abstract

本发明公开了一种光收发芯片的自动测试装置及方法，装置包括上位机测试模块、USB转I2C模块、MCU控制模块、继电器开关、EEPROM模块、稳压电源模块和信号发生器；MCU控制模块与光收发芯片相连；USB转I2C模块连接于上位机测试模块和MCU控制模块之间；上位机测试模块用于通过MCU控制模块控制继电器开关实现高低电平切换，对寄存器地址进行检测判断，完成参数测试和存储测试结果；EEPROM模块与光收发芯片相连用于将EEPROM的数据导入光收发芯片；稳压电源模块与光收发芯片和继电器开关分别相连用于提供直流电源。本发明通过将硬件电路与上位机测试软件进行结合，能快速、准确地对光收发芯片进行自动化测试，并对测试结果进行存储。

Description

一种光收发芯片的自动测试装置及方法 技术领域
本发明涉及光收发芯片测试技术领域，具体涉及一种光收发芯片的自动测试装置及方法。
背景技术
光通信中光模块有着不可或缺的重要地位，光收发芯片是光收发模块中的集成电路，它是指光纤宽带网络物理层的主要基础芯片，包括跨阻放大器(TIA)、限幅放大器(LA)、激光驱动器(LDD)三种。它们被用于光纤传输的前端，来实现高速传输信号的光电、电光转换，这些功能被集成在光纤收发模块中。光收发芯片是光纤宽带网物理层的重要芯片，关系到光信号的传输质量。因此光网络设备、光收发模块都对这些IC芯片提出了苛刻的要求。因此，如何快速准确地测量光收发芯片的相关参数的测试并直观显示测试结果是非常重要的。现有测试中，大部分采用手动测试，首先需要手动进行输入控制参数，并手动导入测试数据配置表，然后依次对待测试项进行测试并进行人工判断测试结果是否符合要求，测试完成手动记录测试结果，待测试芯片多时，需消耗大量的人力和时间资源，而且长时间测试时容易导致出现错误。
发明内容
本发明的目的在于克服现有技术的不足，提供一种光收发芯片的自动测试装置及方法，主要用于测试光收发合一芯片，即限幅放大器(LA)和激光驱动器(LDD)集成一体化芯片，通过将硬件电路与上位机测试软件进行结合，能快速、准确地对光收发芯片进行自动化测试，并直观地显示测试结果及对测试结果进行存储。
本发明解决其技术问题所采用的技术方案是：
一种光收发芯片的自动测试装置，包括：上位机测试模块、USB转I2C模块、MCU控制模块、继电器开关、EEPROM模块、稳压电源模块和信号发生器；所述MCU控制模块与所述光收发芯片相连；所述USB转I2C模块连接于所述上位机测试模块和MCU控制模块之间用于实现上位机测试模块的USB总线与MCU控制模块的I2C总线之间的通信；所述上位机测试模块用于进行复位测试和光收发芯片的RAM测试，并对光收发芯片进行数据初始化及导入测试数据配置表，通过所述MCU控制模块控制所述继电器开关实现高低电平切换，对寄存器地址进行检测判断，检测正确后进入预设参数测试，测试完成输出测试结果；所述EEPROM模块与所述光收发芯片相连用于在数据初始化时EEPROM的数据通过数据线和时钟线正常导入所述光收发芯片；所述上位机测试模块与所述稳压电源模块相连用于监控稳压电源模块输出的直流电压值；所述稳压电源模块与所述光收发芯片和所述继电器开关分别相连用于提供稳压直流电源；所述继电器开关用于控制所述信号发生器的输出信号是否连接到光所述收发芯 片上。
优选的，所述稳压电源模块与所述光收发芯片相连用于提供+3.3V电源。
优选的，所述稳压电源模块与所述继电器开关相连用于提供+5V电源。
优选的，所述USB转I2C模块包括一USB接口和一CH341T芯片，所述USB接口通过USB数据线与上位机测试模块通信，并与所述CH341T芯片电连接；所述CH341T芯片通过其SDA引脚和SCL引脚与所述MCU控制模块相连。
优选的，所述MCU控制模块包括一F330芯片，所述F330芯片的P0.4引脚与继电器开关K1的输入相连；其P0.1引脚与继电器开关K2的输入相连；其P0.2引脚与继电器开关K3的输入相连。
优选的，所述光收发芯片包括与所述MCU控制模块相连的引脚RESET、SDA、SCL、TX_DISABLE、BIAS_P、TSENSE、MD、TX_FAULT、IROP、RREF和LOS_SD；还包括与继电器开关K1输出相连的LAIN引脚和与继电器开关K2输出相连的LAIP引脚；所述继电器开关K3的输出与所述IROP引脚相连。
优选的，所述上位机测试模块包括依次相连的复位测试单元、RAM测试单元、OMA(光调制幅度)告警测试单元、ROP告警测试单元、ADC测试单元、TX_FAULT(发射告警)测试单元、LOW POWER(低电压/断电)测试单元、模拟量测试单元、TX_DISABLE(发射不使能)测试单元和限幅放大器LA失调测试单元；所述模拟量测试 单元用于对RREF、TX_FAULT、MD、BIAS_P、TSENSE、LOS_SD和IROP引脚的输出电压进行测试，还用于对限幅放大器LA和激光驱动器LDD的输出幅度进行测试。
优选的，所述EEPROM模块包括一AT24C08芯片，所述AT24C08芯片的WA引脚用于接收高低电平切换，使得数据可以进行读取或保护，并使得数据初始化时EEPROM的数据通过其SDA引脚和SCL引脚正常导入所述光收发芯片。
优选的，所述自动测试装置还包括示波器，所述示波器与所述光收发芯片相连用于输出检测波形。
一种光收发芯片的自动测试方法，包括：
使用稳压电源模块为光收发芯片提供+3.3V电源，为各继电器开关提供+5V电源；
上位机测试模块依次进行复位测试和光收发芯片的RAM测试，并对光收发芯片进行数据初始化及导入测试数据配置表，通过MCU控制模块控制继电器开关实现高低电平切换，对寄存器地址进行检测判断，检测正确后进入预设参数测试，测试完成输出测试结果；所述预设参数测试包括OMA告警测试、ROP告警测试、ADC测试、TX_FAULT测试、低电压测试、模拟量测试、TX_DISABLE测试和限幅放大器LA失调测试；所述模拟量测试包括对光收发芯片的RREF、TX_FAULT、MD、BIAS_P、TSENSE、LOS_SD和IROP引脚的输出电压进行测试，还包括对限幅放大器LA和激光驱动器LDD的输出幅度进行测试。
本发明提供的技术方案带来的有益效果是：
本发明的一种光收发芯片的自动测试装置及方法，装置包括上位机测试模块、USB转I2C模块、MCU控制模块、继电器开关、EEPROM模块、稳压电源模块和信号发生器，所述上位机测试模块通过软件实现，所述USB转I2C模块、MCU控制模块、继电器开关、EEPROM模块和稳压电源模块通过硬件电路实现，通过上位机测试模块对硬件电路控制与测试，实现快速、准确地对光收发芯片进行自动化测试，并直观地显示测试结果及对测试结果进行存储。
以下结合附图及实施例对本发明作进一步详细说明；但本发明的一种光收发芯片的自动测试装置及方法不局限于实施例。
附图说明
图1为本发明光收发芯片的自动测试装置的整体框架图；
图2为本发明实施例的稳压电源模块的电路图；
图3为本发明实施例的USB转I2C模块的电路图；
图4为本发明实施例的MCU控制模块的电路图；
图5为本发明实施例的待测光收发芯片的电路图；
图6为本发明实施例的EEPROM模块的电路图；
图7为本发明实施例的软件测试流程图；
图8为本发明实施例的上位机测试模块的界面图。
具体实施方式
参见图1所示，一种光收发芯片的自动测试装置，用于测试光收发芯片7，所述光收发芯片7为限幅放大器(LA)和激光驱动器(LDD)集成一体化芯片，所述自动化测试装置包括：上位机测试模块1、USB转I2C模块2、MCU控制模块3、继电器开关4、EEPROM模块5、稳压电源模块6和信号发生器8；所述MCU控制模块3与所述光收发芯片7相连；所述USB转I2C模块2连接于所述上位机测试模块1和MCU控制模块3之间用于实现上位机测试模块1的USB总线与MCU控制模块3的I2C总线之间的通信；所述上位机测试模块1用于进行复位测试和光收发芯片7的RAM测试，并对光收发芯片7进行数据初始化及导入测试数据配置表，通过所述MCU控制模块3控制所述继电器开关4实现高低电平切换，对IIC的寄存器地址进行检测判断，检测正确后进入预设参数测试，测试完成输出测试结果；所述EEPROM模块5与所述光收发芯片7相连用于在数据初始化时EEPROM的数据通过数据线和时钟线正常导入所述光收发芯片；所述上位机测试模块1与所述稳压电源模块6相连用于监控稳压电源模块6输出的直流电压值；所述稳压电源模块6与所述光收发芯片7和所述继电器开关4分别相连用于提供稳压直流电源；所述继电器开关4用于控制所述信号发生器8的输出信号是否连接到光所述收发芯片7上。
本实施例中，所述上位机测试模块1运行在PC机上，通过软件实现，具体的基于labview设计的软件；所述USB转I2C模块2、 MCU控制模块3、继电器开关4、EEPROM模块5和稳压电源模块6通过硬件电路实现，本实施例中，所述USB转I2C模块2、MCU控制模块3、继电器开关4、EEPROM模块5和稳压电源模块6集成在测试电路板上组成集成电路，测试时，在测试电路板上插入待测光收发芯片7。
本实施例中，所述上位机测试模块1通过GPIB线使PC机连接稳压电源模块6来监控电源大小，即通过上位机填写数值控制稳压电源模块6的输出电压值，也可以手动控制直接在稳压电源模块6上设置电压值。此外，还可以通过所述上位机测试模块1直观显示电压设定值是多少并进行修改操作。
进一步的，参见图2所示，所述稳压电源模块6通过J2为所述光收发芯片提供+3.3V电源；所述稳压电源模块6通过J1为所述继电器开关4提供+5V电源。
进一步的，参见图3所示，所述USB转I2C模块2包括一USB接口USB和一CH341T芯片U1，所述USB接口通过USB数据线与上位机测试模块1通信，并与所述CH341T芯片U1电连接；所述CH341T芯片通过其SDA引脚和SCL引脚与所述MCU控制模块3相连。
进一步的，参见图4所示，所述MCU控制模块3包括一F330芯片，主要功能是输出高低电平来控制继电器作为开关，采集所述光收发芯片7的引脚输出电压来与内部设定值做比较判断。具体的，所述F330芯片的P0.4引脚与继电器开关K1的输入相连；其P0.1引脚 与继电器开关K2的输入相连；其P0.2引脚与继电器开关K3的输入相连。
进一步的，参见图5所示，所述光收发芯片7包括与所述MCU控制模块3相连的引脚RESET、SDA、SCL、TX_DISABLE、BIAS_P、TSENSE、MD、TX_FAULT、IROP、RREF和LOS_SD；还包括与继电器开关K1输出相连的LAIN引脚和与继电器开关K2输出相连的LAIP引脚；所述继电器开关K3的输出与所述IROP引脚相连。具体的，如下表1所示为所述光收发芯片7的引脚说明。
表1
引脚 名称 类型 功能描述
1 GND 地 限幅放大器和ESD的地
2 LAON 射频输出 限幅放大器的输出
3 LAOP 射频输出 限幅放大器的反向输出
4 VDDRX_3V3 电源 3.3V接收部分电源
5 LDIP 射频输入 发射信号输入
6 LDIN 射频输入 发射信号反向输入
7 RESET 数字输入 数字部分复位
8 SDA 数字双向 IIC从模式的数据接口
9 SCL 数字输入 IIC从模式的时钟接口
10 VDDESD 电源 3.3V数字部分电源
11 TX_DISABLE 数字输入 发射使能控制，内部上拉20K电阻
12 BIAS_P 模拟输出 发射偏置电流输出
13 VDDTX_3V3 电源 3.3V发射部分电源
14 TSENSE 模拟输出 外接一个热敏电阻到地用于温度检测
15 GNDTX 地 发射部分的地
16 LDON 射频输出 发射信号反向输出
17 LDOP 射频输出 发射信号输出
18 GNDTXO 地 发射输出通道的地
19 VDDTX_3V3 电源 3.3V发射部分电源
20 MD 模拟输入 发射监控背光电流输入
21 TX_FAULT 数字输出 发射告警，外部上拉4.7K～10K电阻
22 IROP 模拟输入 监测ROSA输入光功率
23 RREF 模拟输出 外置基准参考10K电阻到地
24 VDDRX_3V3 电源 3.3V限幅放大器电源
25 LAIN 射频输入 限幅放大器信号反向输入
26 LAIP 射频输入 限幅放大器信号输入
27 GND 地 限幅放大器和ESD的地
28 LOS_SD 数字输出 限幅放大器Los告警，外部上拉4.7K～10K
进一步的，参见图6所示，所述EEPROM模块5包括一AT24C08芯片，所述AT24C08芯片的WA引脚用于接收高低电平切换，使得数据可以进行读取或保护，并使得数据初始化时EEPROM的数据通过其SDA引脚和SCL引脚正常导入所述光收发芯片。
进一步的，所述上位机测试模块1包括依次相连的复位测试单元、RAM测试单元、OMA(光调制幅度)告警测试单元、ROP(接 收光功率)告警测试单元、ADC(模拟数字转换)测试单元、TX_FAULT(发射告警)测试单元、LOW POWER(低电压/断电)测试单元、模拟量测试单元、TX_DISABLE(发射不使能)测试单元和限幅放大器LA失调测试单元；所述模拟量测试单元用于对RREF、TX_FAULT、MD、BIAS_P、TSENSE、LOS_SD和IROP引脚的输出电压进行测试，还用于对限幅放大器LA和激光驱动器LDD的输出幅度进行测试。
具体的，参见图7所示，本实施例的上位机软件测试模块的测试过程如下：
软件界面初始化；设定电源电压；对测试电路板上电；设定继电器开关K1和K2为高电平，其他继电器开关为低电平；进入下一步测试
设定RESET为高电平进行软件复位测试，读取IIC(集成电路总线)A2地址16寄存器的值，如果值不为00，则输出错误信息，停止测试；否则显示软件复位测试合格，进入下一步测试；
设定RESET为低电平进行硬件复位测试，读取IIC A2地址16寄存器的值，如果值不为FF，则输出错误信息，停止测试；否则显示硬件复位测试合格，进入下一步测试；
设定RESET为高电平进行RAM测试，写入IIC A2地址寄存器值为AA，读取IIC A2地址寄存器值，如果值不为AA，则输出错误信息，停止测试；否则写入IIC A2地址寄存器值为55，读取IIC A2地址寄存器值，如果值不为55，则输出错误信息，停止测试；否则 显示RAM测试合格，进入下一步测试；
对数据进行初始化，导入测试配置表；进入下一步测试；
读取IIC A2地址1B寄存器值第一位的状态，如果不为1，则输出错误信息，停止测试；否则，读取LOS_SD输出电压；判断LOS_SD输出电压是否为高电平，如果为低电平，输出错误信息，停止测试；如果为高电平，设定继电器K1为低电平，读取IIC A2地址1B寄存器值第一位的状态，如果不为0，输出错误信息，停止测试；如果为0，读取LOS_SD输出电压，判断是否为低电平，如果为高电平，输出错误信息，停止测试，如果为低电平，显示LA OMA LOS(OMA告警检测)合格；进入下一步测试；
设定IIC A2地址10寄存器值第7位为高，读取IIC A2地址1B寄存器值第一位状态，判断值是否为1，如果不是，输出错误信息，停止测试，如果为1，设定继电器K2为低电平；读取IIC A2地址1B寄存器值第一位状态，判读值是否为0，如果不为0，输出错误信息，停止测试；如果为0显示LA ROP LOS(ROP告警检测)合格，进入下一步测试；
读取IIC A2地址1E-27寄存器值，判断是否符合内部ADC测试限值，如果不符合，输出错误信息，停止测试；如果符合，显示内部ADC测试合格，进入下一步测试；
设定IIC A2地址07寄存器值为0，读取IIC A2地址18寄存器值第五位状态，判断值是否为1，如果不为1，输出错误信息，停止测试；如果为1读取TX_Fault输出电压，判断电压是否为高电平， 如果不为高电平，输出错误信息，停止测试；如果为高电平，回复IIC A2地址07寄存器初始值；读取IIC A2地址18寄存器值第五位状态，判断值是否为0，如果不为0，输出错误信息，停止测试，如果为0，读取TX_Fault输出电压，判断电压值是否为低电平，如果不为低电平，输出错误信息，停止测试，如果为低电平，显示TX_Fault测试合格，进入下一步测试；
设定IIC A2地址00寄存器第八位值为高，读取IIC电流，判断是否符合LOW Power(低电压)电流，如果不符合，输出错误信息，停止测试，如果符合，设定IIC A2地址00寄存器第八位值为低，显示LOW Power(低电压)测试合格，进入下一步测试；
读取RREF、TX_Fault、MD、Bias、Tsense、Los_SD、IROP输出电压；读取限幅放大器LA和激光驱动器LDD输出幅度，判断各参数值是否符合限值，如果不符合，输出错误信息，停止测试；否则显示模拟量测试合格，进入下一步测试；
设定IIC A2地址00寄存器第六位值为高，读取LDD输出幅度，判断幅度是否为低电平，如果不为低电平，输出错误信息，停止测试，如果为低电平，设定IIC A2地址00寄存器第六位值为低，读取LDD输出幅度，判断幅度是否为高电平，如果不为高电平，输出错误信息，停止测试，如果为高电平，设定TX_DISABLE引脚为高电平；读取LDD输出幅度，判断幅度是否为低电平，如果不为低电平，输出错误信息，停止测试；否则设定定TX_DISABLE引脚为低电平；读取LDD输出幅度，判断幅度是否为高电平，如果不为高电平，输出错 误信息，停止测试；否则显示TX_DISABLE测试合格，进入下一步测试；
对数据进行初始化，导入LA DC测试配置表，设定继电器开关K1和K2为高电平，其他继电器开关为低电平，测试LA输出直流电平差值；判断差值是否符合限值，如果不符合，输出错误信息，停止测试；如果符合限值，显示LA失调测试合格；进入下一步测试；
对数据进行初始化，导入测试配置表；复位所有开关，测试完成，断电，保存测试数据。
进一步的，如图8所示为上位机测试模块的界面图，本实施例的测试操作步骤如下：
步骤A，连接电源线及相关通讯线，打开电源开关，待电源启动完成后，开启上位机软件测试模块；
步骤B，在夹具上装入测试所需的芯片；
步骤C，单击Start开始测试，测试结果显示在Test Result中，若测试合格，则相应的指示灯为绿色，否则为红色且闪烁；
步骤D，测试完成，取出光收发芯片，放入新的待测芯片，重复步骤C。
进一步的，所述信号发生器8与所述光收发芯片7的SAM3和SAM4相连。
进一步的，所述自动测试装置还包括示波器9，所述示波器与所述光收发芯片相连用于输出检测波形。具体的，所示示波器9与所述光收发芯片7的SAM5和SAM6相连，或与SAM7和SAM8相连。
上述实施例仅用来进一步说明本发明的光收发芯片的自动测试装置及方法，但本发明并不局限于实施例，凡是依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均落入本发明技术方案的保护范围内。

Claims (10)

  1. 一种光收发芯片的自动测试装置，其特征在于，包括：上位机测试模块、USB转I2C模块、MCU控制模块、继电器开关、EEPROM模块、稳压电源模块和信号发生器；所述MCU控制模块与所述光收发芯片相连；所述USB转I2C模块连接于所述上位机测试模块和MCU控制模块之间用于实现USB总线与I2C总线之间的通信；所述上位机测试模块用于进行复位测试和光收发芯片的RAM测试，并对光收发芯片进行数据初始化及导入测试数据配置表，通过所述MCU控制模块控制所述继电器开关实现高低电平切换，对寄存器地址进行检测判断，检测正确后进入预设参数测试，测试完成输出和存储测试结果；所述EEPROM模块与所述光收发芯片相连用于在数据初始化时EEPROM的数据通过数据线和时钟线正常导入所述光收发芯片；所述上位机测试模块与所述稳压电源模块相连用于监控稳压电源模块输出的直流电压值；所述稳压电源模块与所述光收发芯片和所述继电器开关分别相连用于提供稳压直流电源；所述继电器开关用于控制所述信号发生器的输出信号是否连接到光所述收发芯片上。
  2. 根据权利要求1所述的光收发芯片的自动测试装置，其特征在于，所述稳压电源模块与所述光收发芯片相连用于提供+3.3V电源。
  3. 根据权利要求1所述的光收发芯片的自动测试装置，其特征在于，所述稳压电源模块与所述继电器开关相连用于提供+5V电源。
  4. 根据权利要求1所述的光收发芯片的自动测试装置，其特征在于，所述USB转I2C模块包括一USB接口和一CH341T芯片，所 述USB接口通过USB数据线与上位机测试模块通信，并与所述CH341T芯片电连接；所述CH341T芯片通过其SDA引脚和SCL引脚与所述MCU控制模块相连。
  5. 根据权利要求1所述的光收发芯片的自动测试装置，其特征在于，所述MCU控制模块包括一F330芯片，所述F330芯片的P0.4引脚与继电器开关K1的输入相连；其P0.1引脚与继电器开关K2的输入相连；其P0.2引脚与继电器开关K3的输入相连。
  6. 根据权利要求5所述的光收发芯片的自动测试装置，其特征在于，所述光收发芯片包括与所述MCU控制模块相连的引脚
    RESET、SDA、SCL、TX_DISABLE、BIAS_P、TSENSE、MD、TX_FAULT、IROP、RREF和LOS_SD；还包括与继电器开关K1输出相连的LAIN引脚和与继电器开关K2输出相连的LAIP引脚；所述继电器开关K3的输出与所述IROP引脚相连。
  7. 根据权利要求6所述的光收发芯片的自动测试装置，其特征在于，所述上位机测试模块包括依次相连的复位测试单元、RAM测试单元、OMA告警测试单元、ROP告警测试单元、ADC测试单元、TX_FAULT测试单元、LOW POWER测试单元、模拟量测试单元、TX_DISABLE测试单元和限幅放大器LA失调测试单元；所述模拟量测试单元用于对RREF、TX_FAULT、MD、BIAS_P、TSENSE、LOS_SD和IROP引脚的输出电压进行测试，还用于对限幅放大器LA和激光驱动器LDD的输出幅度进行测试。
  8. 根据权利要求1所述的光收发芯片的自动测试装置，其特征 在于，所述EEPROM模块包括一AT24C08芯片，所述AT24C08芯片的WA引脚用于接收高低电平切换，使得数据可以进行读取或保护，并使得数据初始化时EEPROM的数据通过其SDA引脚和SCL引脚正常导入所述光收发芯片。
  9. 根据权利要求1所述的光收发芯片的自动测试装置，其特征在于，所述自动测试装置还包括示波器，所述示波器与所述光收发芯片相连用于输出检测波形。
  10. 一种光收发芯片的自动测试方法，其特征在于，包括：
    使用稳压电源模块为光收发芯片提供+3.3V电源，为各继电器开关提供+5V电源；
    上位机测试模块依次进行复位测试和光收发芯片的RAM测试，并对光收发芯片进行数据初始化及导入测试数据配置表，通过MCU控制模块控制继电器开关实现高低电平切换，对寄存器地址进行检测判断，检测正确后进入预设参数测试，测试完成输出测试结果；所述预设参数测试包括OMA告警测试、ROP告警测试、ADC测试、TX_FAULT测试、低电压测试、模拟量测试、TX_DISABLE测试和限幅放大器LA失调测试；所述模拟量测试包括对光收发芯片的RREF、TX_FAULT、MD、BIAS_P、TSENSE、LOS_SD和IROP引脚的输出电压进行测试，还包括对限幅放大器LA和激光驱动器LDD的输出幅度进行测试。
PCT/CN2018/077365 2017-03-23 2018-02-27 一种光收发芯片的自动测试装置及方法 WO2018171389A1 (zh)

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