WO2018166450A1 - 一种通信设备及增益控制方法 - Google Patents

一种通信设备及增益控制方法 Download PDF

Info

Publication number
WO2018166450A1
WO2018166450A1 PCT/CN2018/078873 CN2018078873W WO2018166450A1 WO 2018166450 A1 WO2018166450 A1 WO 2018166450A1 CN 2018078873 W CN2018078873 W CN 2018078873W WO 2018166450 A1 WO2018166450 A1 WO 2018166450A1
Authority
WO
WIPO (PCT)
Prior art keywords
mipi
gpio
instruction
module
transceiver
Prior art date
Application number
PCT/CN2018/078873
Other languages
English (en)
French (fr)
Inventor
刘道明
刘志钢
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2018166450A1 publication Critical patent/WO2018166450A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/04—TPC
    • H04W52/52—TPC using AGC [Automatic Gain Control] circuits or amplifiers

Definitions

  • Embodiments of the present invention relate to the field of chip technologies, and in particular, to a communication device and a gain control method.
  • the metal Since the metal has the function of shielding the signal of the mobile phone, the metal energy of the mobile phone body will cause the energy of the mobile phone signal radiation to decrease; and when designing the mobile phone, taking into account the standby time and appearance of the mobile phone, the space occupied by the antenna will be reduced. This will affect the antenna efficiency and reduce the signal power radiated by the antenna. Among them, the antenna efficiency can be improved by improving the conduction sensitivity, and the signal power radiated by the antenna can be improved.
  • the LNA can be set for the transceiver's external Low Noise Amplifier (LNA), which is the front-end module of the mobile phone.
  • LNA Low Noise Amplifier
  • the front-end module sends the signal received by the mobile phone antenna to the transceiver, and then the transceiver sends the signal to the baseband processor (BBP), and the BBP sends the signal to the multiple common
  • a General Purpose Input Output (GPIO) interface and a transceiver transmit a Mobile Industry Processor Interface (Mipi) command, and a plurality of GPIO interfaces and transceivers are integrated in a mobile phone's System On Chip (SoC);
  • Each GPIO interface converts the received mipi instruction into a GPIO instruction, and outputs a GPIO instruction to the front end module, so that the LNA of the front end module generates an amplification gain; after receiving the mipi instruction, the transceiver can generate an amplification according to the received mipi instruction.
  • Gain the front-end module sends the signal received by the mobile phone antenna to the transceiver, and then the transceiver sends the signal to the baseband processor (BBP),
  • the above method uses multiple GPIO interfaces to control the LNA of the front-end module, the SoC package area and cost of the mobile phone are excessively large; and, since the amplification gain of the LNA of the transceiver and the front-end module is synchronized, the improvement can be improved.
  • the gain of the mobile phone signal, while the time at which the LNA of the front-end module generates the amplification gain in the above method may not be synchronized with the timing at which the transceiver generates the amplification gain, and thus the gain of the signal cannot be improved, thereby improving the conduction sensitivity.
  • the present application provides a communication device and a gain control method, which can reduce the package area and cost of the SoC by using the mipi to GPIO module to control the front end module; and can achieve the purpose of generating the amplification gain synchronously by the front end module and the transceiver.
  • a communication device which may include: a BBP, a transceiver, a mipi to GPIO module, and at least one front end module.
  • the BBP is coupled to the transceiver and the mipi to GPIO module, respectively, and the mipi to GPIO module is coupled to at least one front end module, respectively, and the transceiver is coupled to at least one front end module.
  • the BBP is configured to send a mipi instruction to the mipi-to-GPIO module and the transceiver according to the preset first duration.
  • the first duration is when the BBP sends the mipi instruction to the mipi-to-GPIO module and the transceiver at the same time, the mipi-to-GPIO module and the transceiver respectively receive the time difference of the mipi instruction; or, the first duration is from the BBP in the same time.
  • the mipi command is sent to the mipi to GPIO module and the transceiver respectively, and the time difference of the amplification gain is generated by the at least one front end module and the transceiver respectively.
  • the transceiver is configured to receive the mipi instruction sent by the BBP, and generate an amplification gain when the mipi instruction is enabled.
  • the mipi to GPIO module is configured to receive the mipi instruction sent by the BBP, and convert the mipi instruction into a GPIO instruction to enable the GPIO instruction for at least one front end module, enabled by the mipi instruction.
  • At least one front end module is configured to respectively receive the GPIO instruction sent by the mipi to the GPIO module, and generate an amplification gain when the GPIO instruction is enabled.
  • the mipi to GPIO module can convert the mipi instruction sent by the BBP into a GPIO instruction, and send the GPIO instruction to at least one front end module, so that at least one front end module generates an amplification gain; and does not need to adopt multiple GPIO interfaces. Controlling at least one front end module produces an amplification gain, thereby reducing the package area and cost of the SoC.
  • the transceiver and the mipi to GPIO module respectively receive the time difference of the mipi instruction, so when the BBP is according to the preset first duration,
  • the mipi instruction is sent to the mipi to GPIO module and the transceiver respectively, it can ensure that the transceiver and the mipi to GPIO module can receive the mipi instruction at the same time; and, because of the time taken by the "transceiver to generate the amplification gain according to the mipi instruction" and "mipi"
  • the time taken to convert the mipi instruction to a GPIO instruction and the amplification gain is generated by at least one front-end module according to the GPIO instruction is relatively short.
  • the time taken by the transceiver to generate the amplification gain according to the mipi instruction and the mipi turn
  • the time difference between the time taken by the GPIO module to convert the mipi instruction to a GPIO instruction and the amplification gain generated by at least one front-end module based on the GPIO instruction is also small.
  • the transceiver and the at least one front-end module can generate the amplification gain within a certain time difference, that is, the transceiver and the mipi-to-GPIO module start from receiving the mipi command, and the time difference between the transceiver and the at least one front-end module generating the amplification gain is less than The predetermined time is reached, so that the transceiver and the at least one front end module simultaneously generate the amplification gain.
  • the first duration can also be a time difference between the transceiver and the at least one front-end module respectively generating the amplification gain from the time when the BBP sends the mipi command to the transceiver and the mipi to the GPIO module at the same time, respectively, when the BBP is based on the preset first
  • the transceiver and the at least one front-end module can simultaneously generate the amplification gain.
  • the communication device of the present application can reduce the package area and cost of the SoC, and can synchronize the transceiver and the at least one front-end module to generate amplification gain.
  • the mipi to GPIO module may include: a mii interface, a processing module, and an output module.
  • the mipi interface is used to receive the mipi command sent by the BBP.
  • the processing module is coupled to the mipi interface for converting the mipi instruction received by the mipi interface into a GPIO instruction and buffering the GPIO instruction.
  • An output interface for transmitting GPIO instructions to at least one front end module.
  • the transceiver may be further configured to: receive a mipi instruction sent by the BBP, and generate an amplification gain after the third period of time is enabled by the mipi instruction.
  • the transceiver can start generating the amplification gain in the mipi instruction after receiving the mipi instruction, or can start generating the amplification gain in the mipi instruction after the third time period.
  • the BBP when the BBP sends a mipi instruction to the transceiver and the mipi to GPIO module at the same time, the transceiver and the mipi to GPIO module respectively receive the mipi.
  • the BBP can also be used to control the mipi to GPIO module to send a GPIO command to at least one front end module after a second time period from the receipt of the mipi instruction.
  • the second duration is when the transceiver and the mipi-to-GPIO module receive the mipi command, and the transceiver and the at least one front-end module generate a time difference of the amplification gain.
  • the transceiver and the at least one front end module respectively generate a time difference of the amplification gain; therefore, the transceiver and the mipi to GPIO module can receive simultaneously.
  • the BBP controls the mipi to GPIO module to send a GPIO command to at least one front end module after receiving the second duration from the mipi instruction, it is ensured that the transceiver and the at least one front end module simultaneously generate amplification gain.
  • the BBP sends a mipi command to the mipi-to-GPIO module and the transceiver according to the preset first duration, so that the transceiver and the mipi-to-GPIO module can receive the mipi command simultaneously.
  • the BBP may be specifically configured to: send a first command to the transceiver, where the first command carries a second duration, where the first command is used to instruct the transceiver to After receiving the second duration of the start of the mipi instruction, the mipi to GPIO module sends an enable command.
  • the enable command is used to instruct the mipi to GPIO module to send a GPIO command to the at least one front end module.
  • the enable command can be a sync signal, and the value of the sync signal can be 0 or 1.
  • the BBP can be preset to have an enable command for instructing the mipi to GPIO module to send a GPIO command to at least one front end module when the value of the synchronization signal is one.
  • the BBP may also be preset to enable the mipi to GPIO module to send a GPIO command to the at least one front end module when the value of the synchronization signal is zero.
  • At least one front end module may have generated an amplification gain or at least one front end module does not include an LNA, at least one front end module does not need to generate an amplification gain, so
  • the BBP may determine whether at least one front end module needs to generate an amplification gain before transmitting the first command to the transceiver.
  • the BBP can also be used to: determine that at least one front end module does not generate an amplification gain; and send a second command to the transceiver, the second command is used to instruct the transceiver to send a prohibition instruction to the mipi to GPIO module after receiving the mipi instruction.
  • the prohibition instruction may be used to instruct the mipi to GPIO module not to send the GPIO instruction to the at least one front end module.
  • the disable command may be a sync signal, and the sync signal may have a value of 0 or 1.
  • the BBP can be preset to disable the instruction to instruct the mipi to GPIO module not to send a GPIO command to at least one front end module when the value of the synchronization signal is one.
  • the BBP may also be preset to disable the instruction to instruct the mipi to GPIO module not to send a GPIO command to at least one front end module when the value of the synchronization signal is zero.
  • a gain control method is provided.
  • the BBP is coupled to a transceiver and a mipi to GPIO module, respectively, and the mipi to GPIO module is coupled to at least one front end module, respectively.
  • the method of the present application may include: the BBP sends a mipi instruction to the mipi to the GPIO module and the transceiver according to the preset first duration, respectively, instructing the mipi to GPIO module to convert the mipi instruction into the GPIO instruction by using the mipi instruction.
  • the GPIO instruction is provided for the at least one front end module to enable the at least one front end module to generate an amplification gain when the GPIO instruction is enabled, instructing the transceiver to generate an amplification gain when the mipi instruction is enabled.
  • the first duration is when the BBP sends the mipi instruction to the mipi-to-GPIO module and the transceiver at the same time, the mipi-to-GPIO module and the transceiver respectively receive the time difference of the mipi instruction; or, the first duration is from the BBP in the same time.
  • the mipi command is sent to the mipi to GPIO module and the transceiver respectively, and the time difference of the amplification gain is generated by the at least one front end module and the transceiver respectively.
  • the mipi instruction sent by the BBP can be converted into a GPIO instruction by the mipi to GPIO module, and the GPIO instruction is sent to at least one front end module, so that at least one front end module generates an amplification gain; and does not need to adopt multiple GPIO interface control. At least one front end module produces an amplification gain, thereby reducing the package area and cost of the SoC.
  • the transceiver and the mipi to GPIO module respectively receive the time difference of the mipi instruction, so when the BBP is according to the preset first duration
  • the transceiver and the mipi to GPIO module can receive the mipi instruction at the same time; and, because of the time taken by the "transceiver to generate the amplification gain according to the mipi instruction" and "
  • the mipi to GPIO module converts the mipi instruction to a GPIO instruction, and the time taken by at least one front-end module to generate an amplification gain based on the GPIO instruction is relatively short.
  • the time taken by the "transceiver to generate amplification gain according to the mipi instruction" and "mipi” The time difference between the time taken to convert the mipi instruction to a GPIO instruction and the amplification gain generated by at least one front-end module based on the GPIO instruction is also small.
  • the transceiver and the at least one front-end module can generate the amplification gain within a certain time difference, that is, the transceiver and the mipi-to-GPIO module start from receiving the mipi command, and the time difference between the transceiver and the at least one front-end module generating the amplification gain is less than The predetermined time, so that the front-end module and the transceiver synchronize to generate amplification gain.
  • the first duration can also be a time difference between the transceiver and the at least one front-end module respectively generating the amplification gain from the time when the BBP sends the mipi command to the transceiver and the mipi to the GPIO module at the same time, respectively, when the BBP is based on the preset first
  • the transceiver and the at least one front-end module can simultaneously generate the amplification gain.
  • the gain control method of the present application can reduce the package area and cost of the SoC, and can cause the transceiver and the at least one front end module to simultaneously generate an amplification gain.
  • the method of the present application may further include: the BBP controlling the mipi to GPIO module to send the GPIO instruction to the at least one front end module after the second time period from the receipt of the mipi instruction.
  • the second time period is when the transceiver and the mipi to GPIO module receive the mipi command at the same time, the transceiver and the at least one front end module respectively generate a time difference of the amplification gain.
  • the transceiver and the at least one front end module respectively generate a time difference of the amplification gain; therefore, the transceiver and the mipi to GPIO module can receive simultaneously.
  • the BBP controls the mipi to GPIO module to send a GPIO command to at least one front end module after receiving the second duration from the mipi instruction, it is ensured that the transceiver and the at least one front end module simultaneously generate amplification gain.
  • the BBP sends a mipi command to the mipi-to-GPIO module and the transceiver according to the preset first duration, so that the transceiver and the mipi-to-GPIO module can receive the mipi command simultaneously.
  • the method for the “BBP control mipi to GPIO module sends a GPIO command to at least one front-end module after receiving the mipi instruction for a second time period” may include: BBP Sending a first command to the transceiver, where the first command carries a second duration, the first command is used to instruct the transceiver to send an enable command to the mipi-to-GPIO module after receiving the second duration from the mipi command.
  • the enable command is used to instruct the mipi to GPIO module to send a GPIO command to the at least one front end module.
  • the BBP may send the first command to the transceiver, so that after receiving the second duration of the mipi instruction, the transceiver sends an enable command to the mipi to the GPIO module, so that the mipi to GPIO module receives the second command.
  • the GPIO command is sent to the at least one front end module, so that at least one front end module generates an amplification gain.
  • At least one front end module may have generated an amplification gain or at least one front end module does not include an LNA, at least one front end module does not need to generate an amplification gain, so
  • the BBP may determine whether at least one front end module needs to generate an amplification gain before transmitting the first command to the transceiver.
  • the method of the present application may further include: the BBP determines that at least one front end module does not generate an amplification gain; the BBP sends a second command to the transceiver, where the second command may be used to instruct the transceiver to transfer the mipi to the GPIO after receiving the mipi instruction.
  • the module sends a disable instruction.
  • the prohibition instruction may be used to instruct the mipi to GPIO module not to send the GPIO instruction to the at least one front end module.
  • the second command may be sent to the mipi-to-GPIO module, so that after receiving the mipi instruction, the transceiver directly sends a prohibition instruction to the mipi-to-GPIO module, and the prohibition instruction may be
  • the synchronization signal may have a value of 0 or 1.
  • the BBP can be preset to disable the instruction to instruct the mipi to GPIO module not to send a GPIO command to at least one front end module when the value of the synchronization signal is one.
  • the BBP may also be preset to disable the instruction to instruct the mipi to GPIO module not to send a GPIO command to at least one front end module when the value of the synchronization signal is zero.
  • FIG. 1 is a schematic structural diagram of a conventional communication device
  • FIG. 2 is a schematic structural diagram 1 of a communication device according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a mipi-to-GPIO module according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram 2 of a communication device according to an embodiment of the present disclosure.
  • FIG. 5 is a flowchart 1 of a gain control method according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of an example of determining a first duration of a BBP according to an embodiment of the present disclosure
  • FIG. 7 is a second flowchart of a gain control method according to an embodiment of the present invention.
  • FIG. 8 is a flowchart 3 of a gain control method according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of an example of operation timing of a gain control method according to an embodiment of the present disclosure.
  • FIG. 10 is a flowchart 4 of a gain control method according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of an example of a gain control method according to an embodiment of the present invention.
  • the communication device and the gain control method provided by the embodiments of the present invention can be applied to the process of controlling the amplification gain synchronization.
  • the BBP can be applied to the process in which the BBP controls the transceiver and the at least one front-end module to generate the amplification gain synchronously through the mipi command.
  • the communication device 10 can include a BBP 100, at least one GPIO interface (such as GPIO interface 201 and GPIO interface 202), a transceiver 300, and at least one front end module (such as front end module 401 and front end module 402).
  • GPIO interface such as GPIO interface 201 and GPIO interface 202
  • transceiver 300 such as transceiver 300
  • front end module such as front end module 401 and front end module 402
  • the BBP 100 is coupled to the transceiver 300, the GPIO interface 201, and the GPIO interface 202, the GPIO interface 201 is coupled to the front end module 401, the GPIO interface 202 is coupled to the front end module 402, and the transceiver 300 is coupled to the front end module 401 and the front end, respectively.
  • Module 402 is coupled, and front end module 401 and front end module 402 are also coupled to the antenna, respectively.
  • the front end module 401 and the front end module 402 respectively include an LNA. When the front end module 401 and the front end module 402 respectively receive the wireless signal from the antenna, the front end module 401 and the front end module 402 can respectively generate an amplification gain for receiving the wireless signal.
  • the transceiver 300 includes an amplification module (eg, an LNA integrated in the transceiver) that can be used to generate an amplification gain for the wireless signals amplified by the front end module 401 and the front end module 402, respectively.
  • the BBP 100 can be used to send a mipi command to at least one GPIO interface and transceiver 300 and control the transceiver 300 and a front end module corresponding to at least one GPIO interface to generate an amplification gain.
  • the mutual coupling between the modules in the embodiment of the present invention may be a way of connecting the modules through a wired connection or a method of connecting by wireless.
  • the BBP 100 and the transceiver 300 may be wired or wireless.
  • the front end module 401 and the front end module 402 can transmit the received signal to the transceiver 300 through a channel with the transceiver 300, and then the transceiver 300 transmits a signal to the BBP 100; the BBP 100 is receiving
  • the mipi instruction can be sent to the GPIO interface 201 through the mipi_0 channel
  • the mipi instruction can be sent to the GPIO interface 202 through the mipi_1 channel
  • the mipi instruction can be sent to the transceiver 300 through the mipi_2 channel.
  • the GPIO interface 201 can convert the received mipi instruction into a GPIO instruction and output the GPIO instruction to the front end module 401.
  • the GPIO interface 202 can convert the received mipi instruction into a GPIO instruction and output the GPIO instruction to the front end module 402.
  • the front end module 401 and the front end module 402 are caused to generate an amplification gain; after receiving the mipi instruction, the transceiver 300 can generate an amplification gain according to the received mipi instruction.
  • the mipi instruction in the embodiment of the present invention may be an enable command for enabling the transceiver 300 to generate an amplification gain for enabling the GPIO interface 201 and the GPIO interface 202 to generate a GPIO instruction; the GPIO instruction may also be The command can be used to enable the front end module 401 and the front end module 402 to generate an amplification gain.
  • the BBP 100 needs to control the front end module 401 and the front end module 402 by using two GPIO interfaces respectively, which may cause the package area and cost of the SoC to be excessive; and, because the time taken by the at least one front end module to generate the amplification gain and the transceiver 300 generate the amplification gain.
  • the time used may vary, so after the BBP 100 sends the mipi command to the plurality of GPIO interfaces and the transceiver 300, respectively, the transceiver 300 and the at least one front end module are not capable of simultaneously generating the amplification gain.
  • the communication device 11 may include: a BBP 100, a mipi-to-GPIO module 203, a transceiver 300, and at least one front-end module (such as a front-end module). 401 and front end module 402).
  • the BBP 100 is coupled to the transceiver 300 and the mipi to GPIO module 203, respectively, and the mipi to GPIO module 203 is coupled to the front end module 401 and the front end module 402, respectively, and the transceiver 300 is coupled to the front end module 401 and the front end module 402, respectively.
  • the BBP 100 is configured to send a mipi instruction to the mipi-to-GPIO module 203 through the mipi_0 channel according to the preset first duration, and send a mipi instruction to the transceiver 300 through the mipi_1 channel.
  • the mipi to GPIO module 203 is configured to receive the mipi instruction sent by the BBP 100, and convert the mipi instruction into a GPIO instruction, and provide the GPIO instruction to the front end module 401 and the front end module 402 to enable the front end module 401 to be enabled by the mipi instruction. And the front end module 402 generates an amplification gain with the GPIO command enabled.
  • the transceiver 300 is configured to receive the mipi instruction sent by the BBP 100, and generate an amplification gain when the mipi instruction is enabled.
  • the first duration is when the BBP 100 sends the mipi command to the transceiver 300 and the mipi to GPIO module 203 at the same time, respectively, the transceiver 300 and the mipi to GPIO module 203 respectively receive the time difference of the mipi instruction; or, the first duration To transmit a mipi command from the BBP 100 to the transceiver 300 and the mipi to GPIO module 203 at the same time, respectively, the transceiver 300 and at least one front end module (such as the front end module 401 and the front end module 402) respectively generate a time difference of the amplification gain.
  • the transceiver 300 and at least one front end module such as the front end module 401 and the front end module 402
  • the communication device 11 of the present invention may be a multi-antenna multi-channel communication device, that is, each front-end module corresponds to one antenna (not shown), and the communication device 11 of the present invention may also be a single antenna.
  • the communication device, that is, the plurality of front-end modules are coupled to the same antenna, and the BBP 100 completes the reception of the wireless signal by enabling one of the front-end modules. Since the amplification gains of the plurality of front-end modules are different from each other, multiple gain files can be provided. Bits to meet different design needs.
  • the communication device may convert the mipi instruction sent by the BBP into a GPIO instruction by the mipi to GPIO module, and send the GPIO instruction to the at least one front end module, so that at least one front end module generates an amplification gain;
  • the use of multiple GPIO interfaces controls at least one front-end module to generate amplification gain, thereby reducing the package area and cost of the SoC.
  • the transceiver 300 and the mipi-to-GPIO module 203 respectively transmit the mipi command to the transceiver 300 and the mipi-to-GPIO module 203 when the BBP 100 transmits the mipi command to the transceiver 300 and the mipi-to-GPIO module 203 at the same time.
  • the time difference of the mipi instruction is received; therefore, when the BBP 100 transmits the mipi instruction to the mipi to GPIO module 203 and the transceiver 300 respectively according to the preset first duration, it can be ensured that the transceiver 300 and the mipi to GPIO module 203 can simultaneously Received mipi command.
  • the time taken by "the transceiver 300 generates the amplification gain according to the mipi instruction” and the time taken by "mipi to GPIO module 203 to convert the mipi instruction into a GPIO instruction and the amplification gain is generated by at least one front-end module according to the GPIO instruction” are compared. Short, therefore, the time taken by "transceiver 300 generates amplification gain according to mipi instruction” and the time taken by "mipi to GPIO module 203 to convert mipi instruction to GPIO instruction and generate amplification gain by at least one front-end module according to GPIO instruction” The time difference will be smaller.
  • the transceiver 300 and the at least one front-end module can generate amplification gain within a certain time difference, that is, the transceiver 300 and the mipi-to-GPIO module 203 start from receiving the mipi command, and the transceiver 300 and the at least one front-end module generate amplification gain.
  • the time difference is less than the predetermined time, so that the transceiver 300 and the at least one front end module simultaneously generate the amplification gain.
  • the transceiver 300 and the at least one front-end module respectively generate a time difference of the amplification gain; therefore, when the mipi instruction is respectively sent to the mipi to GPIO module 203 and the transceiver 300 according to the preset first duration, the transceiver 300 and the transceiver 300 can be guaranteed.
  • At least one front end module simultaneously produces an amplification gain.
  • the communication device of the present application can reduce the package area and cost of the SoC, and can synchronize the transceiver and the at least one front-end module to generate amplification gain.
  • the mipi-to-GPIO module 203 shown in FIG. 2 may include a mipi interface 2001, a processing module 2002, and an output module 2003.
  • the mipi interface 2001 can be used to receive the mipi instruction sent by the BBP 100.
  • the above mipi instruction may include mipi data and a mipi clock sequence, the SDATA port in the mipi interface 2001 is used to receive mipi data, and the SCLK port in the mipi interface 2001 is used to receive the mipi clock sequence.
  • the processing module 2002 is coupled to the mipi interface 2001, and the processing module 2002 can be used to convert the mipi instruction received by the mipi interface 2001 into a GPIO instruction and cache the GPIO instruction.
  • the output interface 2003 is configured to separately send the GPIO instructions to the at least one front end module.
  • the processing module 2002 can write the mipi instruction received by the mipi interface 2001 into the register 1 (Register, Reg), and according to the mapping of the bits D0-D7 and GPIO_0-GPIO_7 in Reg1.
  • the relationship is decoded by decoding the 8 bits in Reg1 to the GPIO_7-GPIO_0 port.
  • the mipi to GPIO module 203 may further include: a power supply module.
  • the power supply module can be used to power the various parts of the mipi to GPIO module 203.
  • the power supply voltage (Voltage Device Device, VDD) can supply power to the mipi interface 2001, the processing module 2002, and the output module 2003.
  • the input and output voltages (VIO) can supply power to the SDATA port and the SCLK port.
  • the mipi-to-GPIO module in the embodiment of the present invention can be used not only to control at least one front-end module, but also to control a power amplifier, an antenna switch, an antenna coordinator, and the like.
  • the first duration is “When the BBP 100 sends the mipi command to the transceiver 300 and the mipi to GPIO module 203 at the same time, the transceiver 300 and the mipi to GPIO module 203 respectively receive When the time difference to the mipi command is reached, even if the BBP transmits the mipi command to the mipi-to-GPIO module 203 and the transceiver 300 according to the preset first duration, the transceiver 300, the front-end module 401, and the front-end module 402 cannot simultaneously generate the amplification gain.
  • the time difference between the transceiver 300, the front end module 401, and the front end module 402 for generating the amplification gain can be ensured to be less than the predetermined time, that is, the transceiver and the at least one front end module can generate the amplification gain within a certain time difference.
  • the BBP 100 can also be used to control the mipi to GPIO module 203 to the front end module 401 and the front end module 402 after the second time period from the receipt of the mipi instruction. Send a GPIO command.
  • the transceiver 300 and the at least one front-end module (such as the front-end module 401 and the front-end module 402) respectively generate a time difference of the amplification gain.
  • the second duration can be that the transceiver 300 and the mipi-to-GPIO module 203 receive the mipi command simultaneously, the transceiver 300 and the at least one front-end module respectively generate a time difference of the amplification gain; therefore, in the "transceiver 300 and the mipi-to-GPIO module 203"
  • the transceiver 300 and the at least one front-end module respectively generate a time difference of the amplification gain; therefore, in the "transceiver 300 and the mipi-to-GPIO module 203"
  • the BBP 100 controls the mipi to GPIO module 203 to send a GPIO command to at least one front end module after receiving the second time period from the reception of the mipi instruction, the transceiver 300 and at least one can be guaranteed.
  • the front end module simultaneously produces amplification gain.
  • the BBP 100 sends a mipi command to the mipi-to-GPIO module 203 and the transceiver 300 according to the preset first duration, so that "the transceiver 300 and the mipi-to-GPIO module 203 can receive the mipi command simultaneously".
  • the BBP 100 can control the mipi-to-GPIO module 203 to receive the second from the receipt of the mipi command by sending a first command to the transceiver 300 (the second command carries the second duration). After the duration, the GPIO command is sent to the front end module 401 and the front end module 402.
  • the first command is used to instruct the transceiver 300 to send an enable command to the mipi-to-GPIO module 203 after receiving the second duration from the start of the mipi command.
  • the transceiver 300 can execute the second time period from the receipt of the mipi command, and then send an enable command to the mipi to GPIO module 203 to instruct the mipi to GPIO module 203 to the front end module 401 and the front end.
  • Module 402 sends a GPIO command.
  • the above enable command may be a synchronization signal, and the value of the synchronization signal may be 0 or 1.
  • the BBP 100 can be preset to enable the mipi-to-GPIO module 203 to send a GPIO command to at least one front-end module when the value of the synchronization signal is one.
  • the BBP 100 may also preset that when the value of the synchronization signal is 0, the enable command is used to instruct the mipi to GPIO module 203 to send a GPIO command to the at least one front end module.
  • the synchronization signal duration is one mipi instruction period. After the period is exceeded, the transceiver 300 sets the synchronization signal to zero.
  • the front end module 401 and the front end module 402 may have generated amplification gains or the front end module 401 and the front end module 402 do not include an LNA, that is, the front end module 401 and the front end module 402 may not need to generate amplification gain, and the BBP 100 may First determining whether the front end module 401 and the front end module 402 need to generate an amplification gain, and sending a command to the transceiver 300 according to the determination result, the command is used to instruct the transceiver 300 to send an enable command or a disable command to the mipi to GPIO module 203.
  • the command can be a synchronization signal, and the value of the synchronization signal can be 0 or 1.
  • the BBP 100 can be further configured to: determine that at least one front end module does not need to generate an amplification gain; and send a second command to the transceiver 300, the second command is used to instruct the transceiver 300 to send mipi after receiving the mipi instruction.
  • the GPIO module 203 sends a disable command.
  • the prohibition instruction may be used to instruct the mipi to GPIO module 203 not to send GPIO instructions to at least one front end module (such as the front end module 401 and the front end module 402).
  • the BBP 100 can obtain the service status of the communication device (such as the terminal device or the base station) where the BBP 100 is located. If the service condition acquired by the BBP 100 is that at least one front-end module has generated amplification gain or at least one front-end module does not include When there is an LNA, the BBP 100 can be used to send a second command to the transceiver 300, so that the transceiver 300 sends a disable command to the mipi-to-GPIO module 203, and the disable command can be a synchronization signal, and the value of the synchronization signal can be 0. Or 1.
  • the BBP can be preset to disable the instruction to instruct the mipi to GPIO module not to send a GPIO command to at least one front end module when the value of the synchronization signal is one.
  • the BBP may also be preset to disable the instruction to instruct the mipi to GPIO module not to send a GPIO command to at least one front end module when the value of the synchronization signal is zero.
  • the BBP pre-set enable command is a synchronization signal, and the value of the synchronization signal is 1, then when the BBP preset pre-set command is a synchronization signal, the value of the synchronization signal is 0; If the BBP preset enable command is a synchronization signal, and the value of the synchronization signal is 0, then the synchronization signal has a value of 1 when the BBP preset disable command is a synchronization signal.
  • the communication device provided by the embodiment of the present invention may further include at least two mipi-to-GPIO modules.
  • two mipi-to-GPIO modules may be included in the communication device 11 as shown in FIG.
  • the communication device 11 may include a mipi-to-GPIO module 204 and a front-end module 403 in addition to the BBP 100, the transceiver 300, and the mipi-to-GPIO module 203 as shown in FIG.
  • the mipi to GPIO module 204 is coupled to the BBP 100, and the mipi to GPIO module 204 is coupled to at least one front end module. For example, as shown in FIG. 4, the mipi to GPIO module 204 is coupled to the front end module 403.
  • the BBP 100 may be configured to send a mipi instruction to the mipi to GPIO module 203 through the mipi_0 channel according to the preset first duration, send a mipi instruction to the transceiver 300 through the mipi_1 channel, and send the mipi to the mipi to GPIO module 204 through the mipi_2 channel. instruction,
  • the mipi to GPIO module 204 can be used to receive the mipi instruction sent by the BBP 100.
  • the mipi instruction is converted to a GPIO instruction by the mipi instruction, and the front end module 403 is provided with a GPIO instruction, so that the front end module 403 is in the GPIO.
  • the amplification gain is generated by the enable of the instruction.
  • the transceiver 300 is configured to receive a mipi instruction sent by the BBP 100, and generate an amplification gain by using the mipi instruction.
  • the communication device 11 provided by the embodiment of the present invention can implement the synchronization gain generated by the transceiver 300, the front end module 401, the front end module 402, and the front end module 403.
  • the communication device provided by the embodiment of the invention can not only reduce the encapsulation area and cost of the SoC, but also realize the synchronization gain of the transceiver and the at least one front-end module, and can also control the transceiver to the mipi according to the actual service condition of the communication device where the BBP is located.
  • the GPIO module sends a first command or a second command.
  • the embodiment of the invention provides a gain control method, which can be applied to the above communication device.
  • the gain control method may include S501-S506:
  • S501 and BBP determine the first duration.
  • the first duration is when the BBP sends the mipi instruction to the transceiver and the mipi to GPIO module at the same time, respectively, the time difference between the transceiver and the mipi to GPIO module respectively receiving the mipi instruction .
  • the transceiver and the mipi to GPIO module receive the mipi instruction at different times, that is, the transceiver and the mipi to GPIO module cannot receive the mipi at the same time.
  • the instruction may cause the transceiver and the at least one front-end module to fail to generate the amplification gain simultaneously; therefore, in order to ensure that the transceiver and the mipi-to-GPIO module can simultaneously receive the mipi instruction, the BBP can determine that the BBP is separately addressed to the transceiver and When the mipi to GPIO module sends the mipi command, the transceiver and the mipi to GPIO module respectively receive the time difference (ie, the first duration) of the mipi command, and then can send the mipi instruction to the transceiver and the mipi to GPIO module according to the first duration.
  • the time difference ie, the first duration
  • the BBP can send the mipi instruction to the transceiver and the mipi to GPIO module at the same time, and record the BBP transmission and reception in the non-volatile (Nonvolatile, NV) item of the communication device (such as the terminal device or the base station) where the BBP is located. And the time when the mipi to GPIO module sends the mipi command (recorded as the first time), and then records the time at which the transceiver acquired from the transceiver receives the mipi command (recorded as the second time) in the NV item, in the NV item.
  • the mipi to GPIO module sends the mipi command (recorded as the first time)
  • the time at which the transceiver acquired from the transceiver receives the mipi command (recorded as the second time) in the NV item, in the NV item.
  • the BBP determines to send the mipi command from the BBP to the receiving and receiving according to the first time and the second time recorded in the NV item.
  • the time required for the machine to receive the mipi command (recorded as the first time); the BBP determines that the mipi instruction is sent from the BBP according to the first time and the third time recorded in the NV item, and is required to receive the mipi instruction from the mipi to the GPIO module.
  • Time (recorded as the second time); BBP calculates the difference between the first time and the second time, obtains the first duration, and records it in the NV term.
  • the time from "starting the mipi instruction from BBP to receiving the mipi instruction from mipi to GPIO module” is greater than the time required from “starting from the BBP to send the mipi instruction to the radio transceiver module receiving the mipi instruction”.
  • the first time recorded by the BBP in the NV item of the mobile phone ie, the time when the BBP sends the mipi command to the transceiver and the mipi to the GPIO module
  • the second time of recording ie, the transceiver receives the mipi.
  • the time of the instruction is t2, and the third time of recording (that is, the time when the mipi to GPIO module receives the mipi instruction) is t3, then the first time determined by BBP is t2-t1, and the second time determined by BBP is t3-t1.
  • the BBP calculates the difference between the first time and the second time as t3-t1-(t2-t1), that is, the first duration in the first application scenario is t3-t2.
  • the first duration is that when the BBP sends the mipi instruction to the transceiver and the mipi to GPIO module at the same time, the transceiver and the at least one front end module respectively generate a time difference of the amplification gain.
  • the transceiver and the at least one front end module respectively generate amplification gains.
  • the time difference ie, the first duration
  • the BBP can send the mipi instruction to the transceiver and the mipi to GPIO module at the same time, and record the time when the BBP sends the mipi instruction to the transceiver and the mipi to the GPIO module in the NV item of the device where the BBP is located (denoted as the first At a moment), then in the NV item, the time at which the transceiver obtained from the transceiver generates the amplification gain (recorded as the fourth time) is recorded, and the front end module corresponding to the mipi to GPIO module acquired from the mipi to GPIO module is recorded in the NV item.
  • the time at which the amplification gain is generated (denoted as the fifth time); the BBP determines the time required to transmit the mipi command from the BBP to the transceiver to generate the amplification gain based on the first time and the fourth time recorded in the NV term (denoted as Three times); BBP determines the time required to send the mipi instruction from the BBP to the front end module corresponding to the mipi to GPIO module to generate the amplification gain according to the first time and the fifth time recorded in the NV item (recorded as the fourth time) BBP calculates the difference between the third time and the fourth time to obtain the first duration and records it in the NV term.
  • the time required to "generate the amplification gain from the start of the mipi instruction by the BBP to the front-end module corresponding to the mipi to GPIO module” is greater than the time required from the "transmission of the mipi instruction from the BBP to the amplification of the RF transceiver module".
  • the first time recorded by the BBP in the NV item of the mobile phone that is, the time when the BBP sends the mipi command to the transceiver and the mipi to the GPIO module
  • the fourth time recorded that is, the time when the transceiver generates the amplification gain
  • the fifth time recorded (ie, the time when the mipi to GPIO module corresponds to the front-end module generating the amplification gain) is t5, then the third time determined by BBP is t4-t1, and the fourth time determined by BBP is t5-t1, BBP calculation The difference between the three time and the fourth time is t5-t1-(t4-t1), that is, the first time length in the second application scenario is t5-t4.
  • S502 and BBP respectively send a mipi instruction to the mipi-to-GPIO module and the transceiver according to the preset first duration.
  • the mipi instruction may be an enable instruction, instructing the mipi to GPIO module to convert the mipi instruction into a GPIO instruction, and provide a GPIO instruction to at least one front end module to enable at least one front end module in the GPIO instruction.
  • an amplification gain is generated that instructs the transceiver to generate an amplification gain with the enable of the mipi command.
  • the first time duration is that when the BBP sends the mipi instruction to the transceiver and the mipi to the GPIO module at the same time, the transceiver and the mipi to GPIO module respectively receive the mipi instruction.
  • the time difference therefore, according to the preset first duration, the BBP sends the mipi instruction to the mipi to GPIO module and the transceiver respectively, so that the transceiver and the mipi to GPIO module can simultaneously receive the mipi instruction.
  • the first time (that is, the time required to send the mipi instruction from the BBP to the time the transceiver receives the mipi instruction) t2-t1 is 1 minute
  • the second time (ie, sending the mipi instruction from the BBP to the mipi to the GPIO module receiving The time required for the mipi instruction) t3-t1 is 3 minutes
  • the first duration t3-t2 in the first application scenario is 2 minutes.
  • BBP can send mipi instructions to mipi to GPIO module, then send mipi instructions to the transceiver after 2 minutes, so that the transceiver and mipi to GPIO module can receive mipi instructions at the same time.
  • the first time duration may also be that when the BBP sends the mipi instruction to the transceiver and the mipi to the GPIO module at the same time, the transceiver and the at least one front end module respectively generate the time difference of the amplification gain, so the BBP According to the preset first duration, when the mipi instruction is sent to the mipi to GPIO module and the transceiver respectively, the transceiver and the at least one front end module can simultaneously generate the amplification gain.
  • the third time ie, the time required to send the mipi instruction from the BBP to the transceiver to generate the amplification gain
  • t4-t1 the fourth time (ie, sending the mipi instruction from the BBP to at least one front-end module to generate the amplification gain)
  • the required time) t5-t1 is 4 minutes
  • the first time length t5-t4 in the second application scenario is 1 minute.
  • the BBP can first send the mipi command to the mipi to GPIO module, and then send the mipi command to the transceiver after 1 minute. This ensures that the transceiver and at least one front-end module can simultaneously generate amplification gain.
  • the transceiver receives the mipi instruction and generates an amplification gain by using the mipi instruction.
  • the transceiver includes an amplification module.
  • the amplification module in the transceiver generates an amplification gain when the mipi command is enabled.
  • the transceiver can start to generate the amplification gain after the mipi instruction is received, and the transceiver can also start the mipi instruction after a "waiting time" after receiving the mipi instruction.
  • the amplification gain is generated below.
  • the transceiver starts to generate the amplification gain under the mipi instruction after receiving the mipi instruction, or after receiving the mipi instruction, after a "waiting time", it starts to generate the amplification gain under the enable of the mipi instruction, as long as
  • the time difference between "the transceiver starts receiving the mipi instruction and generates the amplification gain" and "mipi to the GPIO module from receiving the mipi instruction to sending the GPIO instruction to at least one front-end module, so that at least one front-end module generates the amplification gain" is less than
  • the predetermined time that is, the transceiver and the at least one front end module can generate the amplification gain within a certain time difference, so that the transceiver and the at least one front end module can synchronously generate the amplification gain.
  • the mipi to GPIO module receives the mipi instruction and converts the mipi instruction into a GPIO instruction with the aid of the mipi instruction.
  • the mipi to GPIO module may include a mipi interface, a processing module, and an output module.
  • the processing module can convert the mipi instruction received by the mipi interface into a GPIO instruction after the mipi instruction receives the mipi instruction, and send the GPIO instruction to the at least one front end module through the output module.
  • the mipi to GPIO module sends a GPIO command to at least one front end module.
  • the GPIO instruction may be an enable instruction for instructing at least one front end module to generate an amplification gain when the GPIO instruction is enabled.
  • the time taken by the mipi to GPIO module to send the GPIO command to the at least one front end module is short, which can be neglected in the embodiment of the present invention.
  • the front end module receives the GPIO instruction and generates an amplification gain when the GPIO instruction is enabled.
  • the LNA of the front-end module can generate an amplification gain when the GPIO instruction is enabled.
  • the BBP after transmitting the mipi instruction to the transceiver and the mipi to GPIO module according to the determined first duration, the BBP can ensure that the transceiver and the mipi to GPIO module receive the mipi instruction at the same time.
  • the transceiver starts from receiving the mipi instruction, to generate the amplification gain" and "mipi to GPIO module from the receipt of the mipi instruction, to the GPIO command sent to at least one front-end module, so that at least one front-end module generates amplification
  • the time difference of the gain is less than the predetermined time, that is, the transceiver and the at least one front end module can generate the amplification gain within a certain time difference, so that the transceiver and the at least one front end module can synchronously generate the amplification gain.
  • the first time that is, the time required to send the mipi instruction from the BBP to the time when the transceiver receives the mipi instruction
  • t2-t1 the time required to send the mipi instruction from the BBP
  • the second time ie, sending the mipi instruction from the BBP
  • the time required for the mipi to GPIO module to receive the mipi command t3-t1
  • the first duration t3-t2 in the first application scenario is 2 minutes.
  • BBP can send the mipi instruction to the mipi to GPIO module, and then send the mipi instruction to the transceiver after 2 minutes.
  • the transceiver and the mipi to GPIO module can receive the mipi command at the same time; "the transceiver receives the mipi command from the receiver.
  • the time to generate the amplification gain is 2 minutes, "mipi to GPIO module starts from receiving the mipi instruction, and sends GPIO instructions to at least one front-end module, so that at least one front-end module generates amplification gain" for 1 minute.
  • the transceiver starts from receiving the mipi instruction, to the time when the amplification gain is generated" and "mipi to the GPIO module starts from receiving the mipi instruction, and sends a GPIO instruction to at least one front-end module, so that at least one front-end module generates amplification gain.
  • the time difference of time is less than the predetermined time, so that the transceiver and the at least one front end module can simultaneously generate the amplification gain.
  • S503 and S504-S506 can be simultaneously performed.
  • the embodiment of the present invention provides a gain control method, which can convert a mipi instruction sent by a BBP into a GPIO instruction by a mipi-to-GPIO module, and send the GPIO instruction to at least one front-end module, so that at least one front-end module generates an amplification gain; It is not necessary to use multiple GPIO interfaces to control at least one front-end module to generate amplification gain, thereby reducing the package area and cost of the SoC.
  • the transceiver and the mipi to GPIO module respectively receive the time difference of the mipi instruction, so when According to the preset first duration, the BBP sends the mipi instruction to the mipi to GPIO module and the transceiver respectively, so that the transceiver and the mipi to GPIO module can receive the mipi instruction at the same time.
  • the transceiver and the at least one front-end module can generate an amplification gain within a certain time difference, so that the transceiver and the at least one front-end module synchronously generate the amplification gain.
  • the first time duration may also be that when the BBP sends the mipi command to the transceiver and the mipi to the GPIO module at the same time, the transceiver and the at least one front end module respectively generate a time difference of the amplification gain, so
  • the BBP sends a mipi command to the mipi-to-GPIO module and the transceiver according to the preset first duration, it can ensure that the transceiver and the at least one front-end module simultaneously generate the amplification gain.
  • the gain control method provided by the embodiment of the present invention can reduce the package area and cost of the SoC, and realize that the transceiver and the at least one front end module generate the amplification gain synchronously.
  • the BBP sends a mipi instruction to the transceiver and the mipi to GPIO module according to the first duration, so that the transceiver and the mipi to GPIO module can receive the mipi instruction at the same time.
  • the method of the embodiment of the present invention may further include S701 and S702:
  • S701 and BBP determine the second duration.
  • the transceiver and the at least one front end module respectively generate a time difference of the amplification gain.
  • the BBP can send the mipi instruction to the mipi-to-GPIO module and the transceiver according to the preset first duration, so that the mipi-to-GPIO module and the transceiver can simultaneously receive the mipi instruction; then, the BBP can acquire at least A time when the front end module generates the amplification gain (referred to as the sixth time), and acquires the time at which the transceiver generates the amplification gain (referred to as the seventh time); the BBP calculates the second time length according to the sixth time and the seventh time.
  • the time required for the transceiver to start from receiving the mipi command to generate the amplification gain is greater than the mipi to GPIO module receiving the mipi command. At the beginning, it takes time for at least one front-end module to generate an amplification gain.
  • the sixth time acquired by the BBP ie, the time at which at least one front-end module generates the amplification gain
  • the seventh time acquired by the BBP ie, the time at which the transceiver generates the amplification gain
  • the second time period calculated by the BBP is For t7-t6.
  • the BBP controls the mipi to GPIO module to send a GPIO command to the at least one front end module after receiving the second duration from the mipi instruction.
  • the transceiver and the at least one front end module respectively generate a time difference of the amplification gain; therefore, the transceiver and the mipi to GPIO module can receive simultaneously.
  • the BBP controls the mipi to GPIO module to send a GPIO command to at least one front end module after receiving the second duration from the mipi instruction, it is ensured that the transceiver and the at least one front end module simultaneously generate amplification gain.
  • the BBP sends a mipi command to the mipi-to-GPIO module and the transceiver according to the preset first duration, so that the transceiver and the mipi-to-GPIO module can receive the mipi command simultaneously.
  • the second duration t7-t6 determined by the BBP is 1 minute
  • the BBP can control the mipi to GPIO module to send a GPIO instruction to at least one front end module 1 minute after receiving the mipi instruction, so that at least one front end module generates an amplification gain. This allows the transceiver and at least one front-end module to simultaneously generate amplification gain.
  • S505 shown in FIG. 5 can be replaced with S505a:
  • the S505a, mipi-to-GPIO module sends a GPIO command to at least one front-end module after receiving the second duration of the mipi command according to the control of the BBP.
  • the mipi-to-GPIO module After receiving the mipi instruction sent by the BBP, the mipi-to-GPIO module decodes and converts the mipi instruction to obtain a GPIO instruction, and sends a GPIO instruction to the at least one front-end module after the second time period, so that at least one front-end module is receiving The amplification gain is generated after the GPIO instruction.
  • the transceiver and the mipi to GPIO module Since the second duration is that the transceiver and the mipi to GPIO module receive the mipi instruction at the same time, the transceiver and the at least one front end module generate a time difference of the amplification gain; therefore, if the mipi to GPIO module receives the second duration from the mipi instruction Sending a GPIO command to at least one front end module enables the transceiver and the at least one front end module to simultaneously generate an amplification gain.
  • the first command (the second command carries the second duration) is sent to the transceiver by the BBP, so that the transceiver and the at least one front-end module synchronously generate the amplification gain.
  • S702 shown in FIG. 7 may be replaced by S702a
  • S505a shown in FIG. 7 may be replaced by S505b-S505e:
  • the first command carries a second duration, and the first command is used to instruct the transceiver to send an enable command to the mipi-to-GPIO module after receiving the second duration from the mipi command.
  • the enable command is used to instruct the mipi to GPIO module to send a GPIO command to at least one front end module.
  • the BBP may send the first command to the transceiver, so that after receiving the second duration of the mipi instruction, the transceiver sends an enable command to the mipi to GPIO module, so that the mipi to GPIO module is receiving.
  • the enable command the GPIO command is sent to the at least one front end module, so that at least one front end module generates an amplification gain.
  • the above enable command may be a synchronization signal, and the value of the synchronization signal may be 0 or 1.
  • the BBP can be preset to have an enable command for instructing the mipi to GPIO module to send a GPIO command to at least one front end module when the value of the synchronization signal is one.
  • the BBP may also be preset to enable the mipi to GPIO module to send a GPIO command to the at least one front end module when the value of the synchronization signal is zero.
  • the transceiver receives the first command sent by the BBP.
  • the first command is used to instruct the transceiver to send an enable command to the mipi-to-GPIO module after receiving the second duration from the start of the mipi instruction.
  • the transceiver may send an enable command to the mipi-to-GPIO module after receiving the second duration from the mipi command, so that the mipi-to-GPIO module receives at least one after receiving the enable command.
  • the front end module sends a GPIO command to cause at least one front end module to generate an amplification gain.
  • the enable command is used to instruct the mipi to GPIO module to send a GPIO command to the at least one front end module.
  • the GPIO instruction can be an enable command to enable at least one front end module to generate an amplification gain.
  • mipi to GPIO module When the S505e, mipi to GPIO module receives the enable command, it sends a GPIO command to at least one front end module.
  • the mipi to GPIO module can include a mii interface, a processing module, and an output module.
  • the processing module can convert the mipi instruction received by the mipi interface into a GPIO instruction, and send the GPIO instruction to the at least one front end module through the output module when receiving the enable instruction.
  • FIG. 9 shows a timing diagram of the operation of the mipi to GPIO module processing mipi instruction in the embodiment of the present invention.
  • the mipi to GPIO module can write the received mipi instruction to Reg1, and according to the mapping relationship between the bits D0-D7 and GPIO_0-GPIO_7 in Reg1, after the second duration td, the bits in Reg1
  • the value is decoded to the corresponding GPIO port for output.
  • the output value of the GPIO instruction in Figure 9 is marked as Vh from the low-to-high transition value
  • the output value of the GPIO instruction is marked as Vlow from the high-to-low transition value.
  • the timing of bit 0 and GPIO_0 output in Reg1 is shown in Figure 9.
  • the mipi to GPIO module decodes bit 0 in Reg1 into a GPIO_0 instruction and decodes it onto the GPIO_0 port.
  • the output value of the GPIO_0 instruction passes through After reaching the high level Vh after the second time td, the GPIO_0 instruction is output to at least one front end module.
  • At least one front end module may have generated an amplification gain or at least one front end module does not include an LNA. At this time, at least one front end module does not need to generate an amplification gain. Therefore, the BBP can determine whether the at least one front-end module needs to generate an amplification gain before transmitting the first command to the transceiver, and send a command to the transceiver according to the determination result, the command is used to instruct the transceiver to send the enable to the mipi-to-GPIO module. instruction.
  • the method of the embodiment of the present invention may further include S1001:
  • BBP determine whether at least one front end module generates an amplification gain.
  • the BBP can determine whether at least one front end module needs to generate an amplification gain by acquiring a service condition of the terminal or the base station. If at least one front end module has generated an amplification gain, or at least one front end module does not include an LNA, the BBP determines that at least one front end module does not need to generate an amplification gain.
  • S1002 The BBP sends a second command to the transceiver.
  • the second command is used to instruct the transceiver to send a prohibition instruction to the mipi to GPIO module after receiving the mipi instruction.
  • the disable instruction is used to instruct the mipi to GPIO module not to send GPIO instructions to at least one front end module.
  • the BBP may send a prohibition instruction to the mipi-to-GPIO module, so that the transceiver directly sends a prohibition instruction to the mipi-to-GPIO module after receiving the mipi instruction.
  • the BBP may send a second command to the transceiver, so that the transceiver sends a prohibition instruction to the mipi-to-GPIO module.
  • the prohibition command may be a synchronization signal, and the value of the synchronization signal may be 0 or 1.
  • the BBP can be preset to disable the instruction to instruct the mipi to GPIO module not to send a GPIO command to at least one front end module when the value of the synchronization signal is one.
  • the BBP may also be preset to disable the instruction to instruct the mipi to GPIO module not to send a GPIO command to at least one front end module when the value of the synchronization signal is zero.
  • the transceiver receives the second command sent by the BBP.
  • mipi to GPIO module does not send GPIO instructions to at least one front end module.
  • the BBP may generate the amplification gain regardless of whether the transceiver and the at least one front-end module are synchronized, and only need to send a second command to the transceiver, so that the transceiver receives the second.
  • the mipi to GPIO module is sent to the at least one front-end module to send a GPIO command whose output value is all 0, that is, the mipi-to-GPIO module does not send the GPIO command to the at least one front-end module.
  • the BBP may not send the first command or the second command to the transceiver, and the BBP only needs to send the mipi instruction to the transceiver and the mipi-to-GPIO module respectively. So that the transceiver and the mipi to GPIO module process data and the like according to the mipi instruction, respectively.
  • the BBP 100 can send a first command to the transceiver 300, which is carried in the first command.
  • the first command is used to instruct the transceiver 300 to send an enable command to the mipi to GPIO module 203 and the mipi to GPIO module 204 respectively after the second duration from the receipt of the mipi instruction.
  • the BBP 100 may send a first command to the transceiver 300, the first command is used to indicate transmission and reception. After receiving the second duration from the mipi command, the machine 300 transmits an enable command only to the mipi-to-GPIO module 203.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the modules or units is only a logical function division.
  • there may be another division manner for example, multiple units or components may be used. Combinations can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present invention which is essential or contributes to the prior art, or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) or a processor to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Transceivers (AREA)

Abstract

本发明实施例公开了一种通信设备及增益控制方法，涉及芯片技术领域，可以解决采用多个GPIO接口控制前端模块时需要的GPIO接口个数较多，导致的SoC的封装面积和成本过大的问题；并且，可以达到前端模块和收发机同步产生放大增益的目的。具体方案为：BBP根据预设的第一时长，分别向mipi转GPIO模块和收发机发送mipi指令，指示mipi转GPIO模块在mipi指令的使能下，将mipi指令转换为GPIO指令，为至少一个前端模块提供GPIO指令，以使至少一个前端模块在GPIO指令的使能下产生放大增益，指示收发机在mipi指令的使能下产生放大增益。本发明实施例应用于控制放大增益同步的过程中。

Description

一种通信设备及增益控制方法
本申请要求于2017年03月14日提交中国专利局、申请号为201710150893.1、申请人为“华为技术有限公司”、申请名称为《一种通信设备及增益控制方法》的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及芯片技术领域，尤其涉及一种通信设备及增益控制方法。
背景技术
由于金属具有屏蔽手机信号的功能，随着手机机身的金属化，会导致手机信号辐射的能量降低；并且在设计手机时，考虑到手机待机时长和外观，会缩减天线占用空间。这样会影响天线效率，降低天线辐射的信号功率。其中，可以通过提高传导灵敏度来提高天线效率，提升天线辐射的信号功率。
为了提高传导灵敏度，可以为手机中的收发机外置低噪声放大器(Low Noise Amplifier，LNA)，即为手机的前端模块设置LNA，当前端模块的LNA和收发机同步产生放大增益时，便可以提高手机信号的增益，从而提高传导灵敏度。
具体实现方式如下：前端模块将手机天线接收到的信号发送给收发机，然后收发机将该信号发送基带信号处理器(Base Band Processor，BBP)，BBP在接收到信号后，分别向多个通用输入输出(General Purpose Input Output，GPIO)接口和收发机发送移动处理器接口(Mobile Industry Processor Interface，Mipi)指令，多个GPIO接口和收发机集成在手机的片上系统(System On Chip，SoC)；每个GPIO接口将接收到的mipi指令转换为GPIO指令，并向前端模块输出GPIO指令，使得前端模块的LNA产生放大增益；收发机在接收到mipi指令后，可以根据接收到的mipi指令产生放大增益。
但是，由于上述方法是采用多个GPIO接口控制前端模块的LNA，因而会造成手机的SoC封装面积和成本过大；并且，由于当收发机和前端模块的LNA同步产生放大增益时，才可以提高手机信号的增益，而上述方法中的前端模块的LNA产生放大增益的时刻与收发机产生放大增益的时刻可能并不同步，因而无法提高信号的增益，进而提高传导灵敏度。
发明内容
本申请提供一种通信设备及增益控制方法，可以通过采用mipi转GPIO模块控制前端模块，减小SoC的封装面积和成本；并且可以达到前端模块和收发机同步产生放大增益的目的。
为达到上述目的，本申请采用如下技术方案：
本申请的第一方面，提供一种通信设备，该通信设备可以包括：BBP、收发机、mipi转GPIO模块和至少一个前端模块。BBP分别与收发机和mipi转GPIO模块相耦合，mipi转GPIO模块分别与至少一个前端模块相耦合，收发机分别与至少一个前端 模块相耦合。BBP，用于根据预设的第一时长，分别向mipi转GPIO模块和收发机发送mipi指令。其中，第一时长为当BBP在同一时刻分别向mipi转GPIO模块和收发机发送mipi指令时，mipi转GPIO模块和收发机分别接收到mipi指令的时间差；或者，第一时长为从BBP在同一时刻分别向mipi转GPIO模块和收发机发送mipi指令开始，到至少一个前端模块和收发机分别产生放大增益的时间差。收发机，用于接收BBP发送的mipi指令，并在mipi指令的使能下，产生放大增益。mipi转GPIO模块，用于接收BBP发送的mipi指令，并在mipi指令的使能下，将mipi指令转换为GPIO指令，为至少一个前端模块提供GPIO指令。至少一个前端模块用于分别接收mipi转GPIO模块发送的GPIO指令，并在GPIO指令的使能下，产生放大增益。
本申请中，可以由mipi转GPIO模块将BBP发送的mipi指令转换为GPIO指令，并将GPIO指令发送给至少一个前端模块，使至少一个前端模块产生放大增益；而并不需要采用多个GPIO接口控制至少一个前端模块产生放大增益，因此可以减小SoC的封装面积和成本。
由于第一时长可以为当BBP在同一时刻向收发机和mipi转GPIO模块发送mipi指令时，收发机和mipi转GPIO模块分别接收到mipi指令的时间差，因此当BBP根据预设的第一时长，分别向mipi转GPIO模块和收发机发送mipi指令时，便可以保证收发机和mipi转GPIO模块能够同时接收到mipi指令；并且，由于“收发机根据mipi指令产生放大增益”所用的时间和“mipi转GPIO模块将mipi指令转换为GPIO指令，并由至少一个前端模块根据GPIO指令产生放大增益”所用的时间都比较短，因此，“收发机根据mipi指令产生放大增益”所用的时间和“mipi转GPIO模块将mipi指令转换为GPIO指令，并由至少一个前端模块根据GPIO指令产生放大增益”所用的时间的时间差也会比较小。这样，可以保证收发机和至少一个前端模块可以在一定时间差内产生放大增益，也即收发机和mipi转GPIO模块从接收到mipi指令开始，到收发机和至少一个前端模块产生放大增益的时间差小于预定时间，从而达到收发机和至少一个前端模块同步产生放大增益的目的。
由于第一时长也可以为从BBP在同一时刻分别向收发机和mipi转GPIO模块发送mipi指令开始，到收发机和至少一个前端模块分别产生放大增益的时间差，因此当BBP根据预设的第一时长，分别向mipi转GPIO模块和收发机发送mipi指令时，便可以保证收发机和至少一个前端模块同时产生放大增益。
综上所述，本申请的通信设备可以减小SoC的封装面积和成本，可以使收发机和至少一个前端模块同步产生放大增益。
在本申请的一种实现方式中，mipi转GPIO模块可以包括：mipi接口、处理模块和输出模块。其中，mipi接口，用于接收BBP发送的mipi指令。处理模块与mipi接口相耦合，用于将mipi接口接收的mipi指令转换为GPIO指令，并缓存GPIO指令。输出接口，用于将GPIO指令分别发送给至少一个前端模块。
结合第一方面，在本申请的一种实现方式中，收发机，还可以用于：接收BBP发送的mipi指令，并经过第三时长后，在mipi指令的使能下产生放大增益。
其中，收发机可以在接收到mipi指令后，开始在mipi指令的使能产生放大增益，也可以在经过第三时长后，开始在mipi指令的使能产生放大增益。
结合第一方面，在本申请的一种实现方式中，在第一时长为当BBP在同一时刻分别向收发机和mipi转GPIO模块发送mipi指令时，收发机和mipi转GPIO模块分别接收到mipi指令的时间差的情况下，BBP还可以用于控制mipi转GPIO模块从接收到mipi指令开始的第二时长后，向至少一个前端模块发送GPIO指令。其中，第二时长为收发机和mipi转GPIO模块同时接收到mipi指令时，收发机和至少一个前端模块产生放大增益的时间差。
其中，由于第二时长为收发机和mipi转GPIO模块同时接收到mipi指令时，收发机和至少一个前端模块分别产生放大增益的时间差；因此，在“收发机和mipi转GPIO模块能够同时接收到mipi指令”的情况下，如果BBP控制mipi转GPIO模块从接收到mipi指令开始的第二时长后，向至少一个前端模块发送GPIO指令，便可以保证收发机和至少一个前端模块同时产生放大增益。其中，BBP根据预设的第一时长，分别向mipi转GPIO模块和收发机发送mipi指令，便可以保证“收发机和mipi转GPIO模块能够同时接收到mipi指令”。
结合第一方面，在本申请的一种实现方式中，BBP具体可以用于：向收发机发送第一命令，该第一命令中携带有第二时长，该第一命令用于指示收发机从接收到mipi指令开始的第二时长后，向mipi转GPIO模块发送使能指令。
其中，上述使能指令用于指示mipi转GPIO模块向至少一个前端模块发送GPIO指令。使能指令可以为同步信号，该同步信号的取值可以为0或1。BBP可以预先设定当同步信号的取值为1时，使能指令用于指示mipi转GPIO模块向至少一个前端模块发送GPIO指令。或者，BBP也可以预先设定当同步信号的取值为0时，使能指令用于指示mipi转GPIO模块向至少一个前端模块发送GPIO指令。
结合第一方面，在本申请的一种实现方式中，由于至少一个前端模块可能已经产生放大增益或者至少一个前端模块中未包含有LNA，此时，至少一个前端模块不需要产生放大增益，因此，BBP可以在向收发机发送第一命令之前，可以先确定至少一个前端模块是否需要产生放大增益。BBP还可以用于：确定至少一个前端模块均不产生放大增益；向收发机发送第二命令，该第二命令用于指示收发机在接收到mipi指令后，向mipi转GPIO模块发送禁止指令。
其中，禁止指令可以用于指示mipi转GPIO模块不向至少一个前端模块发送GPIO指令。禁止指令可以为同步信号，该同步信号的取值可以为0或1。BBP可以预先设定当同步信号的取值为1时，禁止指令用于指示mipi转GPIO模块不向至少一个前端模块发送GPIO指令。或者，BBP也可以预先设定当同步信号的取值为0时，禁止指令用于指示mipi转GPIO模块不向至少一个前端模块发送GPIO指令。
本申请的第二方面，提供一种增益控制方法，BBP分别与收发机和mipi转GPIO模块相耦合，mipi转GPIO模块分别与至少一个前端模块相耦合。本申请的方法可以包括：BBP根据预设的第一时长，分别向mipi转GPIO模块和收发机发送mipi指令，指示mipi转GPIO模块在mipi指令的使能下，将mipi指令转换为GPIO指令，为至少一个前端模块提供GPIO指令，以使至少一个前端模块在GPIO指令的使能下，产生放大增益，指示收发机在mipi指令的使能下，产生放大增益。其中，第一时长为当BBP在同一时刻分别向mipi转GPIO模块和收发机发送mipi指令时，mipi转GPIO模 块和收发机分别接收到mipi指令的时间差；或者，第一时长为从BBP在同一时刻分别向mipi转GPIO模块和收发机发送mipi指令开始，到至少一个前端模块和收发机分别产生放大增益的时间差。
本申请中，可以由mipi转GPIO模块将BBP发送的mipi指令转换为GPIO指令，并将GPIO指令发送至少一个前端模块，使至少一个前端模块产生放大增益；而并不需要采用多个GPIO接口控制至少一个前端模块产生放大增益，因此可以减小SoC的封装面积和成本。
由于第一时长可以为当BBP在同一时刻分别向收发机和mipi转GPIO模块发送mipi指令时，收发机和mipi转GPIO模块分别接收到mipi指令的时间差，因此当BBP根据预设的第一时长，分别向mipi转GPIO模块和收发机发送mipi指令时，便可以保证收发机和mipi转GPIO模块能够同时接收到mipi指令；并且，由于“收发机根据mipi指令产生放大增益”所用的时间和“mipi转GPIO模块将mipi指令转换为GPIO指令，并由至少一个前端模块根据GPIO指令产生放大增益”所用的时间都比较短，因此，“收发机根据mipi指令产生放大增益”所用的时间和“mipi转GPIO模块将mipi指令转换为GPIO指令，并由至少一个前端模块根据GPIO指令产生放大增益”所用的时间的时间差也会比较小。这样，可以保证收发机和至少一个前端模块可以在一定时间差内产生放大增益，也即收发机和mipi转GPIO模块从接收到mipi指令开始，到收发机和至少一个前端模块产生放大增益的时间差小于预定时间，从而实现前端模块和收发机同步产生放大增益。
由于第一时长也可以为从BBP在同一时刻分别向收发机和mipi转GPIO模块发送mipi指令开始，到收发机和至少一个前端模块分别产生放大增益的时间差，因此当BBP根据预设的第一时长，分别向mipi转GPIO模块和收发机发送mipi指令时，便可以保证收发机和至少一个前端模块同时产生放大增益。
综上所述，本申请的增益控制方法可以减小SoC的封装面积和成本，可以使收发机和至少一个前端模块同步产生放大增益。
结合第二方面，在本申请的一种实现方式中，在第一时长为当BBP在同一时刻分别向收发机和mipi转GPIO模块发送mipi指令时，收发机和mipi转GPIO模块分别接收到mipi指令的时间差的情况下，本申请的方法还可以包括：BBP控制mipi转GPIO模块从接收到mipi指令开始的第二时长后，向至少一个前端模块发送GPIO指令。第二时长为收发机和mipi转GPIO模块同时接收到mipi指令时，收发机和至少一个前端模块分别产生放大增益的时间差。
其中，由于第二时长为收发机和mipi转GPIO模块同时接收到mipi指令时，收发机和至少一个前端模块分别产生放大增益的时间差；因此，在“收发机和mipi转GPIO模块能够同时接收到mipi指令”的情况下，如果BBP控制mipi转GPIO模块从接收到mipi指令开始的第二时长后，向至少一个前端模块发送GPIO指令，便可以保证收发机和至少一个前端模块同时产生放大增益。其中，BBP根据预设的第一时长，分别向mipi转GPIO模块和收发机发送mipi指令，便可以保证“收发机和mipi转GPIO模块能够同时接收到mipi指令”。
结合第二方面，在本申请的一种实现方式中，上述“BBP控制mipi转GPIO模块 从接收到mipi指令开始的第二时长后，向至少一个前端模块发送GPIO指令”的方法可以包括：BBP向收发机发送第一命令，该第一命令中携带有第二时长，该第一命令用于指示收发机从接收到mipi指令开始的第二时长后，向mipi转GPIO模块发送使能指令。
其中，上述使能指令用于指示mipi转GPIO模块向至少一个前端模块发送GPIO指令。BBP可以在确定第二时长后，通过向收发机发送第一命令，使收发机在接收到mipi指令的第二时长后，向mipi转GPIO模块发送使能指令，使得mipi转GPIO模块在接收到使能指令后，向至少一个前端模块发送GPIO指令，从而使至少一个前端模块产生放大增益。
结合第二方面，在本申请的一种实现方式中，由于至少一个前端模块可能已经产生放大增益或者至少一个前端模块中未包含有LNA，此时，至少一个前端模块不需要产生放大增益，因此，BBP可以在向收发机发送第一命令之前，先确定至少一个前端模块是否需要产生放大增益。本申请中方法还可以包括：BBP确定至少一个前端模块均不产生放大增益；BBP向收发机发送第二命令，该第二命令可以用于指示收发机在接收到mipi指令后，向mipi转GPIO模块发送禁止指令。
其中，禁止指令可以用于指示mipi转GPIO模块不向至少一个前端模块发送GPIO指令。当BBP确定至少一个前端模块不需要产生放大增益时，可以向mipi转GPIO模块发送第二命令，使得收发机在接收到mipi指令后，直接向mipi转GPIO模块发送禁止指令，该禁止指令可以为同步信号，该同步信号的取值可以为0或1。BBP可以预先设定当同步信号的取值为1时，禁止指令用于指示mipi转GPIO模块不向至少一个前端模块发送GPIO指令。或者，BBP也可以预先设定当同步信号的取值为0时，禁止指令用于指示mipi转GPIO模块不向至少一个前端模块发送GPIO指令。
附图说明
图1为现有的一种通信设备的结构示意图；
图2为本发明实施例提供的一种通信设备的结构示意图一；
图3为本发明实施例提供的一种mipi转GPIO模块的结构示意图；
图4为本发明实施例提供的一种通信设备的结构示意图二；
图5为本发明实施例提供的一种增益控制方法流程图一；
图6为本发明实施例提供的一种BBP确定第一时长的实例示意图；
图7为本发明实施例提供的一种增益控制方法流程图二；
图8为本发明实施例提供的一种增益控制方法流程图三；
图9为本发明实施例提供的一种增益控制方法的运行时序实例示意图；
图10为本发明实施例提供的一种增益控制方法流程图四；
图11为本发明实施例提供的一种增益控制方法的实例示意图。
具体实施方式
本发明实施例提供的通信设备及增益控制方法可以应用于控制放大增益同步的过程中，具体的，可以应用于BBP通过mipi指令控制收发机和至少一个前端模块同步产生放大增益的过程中。
请参考图1，其示出了现有的一种通信设备结构示意图。如图1所示，该通信设 备10可以包括：BBP 100、至少一个GPIO接口(如GPIO接口201和GPIO接口202)、收发机300和至少一个前端模块(如前端模块401和前端模块402)。
其中，BBP 100分别与收发机300、GPIO接口201和GPIO接口202相耦合，GPIO接口201与前端模块401相耦合，GPIO接口202与前端模块402相耦合，收发机300分别与前端模块401和前端模块402相耦合，前端模块401和前端模块402还分别与天线耦合。前端模块401和前端模块402中均包含有LNA，当前端模块401和前端模块402分别从天线接收到无线信号时，前端模块401和前端模块402可以分别用于对接收到无线信号产生放大增益，收发机300中包含有放大模块(例如，集成在收发机中的LNA)，可以用于对经前端模块401和前端模块402分别放大后的无线信号产生放大增益。BBP 100可以用于向至少一个GPIO接口和收发机300发送mipi指令，并控制收发机300和与至少一个GPIO接口对应的前端模块产生放大增益。
示例性的，本发明实施例中的各个模块之间的相互耦合，可以是各个模块之间通过有线连接的方式，也可以是通过无线连接的方式。例如BBP 100与收发机300可以是有线连接，也可以是无线连接。
如图1所示，前端模块401和前端模块402可以通过与收发机300之间的通道，将接收到的信号传送给收发机300，然后收发机300将信号发送给BBP 100；BBP 100在接收到信号后，可以通过mipi_0通道向GPIO接口201发送mipi指令，通过mipi_1通道向GPIO接口202发送mipi指令，通过mipi_2通道向收发机300发送mipi指令。GPIO接口201可以将接收到的mipi指令转换为GPIO指令，并向前端模块401输出该GPIO指令，GPIO接口202可以将接收到的mipi指令转换为GPIO指令，并向前端模块402输出该GPIO指令，使得前端模块401和前端模块402产生放大增益；收发机300在接收到mipi指令后，可以根据接收到的mipi指令产生放大增益。
示例性的，本发明实施例中的mipi指令可以为使能指令，用于使能收发机300产生放大增益，用于使能GPIO接口201和GPIO接口202产生GPIO指令；GPIO指令也可以为使能指令，用于使能前端模块401和前端模块402产生放大增益。
但是，BBP 100需要采用两个GPIO接口分别控制前端模块401和前端模块402，会造成SoC的封装面积和成本过大；并且，由于至少一个前端模块产生放大增益所用时间与收发机300产生放大增益所用时间可能不同，因此在BBP 100分别向多个GPIO接口和收发机300发送mipi指令后，收发机300和至少一个前端模块并不能够同步产生放大增益。
为了解决上述问题，本发明实施例提供一种通信设备11，如图2所示，该通信设备11可以包括：BBP 100、mipi转GPIO模块203、收发机300和至少一个前端模块(如前端模块401和前端模块402)。
具体的，BBP 100分别与收发机300和mipi转GPIO模块203相耦合，mipi转GPIO模块203分别与前端模块401和前端模块402相耦合，收发机300分别与前端模块401和前端模块402相耦合。
BBP 100，用于根据预设的第一时长，通过mipi_0通道向mipi转GPIO模块203发送mipi指令，通过mipi_1通道向收发机300发送mipi指令。
mipi转GPIO模块203，用于接收BBP 100发送的mipi指令，并在mipi指令的使 能下，将mipi指令转换为GPIO指令，为前端模块401和前端模块402提供GPIO指令，以使前端模块401和前端模块402在GPIO指令的使能下产生放大增益。
收发机300，用于接收BBP 100发送的mipi指令，并在mipi指令的使能下，产生放大增益。
其中，第一时长为当BBP 100在同一时刻分别向收发机300和mipi转GPIO模块203发送mipi指令时，收发机300和mipi转GPIO模块203分别接收到mipi指令的时间差；或者，第一时长为从BBP 100在同一时刻向收发机300和mipi转GPIO模块203分别发送mipi指令开始，到收发机300和至少一个前端模块(如前端模块401和前端模块402)分别产生放大增益的时间差。
需要说明的是，本发明的通信设备11可以是多天线多通道的通信设备，即每个前端模块分别对应一根天线(图中未示出)，本发明的通信设备11还可以是单天线的通信设备，即多个前端模块耦合到同一根天线，BBP 100通过使能其中一个前端模块，完成无线信号的接收，由于多个前端模块的放大增益互不相同，从而可以提供多个增益档位，满足不同的设计需求。
本发明实施例提供的通信设备，可以由mipi转GPIO模块将BBP发送的mipi指令转换为GPIO指令，并将GPIO指令发送给至少一个前端模块，使至少一个前端模块产生放大增益；而并不需要采用多个GPIO接口控制至少一个前端模块产生放大增益，因此可以减小SoC的封装面积和成本。
在本发明实施例的第一种应用场景中，由于第一时长为当BBP 100在同一时刻分别向收发机300和mipi转GPIO模块203发送mipi指令时，收发机300和mipi转GPIO模块203分别接收到mipi指令的时间差；因此，当BBP 100根据预设的第一时长，分别向mipi转GPIO模块203和收发机300发送mipi指令时，便可以保证收发机300和mipi转GPIO模块203能够同时接收到mipi指令。
并且，由于“收发机300根据mipi指令产生放大增益”所用的时间和“mipi转GPIO模块203将mipi指令转换为GPIO指令，并由至少一个前端模块根据GPIO指令产生放大增益”所用的时间都比较短，因此，“收发机300根据mipi指令产生放大增益”所用的时间和“mipi转GPIO模块203将mipi指令转换为GPIO指令，并由至少一个前端模块根据GPIO指令产生放大增益”所用的时间的时间差也会比较小。这样，可以保证收发机300和至少一个前端模块可以在一定时间差内产生放大增益，即收发机300和mipi转GPIO模块203从接收到mipi指令开始，到收发机300和至少一个前端模块产生放大增益的时间差小于预定时间，从而达到收发机300和至少一个前端模块同步产生放大增益的目的。
在本发明实施例的第二种应用场景中，由于第一时长从为BBP 100在同一时刻分别向收发机300和mipi转GPIO模块203发送mipi指令开始，到收发机300和至少一个前端模块(如前端模块401和前端模块402)分别产生放大增益的时间差；因此，当根据预设的第一时长，分别向mipi转GPIO模块203和收发机300发送mipi指令时，便可以保证收发机300和至少一个前端模块同时产生放大增益。
综上所述，本申请的通信设备可以减小SoC的封装面积和成本，可以使收发机和至少一个前端模块同步产生放大增益。
进一步的，如图3所示，如图2所示的mipi转GPIO模块203可以包括：mipi接口2001、处理模块2002和输出模块2003。
其中，mipi接口2001，可以用于接收BBP 100发送的mipi指令。上述mipi指令可以包括mipi数据和mipi时钟序列，mipi接口2001中的SDATA端口用于接收mipi数据，mipi接口2001中的SCLK端口用于接收mipi时钟序列。
处理模块2002与mipi接口2001相耦合，处理模块2002可以用于将mipi接口2001接收的mipi指令转换为GPIO指令，并缓存GPIO指令。
输出接口2003，用于将GPIO指令分别发送给至少一个前端模块。
示例性的，如图3所示，处理模块2002可以将mipi接口2001接收的mipi指令写入到寄存器1(Register，Reg)中，并根据Reg1中的比特位D0-D7与GPIO_0-GPIO_7的映射关系，将Reg1中的8比特分别译码到GPIO_7-GPIO_0端口上输出。
进一步的，mipi转GPIO模块203还可以包括：供电模块。该供电模块可以用于向mipi转GPIO模块203的各个部分供电。其中，电源电压(Voltage Device Device，VDD)可以为mipi接口2001、处理模块2002和输出模块2003等供电，输入和输出电压(Voltage For Input And Output，VIO)可以为上述SDATA端口和SCLK端口供电。
其中，本发明实施例中的mipi转GPIO模块，不仅可以用于控制至少一个前端模块，还可以用于控制功率放大器、天线开关以及天线协调器等。
在本发明实施例的一种场景下，即第一时长为“当BBP 100在同一时刻分别向收发机300和mipi转GPIO模块203发送mipi指令时，收发机300和mipi转GPIO模块203分别接收到mipi指令的时间差”时，即使BBP根据预设的第一时长，分别向mipi转GPIO模块203和收发机300发送mipi指令，收发机300、前端模块401和前端模块402也不能同时产生放大增益，只能保证收发机300、前端模块401和前端模块402产生放大增益的时间差小于预定时间，即收发机和至少一个前端模块可以在一定时间差内产生放大增益。
为了使得收发机300、前端模块401和前端模块402可以同时产生放大增益，BBP100还可以用于控制mipi转GPIO模块203从接收到mipi指令开始的第二时长后，向前端模块401和前端模块402发送GPIO指令。
其中，第二时长为收发机300和mipi转GPIO模块203同时接收到mipi指令时，收发机300与至少一个前端模块(如前端模块401和前端模块402)分别产生放大增益的时间差。
由于第二时长可以为收发机300和mipi转GPIO模块203同时接收到mipi指令时，收发机300和至少一个前端模块分别产生放大增益的时间差；因此，在“收发机300和mipi转GPIO模块203能够同时接收到mipi指令”的情况下，如果BBP 100控制mipi转GPIO模块203从接收到mipi指令开始的第二时长后，向至少一个前端模块发送GPIO指令，便可以保证收发机300和至少一个前端模块同时产生放大增益。其中，BBP 100据预设的第一时长，分别向mipi转GPIO模块203和收发机300发送mipi指令，便可以保证“收发机300和mipi转GPIO模块203能够同时接收到mipi指令”。
示例性的，本发明实施例中，BBP 100可以通过向收发机300发送第一命令(该 第一命令中携带有第二时长)，控制mipi转GPIO模块203从接收到mipi指令开始的第二时长后，向前端模块401和前端模块402发送GPIO指令。
其中，第一命令用于指示收发机300从接收到mipi指令开始的第二时长后，向mipi转GPIO模块203发送使能指令。
收发机300在接收到第一命令后，便可以执行从接收到mipi指令开始的第二时长后，向mipi转GPIO模块203发送使能指令，以指示mipi转GPIO模块203向前端模块401和前端模块402发送GPIO指令。
示例性的，上述使能指令可以为同步信号，该同步信号的取值可以为0或1。BBP 100可以预先设定当同步信号的取值为1时，使能指令用于指示mipi转GPIO模块203向至少一个前端模块发送GPIO指令。或者，BBP 100也可以预先设定当同步信号的取值为0时，使能指令用于指示mipi转GPIO模块203向至少一个前端模块发送GPIO指令。
需要说明的是，在收发机300向mipi转GPIO模块203发送同步信号后，该同步信号持续时间为1个mipi指令周期，超出该周期后，收发机300将同步信号置0。
进一步的，前端模块401和前端模块402可能已经产生放大增益或者前端模块401和前端模块402中并未包含有LNA，即可能会存在前端模块401和前端模块402不需要产生放大增益，BBP 100可以先判断前端模块401和前端模块402是否需要产生放大增益，并根据判断结果向收发机300发送命令，该命令用于指示收发机300向mipi转GPIO模块203发送使能指令或者禁止指令，该使能指令可以为同步信号，该同步信号的取值可以为0或者1。
进一步的，BBP 100还可以用于：确定至少一个前端模块均不需要产生放大增益；向收发机300发送第二命令，该第二命令用于指示收发机300在接收到mipi指令后，向mipi转GPIO模块203发送禁止指令。
其中，禁止指令可以用于指示mipi转GPIO模块203不向至少一个前端模块(如前端模块401和前端模块402)发送GPIO指令。
示例性的，BBP 100可以获取BBP 100所在的通信设备(如终端设备或者基站)的业务情况，若BBP 100获取的业务情况为至少一个前端模块已经产生放大增益或者至少一个前端模块中并未包含有LNA时，BBP 100则可以用于向收发机300发送第二命令，使收发机300向mipi转GPIO模块203发送禁止指令，该禁止指令可以为同步信号，该同步信号的取值可以为0或1。BBP可以预先设定当同步信号的取值为1时，禁止指令用于指示mipi转GPIO模块不向至少一个前端模块发送GPIO指令。或者，BBP也可以预先设定当同步信号的取值为0时，禁止指令用于指示mipi转GPIO模块不向至少一个前端模块发送GPIO指令。
需要说明的是，若BBP预先设定的使能指令为同步信号，且该同步信号的取值为1时，那么当BBP预先设定的禁止指令为同步信号时，该同步信号的取值为0；若BBP预先设定的使能指令为同步信号，且该同步信号的取值为0时，那么当BBP预先设定的禁止指令为同步信号时，该同步信号的取值为1。
进一步的，本发明实施例提供的通信设备中还可以包括至少两个mipi转GPIO模块。例如，如图4所示的通信设备11中可以包括两个mipi转GPIO模块。如图4所 示，通信设备11除如图2所示的BBP 100、收发机300和mipi转GPIO模块203之外，还可以包括mipi转GPIO模块204和前端模块403。
其中，mipi转GPIO模块204与BBP 100相耦合，mipi转GPIO模块204与至少一个前端模块相耦合，例如，如图4所示，mipi转GPIO模块204与前端模块403相耦合。
BBP 100，具体可以用于根据预设的第一时长，通过mipi_0通道向mipi转GPIO模块203发送mipi指令，通过mipi_1通道向收发机300发送mipi指令，通过mipi_2通道向mipi转GPIO模块204发送mipi指令，
mipi转GPIO模块204，可以用于接收BBP 100发送的mipi指令，将在mipi指令的使能下，将mipi指令转换为GPIO指令，并为前端模块403提供GPIO指令，以使前端模块403在GPIO指令的使能下产生放大增益。
收发机300，用于接收BBP 100发送的mipi指令，并在mipi指令的使能下产生放大增益。
本发明实施例提供的通信设备11可以实现收发机300、前端模块401、前端模块402和前端模块403同步产生放大增益。
本发明实施例提供的通信设备，不仅可以减小SoC的封装面积和成本，实现收发机和至少一个前端模块同步产生放大增益，还可以根据BBP所在通信设备的实际业务情况，控制收发机向mipi转GPIO模块发送第一命令或者第二命令。
本发明实施例提供一种增益控制方法，可以应用于上述通信设备，如图5所示，该增益控制方法可以包括S501-S506：
S501、BBP确定第一时长。
在本发明实施例的第一种应用场景中，第一时长为当BBP在同一时刻分别向收发机和mipi转GPIO模块发送mipi指令时，收发机和mipi转GPIO模块分别接收到mipi指令的时间差。
由于如果BBP在同一时刻分别向收发机和mipi转GPIO模块发送mipi指令，则收发机和mipi转GPIO模块接收到mipi指令的时间也不相同，即收发机和mipi转GPIO模块不能同时接收到mipi指令，从而会导致收发机和至少一个前端模块可能不能够同步产生放大增益；因此，为了保证收发机和mipi转GPIO模块可以同时接收到mipi指令，BBP可以确定BBP在同一时刻分别向收发机和mipi转GPIO模块发送mipi指令时，收发机和mipi转GPIO模块分别接收到mipi指令的时间差(即第一时长)，然后可以根据第一时长分别向收发机和mipi转GPIO模块发送mipi指令。
示例性的，BBP可以在同一时刻分别向收发机和mipi转GPIO模块发送mipi指令，并在BBP所在通信设备(如终端设备或者基站)的非失忆性(Nonvolatile，NV)项中记录BBP向收发机和mipi转GPIO模块发送mipi指令的时刻(记为第一时刻)，然后在NV项中记录从收发机获取的收发机接收到mipi指令的时刻(记为第二时刻)，在NV项中记录从mipi转GPIO模块获取的mipi转GPIO模块接收到mipi指令的时刻(记为第三时刻)；BBP根据NV项中记录的第一时刻和第二时刻，确定从BBP发送mipi指令，到收发机接收到mipi指令所需的时间(记为第一时间)；BBP根据NV项中记录的第一时刻和第三时刻，确定从BBP发送mipi指令，到mipi转GPIO模块接 收到mipi指令所需的时间(记为第二时间)；BBP计算第一时间和第二时间的差值，得到第一时长，并记录在NV项中。
例如，假设“从BBP发送mipi指令开始，到mipi转GPIO模块接收到mipi指令”所需时间大于“从BBP发送mipi指令开始，到射频收发模块接收到mipi指令”所需时间。如图6所示，BBP在手机的NV项中记录的第一时刻(即BBP向收发机和mipi转GPIO模块发送mipi指令的时刻)为t1，记录的第二时刻(即收发机接收到mipi指令的时刻)为t2，记录的第三时刻(即mipi转GPIO模块接收到mipi指令的时刻)为t3，则BBP确定的第一时间为t2-t1，BBP确定的第二时间为t3-t1，BBP计算第一时间和第二时间的差值为t3-t1-(t2-t1)，即第一种应用场景中的第一时长为t3-t2。
在本发明实施例的第二种应用场景中，第一时长为当BBP在同一时刻分别向收发机和mipi转GPIO模块发送mipi指令时，收发机和至少一个前端模块分别产生放大增益的时间差。其中，即使收发机和mipi转GPIO模块不能同时接收到mipi指令，只要BBP根据“BBP在同一时刻分别向收发机和mipi转GPIO模块发送mipi指令时，收发机和至少一个前端模块分别产生放大增益的时间差(即第一时长)”分别向收发机和mipi转GPIO模块发送mipi指令，便可以保证收发机和至少一个前端模块同时产生放大增益。
示例性的，BBP可以在同一时刻分别向收发机和mipi转GPIO模块发送mipi指令，并在BBP所在设备的NV项中记录BBP向收发机和mipi转GPIO模块发送mipi指令的时刻(记为第一时刻)，然后在NV项中记录从收发机获取的收发机产生放大增益的时刻(记为第四时刻)，在NV项中记录从mipi转GPIO模块获取的mipi转GPIO模块对应的前端模块产生放大增益的时刻(记为第五时刻)；BBP根据在NV项中记录的第一时刻和第四时刻，确定从BBP发送mipi指令，到收发机产生放大增益所需的时间(记为第三时间)；BBP根据在NV项中记录的第一时刻和第五时刻，确定从BBP发送mipi指令，到mipi转GPIO模块对应的前端模块产生放大增益所需的时间(记为第四时间)；BBP计算第三时间和第四时间的差值，得到第一时长，并记录在NV项中。
例如，假设“从BBP发送mipi指令开始，到mipi转GPIO模块对应的前端模块产生放大增益”所需时间大于“从BBP发送mipi指令开始，到射频收发模块产生放大增益”所需时间。BBP在手机的NV项中记录的第一时刻(即BBP向收发机和mipi转GPIO模块发送mipi指令的时刻)为t1，记录的第四时刻(即收发机产生放大增益的时刻)为t4，记录的第五时刻(即mipi转GPIO模块对应的前端模块产生放大增益的时刻)为t5，则BBP确定的第三时间为t4-t1，BBP确定的第四时间为t5-t1，BBP计算第三时间和第四时间的差值为t5-t1-(t4-t1)，即第二种应用场景中的第一时长为t5-t4。
S502、BBP根据预设的第一时长，分别向mipi转GPIO模块和收发机发送mipi指令。
其中，mipi指令可以为使能指令，指示mipi转GPIO模块在mipi指令的使能下，将mipi指令转换为GPIO指令，为至少一个前端模块提供GPIO指令，以使至少一个前端模块在GPIO指令的使能下，产生放大增益，指示收发机在mipi指令的使能下， 产生放大增益。
在本发明实施例的第一种应用场景中，由于第一时长为当BBP在同一时刻分别向收发机和mipi转GPIO模块发送mipi指令时，收发机和mipi转GPIO模块分别接收到mipi指令的时间差，因此BBP根据预设的第一时长，分别向mipi转GPIO模块和收发机发送mipi指令时，便可以保证收发机和mipi转GPIO模块同时接收到mipi指令。
例如，第一时间(即从BBP发送mipi指令，到收发机接收到mipi指令所需的时间)t2-t1为1分钟，第二时间(即从BBP发送mipi指令，到mipi转GPIO模块接收到mipi指令所需的时间)t3-t1为3分钟，则第一种应用场景中的第一时长t3-t2为2分钟。BBP可以先向mipi转GPIO模块发送mipi指令，然后在2分钟之后向收发机发送mipi指令，如此便可以保证收发机和mipi转GPIO模块能够同时接收到mipi指令。
在第二种应用场景中，由于第一时长也可以为从BBP在同一时刻分别向收发机和mipi转GPIO模块发送mipi指令时，收发机和至少一个前端模块分别产生放大增益的时间差，因此BBP根据预设的第一时长，分别向mipi转GPIO模块和收发机发送mipi指令时，便可以使得收发机和至少一个前端模块同时产生放大增益。
例如，第三时间(即从BBP发送mipi指令，到收发机产生放大增益所需的时间)t4-t1为3分钟，第四时间(即从BBP发送mipi指令，到至少一个前端模块产生放大增益所需的时间)t5-t1为4分钟，则第二种应用场景中的第一时长t5-t4为1分钟。BBP可以先向mipi转GPIO模块发送mipi指令，然后在1分钟之后向收发机发送mipi指令，如此便可以保证收发机和至少一个前端模块能够同时产生放大增益。
S503、收发机接收mipi指令，并在mipi指令的使能下产生放大增益。
其中，收发机中包含有放大模块，当收发机接收mipi指令后，收发机中的放大模块在mipi指令的使能下会产生放大增益。
示例性的，收发机可以在接收mipi指令后，开始在mipi指令的使能下产生放大增益；收发机也可以在接收mipi指令后，经过一个“等待时间”后，开始在mipi指令的使能下产生放大增益。
不论收发机是在接收mipi指令后，开始在mipi指令的使能下产生放大增益，还是在接收mipi指令后，经过一个“等待时间”后，开始在mipi指令的使能下产生放大增益，只要“收发机从接收到mipi指令开始，到产生放大增益”和“mipi转GPIO模块从接收到mipi指令开始，到向至少一个前端模块发送GPIO指令，使得至少一个前端模块产生放大增益”的时间差小于预定时间，即收发机和至少一个前端模块可以在一定时间差内产生放大增益，便可以实现收发机和至少一个前端模块同步产生放大增益。
S504、mipi转GPIO模块接收mipi指令，并在mipi指令的使能下，将mipi指令转化为GPIO指令。
其中，mipi转GPIO模块可以包括mipi接口、处理模块和输出模块。处理模块可以在mipi接口接收到mipi指令后，在mipi指令的使能下，将mipi接口接收的mipi指令转换为GPIO指令，并通过输出模块向至少一个前端模块发送GPIO指令。
S505、mipi转GPIO模块分别向至少一个前端模块发送GPIO指令。
其中，GPIO指令可以为使能指令，用于指示至少一个前端模块在GPIO指令的使能下产生放大增益。
需要说明的是，mipi转GPIO模块分别向至少一个前端模块发送GPIO指令所用的时间很短，在本发明实施例中可以忽略不计。
S506、前端模块接收GPIO指令，并在GPIO指令的使能下产生放大增益。
其中，前端模块接收到mipi转GPIO模块发送的GPIO指令后，前端模块的LNA在GPIO指令的使能下可以产生放大增益。
在本发明实施例的第一种应用场景中，BBP在根据确定的第一时长，分别向收发机和mipi转GPIO模块发送mipi指令后，可以保证收发机和mipi转GPIO模块同时接收到mipi指令；此时，只要“收发机从接收到mipi指令开始，到产生放大增益”和“mipi转GPIO模块从接收到mipi指令开始，到向至少一个前端模块发送GPIO指令，使得至少一个前端模块产生放大增益”的时间差小于预定时间，即收发机和至少一个前端模块可以在一定时间差内产生放大增益，便可以实现收发机和至少一个前端模块同步产生放大增益。
例如，假设上述预定时间为2分钟，第一时间(即从BBP发送mipi指令，到收发机接收到mipi指令所需的时间)t2-t1为1分钟，第二时间(即从BBP发送mipi指令，到mipi转GPIO模块接收到mipi指令所需的时间)t3-t1为3分钟，则第一种应用场景中的第一时长t3-t2为2分钟。BBP可以先向mipi转GPIO模块发送mipi指令，然后在2分钟之后向收发机发送mipi指令，如此便可以保证收发机和mipi转GPIO模块能够同时接收到mipi指令；“收发机从接收到mipi指令开始，到产生放大增益”的时间为2分钟，“mipi转GPIO模块从接收到mipi指令开始，到向至少一个前端模块发送GPIO指令，使得至少一个前端模块产生放大增益”的时间为1分钟，则“收发机从接收到mipi指令开始，到产生放大增益的时间”和“mipi转GPIO模块从接收到mipi指令开始，到向至少一个前端模块发送GPIO指令，使得至少一个前端模块产生放大增益的时间”的时间差小于预定时间，如此收发机和至少一个前端模块可以同步产生放大增益。
其中，本发明实施例中，可以同时执行S503和S504-S506。
本发明实施例提供一种增益控制方法，可以由mipi转GPIO模块将BBP发送的mipi指令转换为GPIO指令，并将GPIO指令发送给至少一个前端模块，使至少一个前端模块产生放大增益；而并不需要采用多个GPIO接口控制至少一个前端模块产生放大增益，因此可以减小SoC的封装面积和成本。
在第一种应用场景中，由于第一时长可以为当BBP在同一时刻分别向收发机和mipi转GPIO模块发送mipi指令时，收发机和mipi转GPIO模块分别接收到mipi指令的时间差，因此当BBP根据预设的第一时长，分别向mipi转GPIO模块和收发机发送mipi指令时，便可以保证收发机和mipi转GPIO模块能够同时接收到mipi指令。这样，可以保证收发机和至少一个前端模块可以在一定时间差内产生放大增益，从而实现收发机和至少一个前端模块同步产生放大增益。
在第二种应用场景中，由于第一时长也可以为从BBP在同一时刻分别向收发机和mipi转GPIO模块发送mipi指令时，收发机和至少一个前端模块分别产生放大增益的 时间差，因此当BBP根据预设的第一时长，分别向mipi转GPIO模块和收发机发送mipi指令时，便可以保证收发机和至少一个前端模块同时产生放大增益。
综上所述，本发明实施例提供的增益控制方法可以减小SoC的封装面积和成本，实现收发机和至少一个前端模块同步产生放大增益。
进一步的，在第一种应用场景中，BBP根据第一时长，分别向收发机和mipi转GPIO模块发送mipi指令，可以保证收发机和mipi转GPIO模块可以同时接收到mipi指令。但是，收发机和mipi转GPIO模块分别产生放大增益的时间还是存在一定的时间差。为了使得收发机和至少一个前端模块可以同时产生放大增益，如图7所示，在图5所示的S505之前，本发明实施例的方法还可以包括S701和S702：
S701、BBP确定第二时长。
其中，第二时长为收发机和mipi转GPIO模块同时接收到mipi指令时，收发机和至少一个前端模块分别产生放大增益的时间差。
示例性的，BBP可以根据预设的第一时长，分别向mipi转GPIO模块和收发机发送mipi指令，这样便可以保证mipi转GPIO模块和收发机同时接收到mipi指令；然后，BBP可以获取至少一个前端模块产生放大增益的时刻(记为第六时刻)，获取收发机产生放大增益的时刻(记为第七时刻)；BBP根据第六时刻和第七时刻计算得到第二时长。
一般而言，在收发机和mipi转GPIO模块同时接收到mipi指令的情况下，“收发机从接收到mipi指令开始，到产生放大增益”所需时间大于“mipi转GPIO模块从接收到mipi指令开始，到至少一个前端模块产生放大增益”所需时间。
例如，假设BBP获取的第六时刻(即至少一个前端模块产生放大增益的时刻)为t6，BBP获取的第七时刻(即收发机产生放大增益的时刻)为t7，则BBP计算的第二时长为t7-t6。
S702、BBP控制mipi转GPIO模块从接收到mipi指令开始的第二时长后，向至少一个前端模块发送GPIO指令。
其中，由于第二时长为收发机和mipi转GPIO模块同时接收到mipi指令时，收发机和至少一个前端模块分别产生放大增益的时间差；因此，在“收发机和mipi转GPIO模块能够同时接收到mipi指令”的情况下，如果BBP控制mipi转GPIO模块从接收到mipi指令开始的第二时长后，向至少一个前端模块发送GPIO指令，便可以保证收发机和至少一个前端模块同时产生放大增益。其中，BBP根据预设的第一时长，分别向mipi转GPIO模块和收发机发送mipi指令，便可以保证“收发机和mipi转GPIO模块能够同时接收到mipi指令”。
例如，BBP确定的第二时长t7-t6为1分钟，BBP可以控制mipi转GPIO模块从接收到mipi指令开始的1分钟后，向至少一个前端模块发送GPIO指令，使得至少一个前端模块产生放大增益，如此便使得收发机和至少一个前端模块可以同时产生放大增益。
相应的，如图7所示，图5所示的S505可以替换为S505a：
S505a、mipi转GPIO模块根据BBP的控制，从接收到mipi指令开始的第二时长后，向至少一个前端模块发送GPIO指令。
其中，mipi转GPIO模块在接收到BBP发送的mipi指令后，对mipi指令译码转换处理，得到GPIO指令，并在第二时长后向至少一个前端模块发送GPIO指令，使得至少一个前端模块在接收到GPIO指令后产生放大增益。
由于第二时长为收发机和mipi转GPIO模块同时接收到mipi指令时，收发机和至少一个前端模块产生放大增益的时间差；因此，如果mipi转GPIO模块从接收到mipi指令开始的第二时长后，向至少一个前端模块发送GPIO指令，便可以使得收发机和至少一个前端模块同时产生放大增益。
本发明实施例可以通过BBP向收发机发送第一命令(该第一命令中携带有第二时长)的方法，实现收发机和至少一个前端模块同步产生放大增益。具体的，如图8所示，图7所示的S702可以替换为S702a，图7所示的S505a可以替换为S505b-S505e：
S702a、BBP向收发机发送第一命令。
其中，该第一命令中携带有第二时长，该第一命令用于指示收发机从接收到mipi指令开始的第二时长后，向mipi转GPIO模块发送使能指令。使能指令用于指示mipi转GPIO模块向至少一个前端模块发送GPIO指令。
BBP可以在确定第二时长后，通过向收发机发送第一命令，使收发机在接收到mipi指令的第二时长后，向mipi转GPIO模块发送使能指令，使得该mipi转GPIO模块在接收到使能指令后，向至少一个前端模块发送GPIO指令，从而使至少一个前端模块产生放大增益。
示例性的，上述使能指令可以为同步信号，该同步信号的取值可以为0或1。BBP可以预先设定当同步信号的取值为1时，使能指令用于指示mipi转GPIO模块向至少一个前端模块发送GPIO指令。或者，BBP也可以预先设定当同步信号的取值为0时，使能指令用于指示mipi转GPIO模块向至少一个前端模块发送GPIO指令。
S505b、收发机接收BBP发送的第一命令。
其中，第一命令用于指示收发机从接收到mipi指令开始的第二时长后，向mipi转GPIO模块发送使能指令。
S505c、收发机从接收到mipi指令开始的第二时长后，向mipi转GPIO模块发送使能指令。
其中，收发机在接收第一命令后，可以从接收到mipi指令开始的第二时长后，向mipi转GPIO模块发送使能指令，使得mipi转GPIO模块在接收到使能指令后，向至少一个前端模块发送GPIO指令，从而使至少一个前端模块产生放大增益。
S505d、mipi转GPIO模块接收使能指令。
其中，使能指令用于指示mipi转GPIO模块向至少一个前端模块发送GPIO指令。GPIO指令可以为使能指令，用于使能至少一个前端模块产生放大增益。
S505e、mipi转GPIO模块接收到使能指令时，向至少一个前端模块发送GPIO指令。
示例性的，mipi转GPIO模块可以包括mipi接口、处理模块和输出模块。处理模块可以将mipi接口接收的mipi指令转换为GPIO指令，并在接收到使能指令时，通过输出模块向至少一个前端模块发送GPIO指令。
示例性的，如图9所示，其示出了本发明实施例中的mipi转GPIO模块处理mipi 指令的运行时序示意图。其中，mipi转GPIO模块可以将接收到的mipi指令写入到Reg1中，并根据Reg1中的比特位D0-D7与GPIO_0-GPIO_7的映射关系，在经过第二时长td后，将Reg1中的比特值译码到对应的GPIO端口上输出。其中，图9中GPIO指令的输出值由低电平到高电平转换值标记为Vh，GPIO指令的输出值由高电平到低电平转换值标记为Vlow。
例如，Reg1中的比特0与GPIO_0输出的时序如图9所示，mipi转GPIO模块将Reg1中的比特0译码为GPIO_0指令，并译码到GPIO_0端口上，在GPIO_0指令的输出值经过第二时长td后达到高电平Vh后，向至少一个前端模块输出GPIO_0指令。
进一步的，至少一个前端模块可能已经产生放大增益或者至少一个前端模块中并未包含有LNA，此时，至少一个前端模块并不需要产生放大增益。因此，BBP可以在向收发机发送第一命令之前，判断至少一个前端模块是否需要产生放大增益，并根据判断结果向收发机发送命令，该命令用于指示收发机向mipi转GPIO模块发送使能指令。具体的，如图10所示，在图8所示的S702a之前，本发明实施例的方法还可以包括S1001：
S1001、BBP判断至少一个前端模块是否产生放大增益。
示例性的，BBP可以通过获取终端或者基站的业务情况，确定至少一个前端模块是否需要产生放大增益。若至少一个前端模块已经产生放大增益，或者至少一个前端模块中未包含有LNA时，BBP则确定至少一个前端模块不需要产生放大增益。
若BBP确定至少一个前端模块需要产生放大增益，则继续执行S702a、S505b-S505e和S506；若BBP确定至少一个前端模块不产生需要放大增益，则继续执行S1002-S1004：
S1002、BBP向收发机发送第二命令。
其中，第二命令用于指示收发机在接收到mipi指令后，向mipi转GPIO模块发送禁止指令。禁止指令用于指示mipi转GPIO模块不向至少一个前端模块发送GPIO指令。
当BBP确定至少一个前端模块不需要产生放大增益时，可以向mipi转GPIO模块发送禁止指令，使得收发机在接收到mipi指令后，直接向mipi转GPIO模块发送禁止指令。
示例性的，若BBP确定至少一个前端模块已经产生放大增益或者至少一个前端模块中未包含有LNA时，BBP则可以向收发机发送第二命令，使收发机向mipi转GPIO模块发送禁止指令，该禁止指令可以为同步信号，该同步信号的取值可以为0或1。BBP可以预先设定当同步信号的取值为1时，禁止指令用于指示mipi转GPIO模块不向至少一个前端模块发送GPIO指令。或者，BBP也可以预先设定当同步信号的取值为0时，禁止指令用于指示mipi转GPIO模块不向至少一个前端模块发送GPIO指令。
S1003、收发机接收BBP发送的第二命令。
S1004、mipi转GPIO模块不向至少一个前端模块发送GPIO指令。
其中，由于BBP确定至少一个前端模块不需要产生放大增益，BBP可以不考虑收发机与至少一个前端模块是否同步产生放大增益，只需要向收发机发送第二命令，使得收发机在接收到第二命令后，指示mipi转GPIO模块向至少一个前端模块发送输出 值全为0的GPIO指令，即指示mipi转GPIO模块不向至少一个前端模块发送GPIO指令即可。
当然，本发明实施例中的至少一个前端模块不需要产生放大增益时，BBP也可以不向收发机发送第一命令或者第二命令，BBP只需要分别向收发机和mipi转GPIO模块发送mipi指令，使得收发机和mipi转GPIO模块分别根据mipi指令处理数据等。
示例性的，如图11所示，若图11中的前端模块401、前端模块402和前端模块403均需要产生放大增益，BBP 100可以向收发机300发送第一命令，该第一命令中携带有第二时长，该第一命令用于指示收发机300从接收到mipi指令开始的第二时长后，分别向mipi转GPIO模块203和mipi转GPIO模块204发送使能指令。
若图11中的前端模块401和/或前端模块402需要产生放大增益，而前端模块403不需要产生放大增益时，BBP 100可以向收发机300发送第一命令，该第一命令用于指示收发机300从接收到mipi指令开始的第二时长后，仅向mipi转GPIO模块203发送使能指令。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(processor)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (9)

  1. 一种通信设备，其特征在于，包括：基带信号处理器BBP、收发机、移动行业处理器接口mipi转通用输入输出GPIO模块和至少一个前端模块；
    所述BBP分别与所述收发机和所述mipi转GPIO模块相耦合，所述mipi转GPIO模块分别与所述至少一个前端模块相耦合，所述收发机分别与所述至少一个前端模块相耦合；
    所述BBP，用于根据预设的第一时长，分别向所述mipi转GPIO模块和所述收发机发送mipi指令；
    其中，所述第一时长为当所述BBP在同一时刻分别向所述mipi转GPIO模块和所述收发机发送mipi指令时，所述mipi转GPIO模块和所述收发机分别接收到所述mipi指令的时间差；或者，所述第一时长为从BBP在同一时刻分别向所述mipi转GPIO模块和所述收发机发送mipi指令开始，到所述至少一个前端模块和所述收发机分别产生放大增益的时间差；
    所述收发机，用于接收所述BBP发送的所述mipi指令，并在所述mipi指令的使能下，产生放大增益；
    所述mipi转GPIO模块，用于接收所述BBP发送的所述mipi指令，并在所述mipi指令的使能下，将所述mipi指令转换为GPIO指令，为所述至少一个前端模块提供所述GPIO指令；
    所述至少一个前端模块用于分别接收所述mipi转GPIO模块发送的所述GPIO指令，并在所述GPIO指令的使能下，产生放大增益。
  2. 根据权利要求1所述的通信设备，其特征在于，所述mipi转GPIO模块包括：mipi接口、处理模块、和输出接口；
    所述mipi接口，用于接收所述BBP发送的所述mipi指令；
    所述处理模块，用于将所述mipi接口接收的所述mipi指令转换为所述GPIO指令，并缓存所述GPIO指令；
    所述输出接口，用于将所述GPIO指令分别发送给所述至少一个前端模块。
  3. 根据权利要求1所述的通信设备，其特征在于，在第一时长为当所述BBP在同一时刻分别向所述mipi转GPIO模块和所述收发机发送mipi指令时，所述mipi转GPIO模块和所述收发机分别接收到所述mipi指令的时间差的情况下，
    所述BBP，还用于控制所述mipi转GPIO模块从接收到所述mipi指令开始的第二时长后，向所述至少一个前端模块发送所述GPIO指令；
    其中，所述第二时长为所述收发机和所述mipi转GPIO模块同时接收到所述mipi指令时，所述收发机和所述至少一个前端模块分别产生放大增益的时间差。
  4. 根据权利要求3所述的通信设备，其特征在于，所述BBP，具体用于：
    向所述收发机发送第一命令，所述第一命令中携带有所述第二时长，所述第一命令用于指示所述收发机从接收到所述mipi指令开始的所述第二时长后，向所述mipi转GPIO模块发送使能指令；
    其中，所述使能指令用于指示所述mipi转GPIO模块向所述至少一个前端模块发送所述GPIO指令。
  5. 根据权利要求3或4所述的通信设备，其特征在于，所述BBP，还用于：
    确定所述至少一个前端模块均不产生放大增益；
    向所述收发机发送第二命令，所述第二命令用于指示所述收发机在接收到所述mipi指令后，向所述mipi转GPIO模块发送禁止指令；
    其中，所述禁止指令用于指示所述mipi转GPIO模块不向所述至少一个前端模块发送所述GPIO指令。
  6. 一种增益控制方法，其特征在于，基带信号处理器BBP分别与收发机和移动行业处理器接口mipi转通用输入输出GPIO模块相耦合，所述mipi转GPIO模块分别与至少一个前端模块相耦合，所述方法包括：
    所述BBP根据预设的第一时长，分别向所述mipi转GPIO模块和所述收发机发送mipi指令，指示所述mipi转GPIO模块在所述mipi指令的使能下，将所述mipi指令转换为GPIO指令，为所述至少一个前端模块提供所述GPIO指令，以使所述至少一个前端模块在所述GPIO指令的使能下产生放大增益，指示所述收发机在所述mipi指令的使能下产生放大增益；
    其中，所述第一时长为当所述BBP在同一时刻分别向所述mipi转GPIO模块和所述收发机发送mipi指令时，所述mipi转GPIO模块和所述收发机分别接收到所述mipi指令的时间差；或者，所述第一时长为从BBP在同一时刻分别向所述mipi转GPIO模块和所述收发机发送mipi指令开始，到所述至少一个前端模块和所述收发机分别产生放大增益的时间差。
  7. 根据权利要求6所述的方法，其特征在于，在所述第一时长为当所述BBP在同一时刻分别向所述mipi转GPIO模块和所述收发机发送mipi指令时，所述mipi转GPIO模块和所述收发机分别接收到所述mipi指令的时间差的情况下，
    所述方法还包括：
    所述BBP控制所述mipi转GPIO模块从接收到所述mipi指令开始的第二时长后，向所述至少一个前端模块发送所述GPIO指令；
    其中，所述第二时长为所述收发机和所述mipi转GPIO模块同时接收到所述mipi指令时，所述收发机和所述至少一个前端模块分别产生放大增益的时间差。
  8. 根据权利要求7所述的方法，其特征在于，所述BBP控制所述mipi转GPIO模块从接收到所述mipi指令开始的第二时长后，向所述至少一个前端模块发送所述GPIO指令，包括：
    所述BBP向所述收发机发送第一命令，所述第一命令中携带有所述第二时长，所述第一命令用于指示所述收发机从接收到所述mipi指令开始的所述第二时长后，向所述mipi转GPIO模块发送使能指令；
    其中，所述使能指令用于指示所述mipi转GPIO模块向所述至少一个前端模块发送所述GPIO指令。
  9. 根据权利要求7或8所述的方法，其特征在于，还包括：
    所述BBP确定所述至少一个前端模块均不产生放大增益；
    所述BBP向所述收发机发送第二命令，所述第二命令用于指示所述收发机在接收到所述mipi指令后，向所述mipi转GPIO模块发送禁止指令；
    其中，所述禁止指令用于指示所述mipi转GPIO模块不向所述至少一个前端模块发送所述GPIO指令。
PCT/CN2018/078873 2017-03-14 2018-03-13 一种通信设备及增益控制方法 WO2018166450A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710150893.1A CN106851811B (zh) 2017-03-14 2017-03-14 一种通信设备及增益控制方法
CN201710150893.1 2017-03-14

Publications (1)

Publication Number Publication Date
WO2018166450A1 true WO2018166450A1 (zh) 2018-09-20

Family

ID=59143881

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/078873 WO2018166450A1 (zh) 2017-03-14 2018-03-13 一种通信设备及增益控制方法

Country Status (2)

Country Link
CN (1) CN106851811B (zh)
WO (1) WO2018166450A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106851811B (zh) * 2017-03-14 2019-11-05 华为技术有限公司 一种通信设备及增益控制方法
CN114745772B (zh) * 2022-06-14 2022-08-23 杰创智能科技股份有限公司 数字自动增益控制方法、装置、设备及其程序产品
CN117707028B (zh) * 2024-02-06 2024-06-14 芯睿微电子(昆山)有限公司 射频模式控制电路、射频控制芯片和射频芯片

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104426577A (zh) * 2013-08-21 2015-03-18 美国频顺通讯科技公司 用于控制rf前端组件的简单且灵活的接口架构
CN104917541A (zh) * 2014-03-14 2015-09-16 英飞凌科技股份有限公司 移动设备中的从设备的连接性
CN105657786A (zh) * 2016-01-20 2016-06-08 华为技术有限公司 用户设备和低噪声放大器的调整增益的方法
CN106851811A (zh) * 2017-03-14 2017-06-13 华为技术有限公司 一种通信设备及增益控制方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104426577A (zh) * 2013-08-21 2015-03-18 美国频顺通讯科技公司 用于控制rf前端组件的简单且灵活的接口架构
CN104917541A (zh) * 2014-03-14 2015-09-16 英飞凌科技股份有限公司 移动设备中的从设备的连接性
CN105657786A (zh) * 2016-01-20 2016-06-08 华为技术有限公司 用户设备和低噪声放大器的调整增益的方法
CN106851811A (zh) * 2017-03-14 2017-06-13 华为技术有限公司 一种通信设备及增益控制方法

Also Published As

Publication number Publication date
CN106851811B (zh) 2019-11-05
CN106851811A (zh) 2017-06-13

Similar Documents

Publication Publication Date Title
US10609538B2 (en) Method and device for identifying bluetooth headset voice source
US10627893B2 (en) HSIC communication system and method
EP2924584B1 (en) Connecting usb type-c devices
WO2018166450A1 (zh) 一种通信设备及增益控制方法
US8799492B2 (en) Electronic device
EP2423806A1 (en) Method and device for transmitting universal serial bus audio data through a wireless data terminal
KR20200021559A (ko) 단말 및 그 통신 방법
US10880728B2 (en) Method for data migration and terminal device
US20140115205A1 (en) Secure Digital Card Capable of Transmitting Data Over Wireless Network
US9347990B2 (en) Communication device, test system and test method thereof
US9813988B2 (en) Method and device for data transmission in wireless local area network
CN111277988B (zh) 一种提高微信小程序蓝牙传输速度的方法
WO2016000339A1 (zh) 一种芯片互连的方法、芯片及装置
US11442888B2 (en) Serial communication apparatus for unidirectional communication between chips of radio frequency front-end module and inside the chips
WO2018058862A1 (zh) 一种基于spi的数据传输方法及装置
WO2020077496A1 (zh) 增加射频通路改善mimo吞吐方向的方法及终端设备
WO2014134947A1 (zh) 控制信息的收发装置和方法
TW200941956A (en) Systems and methods for controlling the voltage of signals used to control power amplifiers
US11106318B2 (en) Method and system for transmitting signal, active stylus, touch screen and readable storage medium
CN107623557B (zh) 与射频集成电路进行数字通信的基带集成电路及其设备
EP4016862A1 (en) Channel state information processing method and apparatus, and channel state information receiving method and apparatus
EP3911015A1 (en) Method for transferring between communication systems and related device
US20100216506A1 (en) System and Methods for Supporting Multiple Communications Protocols on a Mobile Phone Device
WO2012167520A1 (zh) 自动功耗控制方法及系统
US7221926B1 (en) Short range radio

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18767960

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18767960

Country of ref document: EP

Kind code of ref document: A1