WO2018166222A1

WO2018166222A1 - High-speed fully-digital receiver calibration system and method based on interleaved encoding

Info

Publication number: WO2018166222A1
Application number: PCT/CN2017/109844
Authority: WO
Inventors: 张璋; 黄博; 杨宁
Original assignee: 烽火通信科技股份有限公司
Priority date: 2017-03-15
Filing date: 2017-11-08
Publication date: 2018-09-20
Also published as: MA44946B1; CN106953715B; RU2704238C1; MA44946A1; CN106953715A; BR112019005321A2

Abstract

The present invention relates to the field of communications. Disclosed are a high-speed fully-digital receiver calibration system and method based on interleaved encoding. The system comprises a transmitter and a receiver. The transmitter comprises a demultiplexer, a baseband signal processor, a flipping device, and a multiplexer. The calibration method comprises the following steps: the transmitter is started, and baseband signals are encoded in an interleaved fashion during an initial state of the transmitter; the transmitter enters a normal operation state, and the baseband signals are encoded normally during the normal operating state of the transmitter; the receiver performs digital signal processing on received signals to obtain demodulated baseband signals, and continuously checks whether the baseband signals are encoded normally or in an interleaved fashion; after fine calibration of an analog-to-digital converter (ADC) of the receiver is completed, the receiver enters the normal operating state. According to the present invention, a receiver can learn about the operating state of a transmitter, and it can be ensured that the receiver achieves the optimum performance.

Description

High-speed full digital receiver calibration system and method based on interlaced coding

Technical field

The invention relates to the field of communications, and in particular to a high-speed full digital receiver calibration system and method based on interlaced coding, which is suitable for a communication system of an all-digital receiver directly sampled by a high-speed analog-to-digital converter (ADC).

Background technique

The all-digital receiver converts the carrier signal into a digital signal with an analog-to-digital converter (ADC) at the front end of the receiver, ie at the intermediate frequency, high frequency or close to the receiving antenna. The subsequent functions of the receiver (such as frequency conversion, filtering and demodulation, etc.) All are realized by digital signal processing technology. It is a combination of communication technology, computer technology and large-scale digital integrated circuit technology. It has the advantages of simple system structure, small size, low cost and good versatility. Applications.

According to the bandpass sampling law, the sampling rate of the ADC should be greater than twice the operating bandwidth of the all-digital receiver. This means that as the bandwidth of communication systems grows, the sampling rate of ADCs will multiply, and high-speed ADCs will become more widespread in future communication systems. Limited to the speed of electronic devices, high-speed ADCs are typically implemented with multiple low-speed (<1GS/s or lower) ADC time-division interleaved samples, thus calibrating the gain and phase of these low-speed ADCs to coordinate their operation into an all-digital receiver An important factor in performance.

The receiver's ADC calibration needs to use the stable signal from the transmitter as a reference. However, the receiver does not know exactly when the remote transmitter will send a stable signal. Therefore, there are two solutions in the past: 1. Receive The machine detects the received signal. If the signal amplitude is greater than the threshold, the transmitter is considered to have issued a stable signal, and the signal is utilized. No. ADC calibration of the analog-to-digital converter of the receiver; 2. Design an analog-to-digital converter ADC calibration error computer system. When the calibration error is greater than the threshold, the calibration is considered unsuccessful and recalibrated until the calibration error is less than the threshold.

However, both methods have drawbacks in the ADC calibration of the receiver. In the first method, when the remote transmitter is initializing, an unstable signal is also generated; the receiver mistakes the unstable signal for a stable signal, and uses the signal to perform ADC calibration of the receiver to cause reception. Machine performance is degraded. The second method, the computer calibration design of ADC calibration error is more difficult, and there is no general calculation method at present.

Summary of the invention

The object of the present invention is to overcome the deficiencies of the above background art, and to provide a high-speed full digital receiver calibration system and method based on interlaced coding, which can enable a receiver to know the working state of the transmitter and ensure that the receiver receives a stable signal. Receiver ADC calibration is performed to ensure optimal receiver performance.

The present invention provides a high speed all digital receiver calibration system based on interlaced coding, the system comprising a transmitter and a receiver;

The transmitter is configured to: select to transmit a normal encoded signal or an interlaced encoded signal according to a signal amplitude;

The receiver is configured to: receive a signal of the transmitter, and perform an analog-to-digital converter ADC calibration of the receiver;

The transmitter includes a demultiplexer, a baseband signal processor, a flipper, and a multiplexer, the demultiplexer connecting two or more baseband signal processors, the demultiplexer and a baseband signal The processor converts the input serial high-speed data into parallel data and performs baseband signal processing. The flipper can invert the output signal of the transmitter baseband signal processor, and the multiplexer is used to convert the parallel data into a serial high-speed baseband signal.

Based on the above technical solution, the transmitter and the receiver are both based on numbers The baseband signal processing circuit of the circuit, the normal encoding and the interleaving encoding are generated by digital circuits.

Based on the above technical solution, the baseband signal transmitted by the transmitter adopts a fixed format, and when the receiver receives the signal and processes the baseband signal, the fixed format is synchronized, and the receiver checks the coding state at the receiver. Interleaved coding is identified using a pattern synchronization fixed to the baseband signal transmitted by the transmitter.

On the basis of the above technical solution, the receiver sequentially attempts to format the received signal by using the interlaced coding receiving mode and the normal coding receiving mode, and identifies the current transmission by being able to format in the receiving mode. Whether the encoding method of the machine is normal encoding or interlaced encoding.

Based on the above technical solution, two or more baseband signal processors of the transmitter are connected with flippers, and each baseband signal processor and a flipper connected to the baseband signal processor form a flip The data output path, the switching of the flipper on each path is switched on, and the switching of the normal coded signal sequence and the interleaved coded signal sequence is performed by the baseband signal processing circuit, so that the multiplexer outputs the normal coded signal and the interlaced coded signal. .

Based on the above technical solution, the flipper is activated and activated by means of software setting.

On the basis of the above technical solution, for the interlaced coded signal, the flipper of the odd path is turned on, the flipper of the even path is not turned on, the multiplexer outputs the interleaved coded signal, or the flipper of the even path is turned on, and the flipper of the odd path is not When enabled, the multiplexer outputs an interleaved coded signal; for a normal coded signal, the flipper of the odd path is not turned on, the flipper of the even path is not turned on, and the multiplexer outputs a normal coded signal.

The invention also provides a high-speed full digital receiver calibration method based on interlaced coding, the calibration method comprising the following steps:

A. The transmitter is started. In the initial state of the transmitter, the amplitude of the signal sent by the transmitter is unstable, and the baseband signal is interlaced.

B. The transmitter enters the normal working state. Under the normal working state of the transmitter, the amplitude of the signal sent by the transmitter is stable, and the baseband signal is changed to normal coding;

C. The receiver performs digital signal processing on the received signal to obtain a demodulated baseband signal, and continuously checks whether the baseband signal is normal or interlaced;

D. When the receiver finds that the baseband signal becomes normal coding, the receiver uses the signal to perform fine calibration of the analog-to-digital converter of the receiver. After the receiver's analog-to-digital converter ADC is perfectly calibrated, the receiver enters normal operation. status.

Based on the above technical solution, between step A and step B, the method further includes the following steps: after the initialization state is completed, the transmitter enters a short waiting state, and the transmitter sends out when the transmitter waits for a short time. The signal amplitude is stable, and the baseband signal is still interlaced. After the transmitter ends the short wait state, it enters the normal working state of the transmitter.

Based on the above technical solution, between step B and step C, the method further includes the following steps: when the amplitude of the signal received by the receiver is less than the amplitude threshold, the receiver is in a receiver signal loss state; when the receiver When detecting that the amplitude of the received signal is greater than the amplitude threshold, the receiver uses the received signal to perform coarse calibration of the analog-to-digital converter ADC of the receiver; after the rough calibration of the analog-to-digital converter ADC of the receiver is completed, the receiver enters the check code. status.

The advantages of the present invention over the prior art are as follows:

The invention provides a high-speed full digital receiver calibration system and method based on interlaced coding, which can enable the receiver to know the working state of the transmitter, and ensure that the receiver performs receiver ADC calibration when receiving a stable signal to ensure the receiver. The performance is optimal; at the same time, it is not interfered by noise and unstable signals, avoiding the receiver repeatedly Calibrating the receiver ADC reduces the complexity of the calibration algorithm and associated control circuitry.

Moreover, since both the transmitter and the receiver are based on digital circuits, the conversion of normal coding and interleaved coding is very simple to implement by digital circuits, without adding any hardware, and the increase in software complexity is negligible.

DRAWINGS

1 is a comparison diagram of a normal encoded signal sequence and an interleaved encoded signal sequence according to an embodiment of the present invention, wherein the signal sequence has a length of 8 bits.

2 is a conventional parallel digital circuit based baseband signal processing circuit in which the parallel digital circuit is two channels.

FIG. 3 is a schematic diagram of a two-channel baseband signal processing circuit capable of outputting a normal encoded signal sequence or an interleaved encoded signal sequence according to an embodiment of the present invention.

4 is a baseband signal processing circuit capable of outputting a normal coded signal sequence or an interleaved coded signal sequence according to an embodiment of the present invention.

FIG. 5 is a baseband signal processing circuit capable of outputting a normal coded signal sequence or an interleaved coded signal sequence according to an embodiment of the present invention.

FIG. 6 is a diagram showing an operation state of a high-speed full digital receiver calibration method based on interlaced coding according to an embodiment of the present invention.

In the figure, 101 - transmitter initialization state, 102 - transmitter short wait state, 103 - transmitter normal operating state, 104 - receiver signal loss state, 105 - receiver ADC coarse calibration, 106 - receiver check coding state, 107-receiver ADC fine calibration, 108-receiver normal operating state, 301-transmitter demultiplexer, 302-first transmitter baseband signal processor, 303-second transmitter baseband signal processor, 304-transmit Machine multiplexer, 401-two-channel transmitter demultiplexer, 402-two-channel first transmitter baseband signal processor, 403-two-channel second transmitter baseband signal processor, 404-two-channel transmitter multiplexing , 405-two-channel first transmitter flipper, 406-two-channel second transmitter flipper, 501- Eight-channel transmitter demultiplexer, 502-eight-channel transmitter multiplexer, 503-eight-channel first transmitter baseband signal processor, 504-eight-channel first transmitter flip-flop, 505-eight-channel second transmitter Baseband signal processor, 506-eight-channel second transmitter flip-flop, 507-eight-channel third transmitter baseband signal processor, 508-eight-channel third transmitter flip-flop, 509-eight-channel fourth transmitter baseband Signal processor, 510-eight-channel fourth transmitter flip-flop, 511-eight-channel fifth transmitter baseband signal processor, 512-eight-channel fifth transmitter flip-flop, 513-eight-channel sixth transmitter baseband signal processing 514-eight-channel sixth transmitter flip-flop, 515-eight-channel seventh transmitter baseband signal processor, 516-eight-channel seventh transmitter flip-flop, 517-eight-channel eighth transmitter baseband signal processor, 518-eight-channel eighth transmitter flipper, 601-2n path transmitter demultiplexer, 602-2n path transmitter multiplexer, 603-2n path first transmitter baseband signal processor, 604-2n path a transmitter flipper, 605-2n path second transmitter baseband signal Processor, 606-2n path second transmitter flipper, 607-2n path third transmitter baseband signal processor, 608-2n path third transmitter flipper, 609-2n path fourth transmitter baseband signal processor , 610-2n path fourth transmitter flipper, 611-2n path 2n-1 transmitter baseband signal processor, 612-2n path 2n-1 transmitter flipper, 613-2n path 2n transmitter baseband signal Processor, 614-2n path 2n transmitter flipper.

detailed description

The present invention will be further described in detail below with reference to the drawings and specific embodiments.

Embodiments of the present invention provide a high-speed full digital receiver calibration system based on interlaced coding, the system including a transmitter and a receiver;

The transmitter is configured to: select a normal coded signal or an interlaced coded signal according to a signal amplitude; the receiver is configured to: receive a signal of the transmitter, and perform analog to digital converter ADC calibration of the receiver; A demultiplexer, a baseband signal processor, a flipper, and a multiplexer are included, the demultiplexer connecting two or more baseband signal processing The demultiplexer and the baseband signal processor convert the input serial high speed data into parallel data and perform baseband signal processing, and the flipper can invert the output signal of the transmitter baseband signal processor, and the multiplexer is used Parallel data is converted to a serial high speed baseband signal.

Wherein, both the transmitter and the receiver adopt a digital circuit based baseband signal processing circuit, and the normal coding and interlace coding conversion are generated by the digital circuit. The baseband signal transmitted by the transmitter adopts a fixed format, and the receiver synchronizes the fixed format when receiving the signal and processing the baseband signal, and the receiver is fixed by the baseband signal transmitted by the transmitter when the receiver checks the coding state. The format synchronization feature identifies interlaced codes.

Wherein, the receiver sequentially uses the interleave coding reception mode and the normal coding reception mode to try to format the received signal, and by using which reception mode can be formatted, the synchronization is used to identify that the current transmitter coding mode is normal. Encoding is also interleaved.

In actual operation, two or more baseband signal processors of the transmitter are connected with flippers, and each baseband signal processor and the flipper connected to the baseband signal processor form a data output path. The switching of the flipper on each path is switched on and off, so that the baseband signal processing circuit outputs the switching of the normal encoded signal sequence and the interleaved encoded signal sequence, so that the multiplexer outputs the normal encoded signal and the interleaved encoded signal.

In actual operation, for the interleaved coded signal, the flipper of the odd path is turned on, the flipper of the even path is not turned on, the multiplexer outputs the interleaved coded signal, or the flipper of the even path is turned on, the flipper of the odd path is not turned on, and multiplexing The device outputs an interleaved coded signal; for a normal coded signal, the flipper of the odd path is not turned on, the flipper of the even path is not turned on, and the multiplexer outputs a normal coded signal.

It is conceivable that in practical applications, only the transmitter baseband signal processor of the odd-numbered path may be connected with the transmitter flip-flop, and the transmitter flip-flop may be flipped by software; similarly, the transmitter baseband signal processing of only the even-numbered path may be used. Transmitter connection flipped Set the transmitter flipper to flip through the software.

Referring to FIG. 1, the normal coded signal sequence and the interlaced coded signal sequence are respectively compared. The figure shows an 8-bit length normal coded signal sequence and an 8-bit length interleaved coded signal sequence, where T1, T3, T5, The T7 bit is flipped, and the meaning of the flip is that 0 becomes 1, and 1 becomes 0.

Referring to Figure 2, a conventional parallel digital circuit based baseband signal processing circuit is shown. The existing transmitter demultiplexer 301 converts the input serial high speed data into two channels of relatively low speed parallel data, and the first transmitter baseband signal processor 302 and the second transmitter baseband signal processor 303 pair parallel data. The digital signal processing is performed, and the processed parallel signal is sent to the transmitter multiplexer 304 for conversion to a serial high speed baseband signal.

Referring to FIG. 3, an embodiment is shown in which two channels of parallel digital circuits can output a normal coded signal sequence or a baseband signal processing circuit of an interleaved coded signal sequence. In this embodiment, the flipper of the odd path is turned on, the flipper of the even path is not turned on, and the multiplexer outputs the interleaved coded signal as an example. The two-channel transmitter demultiplexer 401 converts the input serial high-speed data into The two channels of relatively low speed parallel data are activated by software to activate the two-channel first transmitter flip 405 in the two-channel first transmitter baseband signal processor 402, and the two-pass first transmitter baseband signal processor 402 The output signal is flipped. The meaning of flipping is that 0 becomes 1, and 1 becomes 0. The two-pass second transmitter baseband signal processor 403 also includes a two-channel second transmitter flip 406. The two-channel first transmitter flip 405 is turned on, and the two-channel second transmitter flip 406 is not turned on. The two-channel transmitter multiplexer 404 output signal will be an interlaced coded signal; the two-channel first transmitter flip 405 is not turned on. The two-pass second transmitter flip 406 is not turned on, and the two-pass transmitter multiplexer 404 output signal will be a normal encoded signal. Similarly, the flipper of the even path is turned on, the flipper of the odd path is not turned on, and the multiplexer also outputs the interleaved coded signal.

Referring to FIG. 4, an embodiment is provided for eight channels of parallel digital circuits. A baseband signal processing circuit that outputs a normal encoded signal sequence or an interleaved encoded signal sequence. In this embodiment, the flipper of the odd path is turned on, the flipper of the even path is not turned on, and the multiplexer outputs the interleaved coded signal as an example. The eight-channel transmitter demultiplexer 501 converts the input serial high-speed data into Eight channels of relatively low speed parallel data are activated by software to activate an eight-channel first transmitter flip 504 in the eight-channel first transmitter baseband signal processor 503 to activate an eight-channel third transmitter baseband signal processor 507. The eight-channel third transmitter flip 508 activates an eight-channel fifth transmitter flip 512 in the eight-channel fifth transmitter baseband signal processor 511 to activate eight of the eight-channel seventh transmitter baseband signal processor 515 The seventh transmitter flip 516 of the path, the eight-channel first transmitter baseband signal processor 503, the eight-channel third transmitter baseband signal processor 507, the eight-channel fifth transmitter baseband signal processor 511, and the eight-channel seventh The output signal of the transmitter baseband signal processor 515 is inverted, the eight-channel second transmitter baseband signal processor 505, the eight-channel fourth transmitter baseband signal processor 509, and eight A sixth transmitter channel baseband signal processor 513, the output signal of the eighth passage eight transmitter baseband signal processor 517 is not inverted. The meaning of flipping is that 0 becomes 1, and 1 becomes 0.

The eight-channel first transmitter flip 504, the eight-channel third transmitter flip 508, the eight-channel fifth transmitter flip 512, the eight-channel seventh transmitter flip 516, and the eight-channel second transmitter flip are turned on. 506, an eight-channel fourth transmitter flip 510, an eight-channel sixth transmitter flip 514, an eight-channel eighth transmitter flip 518, and an eight-channel transmitter multiplexer 502 output signal will be an interlaced coded signal; The flipper of the even path is turned on, the flipper of the odd path is not turned on, and the multiplexer also outputs the interleaved coded signal.

The eight-channel first transmitter flip 504, the eight-channel third transmitter flip 508, the eight-channel fifth transmitter flip 512, the eight-channel seventh transmitter flip 516, and the eight-channel second transmitter are not turned on. a flip 506, an eight-channel fourth transmitter flip 510, An eight-pass sixth transmitter flip 514, an eight-way eighth transmitter flip 518, and an eight-channel transmitter multiplexer 502 output signal will be the normal encoded signal.

Referring to FIG. 5, a parallel digital circuit of 2n channels is provided, which can output a normal coded signal sequence or a baseband signal processing circuit of an interleaved coded signal sequence. In this embodiment, the flipper of the odd path is turned on, the flipper of the even path is not turned on, and the multiplexer outputs the interleaved coded signal as an example. The 2n path transmitter demultiplexer 601 converts the input serial high speed data into 2n channels of relatively low speed parallel data, activated by software, activate 2n path first transmitter baseband flip 604 in 2n path first transmitter baseband signal processor 603, activate 2n path third transmitter baseband signal processor 607 The 2n path third transmitter flip 608, and so on, activates the odd-pass transmitter flip-flop to activate the 2n-path 2n-1 transmitter flip 612 in the 2n-channel 2n-1 transmitter baseband signal processor 611. Inverting the output signal of the odd-numbered path such as the 2n path first transmitter

baseband signal processor

603, 2n path third transmitter

baseband signal processor

607, 2n path 2n-1 transmitter

baseband signal processor

611, 2n path The output signals of the even path of the second transmitter

baseband signal processor

605, 2n path fourth transmitter

baseband signal processor

609, 2n path 2n transmitter baseband signal processor 613 are not inverted. The meaning of flipping is that 0 becomes 1, and 1 becomes 0.

Turn on the 2n path

first transmitter flip

604, 2n path

third transmitter flip

608, 2n path 2n-1 transmitter flip 612 and other odd-numbered channel flip-flops, do not turn on 2n path

second transmitter flip

606, 2n path fourth

transmitter flip flop

610, 2n path 2n transmitter flip 614 and other even path transmitter flip-flops, 2n path transmitter multiplexer 602 output signal will be interlaced coded signal; similarly, The flipper of the even path is turned on, the flipper of the odd path is not turned on, and the multiplexer also outputs the interleaved coded signal.

Transmitter flipping of odd-numbered paths such as 2n path

first transmitter flip

604, 2n path

third transmitter flip

608, 2n path 2n-1 transmitter flip 612 The transmitter flipper of the even path of the 2n path

second transmitter flip

606, 2n path

4th transmitter flip

610, 2n path 2n transmitter flip 614, etc., is not turned on, and the output signal will be a normal coded signal.

Referring to FIG. 6, an embodiment of the present invention further provides a high-speed full digital receiver calibration method based on interlaced coding, where the calibration method includes the following steps:

S1, the transmitter starts at time t0, and the transmitter initialization state 101 is between time t0 and time t2. In the transmitter initialization state 101, the amplitude of the signal sent by the transmitter is unstable, and the baseband signal is interlaced.

S2, the transmitter is initialized at time t2, and the transmitter waits for state 102 temporarily between time t2 and time t3. In the transient waiting state 102 of the transmitter, the amplitude of the signal sent by the transmitter is stable, and the baseband signal still uses interlaced coding;

S3. The transmitter ends the transient waiting state 102 of the transmitter at time t3, and enters the normal working state 103 of the transmitter. Under the normal working state 103 of the transmitter, the amplitude of the signal sent by the transmitter is stable, and the baseband signal is changed to normal coding;

S4. When the amplitude of the signal received by the receiver is less than the amplitude threshold, the receiver is in the receiver signal loss state 104; when the receiver detects that the amplitude of the received signal is greater than the amplitude threshold at time t1, it is considered that the transmitter has entered a transmitter initialization state 101, using the received signal for receiver ADC coarse calibration 105;

S5. After the receiver ADC coarse calibration 105 is completed, the receiver enters the receiver to check the coding state 106. When the receiver checks the coding state 106, the receiver performs digital signal processing on the received signal to obtain the demodulated baseband signal. And constantly checking whether the baseband signal is normal or interlaced;

S6. The receiver finds that the baseband signal has become normal coding at time t3, indicating that the remote transmitter has entered the normal working state 103 of the transmitter, and a stable signal is sent, and the receiver uses the signal to perform the precision calibration of the receiver ADC 107. In the receiver ADC fine school After the quasi 107 is completed, the receiver enters the normal operating state 108.

A person skilled in the art can make various modifications and variations to the embodiments of the present invention, and such modifications and variations are within the scope of the present invention. .

The contents not described in detail in the specification are prior art known to those skilled in the art.

Claims

A high-speed full digital receiver calibration system based on interlaced coding, characterized in that the system comprises a transmitter and a receiver;

The transmitter is configured to: select to transmit a normal encoded signal or an interlaced encoded signal according to a signal amplitude;

The receiver is configured to: receive a signal of the transmitter, and perform an analog-to-digital converter ADC calibration of the receiver;

The transmitter includes a demultiplexer, a baseband signal processor, a flipper, and a multiplexer, the demultiplexer connecting two or more baseband signal processors, the demultiplexer and a baseband signal The processor converts the input serial high-speed data into parallel data and performs baseband signal processing. The flipper can invert the output signal of the transmitter baseband signal processor, and the multiplexer is used to convert the parallel data into a serial high-speed baseband signal.
The interleaved code-based high-speed all-digital receiver calibration system according to claim 1, wherein said transmitter and receiver both use a digital circuit-based baseband signal processing circuit, and the normal coding and interlaced coding are converted by digital The circuit is generated.
The high-speed all-digital receiver calibration system based on interlaced coding according to claim 2, wherein the baseband signal transmitted by the transmitter adopts a fixed format, and the receiver fixes the signal when receiving the signal and processing the baseband signal. The format is synchronized, and the receiver recognizes the interlaced code by using the format synchronization with the baseband signal transmitted by the transmitter in the receiver to check the coding state.
A high-speed all-digital receiver calibration system based on interlaced coding according to claim 3, wherein said receiver sequentially attempts to format the received signal by using an interleave coding reception mode and a normal coding reception mode, Which receiving mode is used The format can be synchronized to identify whether the encoding mode of the current transmitter is normal encoding or interlaced encoding.
The high speed all digital receiver calibration system based on interlaced coding according to any one of claims 1 to 4, characterized in that: two or more baseband signal processors of the transmitter are connected with a flip Each baseband signal processor and the flipper connected to the baseband signal processor form a data output path, and the flipper on each path is switched on and off, enabling the baseband signal processing circuit to output a normal coded signal sequence. And switching of the interleaved coded signal sequence such that the multiplexer outputs the normal coded signal and the interleaved coded signal.
The interlaced coded high speed all digital receiver calibration system of claim 5 wherein said flipper is activated by software setting.
The interleaved code-based high speed all digital receiver calibration system of claim 6 wherein:

For interlaced coded signals, the flipper of the odd path is turned on, the flipper of the even path is not turned on, the multiplexer outputs the interleaved coded signal, or the flipper of the even path is turned on, the flipper of the odd path is not turned on, and the multiplexer outputs the interleaved code signal;

For a normal coded signal, the flipper of the odd path is not turned on, the flipper of the even path is not turned on, and the multiplexer outputs a normal coded signal.
A method for interleaving-based high-speed full digital receiver calibration system according to claim 1, comprising the steps of:

A. The transmitter is started. In the initial state of the transmitter, the amplitude of the signal sent by the transmitter is unstable, and the baseband signal is interlaced.

B. The transmitter enters the normal working state and transmits under the normal working state of the transmitter. The amplitude of the signal sent by the machine is stable, and the baseband signal is changed to normal coding;

C. The receiver performs digital signal processing on the received signal to obtain a demodulated baseband signal, and continuously checks whether the baseband signal is normal or interlaced;

D. When the receiver finds that the baseband signal becomes normal coding, the receiver uses the signal to perform fine calibration of the analog-to-digital converter of the receiver. After the receiver's analog-to-digital converter ADC is perfectly calibrated, the receiver enters normal operation. status.
The interleaved code-based high-speed all-digital receiver calibration method according to claim 8, wherein the step A and the step B further comprise the following steps: after the transmitter is initialized, the transmitter enters a short time. Waiting state, in the transient waiting state of the transmitter, the amplitude of the signal sent by the transmitter is stable, the baseband signal is still interlaced, and the transmitter enters the normal working state after the transient waiting state.
The high-speed full digital receiver calibration method based on interlaced coding according to claim 8 or 9, wherein the step B and the step C further comprise the following steps: when the amplitude of the signal received by the receiver is smaller than At the amplitude threshold, the receiver is in the receiver signal loss state; when the receiver detects that the received signal amplitude is greater than the amplitude threshold, the receiver uses the received signal to perform coarse calibration of the receiver's analog-to-digital converter ADC; After the machine's analog-to-digital converter ADC is roughly calibrated, the receiver enters the check code state.