CN117539815A - Communication method and communication system between double FPGAs - Google Patents

Abstract

The invention provides a communication method and a communication system between double FPGAs, which solve the problem of low communication transmission rate between FPGAs. The communication method comprises the following steps: receiving a first clock signal, and performing frequency conversion on the first clock signal to obtain a second clock signal, wherein the frequency of the second clock signal is N times of that of the first clock signal, and N is a positive integer greater than 1; performing phase transformation on the first clock signal to obtain a third clock signal, wherein the third clock signal has the same frequency as the first clock signal but a phase difference; transmitting the first bit data at a rising edge of the third clock signal; transmitting one bit data at each rising edge and falling edge of the second clock signal; and transmitting the third clock signal.

Description

Communication method and communication system between double FPGAs

Technical Field

The invention mainly relates to the field of communication, in particular to a communication method and a communication system between double FPGAs.

Background

In power electronics field designs, data transfer involving multiple chips is often required. The data transmission method commonly used between two FPGA chips comprises the following two methods: serial communication is a common way to transfer data between two FPGA chips. It involves transmitting one bit of data at a time over a single data line. The serial communication mode has a slow communication rate, and the transmission rate is generally below 100 Mbps. Parallel communication designs transmit multiple bits of data simultaneously over multiple data lines, which can provide faster data transfer rates than serial communication, but require more IO interfaces and FPGA vendors typically do not provide the relevant communication protocol IP cores or require pay-for-use, with poor portability.

Disclosure of Invention

The invention aims to solve the technical problems of slow serial communication speed and more IO interfaces occupied by parallel communication, and provides a communication method and a communication system between double FPGAs.

In order to solve the technical problems, the invention provides a communication method between double FPGAs, which comprises the following steps: receiving a first clock signal, and performing frequency conversion on the first clock signal to obtain a second clock signal, wherein the frequency of the second clock signal is N times of that of the first clock signal, and N is a positive integer greater than 1; performing phase transformation on the first clock signal to obtain a third clock signal, wherein the third clock signal has the same frequency as the first clock signal but a phase difference; transmitting the first bit data at a rising edge of the third clock signal; transmitting one bit data at each rising edge and falling edge of the second clock signal; and transmitting the third clock signal.

Optionally, the method further comprises: receiving the third clock signal, and performing frequency conversion on the third clock signal to obtain a fourth clock signal, wherein the frequency of the fourth clock signal is N times of that of the third clock signal, and N is a positive integer greater than 1; acquiring first bit data at a rising edge of the third clock signal; one bit data is acquired at each rising edge and falling edge of the fourth clock signal.

Optionally, the phase difference is 90 °.

Optionally, N is equal to 4.

In order to solve the technical problems, the invention provides a communication system between double FPGAs, comprising: the first FPGA module comprises a first phase-locked loop, a first data processing unit and a first communication interface unit which are sequentially connected; the second FPGA module comprises a second phase-locked loop, a second data processing unit and a second communication interface unit, wherein the second communication interface unit is connected with the first communication interface unit, the second phase-locked loop is connected with the second communication interface unit, and the second data processing unit is respectively connected with the second communication interface unit and the second phase-locked loop; the first communication interface unit and the second communication interface unit respectively comprise a TX-data differential interface, a TX-clock differential interface, an RX-data differential interface and an RX-clock differential interface, wherein the TX-data differential interface of the first communication interface unit is connected with the RX-data differential interface of the second communication interface unit, and the TX-clock differential interface of the first communication interface unit is connected with the RX-clock differential interface of the second communication interface unit.

Optionally, the first data processing unit and the second data processing unit each include an ODDR unit and an IDDR unit.

Optionally, the first phase-locked loop is configured to receive a first clock signal, and perform frequency conversion on the first clock signal to obtain a second clock signal, where the frequency of the second clock signal is N times that of the first clock signal, and N is a positive integer greater than 1; the first data processing unit is configured to send one bit of data on each rising edge and each falling edge of the second clock signal through its ODDR unit.

Optionally, the first data processing unit is further configured to: the first clock signal is subjected to phase transformation to obtain a third clock signal, the third clock signal has the same frequency as the first clock signal but a 90-degree phase difference, and first bit data are sent on the rising edge of the third clock signal; and transmitting the third clock signal.

Optionally, the second phase-locked loop is configured to receive the third clock signal, and perform frequency conversion on the third clock signal to obtain a fourth clock signal, where the frequency of the fourth clock signal is N times that of the third clock signal, and N is a positive integer greater than 1; the second data processing unit is configured to acquire one bit data at each rising edge and each falling edge of the fourth clock signal through its IDDR unit.

Optionally, the second data processing unit is further configured to obtain the first bit data on a rising edge of the third clock signal.

Optionally, the first FPGA module further includes a first buffer unit connected to the first data processing unit, and the second FPGA module further includes a second buffer unit connected to the second data processing unit.

Optionally, the system further comprises: and the clock module is connected with the first phase-locked loop and is used for providing the first clock signal for the first phase-locked loop.

Optionally, wherein N is equal to 4.

Optionally, the first data processing unit and the second data processing unit transmit data based on LVDS communication protocol.

Compared with the prior art, the invention has the following advantages:

according to the communication method and the communication system between the double FPGAs, the frequency of the clock signals is converted, and one bit data is updated on each rising edge and each falling edge of the converted clock signals respectively, so that the communication transmission rate is improved, and the communication method of the invention maximally supports the transmission rate of 1 Gbps; according to the invention, at least four groups of differential pins are directly connected with two FPGAs, and data transmission and reception can be completed without additional hardware, so that full duplex communication between the two FPGAs is realized; the communication method between the double FPGAs does not depend on specific FPGA chips and IP verification, and has good portability.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the principles of the invention. In the accompanying drawings:

FIG. 1 is a system block diagram of a communication system between dual FPGAs in accordance with an embodiment of the present invention;

fig. 2 is a schematic diagram of a connection of a first communication interface unit with a second communication interface unit.

Fig. 3 is a schematic diagram of a first FPGA module transmit signal according to an embodiment of the present invention.

Fig. 4 is a signal timing diagram of signals in the first FPGA module of fig. 3.

FIG. 5 is a diagram of a second FPGA module acquisition signal according to an embodiment of the present invention.

Fig. 6 is a signal timing diagram of the signals in the second FPGA module of fig. 5.

FIG. 7 is a flow chart of a method of communication between dual FPGAs in accordance with an embodiment of the present invention.

FIG. 8 is a flow chart of a method of communication between dual FPGAs of the preferred embodiment of FIG. 7.

Detailed Description

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are used in the description of the embodiments will be briefly described below. It is apparent that the drawings in the following description are only some examples or embodiments of the present application, and it is obvious to those skilled in the art that the present application may be applied to other similar situations according to the drawings without inventive effort. Unless otherwise apparent from the context of the language or otherwise specified, like reference numerals in the figures refer to like structures or operations.

Flowcharts are used in this application to describe the operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in order precisely. Rather, the various steps may be processed in reverse order or simultaneously. At the same time, other operations are added to or removed from these processes.

FIG. 1 is a system block diagram of a communication system between dual FPGAs in accordance with an embodiment of the present invention. As shown in fig. 1, the dual FPGA communication system 100 includes a first FPGA module 1 and a second FPGA module 2. The first FPGA module 11 includes a first phase-locked loop 11, a first data processing unit 12, and a first communication interface unit 13, which are sequentially connected. The second FPGA module 2 comprises a second phase-locked loop 21, a second data processing unit 22 and a second communication interface unit 23. The second communication interface unit 23 is connected to the first communication interface unit 13, the second phase locked loop 21 is connected to the second communication interface unit 23, and the second data processing unit 22 is connected to the second communication interface unit 23 and the second phase locked loop 21, respectively.

Fig. 2 is a schematic diagram of a connection of a first communication interface unit with a second communication interface unit. As shown in fig. 2. The first communication interface unit 13 and the second communication interface unit 23 include tx_data differential interfaces (TX DATA P and TX DATA N), TX clock differential interfaces (TX CLK x1_p and TX CLK x1_n), rx_data differential interfaces (rx_data_p and rx_data_n), and rx_clock differential interfaces (rx_clk_x1_p and rx_clk_x1_n), respectively.

The tx_data differential interfaces (tx_data_p and tx_data_n) of the first communication interface unit 13 are connected to the rx_data differential interfaces (rx_data_p and rx_data_n) of the second communication interface unit 23, and the tx_clock differential interfaces (tx_clk_x1_p and tx_clk_x1_n) of the first communication interface unit 13 are connected to the rx_clock differential interfaces (rx_clk_x1_p and rx_clk_x1_n) of the second communication interface unit 23.

The tx_data differential interfaces (tx_data_p and tx_data_n) of the second communication interface unit 23 are connected to the rx_data differential interfaces (rx_data_p and rx_data_n) of the first communication interface unit 13, and the tx_clock differential interfaces (tx_clk_x1_p and tx_clk_x1_n) of the second communication interface unit 23 are connected to the rx_clock differential interfaces (rx_clk_x1_p and rx_clk_x1_n) of the first communication interface unit 13. It can be known that the first FPGA module 1 only needs to occupy 8 IO pins, and the second FPGA module 2 only needs to occupy 8 IO pins, so that full duplex communication between the first FPGA module 1 and the second FPGA module 2 can be achieved.

Alternatively, as shown in fig. 1, the first data processing unit 12 includes an ODDR unit 121 and an IDDR unit 122. The second data processing unit 22 includes an ODDR unit 221 and an IDDR unit 222.ODDR (Output Double Data Rate, double data rate output register) units can convert single-edge data signals to double-edge (rising, falling edge of clock) data signals, commonly used in serial-parallel data designs. IDDR (Input Double Date Rate, double data rate input register) units can convert a two-edge (rising edge, falling edge of clock) data signal to a single-edge data signal, commonly used in serial-parallel data designs.

Optionally, the first FPGA module 1 further comprises a first buffer unit connected to the first data processing unit 12, and the second FPGA module 2 further comprises a second buffer unit connected to the second data processing unit 22. The first buffer unit and the second buffer unit are used for storing the transmitted or received data.

Optionally, the system further comprises a clock module, which is connected to the first phase locked loop 11 and is configured to provide a first clock signal to the first phase locked loop 11.

Fig. 3 is a schematic diagram of a first FPGA module transmit signal according to an embodiment of the present invention. As shown in fig. 3, the first phase-locked loop 11 is configured to receive a first clock signal CLK, and perform frequency conversion on the first clock signal CLK to obtain a second clock signal, where the frequency of the second clock signal is N times that of the first clock signal, and N is a positive integer greater than 1. In this embodiment, N is equal to 4, and the second clock signal is CLKx4. Optionally, the first phase-locked loop 11 is further configured to output the same frequency clock signal CLKx1, wherein there is no phase difference between CLK, CLKx1 and CLKx4. Where the first clock signal CLK may be from a clock unit external to the communication system, the first clock signal CLK may also be from a clock unit internal to the communication system when the communication system 100 further comprises a clock unit. The input data LVDS_IN [7:0] is the data which the first FPGA module needs to send to the second FPGA module. The input data LVDS_IN [7:0] can be from a storage unit outside the system, and when the first FPGA module 1 further comprises a buffer unit, the input data LVDS_IN [7:0] can also be from the buffer unit of the first FPGA module 1.

The first data processing unit 12 is configured to transmit one bit data at each rising edge and falling edge of the second clock signal CLKx4 through its ODDR unit 121, respectively.

Optionally, the first data processing unit 12 is further configured to perform phase transformation on the first clock signal CLK to obtain a third clock signal tx_clk_x1. The third clock signal tx_clk_x1 is the same frequency as the first clock signal CLK, but 90 ° out of phase.

Fig. 4 is a signal timing diagram of signals in the first FPGA module of fig. 3. As shown in fig. 4, the frequency of the second clock signal CLKx4 is four times that of the first clock signal CLK. The third clock signal tx_clk_x1 is the same frequency as the first clock signal CLK, but 90 ° out of phase. The first data processing unit 12 transmits the first bit data (bit 0) on the rising edge of the third clock signal tx_clk_x1, and then transmits one bit data on each of the rising and falling edges of the second clock signal CLKx4, respectively, to realize transmission of 8 bit data (bit 0 to bit 7) within 1 CLKx1 time.

As shown in fig. 3, the first DATA processing unit 12 outputs a DATA output signal tx_data and a third clock signal tx_clk_x1 to the first communication interface unit 13. Specifically, the DATA output signal tx_data is output to the tx_data differential interface of the first communication interface unit 13, and the third clock signal tx_clk_x1 is output to the tx_clock differential interface of the first communication interface unit 13.

FIG. 5 is a diagram of a second FPGA module acquisition signal according to an embodiment of the present invention. As shown in fig. 5, the second phase locked loop 21 acquires a clock signal RX CLK x1 from the rx_clock differential interface of the second communication interface unit 23, wherein the clock signal RX CLK x1 and the third clock signal TX CLK x1 are the same signal, except that the naming is different in the first FPGA module and the second FPGA module, and the clock signal rx_clk_x1 is hereinafter also referred to as the third clock signal. The second phase-locked loop 21 is configured to perform frequency conversion on the third clock signal rx_clk_x1 to obtain a fourth clock signal, where the frequency of the fourth clock signal is N times that of the third clock signal, and N is a positive integer greater than 1. In this embodiment, N is equal to 4, and the fourth clock signal is r_clkx4. Optionally, the second phase-locked loop 21 is further configured to output the same frequency clock signal r_clkx1, wherein there is no phase difference between rx_clkx1, r_clkx1 and r_clkx4. The second DATA processing unit 22 is configured to obtain a DATA input signal rx_data from the rx_data differential interface of the second communication interface unit 23, where the DATA input signal rx_data and the DATA output signal tx_data in fig. 3 are the same signal. The second data processing unit 22 acquires one bit data at each rising and falling edge of the fourth clock signal r_clkx4 through its IDDR unit 222, respectively.

Fig. 6 is a signal timing diagram of the signals in the second FPGA module of fig. 5. As shown in fig. 6, the fourth clock signal r_clkx4 has a frequency four times that of the third clock signal r_clkx1. The second data processing unit 22 transmits the first bit data (bit 0) on the rising edge of the third clock signal rx_clk_x1, and then transmits one bit data on each of the rising and falling edges of the fourth clock signal r_clkx4, respectively, to realize transmission of 8 bit data (bit 0 to bit 7) within 1 rx_clkx1 time.

Optionally, the first data processing unit and the second data processing unit transmit data based on an LVDS (Low Voltage Differential Signaling ) communication protocol. The core of the LVDS technology is that data is transmitted in a high-speed differential mode by adopting an extremely low voltage swing, so that point-to-point or point-to-multipoint connection can be realized.

The communication system between the double FPGAs realizes full duplex communication between the double FPGAs by mutually matching the first phase-locked loop, the first data processing unit, the second phase-locked loop and the second data processing unit; at least, only four groups of differential pins are directly connected with two FPGAs, and data transmission and reception can be completed without additional hardware; the communication system between the double FPGAs does not depend on a specific FPGA chip and IP verification, and has good portability.

The invention also provides a communication method between the double FPGAs. FIG. 7 is a flow chart of a method of communication between dual FPGAs in accordance with an embodiment of the present invention. The communication method between the double FPGAs is executed between a first FPGA module and a second FPGA module, wherein one FPGA module is used as a transmitting end, and the other FPGA module is used as a receiving end. As shown in fig. 7, the communication method 700 between dual FPGAs includes the following steps:

step S71: and receiving a first clock signal, and performing frequency conversion on the first clock signal to obtain a second clock signal, wherein the frequency of the second clock signal is N times that of the first clock signal, and N is a positive integer greater than 1.

Step S72: the first clock signal is subjected to phase transformation to obtain a third clock signal, and the third clock signal has the same frequency as the first clock signal but a phase difference. Preferably, the phase difference is 90 °.

Step S73: transmitting the first bit data at a rising edge of the third clock signal;

step S74: one bit data is transmitted at each rising and falling edge of the second clock signal, respectively.

Step S75: a third clock signal is transmitted.

Wherein steps S71 to S75 are performed at the transmitting end. Steps S71 to S75 will be described below with reference to fig. 4. As shown in fig. 4, the frequency of the second clock signal CLKx4 is four times that of the first clock signal CLK. The third clock signal tx_clk_x1 is the same frequency as the first clock signal CLK, but 90 ° out of phase. The first bit data (bit 0) is transmitted on the rising edge of the third clock signal tx_clk_x1, and then one bit data is transmitted on each rising edge and falling edge of the second clock signal CLKx4, respectively, so that 8 bit data (bit 0 to bit 7) are transmitted within 1 CLKx1 time.

FIG. 8 is a flow chart of a method of communication between dual FPGAs of the preferred embodiment of FIG. 7. As shown in fig. 8, the communication method 800 between dual FPGAs further includes the steps of:

step S76: receiving a third clock signal, and performing frequency conversion on the third clock signal to obtain a fourth clock signal, wherein the frequency of the fourth clock signal is N times of that of the third clock signal, and N is a positive integer greater than 1;

step S77: the first bit data is acquired at the rising edge of the third clock signal.

Step S78: one bit data is acquired at each rising edge and falling edge of the fourth clock signal, respectively.

Wherein steps S76 to S78 are performed at the receiving end. Steps S76 to S78 will be described below with reference to fig. 6. As shown in fig. 6, the fourth clock signal r_clkx4 has a frequency four times that of the third clock signal r_clkx1. The first bit data (bit 0) is transmitted on the rising edge of the third clock signal rx_clkx1, and then one bit data is transmitted on each rising edge and falling edge of the fourth clock signal r_clkx4, respectively, so that 8 bit data (bit 0 to bit 7) are transmitted within 1 rx_clkx1 time.

According to the communication method between the double FPGAs, the clock signals are subjected to frequency conversion, and one bit data is updated on each rising edge and each falling edge of the converted clock signals respectively, so that the communication transmission rate is improved, and the communication method of the invention maximally supports the transmission rate of 1 Gbps; according to the invention, at least four groups of differential pins are directly connected with two FPGAs, and data transmission and reception can be completed without additional hardware, so that full duplex communication between the two FPGAs is realized; the communication method between the double FPGAs does not depend on specific FPGA chips and IP verification, and has good portability.

While the basic concepts have been described above, it will be apparent to those skilled in the art that the above disclosure is by way of example only and is not intended to be limiting. Although not explicitly described herein, various modifications, improvements, and adaptations of the present application may occur to one skilled in the art. Such modifications, improvements, and modifications are intended to be suggested within this application, and are therefore within the spirit and scope of the exemplary embodiments of this application.

Meanwhile, the present application uses specific words to describe embodiments of the present application. Reference to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic is associated with at least one embodiment of the present application. Thus, it should be emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various positions in this specification are not necessarily referring to the same embodiment. Furthermore, certain features, structures, or characteristics of one or more embodiments of the present application may be combined as suitable.

As used in this application and in the claims, the terms "a," "an," "the," and/or "the" are not specific to the singular, but may include the plural, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that the steps and elements are explicitly identified, and they do not constitute an exclusive list, as other steps or elements may be included in a method or apparatus.

The relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present application unless it is specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate. In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

In addition, the terms "first", "second", etc. are used to define the components, and are merely for convenience of distinguishing the corresponding components, and unless otherwise stated, the terms have no special meaning, and thus should not be construed as limiting the scope of the present application. Furthermore, although terms used in the present application are selected from publicly known and commonly used terms, some terms mentioned in the specification of the present application may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Furthermore, it is required that the present application be understood, not simply by the actual terms used but by the meaning of each term lying within.

Some aspects of the present application may be performed entirely by hardware, entirely by software (including firmware, resident software, micro-code, etc.) or by a combination of hardware and software. The above hardware or software may be referred to as a "data block," module, "" engine, "" unit, "" component, "or" system. The processor may be one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital signal processing devices (DAPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, or a combination thereof. Furthermore, aspects of the present application may take the form of a computer product, comprising computer-readable program code, embodied in one or more computer-readable media. For example, computer-readable media can include, but are not limited to, magnetic storage devices (e.g., hard disk, floppy disk, tape … …), optical disk (e.g., compact disk CD, digital versatile disk DVD … …), smart card, and flash memory devices (e.g., card, stick, key drive … …).

While the present application has been described with reference to the present specific embodiments, those of ordinary skill in the art will recognize that the above embodiments are for illustrative purposes only, and that various equivalent changes or substitutions can be made without departing from the spirit of the present application, and therefore, all changes and modifications to the embodiments described above are intended to be within the scope of the claims of the present application.

Claims (16)

1. A method of communication between dual FPGAs, comprising:

receiving a first clock signal, and performing frequency conversion on the first clock signal to obtain a second clock signal, wherein the frequency of the second clock signal is N times of that of the first clock signal, and N is a positive integer greater than 1;

performing phase transformation on the first clock signal to obtain a third clock signal, wherein the third clock signal has the same frequency as the first clock signal but a phase difference;

transmitting the first bit data at a rising edge of the third clock signal;

transmitting one bit data at each rising edge and falling edge of the second clock signal; and

and transmitting the third clock signal.

2. The communication method as claimed in claim 1, further comprising:

receiving the third clock signal, and performing frequency conversion on the third clock signal to obtain a fourth clock signal, wherein the frequency of the fourth clock signal is N times of that of the third clock signal, and N is a positive integer greater than 1;

acquiring first bit data at a rising edge of the third clock signal;

one bit data is acquired at each rising edge and falling edge of the fourth clock signal.

3. The communication method of claim 2, wherein data is transmitted over a tx_data differential interface and the third clock signal is transmitted over a tx_clock differential interface.

4. A communication method as claimed in claim 3, characterized in that data is acquired via an rx_data differential interface and the third clock signal is received via an rx_clock differential interface.

5. The communication method of claim 1, wherein the phase difference is 90 °.

6. The communication method of claim 1, wherein N is equal to 4.

7. A dual FPGA communication system, comprising:

the first FPGA module comprises a first phase-locked loop, a first data processing unit and a first communication interface unit which are sequentially connected;

the second FPGA module comprises a second phase-locked loop, a second data processing unit and a second communication interface unit, wherein the second communication interface unit is connected with the first communication interface unit, the second phase-locked loop is connected with the second communication interface unit, and the second data processing unit is respectively connected with the second communication interface unit and the second phase-locked loop;

the first communication interface unit and the second communication interface unit respectively comprise a TX-data differential interface, a TX-clock differential interface, an RX-data differential interface and an RX-clock differential interface, wherein the TX-data differential interface of the first communication interface unit is connected with the RX-data differential interface of the second communication interface unit, and the TX-clock differential interface of the first communication interface unit is connected with the RX-clock differential interface of the second communication interface unit.

8. The communication system of claim 7, wherein the first data processing unit and the second data processing unit each comprise an ODDR unit and an IDDR unit.

9. The communication system of claim 8, wherein the first phase-locked loop is configured to receive a first clock signal, and to frequency convert the first clock signal to obtain a second clock signal, the second clock signal having a frequency N times the first clock signal, the N being a positive integer greater than 1;

the first data processing unit is configured to send one bit of data on each rising edge and each falling edge of the second clock signal through its ODDR unit.

10. The communication system of claim 9, wherein the first data processing unit is further configured to: performing phase transformation on the first clock signal to obtain a third clock signal, wherein the third clock signal has the same frequency as the first clock signal but has a phase difference, and first bit data are sent on the rising edge of the third clock signal; and transmitting the third clock signal.

11. The communication system of claim 10, wherein the second phase-locked loop is configured to receive the third clock signal, and to frequency convert the third clock signal to obtain a fourth clock signal, the fourth clock signal having a frequency N times the third clock signal, the N being a positive integer greater than 1;

the second data processing unit is configured to acquire one bit data at each rising edge and each falling edge of the fourth clock signal through its IDDR unit.

12. The communication system of claim 11, wherein the second data processing unit is further configured to obtain the first bit data at a rising edge of the third clock signal.

13. The communication system of claim 7, wherein the first FPGA module further comprises a first buffer unit coupled to the first data processing unit, and the second FPGA module further comprises a second buffer unit coupled to the second data processing unit.

14. The communication system of claim 9, further comprising: and the clock module is connected with the first phase-locked loop and is used for providing the first clock signal for the first phase-locked loop.

15. A communication system according to any of claims 7 to 14, wherein N is equal to 4.

16. The communication system according to any of claims 7 to 14, wherein the first data processing unit and the second data processing unit transmit data based on an LVDS communication protocol.