JP3221201B2 - A / D / D / A converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an A / D converter for converting an analog signal to a digital signal and a D / A converter for converting a digital signal to an analog signal in one LSI.
The present invention relates to an oversampling-type A / D / D / A conversion device housed in a computer.

[0002]

2. Description of the Related Art In recent years, due to improvements in LSI processing technology and design demands for high density, miniaturization, and low power consumption, some of the components of the converter are shared when performing A / D conversion and D / A conversion. By doing so, the system is often simplified.

A conventional A / D / D / A converter is shown in the drawing and will be described. In FIG. 2, reference numeral 201 denotes an A / D converter, which converts an analog signal into digital data that is oversampled to a sampling frequency 64 fs, which is 64 times the sampling frequency fs that is desired to be finally obtained. Reference numeral 202 denotes a comb filter, which is an A / D converter 201.
The sampling frequency of the digital data output by
Decimate to 1/6 sampling frequency 4fs. Reference numeral 205 denotes a serial-parallel converter, which operates as an interface for converting a serial digital signal into parallel digital data. Numeral 203 denotes a digital filter, which operates either as a digital filter for decimation or a digital filter for oversampling in accordance with a control signal MODE. When used as a digital filter for decimation, the sampling frequency of the input digital data is Is decimated to a quarter sampling frequency fs, and when used as a digital filter for oversampling, oversampling is performed to a sampling frequency 8fs which is eight times the sampling frequency of the input digital data. Reference numeral 204 denotes a parallel-serial converter, and a digital filter 203
Operates as an interface for converting the parallel digital data output by the device into a serial digital signal. A D / A converter 206 converts digital data output from the digital filter 203 into an analog signal.

The operation of the A / D / D / A converter configured as described above will be described below.

First, at the time of A / D conversion, the analog signal is A
The digital data is converted into digital data that is oversampled at a sampling frequency of 64 fs by the / D converter 201, and is converted into digital data decimated at 4 fs by the comb filter 202. Then, the signal is decimated to a sampling frequency fs by the digital filter 203 and is converted to a serial digital signal by the parallel-serial converter 204.

On the other hand, at the time of D / A conversion, a serial digital signal is converted into parallel digital data by a serial-parallel converter 205, oversampled by a digital filter 203 to a sampling frequency of 8 fs, and a D / A converter 206. Is converted into an analog signal.

As described above, the operation of the digital filter 203 is selectively used for A / D conversion and D / A conversion, thereby simplifying and streamlining the system.

[0008]

However, in the above-mentioned conventional configuration, at the time of A / D conversion, the serial-parallel converter and the D / A converter which are not involved in the A / D conversion operate.
Conversely, at the time of D / A conversion, A / D that is not involved in D / A conversion
The converter, the comb filter, and the parallel-serial converter also operate, and there is a problem that extra power is consumed.

The present invention solves the above-mentioned conventional problem, in which the operation of blocks not involved in A / D conversion is stopped during A / D conversion, and the operation is not involved in D / A conversion during D / A conversion. It is an object of the present invention to provide an A / D / D / A converter with low power consumption by stopping the operation of a block.

[0010]

In order to achieve the above object, an A / D / D / A converter according to the present invention comprises: an A / D converter for converting an analog signal into digital data by oversampling; It removes high-frequency digital data, and the comb filter for decimation operation, di
A first interface for converting digital signals into digital data of a predetermined format; and an output of the comb filter.
Or the output of the first interface as an input,
Performs a simulation operation or oversampling operation.
A digital filter, a second interface for outputting the output of the digital filter in a predetermined format,
A D / A converter for converting digital data output from the digital filter into an analog signal;
It comprises a converter, the comb filter, the second interface or the first interface, and a control circuit for controlling the D / A converter.

[0011]

With this configuration, the oversampling type A / D / D / A converter of the present invention stops the operation of the parallel-serial converter and the D / A converter at the time of A / D conversion, and performs D / A conversion. Sometimes, the power consumption is reduced by stopping the operation of the A / D converter, the comb filter, and the parallel-serial converter.

[0012]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, components having the same configuration as in FIG. 2 are denoted by the same reference numerals, and detailed description is omitted.

In FIG. 1, reference numeral 101 denotes a system clock generator, which includes an A / D converter 201 and a comb filter 20.
2, the clock CLK1 supplied to the parallel-serial converter 204, and the serial-parallel converter 205
A clock CLK2 to be supplied to the A converter 206 and a clock CLK to be supplied to the digital filter 203 are generated, and control is performed to select whether the entire block operates as an A / D converter or a D / A converter. Depending on the signal MODE, the clock CLK1 or the clock C
The supply of LK2 is stopped.

The operation of the oversampling A / D / D / A converter configured as described above will be described.

When the operation of the A / D converter is selected by the control signal MODE, the analog signal input to the A / D converter 201 is converted into digital data oversampled to a sampling frequency of 64 fs. The comb filter 202 decimates the digital data output from the A / D converter 201 to a sampling frequency of 4 fs. The digital filter 203 operates as a digital filter for decimation, and
2 converts the output digital data to the sampling frequency f
Decimate to s. Parallel-serial converter 2
Reference numeral 04 converts the parallel digital data output from the digital filter 203 into a serial digital signal. At this time, the clock CLK2 generated by the system clock generator 101 is
5 and the D / A converter 206 are not supplied, so that the block operation of the serial-parallel converter 205 and the D / A converter 206 is stopped and unnecessary power consumption can be suppressed.

When the operation of the D / A converter is selected by the control signal MODE, the serial digital signal is converted into parallel digital data by the serial-parallel converter 205 and output, and is input to the digital filter 203. The digital filter 203 operates as a digital filter for oversampling, oversamples input digital data to a sampling frequency of 8 fs, and is converted by the D / A converter 206 into an analog signal. At this time, the clock CLK1 generated by the system clock generator 101 is supplied to the A / D converter 2
01, the comb filter 202, and the parallel-serial converter 204, so that the A / D
The converter 201, the comb filter 202, and the parallel-serial converter 204 stop the block operation, and can suppress unnecessary power consumption.

As described above, according to the present embodiment, the control signal M
When the operation of the A / D converter is selected by the ODE, the clock CLK2 is not supplied to the serial-parallel converter 205 and the D / A converter 206 and the operation is stopped, and the D / A converter is controlled by the control signal MODE. When the operation is selected, the clock CLK1 is not supplied to the A / D converter 201, the comb filter 202, and the parallel-serial converter 204, and the operation stops. As a result, the overall power consumption can be reduced.

In this embodiment, C generated by the system clock generator 101 according to the control signal MODE is used.
Although the supply of LK1 or CLK2 is stopped to stop the operation of each block, the supply of power may be stopped for each block and the operation may be stopped for each block. In this case, a power supply line for supplying power to the A / D converter 201, the comb filter 202, the parallel-serial converter 204, and a power supply line for supplying power to the serial-parallel converter 205 and the D / A converter 206 Are connected to the respective analog switches, and the control signal MODE determines which analog switch is to be opened. When the operation of the A / D converter is selected by the control signal MODE,
Serial-parallel converter 205 and D / A converter 206
When the analog switch of the power supply line for supplying power to the power supply is opened and the operation of the D / A converter is selected by the control signal MODE, the A / D converter 201 and the comb filter 202
If the analog switch opens the power supply line for supplying power to the parallel-serial converter 204, the supply of power is stopped and excess power consumption can be suppressed.

[0019]

As described above, according to the present invention, the A / D
During the conversion, the supply of the clock CLK of the block excluding the digital filter involved in the D / A conversion is stopped,
At the time of the / A conversion, the supply of the clock CLK of the block excluding the digital filter involved in the A / D conversion is stopped. Therefore, each operation is stopped, and the low sampling of the oversampling type A / D / D / A converter is performed. Power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an A / D / D / A converter according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional A / D / D / A converter.

[Explanation of symbols]

 Reference Signs List 101 system clock generator 201 A / D converter 202 comb filter 203 digital filter 204 parallel-serial converter 205 serial-parallel converter 206 D / A converter

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yasunori Tani 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-5-183436 (JP, A) 66224 (JP, A) JP-A-62-140519 (JP, A) JP-A-52-43346 (JP, A) JP-A-3-41826 (JP, A) JP-A-60-253330 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 1/00-11/00

Claims (3)

(57) [Claims] An A / D converter for converting an analog signal into digital data by oversampling; and a decimation circuit for removing a high-frequency component of the digital data.
A comb filter for performing an operation , a first interface for converting a digital signal into digital data of a predetermined format, and an output of the comb filter or the first interface.
With the output of the chair as input,
A digital filter that performs a bar sampling operation, a second interface that converts the output of the digital filter in a predetermined format and outputs the digital filter, and a D / A converter that converts digital data output from the digital filter to an analog signal The A / D converter, the comb filter, the second interface, the first interface and the D interface.
A control circuit for controlling the A / D converter. At the time of A / D conversion, the digital filter inputs the output of the comb filter and performs a decimation operation. stops the operation of one of the interface the D / a converter, at the time of D / a converter, the digital filter is the first
And the control circuit stops the operation of the A / D converter, the comb filter, and the second interface. D / A converter. 2. The control circuit according to claim 1 , wherein the A / D converter performs a first I / O conversion.
Stop supplying clock to interface and D / A converter
Therefore, at the time of D / A conversion, the A / D converter, the comb filter, and the
2. The A / D / D / A converter according to claim 1 , wherein the supply of the clock to the second interface is stopped . 3. The control circuit according to claim 1 , wherein the A / D converter performs a first I / O conversion.
Stop supplying power to the interface and D / A converter,
At the time of D / A conversion, the A / D converter, the comb filter, and the second
2. The A / D / D / A converter according to claim 1 , wherein supply of power to the interface is stopped .