JPH10322214A - A/d converter with offset elimination function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate an offset that is changing during the operation and to minimize a time till a stable value is obtained after power-on by allowing the A/D converter to have a high pass filter and a filter coefficient control means that is connected to the high pass filter and generates a coefficient control signal to instruct revision of a variable filter coefficient during the operation. SOLUTION: The converter A is provided with a ΔΣ modulator 1, a decimation filter 2, a high pass filter(HPF) 3, and a filter coefficient control section 4. The HPF 3 receives an output of the decimation filter 2 at its input and receives a signal to control a filter coefficient at its control input and produces an output of a result of applying high pass filter processing by a designated filter coefficient to the output of the decimation filter 2. An output of the filter coefficient control section 4 is given to a control input of the HPF 3, the filter coefficient control signal is fed to the HPF 3 during the operation of the converter A to select a proper coefficient for the HPF 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a .DELTA..SIGMA.-type analog-to-digital converter, and more particularly to the removal of DC components in a .DELTA..SIGMA.-type analog-to-digital converter.

[0002]

2. Description of the Related Art Conventionally, there are roughly two methods for removing a DC component, that is, an offset, in a ΔΣ type analog-to-digital converter (ADC). Part 2
The two methods are offset calibration and
And a method using a high-pass filter. The offset calibration method is described, for example, in US Pat.
3,807, which stores an offset value of a ΔΣ ADC in a memory and subtracts the value from a digitally converted value (a value after passing through a ΔΣ modulator and a decimation filter). By doing so, the DC component is removed. The second high-pass filter (H
The PF) method removes a DC component by passing a digitally converted value through a high-pass filter.

[0003]

In the above offset calibration method, if the offset value changes due to external factors or the like while the ADC operates for a long time, a difference from the value initially stored in the memory appears. And therefore completely DC
The components cannot be removed. On the other hand, the high-pass filter method is also effective in removing such an offset that changes during the operation. However, this high-pass filter method has a very low cut-off frequency required for removing a DC component as a filter characteristic, so that it takes a long time to remove the first DC component after operating the filter. . This time occupies a considerable portion of the time required from when the ADC is powered on until a stable normal value is obtained.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a Δ− type analog-digital converter capable of removing an offset that changes during operation and minimizing the time from power-on until a stable value is obtained. It is to be.

[0005]

According to the present invention, there is provided a ΔΣ analog-to-digital converter which receives an analog input signal and generates a digital output signal representing the digital input signal in digital form. B) a ΔΣ modulator connected to receive the analog input signal and generating a modulator output; and b) decimation connected to receive the modulator output and generating a decimation filter output. A filter, c) a high-pass filter connected to receive the decimation filter output and producing a high-pass filter output, the high-pass filter having a filter coefficient that is variable during operation; D) a coefficient connected to the high-pass filter and instructing a change of the variable filter coefficient during operation; Comprising a filter coefficient control means for generating a control signal.

According to the present invention, the change of the variable filter coefficient can be performed when the converter is powered up. Further, according to the present invention, the characteristic of the high-pass filter is obtained by using a Z function.

Equation 3] _{H (Z) = H 1 (} Z) / H 2 (Z) H 1 (Z) = Σ l = 0 M b l Z -l H 2 (Z) = Σ l = 0 N a l Z expressed in ^-l, where a _l and b _l coefficients, M and N is a positive integer, the filter coefficients of the variable, the first filter coefficients of a first combination of a _l and b _l value , A second combination of _al and _bl values different from the first combination.
And the filter coefficients of Furthermore, according to the present invention, the high-pass filter is a first-order filter, and its characteristic is determined by using a Z function.

H (Z) = H ₁ (Z) / H ₂ (Z) H ₁ (Z) = 1−Z ⁻¹ H ₂ (Z) = 1−kZ ⁻¹ where k is a coefficient Wherein the variable filter coefficient can be composed of a first filter coefficient consisting of a first value k and a second filter coefficient consisting of a second value k. In this case, the first filter coefficient may be a value close to 1, and the second filter coefficient may be 0 or a value close to 0.

Further, according to the present invention, the high-pass filter includes: a) a subtractor having a first input receiving the output of the decimation filter, a second input, and an output; A delay having an input connected to the output and an output; c) a first input connected to receive the output of the decimation filter; a second input connected to the output of the delay; A second adder having an output that produces a filter output;
D) a feedback circuit having an input connected to the output of the adder and an output connected to the second input of the subtractor, the feedback circuit having an in-operation variable feedback coefficient acting as the filter coefficient; , Can be configured.

According to the present invention, the feedback circuit can be of a type using an adder or a type using a multiplier.

Further, according to the present invention, the filter coefficient control means includes timing control means for supplying a first timing signal as the coefficient control signal, wherein the first timing signal is supplied from a reset of the converter. Until a first predetermined time, the second filter coefficient may be indicated to be used. At this time, the converter may further include dither control means for controlling application of a DC dither component to the input of the ΔΣ modulator. In this case, the timing control means can further generate a second timing signal to be supplied to the dither control means, wherein the second timing signal is generated from the reset of the converter by the first predetermined time. May also indicate that the DC dither component should not be applied for a short second predetermined time.

[0010]

Next, the present invention will be described in detail with reference to examples.

FIG. 1 shows a ΔΣ type analog according to the present invention.
1 is a block diagram illustrating a first embodiment A of a digital converter (ADC). As shown, the converter A includes a ΔΣ modulator 1, a decimation filter 2, a high-pass filter (HPF) 3, and a filter coefficient control unit 4. The ΔΣ modulator 1 receives an analog input to be converted to a digital form at an input, and generates a Δ た modulated modulation output at its output. A decimation filter 2 receiving this modulated output at its input performs decimation on its input and produces the result at its output.

The next HPF 3 has one input, one control input, and one output, and has a variable filter coefficient group. The characteristic of this high-pass filter is Z
Generally expressed by a function

Equation 5] _{H (Z) = H 1 (} Z) / H 2 (Z) H 1 (Z) = Σ l = 0 M b l Z -l H 2 (Z) = Σ l = 0 N a l Z ^-l . Here, a _l and b _l are coefficients, and M and N are positive integers. In this case, a first filter coefficient group consisting of a first combination of a _l and b _l value, the first combined with different a _l and b _l value of a second of a second combination of The filter coefficient group forms a variable filter coefficient. The filter time constant of the filter coefficient increases as the cutoff frequency of the HPF approaches zero. On the other hand, HP
As the cutoff frequency of F increases, the time constant decreases. This HPF3 has a decimation
A filter output is received, a control input receives a signal for controlling a filter coefficient, and an output includes a high-pass filter processing by a designated filter coefficient for its decimation.
Generates the result performed on the filter output. The output of the filter coefficient control unit 4 is connected to the control input of the HPF 3, and supplies the filter coefficient control signal to the HPF 3 during the operation of the converter A, and uses an appropriate value as the HPF coefficient. Let it.

With this configuration, during the A / D conversion operation of the converter A, the HPF 3 can execute the filtering process with the filter coefficient group specified by the control unit 4, and accordingly, an appropriate operation can be performed according to the situation during the operation. High-pass filtering can be performed with a time constant or cutoff frequency. Thus, when the offset of the ADC is removed, the filter time constant is set to a large value. On the other hand, when it is desired to stabilize the digital output quickly, for example, at the time of power-on,
The filter time constant can be reduced.

Next, a Δ 図 type analog-digital converter B according to a second embodiment of the present invention will be described with reference to FIG. This converter B is a more specific part of the converter of FIG. 1 and has the same ΔΣ as the elements 1, 2, and 3 of FIG.
Modulator 10, decimation filter 20, and H
The PF includes a PF 30, a timing controller 40 partially corresponding to the filter coefficient controller 4, a serial controller 50, and a dither controller 60. In the case of the present embodiment, the HPF 30 is configured by a first-order filter, and its characteristic is represented by using a Z function.

[6] a _{H (Z) = H 1 (} Z) / H 2 (Z) H 1 (Z) = 1-Z -1 H 2 (Z) = 1-kZ -1, where k is the coefficient It is. The variable filter coefficient is this coefficient k, and in the present embodiment, a first filter coefficient consisting of a first value k and a second filter coefficient consisting of a second value k are used. . The filter coefficient k is, for example, a value in a range from 0 to 1. As the filter coefficient approaches a value of 1, the time constant of the filter increases and the cutoff frequency of the HPF approaches zero. On the other hand, as the filter coefficient approaches 0, the time constant decreases and the cutoff frequency of the HPF increases.

The serial control unit 50 includes an HPF 30
In the form of a serial filter. As is well known, the dither control unit 60 has a certain level of DC bias voltage (this bias voltage source (not shown)) for the analog input received at the input of the Δ た め modulator in order to shift the tone frequency to outside the audio frequency band. Is in the ΔΣ modulator). In the case of this embodiment, the Δ さ ら に modulator 10 further has first and second control inputs, and receives a signal from the timing controller 40 and a control input from the dither control unit 60. . The first control input is for opening and closing an input gate (not shown) for receiving an analog input to the modulator 10, and the second control input is an adder for receiving the analog input. (Not shown) for opening and closing an input gate (not shown) of dither to be added. The serial control unit 50 also has a control input, and activates its serial digital output according to the logic state of this input.

Timing controller 40 generates several timing signals for controlling the operation of converter B. The first timing signal I1 is supplied to a control input of the HPF 30 and a first control input of the modulator 10,
A second timing signal I2 is provided to an input of the dither control, and a third timing signal I3 is provided to a control input of the serial control.

Here, the circuit configuration of the HPF 30 will be described with reference to FIG. As shown, the HPF 30
Subtractor 32, 1-clock delay unit 34, adder 36
And a feedback circuit 38.
The clock frequency of the converter B is 44.1 KHz. The subtractor 32 receives a 28-bit binary input X, which is the output of the decimation filter, at a negative input, and generates a result obtained by subtracting the input X from a positive input as a 28-bit binary output. An adder 36 which receives the output of the subtracter at one positive input via a delay unit 34 receives the input X at the other positive input, and adds the result of addition to each other to 2
Generated as an 8-bit binary output Y. This output Y is
This is an input to the serial control unit 50 at the next stage. The output Y becomes the input A to the feedback circuit, and the feedback circuit generates a binary feedback output B to be applied to the positive input of the subtractor 32.

One embodiment of the feedback circuit 38 according to the present invention shown in FIG. 3 is of the adder type which switches between two non-zero filter coefficients (or feedback coefficients) k1 and k2. k1 is “8191/8192”, which is almost a value of 1, and k2 is “1/8192”, which is almost a value of 0. Specifically, the circuit 38 includes an adder 380
0, a shift circuit 3802 that shifts 13 bits to the left (represented by "$ 13"), 41 AND gates 3804 (represented by "x41"), and 28 (represented by "x28")
EX-OR gate 3806 and inverter 38
08. The adder 3800 internally includes
Most significant M of 28-bit input A [27: 0] received at negative input
41-bit binary signal C by extending the SB bit
[40: 0], that is, multiply A by 1 (note that a binary signal is a two's complement representation). Therefore, this C
Each bit of [40:28] is equal to A [27] and C [27:
0] is equal to A [27: 0]. The shift circuit 3802 shifts the input A 13 bits to the left by 2 ¹³ times (= 81
92 times) to obtain a 41-bit binary signal D [40: 0].
Therefore, D [40:13] is equal to A [27: 0] and D [40:13]
[12: 0] are all 0. An AND gate 3804 receiving this 41-bit output at one input performs an AND operation on each bit and the timing signal, and outputs the result to E [40:
0]. That is, I1 = low (“0”)
, E [40: 0] are all 0, while I1
= High ("1"), E [40: 0] becomes D [40:
0].

The adder 3800 outputs a binary signal E [40: 0].
Is subtracted from the binary signal C [40: 0], and the upper 28
Only the bits are output as F [27: 0]. Since the lower 13 bits are not used, the signal E is 2 ⁻¹³ times. Therefore, the signal E at this time is (EC) / 8192, that is, I1 =
At the time of 1, F = (8192A-A) / 8192 = (8191/819)
2) A = k1 · A On the other hand, when I1 = 0, F
= −A (1/8192) = − k2 · A. This latter I1
In the case of = 0, it becomes negative. Therefore, only when I1 = 0, the signal is inverted by the next-stage EX-OR gate to always generate a positive binary output G [27: 0]. This is B [27: 0].
After all, when I1 = 0, B = k2 · A is almost equal to zero, and therefore the time constant of the HPF becomes very small.
On the other hand, when I1 = 1, B = k1 · A, which is substantially equal to A, which is an extremely large time constant required for removing the DC offset.

Next, an overall operation of the Δ 全体 ADC of FIG. 2 including the high-pass filter circuit of FIG. 3 will be described with reference to FIG. First, as shown in FIG. 4A, a reset signal RS (not shown in FIG. 2) applied from the system using the ADC to the timing controller 40 is used to turn on the ADC. Transition from low to high at t1. Based on this signal, the controller 40, as shown in FIGS. 4 (c), (b) and (d),
It is generated by forming timing signals I1, I2 and I3. Each of these timing signals is initially low. Therefore, the input gate for receiving the analog input of the modulator 10 is closed, and the input gate for applying DC dither in the modulator is also closed. Furthermore, HPF
Since the filter coefficient of 30 is I1 = 0, the filter coefficient is k2 (almost zero), and the digital output of the serial control unit 50 is not active. In such a state, first, the timing signal I2 becomes t1
From low to high at, for example, 300 milliseconds later, thereby causing the dither control unit 60 to apply a DC bias to the analog input in the modulator 10. For this reason, the output of the modulator 10 and the output of the decimation filter ((e) and (f) in FIG.
A DC component in which the C dither bias and the offset are combined appears. At this time, as shown in FIG.
In the output of F30, after t2, a noise (shown in an enlarged manner under FIG. 4 (g)) which rises sharply and gradually falls as shown in the figure appears for several tens of microseconds, and thereafter the DC component is reduced. Completely removed. In the related art, the period of the noise portion is 1-2 seconds because the coefficient value of the HPF is close to 1 in the related art. However, in the present invention, the period can be extremely shortened to several tens of microseconds.

At t3, for example, 20 milliseconds after t2, the timing signal I1 goes high, thereby opening the input gate in the ΔΣ modulator 10 and starting A / D conversion of the analog input at the same time. The filter coefficient of the HPF 30 switches from k1 to k2 (almost 1). As a result, the offset removal function in the A / D conversion is completely activated. At t4, which is 20 milliseconds after t3, the timing signal I3 goes from low to high, activating the digital output of the serial control unit 50, thereby generating an A / D conversion output in serial form.

Although the ADC according to the embodiment of the present invention has been described above, the feedback circuit of the HPF 30 may have various other circuit configurations.
Some examples are described below.

FIG. 5 shows a circuit 38A according to a second embodiment of the feedback circuit 38 of the HPF 30. The purpose of this embodiment of FIG.
The object is to provide a circuit free of bit errors. The reason why a one-bit error occurs in the circuit of FIG. 3 is that, in the circuit of the present invention, since the binary signal is represented by a two's complement, the EX of FIG.
-It is when inverting by the OR gate. Since this one-bit error occurs only while the second coefficient k2 is used, that is, until t3 in FIG. 4 (while I1 = 0), a digital output error does not substantially occur. However, a circuit that does not cause such a one-bit error is possible.

More specifically, the feedback circuit 38 shown in FIG.
In A, one AND gate 3810 and an adder 3812 are further provided in addition to the circuit 38 of FIG. AN
One input of the D gate 3810 has an inverter 3808.
And the other input receives a binary signal of one. The output of this AND gate is received at one input of adder 3812, and the other input is output G [27: 0] of EX-OR gate 3806. The output of the AND gate is high when I1 = 0, and the output of the AND gate is high, that is, 1 at this time.
Add to the least significant bit of the X-OR gate output and output the result as B [27: 0] above. As a result, a one-bit error caused by inversion by EX-OR when I1 = 0 can be eliminated.

FIG. 6 shows a feedback circuit 38B according to a third embodiment, which is of the adder type which does not cause a bit error, and which has the same non-zero value ("8191/1"). 8192 ”,“ 1/8192 ”) and two coefficients k1
And k2. The realization of these coefficients is determined by the circuit 38
In B, it is performed as follows. That is, the left 13-bit shift circuit 3820 multiplies by 8192, and the shift circuit 3822 that receives this output and shifts by 13 bits to the right (represented by “$ 13”) multiplies by 1/8192 so that the output is 1 ×. A. The next selector 3824 receives the output of the shift circuit 3820 at the “1” input,
2 is received at the "0" input and I
Receive 1 Therefore, when I1 = 0, one time A
Is output, and when I1 = 1, 8192 times A is output. The output of this selector is connected to the positive input of an adder 3826, and the negative input of the adder is connected to the output of 28 AND gates 3828. One input of AND gate 3828 receives input A, and the other input receives I1. Therefore, the output of the AND gate is I
When 1 = 0, it is 0, and when I1 = 1, it is 1 times A. The adder 3826 is a circuit similar to the adder 3800 in FIG. 3. The adder 3826 performs bit expansion on a negative input, and outputs 1/8192 times since only the upper 28 bits of 41 bits are used. Has a function. As a result, in the adder 3826, when I = 0, the positive input is 1.
A, the negative input is 0, and the output is (1 · A-0) 8192 = (1 /
8192) A = k2 · A. On the other hand, when I = 1,
The positive input is 8192 · A, the negative input is 1 · A, and the output is (8192 · A−1 ·
A) 8192 = (8191/8192) A = k1 · A Therefore, the same output B as in FIG. 5 can be obtained without performing inversion as in the EX-OR gate.

FIG. 7 shows a feedback circuit 38C for the HPF 30 according to the fourth embodiment, which is also an adder type having a non-zero coefficient without any bit error. In this circuit, a coefficient k1 is realized by “1” input of the selector 3830, and a coefficient k2 is realized by “0” input. First, the "1" input side will be described.
Is of a circuit similar to the adder 3800 of FIG. 3, so that its negative input is 1 × A and its positive input is
8192 · A for the 3-bit shift circuit 3834;
Therefore, the output of the adder is (8191/8192) A = k1 ·
A. On the other hand, on the “0” input side of the selector 3830, (1/81)
92) ・ A. When I = 0, selector 3830 outputs k2 · A, which is a “0” input, as an output. On the other hand, I
When = 1, it is k1 · A which is “1” input. Thereby, the same function as that of FIG. 5 can be realized.

Next, a multiplier type feedback circuit having a non-zero coefficient will be described with reference to FIGS. First, the feedback circuit 38 shown in FIG.
D is a multiplier 3840, a k1 coefficient circuit 3842, k2
It comprises a coefficient circuit 3844 and a switch 3846. The input of the multiplier receives signal A, the output generates signal B, and the coefficient input is connected to the output of switch 3846. The "1" side input terminal of this switch is connected to a circuit 38.
The circuit 3844 is connected to receive a coefficient k1 of a 13-bit binary signal, and the “0” side input terminal is connected to receive a coefficient k2 of a 13-bit binary signal from the circuit 3844.
The control input of this switch receives I1 and, depending on its state, connects the corresponding input to the output. Therefore, when I1 = 1, multiplier 3840 calculates k1 ·
A is output, and when I1 = 0, k2 · A is output. In this embodiment, there is an advantage that the value of the coefficient can be arbitrarily changed.

The feedback circuit 38E of the embodiment shown in FIG.
Is different from the circuit 38D of FIG.
In that a coefficient circuit corresponding to each of the multipliers is provided, and a selector 3847 for selecting and outputting the outputs of the two multipliers is provided. This circuit 3
8E also functions in the same way as the circuit 38D, and has the advantage that the coefficient value can be set arbitrarily.

The feedback circuit 38 of the embodiment shown in FIG.
E is different from the circuit 38E in FIG. 9 in that a set of a multiplier and a k2 coefficient circuit is replaced by a “$ 13” shift circuit 3848.
Is replaced by Therefore, the coefficient k2 is 1 /
8192 is a fixed value. k1 can be set arbitrarily.

Next, an embodiment of a feedback circuit in which k2 of two coefficients k1 and k2 is zero will be described with reference to FIGS. First, the adder type feedback circuit shown in FIGS. 11 and 12 will be described.

The circuit 38G of the eighth embodiment shown in FIG.
An adder 3850 having a circuit similar to the adder 3800 of
“$ 13” shift circuit 3852 and AND gate 385
4. For details, see AND gate 3854
Has one input receiving a binary signal A and the other input receiving I1. The output of this gate is connected to the negative input of adder 3850, and its positive input is connected to the output of gate 3854 via left shift circuit 3852. When I1 = 1, adder 3850 outputs the same output as adder 3832 in FIG. 7, that is, (8191/8192) A =
Generates k1 · A. On the other hand, when I1 = 0, the outputs of the gate 3854 are all zero, and therefore the output of the adder 3850 is also zero. This means that k2 = 0.

The feedback circuit 38H of the ninth embodiment of FIG. 12 is similar to the circuit 38G of FIG. 11, except that an AND gate is provided at the output side of the adder instead of the input side. Is a point. That is, the output of adder 3850 is connected to one input of AND gate 3856, I1 is connected to the other input, and the negative input of the adder and the input of shift circuit 3852 are connected to receive signal A. ing. This circuit H works the same as the circuit 38G.

Next, the multiplier type feedback circuit shown in FIGS. 13 to 15 will be described. First, the first of FIG.
The feedback circuit 38I of the zeroth embodiment includes a multiplier 3860 receiving the signal A at the input, a k1 coefficient circuit 3862 having an output connected to the coefficient input of the multiplier, and one input connected to the output of the multiplier and the other input. And an AND gate 3864 connected to receive I1. This circuit converts the coefficient k2 (= 0) when I1 = 0 into an AND gate 3
The circuit is the same as the circuits in FIGS.

The feedback circuit 38J of the eleventh embodiment shown in FIG.
1 except that the ND gate 3866 is connected.
3 and the function is the same. In this case, the output of the AND gate 3866 when I = 0 is the coefficient k2 (= 0).

The feedback circuit 38K of the twelfth embodiment of FIG. 15 has the same function as the circuit 38I of FIG. 13 except that an AND gate 3868 is provided on the input side of the multiplier. As described above, HPF3
Various configurations are possible for the configuration of the 0 feedback circuit, and an appropriate configuration can be used depending on the purpose, application, and the like.

In the embodiments of the present invention described above, various modifications can be made by those skilled in the art. For example, in the above embodiment, an example of two filter coefficients has been described. However, according to the present invention, if necessary, the number of filter coefficients may be increased or the value of the above example may be used as the value of the filter coefficient. Values other than can be used.

[0037]

According to the present invention described above, the removal of the changing offset and the reduction of the time required for stable generation of the ADC output can be realized only by switching the filter coefficients of the high-pass filter. Further, as a result of shortening the time required for generating a stable output at power-on, it is advantageous for shortening the test time of the ADC. Further, when the ADC is used in a device having a power-down mode for power saving, it is also effective in shortening the time required for generating a stable output at every power-up when returning from the power-down mode.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a ΔΣ type analog-digital converter (ADC) A according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a ΔΣ type analog-digital converter B according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing the high-pass filter of FIG. 2 in detail.

FIG. 4 shows the Δ of FIG. 2 with the high-pass filter circuit of FIG. 3;
6 is a timing chart for explaining the overall operation of the Σ-type ADC.

FIG. 5 is a circuit diagram showing a circuit 38A according to a second embodiment of the feedback circuit 38 of the high-pass filter 30 of FIG. 3;

FIG. 6 is a circuit 3 according to a third embodiment of the feedback circuit 38;
FIG. 8B is a circuit diagram showing 8B.

FIG. 7 is a circuit 3 according to a fourth embodiment of the feedback circuit 38;
The circuit diagram showing 8C.

FIG. 8 is a circuit 3 according to a fifth embodiment of the feedback circuit 38;
FIG. 9 is a circuit diagram showing 8D.

FIG. 9 is a circuit 3 of a sixth embodiment of the feedback circuit 38;
FIG. 8E is a circuit diagram showing 8E.

FIG. 10 is a circuit diagram showing a circuit 38F according to a seventh embodiment of the feedback circuit 38;

FIG. 11 is a circuit diagram showing a circuit 38G according to an eighth embodiment of the feedback circuit 38;

FIG. 12 is a circuit diagram showing a circuit 38H according to a ninth embodiment of the feedback circuit 38;

FIG. 13 is a circuit diagram showing a circuit 381 according to a tenth embodiment of the feedback circuit 38;

FIG. 14 is a circuit diagram showing a circuit 38J of an eleventh embodiment of the feedback circuit 38;

FIG. 15 is a circuit diagram showing a circuit 38K according to a twelfth embodiment of the feedback circuit 38;

[Description of Signs] 1,10: ΔΣ modulator 2, 20: decimation filter 3, 30: high-pass filter (HPF) 4: filter coefficient control unit 40: timing controller 50: serial control unit 60: dither control unit 38 , 38A-38K: Feedback circuit of HPF30

Claims (12)

[Claims] 1. A delta-sigma analog-to-digital converter that receives an analog input signal and generates a digital output signal representing the digital input signal in digital form, a) being connected to receive the analog input signal; A ΔΣ modulator for generating a modulator output, b) a decimation filter connected to receive the modulator output, and a decimation filter for generating a decimation filter output; c) receiving the decimation filter output A high-pass filter for generating a high-pass filter output, said high-pass filter having a variable filter coefficient during operation; and d) being connected to said high-pass filter during operation. Filter coefficient control means for generating a coefficient control signal for instructing a change of the variable filter coefficient. ΔΣ type analog-digital converter. 2. The ΔΣ analog-to-digital converter according to claim 1, wherein the variable filter coefficient is changed when the converter is powered up. 3. The converter according to claim 1, wherein the characteristic of the high-pass filter is expressed by the following equation: H (Z) = H ₁ (Z) / H ₂ (Z ) is represented by _{H 1 (Z) = Σ l} = 0 M b l Z -l H 2 (Z) = Σ l = 0 N a l Z -l, where a _l and b _l are coefficients, M and N is a positive integer, the filter coefficients of the variable, a _l and b _l value of the first filter coefficients of a first combination, wherein the first combination different a _l and b _l And a second filter coefficient comprising a second combination of the values of ?? 4. The converter according to claim 3, wherein the high-pass filter is a first-order filter, and its characteristic is expressed by using a Z function as follows: H (Z) = H ₁ ( Z) / H ₂ (Z) H ₁ (Z) = 1−Z ⁻¹ H ₂ (Z) = 1−kZ ⁻¹ , where k is a coefficient, and the variable filter coefficient is The first consisting of k with the value of 1
And a second filter coefficient consisting of a second value k. A ΔΣ type analog-digital converter. 5. The converter according to claim 4, wherein said first filter coefficient is a value close to 1, and said second filter coefficient is 0 or a value close to 0. ΔΣ type analog-digital converter. 6. The ΔΣ analog-to-digital converter according to claim 5, wherein said second filter coefficient is zero. 7. The converter according to claim 1, wherein said high-pass filter comprises: a) a first receiving means for receiving an output of said decimation filter.
B) a subtractor having an input, a second input, and an output; b) a delay having an input connected to the output of the subtractor; and an output; c) receiving the output of the decimation filter. An adder having a first input connected thereto, a second input connected to the output of the delay unit, and an output for generating the high-pass filter output; d) an input connected to the output of the adder; A feedback circuit having an output connected to a second input of the subtractor, the feedback circuit having an in-operation variable feedback coefficient acting as the filter coefficient. Digital converter. 8. A ΔΣ analog-digital converter according to claim 7, wherein said feedback circuit is of a type using an adder. 9. The ΔΣ analog-digital converter according to claim 7, wherein said feedback circuit is of a type using a multiplier. 10. The converter according to claim 7, wherein the filter coefficient control unit includes a timing control unit that supplies a first timing signal as the coefficient control signal. A ΔΣ analog-to-digital converter, wherein one timing signal indicates that the second filter coefficient is to be used for a first predetermined time from reset of the converter. 11. A converter according to claim 10, further comprising dither control means for controlling application of a DC dither component to an input of said ΔΣ modulator. Digital converter. 12. The converter according to claim 11, wherein said timing control means further generates a second timing signal to be supplied to said dither control means, wherein said second timing signal is output from said converter. From the reset
Indicating that the DC dither component should not be applied for a second predetermined time shorter than the first predetermined time;
ΔΣ type analog-digital converter characterized by the above-mentioned.