JP2005191810A - Digital/analog converter and microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an A/D converter capable of A/D conversion processing while necessary resolutions are flexibly set by analog inputs, and a microcomputer. <P>SOLUTION: Disclosed is the A/D converter which has an A/D control register 60 where control information on A/D conversion is set and has a function of performing oversampling while selecting one of a plurality of analog input channels AN0 to ANn. The A/D converter has a plurality of entries of conversion control information of the A/D control register 60 and also has a field where an oversampling ratio is set in each entry. According to settings of entries, an A/D conversion part 30 performs A/D conversion at a specified oversampling ratio, and a filter arithmetic circuit 10 performs filter processing with a specified filter coefficient and outputs an A/D conversion result data. Thus, the A/D conversion processing is carried out at oversampling ratios by analog inputs. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an analog / digital converter (A / D converter) and a microcomputer having an A / D converter, and more particularly to an A / D converter and a microcomputer having an oversampling function.

  With the development of integrated circuit technology, microcomputers having peripheral modules such as a memory, a timer, and an A / D converter on one chip have become mainstream. In a microcomputer equipped with these peripheral modules, as a control method, the control processing information to the control register by the MPU is not controlled by the micro processing unit (MPU), but the peripheral module includes a control register. Each peripheral module is operated based on the setting. It has been widely practiced to reduce the load on the MPU by such a control method and, as a result, improve the performance of the entire microcomputer.

  For example, when focusing on the technology of the A / D converter that is the subject of the present invention, according to Non-Patent Document 1, the control register (A / D control status register) of the A / D converter in the microcomputer is predetermined. Bits (bits 5 and 4: A / D modes 1 and 0 (ADM1, ADM0)), A / D conversion operation mode for multiple analog input channels, single mode, 4-channel scan mode, 8-channel scan The mode, 12 channel scan mode, etc. can be set. As a result, the A / D converter can perform a scanning operation independently of the MPU and without any involvement of the MPU. Here, the scan operation refers to an operation in which A / D conversion is continuously executed while sequentially selecting a plurality (one or more) of analog input channels. The single mode is a mode in which A / D conversion is performed for a specified single analog input channel.

For example, as described in Non-Patent Document 2, an oversampling A that includes a delta-sigma (ΔΣ) A / D converter in a microcomputer and improves the resolution of conversion by performing an oversampling operation. A / D converter is also provided. The ΔΣ A / D converter applies digital processing to a 1-bit A / D conversion result using a digital filter, an integrator, a sequential 1-bit A / D converter, and a D / A converter. Is.
"Hitachi SuperH RISC engine SH-2 SH7050 Series Hardware Manual", Hitachi, Ltd., September 1999, 5th edition, p. 469 “User's Manual V850ES / PM1 32-bit Single-Chip Microcomputer Hardware Edition μPD703228 Document No. U16237EJ2V0UD00 (2nd edition)”, NEC Electronics Corporation, July 2003, Chapter 12, p. 259-267, Internet <URL: http://www.necel.com/nesdis/image/U16237EJ2V0UD00.pdf>

  According to the prior art such as Non-Patent Document 1, it is possible to reduce the burden on the MPU by operating peripheral modules independently of the MPU, and as a result, it is possible to improve the performance of the entire microcomputer. Further, according to the prior art such as Non-Patent Document 2, the resolution of the A / D converter can be improved by performing an oversampling operation, and a microcomputer suitable for high-precision and high-speed control applications is provided. be able to.

  However, the above-described conventional technology can be more easily used for various applications in consideration of the case where the resolution required for each analog input is different in A / D conversion processing.

  For example, when controlling a hybrid vehicle, a 10-bit resolution A / D converter is sufficient as an input for controlling a vehicle engine, but a battery charge capacity (SOC: State of In order to estimate (Charge), it is necessary to A / D convert the terminal voltage and charge / discharge current of the battery with a resolution of 12 to 14 bits, and the required resolution differs.

  In view of the above problems, the main object of the present invention is to provide an oversampling A / D conversion function, and to perform A / D conversion by flexibly setting a necessary resolution for each analog input. It is to provide a D converter and a microcomputer.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  (1) In order to achieve the above object, an A / D converter according to the present invention includes a plurality of analog inputs, a multiplexer that selects any one of the plurality of analog inputs, and the selected analog input as an A / D converter. A / D conversion unit for D conversion, a filter operation circuit for filtering data after A / D conversion in the A / D conversion unit, a control register (A / D control register) for storing conversion control information, and a conversion result A conversion result register for storing data, the control register has a plurality of entries for conversion control information, has a field for setting an oversampling ratio for each entry, and based on the setting of the entry, An A / D conversion unit and a filter arithmetic circuit are caused to execute A / D conversion processing at an oversampling ratio for each analog input.

  With the above configuration, the A / D converter performs the A / D conversion (sampling) on the designated analog input at the number of times corresponding to the designated oversampling ratio based on the setting of the conversion control information in the plurality of entries of the control register. Filter with a predetermined filter coefficient and output as A / D conversion result data. The A / D converter performs A / D conversion processing at a specified resolution for each analog input based on the setting of the control register.

  (2) Further, the A / D converter of the present invention is characterized in that, in the A / D converter of (1), the plurality of entries in the control register are configured as entries for each analog input.

  In the control register entry format, the attribute of A / D conversion processing for one analog input can be specified by setting one entry, and by setting each entry, A with different attributes for each analog input can be specified. / D conversion processing can be specified.

  (3) In the A / D converter of the present invention, in the A / D converter of (1), the plurality of entries in the control register are configured as entries for each execution order of the A / D conversion process. It is characterized by that.

  In the entry format of the control register, the attribute of A / D conversion processing for one analog input can be specified by setting one entry, and the execution order of A / D conversion processing can be set by a plurality of entries. A / D conversion processing with different attributes for each analog input can be designated and executed in order.

  (4) In the A / D converter of the present invention, in the A / D converter of (1), a plurality of entries in the control register are configured as entries for each A / D conversion start factor. Features.

  In the entry format of the control register, A / D conversion processing with a predetermined attribute can be specified for a plurality of analog inputs by setting an entry corresponding to one conversion start factor, and A / D conversion with a different attribute for each activation start factor. A D conversion process can be specified and executed.

  (5) In the A / D converter according to the present invention, in the A / D converter according to (1), the control register has a field for setting a filter coefficient of a filter arithmetic circuit for each entry. Based on the setting of the coefficient, the filter arithmetic circuit is caused to execute the filtering process.

  With the above configuration, the A / D converter performs the A / D conversion (sampling) on the designated analog input at the number of times corresponding to the designated oversampling ratio based on the setting of the conversion control information in the plurality of entries of the control register. Filter with the specified filter coefficient and output as A / D conversion result data.

(6) The A / D converter of the present invention is the A / D converter of (5), wherein the filter arithmetic circuit has a filter coefficient of 2 ^−m or (1-2 ^−m ) (m : Integer).

In the above configuration, the filter operation circuit includes a shifter, an adder, a subtracter, and the like, and the operation is as follows, for example. The previous value is read from the conversion result register, multiplied by the coefficient 2- ^m, and the input value from the A / D converter is multiplied by the coefficient (1-2- ^m ), and the result of the operation is stored in the conversion result register. Written.

  (7) Moreover, the A / D converter of the present invention performs oversampling with a specified oversampling ratio on the first analog input among the plurality of analog inputs in the A / D converter of (1), In parallel with this, A / D conversion (usually A / D conversion or oversampling) for the second analog input is performed during individual sampling in oversampling of the first analog input while selecting the analog input. It is characterized by performing.

  (8) Moreover, the A / D converter of the present invention performs oversampling with a specified oversampling ratio on the first analog input among the plurality of analog inputs in the A / D converter of (1), At the same time, oversampling is performed on the second analog input with an oversampling ratio different from the oversampling ratio of the first analog input while selecting the analog input.

  (9) The microcomputer of the present invention includes the A / D converter according to any one of (1) to (7), an MPU, and a bus, and converts the control register and the A / D converter. The result register is written to and read from the MPU via the bus.

  With the above configuration, in this microcomputer, the MPU sets the A / D control register via the bus, controls the A / D converter, and performs a predetermined A / D conversion process. Then, the A / D conversion result is obtained by reading the data in the conversion result register. In this microcomputer, based on the setting of conversion control information to a plurality of entries in the control register of the A / D converter, conversion attributes for each analog input, for each A / D conversion processing execution order, or for each A / D conversion start factor To execute A / D conversion processing of a desired pattern.

  (10) The microcomputer of the present invention is the microcomputer of the above (9), which has a random access memory (RAM) and a direct memory access controller (DMAC), and a conversion result register is logically stored on the RAM. The data transfer is performed between the filter operation circuit and the conversion result register on the RAM by the DMAC.

  With this configuration, the microcomputer transfers the A / D conversion result data between the filter arithmetic circuit and the RAM by the DMAC. Since the A / D conversion result data is transferred onto the RAM that can be accessed at high speed from the MPU, the access time to the A / D conversion result data can be shortened.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, A / D conversion with a specified attribute for each analog input to the A / D conversion unit and the filter operation circuit based on the setting in a plurality of entries of conversion control information in the control register of the A / D converter Since the process is executed, an A / D conversion process with a necessary resolution can be realized by designating an oversampling ratio for each analog input channel. According to the present invention, it is possible to provide an A / D converter capable of flexibly setting a required A / D conversion resolution in accordance with an analog input and a microcomputer having the A / D converter.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a block diagram showing a configuration of an A / D converter in the embodiment of the present invention. The configuration of FIG. 1 shows the basic configuration of an A / D converter in some embodiments of the present invention. The A / D converter includes a plurality of analog inputs (analog input channels) AN0 to ANn, a multiplexer 40 that selects from the plurality of analog inputs AN0 to ANn, an A / D converter 30, a filter operation circuit 10, and conversion result data. Conversion result register 20, A / D control register 60 for storing conversion control information, and control logic 50.

  Based on the control from the control logic 50, the multiplexer 40 selects one of the analog inputs AN0 to ANn and inputs it to the A / D converter 30, and the A / D converter 30 selects the analog signal of the selected analog input. A / D conversion is performed on the digital data, and the digital data after A / D conversion is input to the filter arithmetic circuit 10. The filter arithmetic circuit 10 filters the input digital data after A / D conversion with a predetermined filter coefficient, and writes it as A / D conversion result data in the conversion result register 20.

  The control logic 50 controls the analog input selected by the multiplexer 40 based on the setting of the A / D control register 60, or controls the oversampling ratio in the A / D conversion process in the A / D conversion unit 30. The filter coefficient of the filter arithmetic circuit 10 is controlled, and the address selection of the conversion result register 20 is controlled.

  The A / D conversion unit 30 is a circuit unit having a function of performing oversampling A / D conversion, and performs an oversampling operation at an oversampling ratio designated by the setting of the A / D control register 60 or a normal A / D. Perform the conversion operation.

  The A / D control register 60 is a control register for storing various conversion control information related to the execution of A / D conversion processing in the A / D converter in addition to the setting of the oversampling ratio and the filter coefficient. The setting is written from the above. The A / D control register 60 in the A / D converter of the present embodiment has a plurality of entries for storing conversion control information, and each entry has a setting field for an oversampling ratio and a filter coefficient. The entry here is an individual conversion control information setting unit for controlling the execution of the A / D conversion process and designating the attribute. Conversion control information is written to each entry of the A / D control register 60 in response to the generation of an A / D conversion processing request (factor for starting or starting A / D conversion).

  In the case of an oversampling A / D converter, an A / D converter in a narrow sense that converts an analog signal into a digital signal and a filter operation circuit (digital filter) part are also referred to as an “A / D converter”. Often called. Here, the A / D converter in the narrow sense is the A / D converter 30, and the A / D converter including the filter arithmetic circuit 10 is distinguished from the A / D converter. The A / D conversion result data (or simply the conversion result) is data obtained by performing A / D conversion in the A / D conversion unit 30 and filter processing in the filter arithmetic circuit 10.

  When an oversampling A / D converter is realized, a delta sigma (ΔΣ) type is often used as the A / D converter. This is because the use of a delta sigma system improves the resolution almost in proportion to the first power of the oversampling ratio. However, it is not always a good idea to use a delta sigma type A / D converter of the A / D converter provided in the present invention. First of all, the delta-sigma A / D converter must store the remaining residual digitized at the time of conversion in an internal integrator and convert it by adding it to the next input. Therefore, when using a delta-sigma A / D converter with analog inputs switched by a multiplexer, each analog input has an integrator that stores conversion residuals in the number of analog inputs, and is linked to the multiplexer. Control to switch the integrator. For this reason, the circuit area is increased because a plurality of integrators are provided. Assuming that the noise component included in the input signal is statistically independent, the averaging reduces only in inverse proportion to the 1/2 of the oversampling ratio, so that the resolution of the A / D converter is oversampling ratio. Even if it is proportional to the first power of the power, the resolution is improved only in proportion to the first power of the whole as a result of being restricted by the noise component that decreases in inverse proportion to the first power of two.

  Conversion for executing A / D conversion from the MPU or the like to the A / D control register 60 in response to A / D conversion processing with a necessary resolution for analog input, for example, 10-bit resolution for engine control input. Control information is set. In this A / D converter, oversampling A / D conversion processing or normal A / D conversion processing is executed based on control information set in each entry of the A / D control register 60. Normal A / D conversion processing corresponds to A / D conversion processing with an oversampling ratio of 1. The conversion control information includes designation of a conversion target analog input channel, designation of its oversampling ratio and filter coefficient, designation of a conversion start factor, and the like.

  Subsequently, FIGS. 2 to 5 show different examples of the configuration of the A / D control register 60 shown in FIG. 1 as a configuration example of the A / D control register included in the A / D converter according to the embodiment of the present invention. The form is shown. These are respectively referred to as A / D control registers 60a, 60b, 60c, and 60d. The setting of other conversion control information other than that relating to the feature of the present invention in the A / D control register 60 is omitted.

  FIG. 2 is a diagram showing a configuration of the A / D control register 60a. The A / D control register 60a is configured to have an entry for each analog input as a plurality of entries of conversion control information. A / D conversion processing with a conversion attribute for each analog input can be specified by setting each entry. The A / D control register 60a has fields 201, 202, and 203 indicating the setting of the conversion start factor, oversampling ratio, and filter coefficient in each entry for each analog input.

  The conversion start factor field 201 is a field for setting which of a plurality of conversion start factors is a factor (trigger) to start A / D conversion of the corresponding analog input. The conversion start factor is a factor that activates or starts A / D conversion processing (a plurality of A / D conversions or a single A / D conversion) in the A / D converter. This conversion start factor includes a timer, a register write, an external request, and the like.

  The timer factor is a trigger that is generated when a counter of a timer provided in the microcomputer reaches a predetermined value or at a predetermined cycle, and can be set from a register provided in the timer. The register write factor is a trigger generated when the MPU writes to a control register indicating a conversion start request of the A / D converter. The external request factor is a trigger generated when a conversion start signal is input from the outside through an external terminal.

  The oversampling ratio field 202 is a field for designating an oversampling ratio at the time of A / D conversion processing of the corresponding analog input, and the number of times corresponding to the oversampling ratio set here when the A / D conversion processing is executed. Minute A / D conversion is performed. In the case of an instruction for A / D conversion (normal A / D conversion) without oversampling, this oversampling ratio may be set to 1.

In general, since the oversampling ratio is often a power of 2, if the oversampling ratio is expressed as 2 ^k and k is set in the oversampling ratio field 202 in the A / D control register 60, A The number of bits required for the configuration of the / D control register 60 can be reduced. In the case of a configuration in which this oversampling ratio is set by k, k = 0 may be set in the case of an instruction for A / D conversion processing without oversampling.

  The filter coefficient field 203 is a field for setting a decimator filter coefficient for oversampling. Based on the filter coefficient set here, the filter arithmetic circuit 10 performs a filtering process on the data after A / D conversion in the A / D conversion unit 30.

  In the entry format of the A / D control register 60a, an attribute of A / D conversion processing for one analog input can be specified by setting one entry, and different attributes are set for each analog input by setting each entry. A / D conversion processing can be specified.

  FIG. 3 is a diagram illustrating a configuration of the A / D control register 60b. In the configuration example, the A / D control register 60b includes an entry for each A / D conversion processing execution order as a plurality of entries of conversion control information. is there. The A / D control register 60b has fields 301, 302, and 303 indicating the setting of the analog input number, oversampling ratio, and filter coefficient in each entry for each A / D conversion processing execution order. For a plurality of entries in the A / D control register 60b, A / D conversion processing according to the control information set in the field of each entry is executed in order from top to bottom.

  The analog input number field 301 is a field for designating an analog input channel to be converted. For the analog input channel specified in the analog input number field 301, the oversampling operation or the normal A / D conversion operation is executed with the oversampling ratio specified in the oversampling ratio field 302 and the filter coefficient specified in the filter coefficient field 303. Is done. Similar to the oversampling ratio field 202 and the filter coefficient field 203 in FIG. 2, the oversampling ratio field 302 and the filter coefficient field 303 are fields for designating the oversampling ratio and the filter coefficient for the corresponding analog input channel, respectively.

  In the entry format of the A / D control register 60b, the A / D conversion processing attribute for one analog input can be specified by setting one entry, and the execution order of the A / D conversion processing is set by a plurality of entries. Thus, it is possible to designate and execute A / D conversion processing with different attributes for each analog input in order.

  Further, in the entry format of FIG. 3, each entry is further provided with a field for setting a conversion start factor as shown in FIG. 2, and the entry is designated based on the signal input of the conversion start factor designated in this field. The A / D conversion process may be started.

  FIG. 4 is a diagram showing a configuration of the A / D control register 60c. The A / D control register 60c has, as a plurality of entries of conversion control information, entries in the order of execution of A / D conversion processing, particularly A / D conversion. It is a structural example which has an entry for every unit operation | movement. This is a configuration in which a reset / integration field 402, which is a field for setting whether to continue or reset integration in the filter arithmetic circuit 10, is provided instead of the oversampling ratio field 302 in the entry format of FIG. The A / D control register 60c has fields 401, 402, and 403 indicating the setting of an analog input number, reset / integration, and filter coefficient in each entry. The analog input number field 401 is a field for designating an analog input channel to be converted, like the analog input number field 301 of FIG. The filter coefficient field 403 is a field for designating the filter coefficient of the A / D conversion process for the corresponding analog input channel, similarly to the filter coefficient field 303 of FIG.

  In this configuration, A / D conversion processing of a certain pattern, for example, A / D conversion processing with a predetermined oversampling ratio and filter coefficient for a certain input channel, is a set of control information entries for each A / D conversion unit operation. Specified by (multiple entries). In the case of oversampling processing, by setting “integration” in the reset / integration field 402 in the control information entry for each sampling, the integration operation is performed in the sampling of that step.

  In the entry format of the A / D control register 60c, the attribute of A / D conversion unit operation for one analog input can be specified by setting one entry, and A / D conversion processing with different attributes for each analog input is performed. It can be specified and executed in order.

  In the configuration of the A / D control register 60b shown in FIG. 3, when the A / D conversion for the number of times corresponding to the designated oversampling ratio for the analog input designated by an entry of an A / D conversion process is completed, the next entry is entered. The processing format shifts to A / D conversion processing of analog input specified by. On the other hand, in the configuration of the A / D control register 60c shown in FIG. 4, the A / D for another analog input is being executed during the A / D conversion processing corresponding to the designated oversampling ratio for one analog input. Conversion can be performed. The A / D converter performs oversampling at a specified oversampling ratio with a predetermined time interval for a certain analog input, and switches the analog input between the individual samplings while switching A / D for another analog input. Execute with D conversion in between. As the state of the entry in the A / D control register 60c, there is one entry instructing A / D conversion processing with another conversion pattern among a plurality of entries instructing A / D conversion processing with a certain conversion pattern. One or more will be sandwiched. Thus, the overall conversion processing performance can be improved by executing A / D conversion processing with different conversion attributes in parallel. A specific example of such conversion processing will be described later.

  FIG. 5 is a diagram illustrating a configuration of the A / D control register 60d. The A / D control register 60d is a configuration example having entries for each conversion start factor as a plurality of entries of the conversion control information. In the entry of the A / D control register 60d, ADENTr is an entry of control information regarding the A / D conversion process using the register write described above as a conversion start factor, and ADEntt is an A / D conversion of the timer factor described above. This is an entry for control information regarding processing, and ADENTe is an entry for control information regarding A / D conversion processing of the external request factor described above. Each entry for each conversion start factor in the A / D control register 60d has fields 501, 502, and 503 that indicate settings of an analog input number group, an oversampling ratio, and a filter coefficient.

  The analog input number group field 501 is composed of bits AE0 to AEn corresponding to each of a plurality of analog input channels, and is a field for designating an analog input channel to be converted by a corresponding conversion start factor. In the set value of the bit AEx corresponding to the analog input channel ANx, “1” designates “to be converted (valid)” and “0” designates “not to be converted (invalid)”. When the bit AEx is set to “1” (valid) in the analog input number group field 501, the A / D conversion process for the analog input ANx is started or started by the corresponding conversion start factor. If “1” (valid) is set for a plurality of bits in the analog input number group field 501, A / D conversion processing with a specified conversion attribute for a plurality of analog input channels is started or activated by a corresponding conversion start factor. Will be started.

  The oversampling ratio field 502 and the filter coefficient field 503 are fields for designating an oversampling ratio and a filter coefficient, respectively, as attributes in the A / D conversion process with the corresponding conversion start factor.

  In FIG. 5, the A / D control register 60 has a configuration having one entry for each conversion start factor, but a format having a plurality of entries for each conversion start factor is also possible. For example, if a plurality of registers for instructing the start of A / D conversion are provided, the A / D conversion control information entries ADENTr, that is, ADENTr0 to ADENTr1 of a plurality of register write factors can be used. Similarly, a configuration having a plurality of timers can be configured to have a plurality of timer factor entries ADDt0 to ADDtl. Further, if a plurality of external request inputs are provided, a format having a plurality of external request factor entries ADENTe0 to ADENTel can be adopted.

  In the entry format of the A / D control register 60d, predetermined A / D conversion processing attributes can be specified for a plurality of analog inputs by setting an entry corresponding to one conversion start factor. The A / D conversion process can be designated and executed.

  The A / D conversion processing in the A / D converter by the respective configurations 60a, 60b, 60c, 60d (FIGS. 2 to 5) of the A / D control register 60 of the A / D converter according to the present embodiment described above. Therefore, an oversampling ratio can be set for each analog input, and A / D conversion processing with a resolution required for each analog input can be realized. By setting different conversion attributes for each analog input, for each A / D conversion processing execution order, or for each conversion start factor, A / D conversion processing can be performed efficiently with a desired conversion processing pattern.

  FIG. 6 is a diagram showing an example of A / D conversion processing operation by the A / D converter in the embodiment of the present invention. A time-series A / D conversion operation pattern is shown. The triangle in the figure represents the A / D conversion unit operation.

  The A / D conversion process of group 1 on the left side of FIG. 6 shows an oversampling operation in which A / D conversion is continuously repeated for a single analog input channel. As an example, an oversampling operation for the analog input AN0 is shown. Thus, by performing A / D conversion (sampling) on a certain analog input continuously in a short cycle, the resolution of the A / D converter can be increased.

  The A / D conversion processing of group 2 on the right side of FIG. 6 performs oversampling at a predetermined period (oversampling ratio) with a certain time interval for a certain analog input (first analog input). An operation of performing A / D conversion on another one or more analog inputs (referred to as a second analog input) in parallel with the oversampling for the analog input is shown. The operation of A / D conversion for another second analog input is sandwiched between individual samplings (A / D conversion) for the first analog input.

  In the processing of group 2 in FIG. 6, as an example, oversampling is performed on the analog input AN0 at a predetermined period with a predetermined time interval, and at the same time, the analog inputs AN1 to AN10 are switched to normal A / A while switching the inputs. An operation pattern for performing D conversion (oversampling ratio = 1) is shown. The conversion cycle of the analog input AN0 is shorter than the conversion cycle of the analog inputs AN1 to AN10. Between each sampling (A / D conversion) for the analog input AN0 on the time series, A / D conversion operations for other analog inputs (AN1 to AN10) are sequentially sandwiched, and there is no break while switching inputs. In this form, A / D conversion is repeated.

  The example of the A / D conversion operation pattern of the group 2 is a case where the A / D conversion cycle of the first analog input AN0 is shorter than the A / D conversion cycle of the second analog inputs AN1 to AN10. The analog input A / D conversion cycle is the same as the second analog input A / D conversion cycle, and the conversion operation pattern in which both A / D conversions are executed alternately, the first analog input and the first analog input A conversion operation pattern in which both samplings are alternately executed at different oversampling ratios with the two analog inputs, and A / D conversion groups with different A / D conversion periods for a plurality of analog inputs are sequentially executed while switching the inputs. Various conversion operation patterns such as conversion operation patterns are possible.

  The conversion operation pattern (oversampling A / D conversion process for a single analog input) shown in group 1 of FIG. 6 can be realized by the configuration of all the A / D control registers 60 shown in FIGS. . When the conversion processing shown in group 1 is performed with the configuration of the A / D control register 60a in FIG. 2 (entry format for each analog input), a predetermined conversion start factor (for example, a timer factor is selected) for the entry of the analog input AN0. This can be realized by setting a conversion cycle in the timer register), an oversampling ratio, and a filter coefficient.

  When the conversion process shown in group 1 is performed with the configuration of the A / D control register 60b in FIG. 3 (entry format in the order of execution of the A / D conversion process), AN0 is designated as the analog input number in the first entry, This can be realized by setting a predetermined oversampling ratio and filter coefficient.

  When the conversion processing shown in group 1 is performed with the configuration of the A / D control register 60c in FIG. 4 (A / D conversion processing execution order, particularly entry format for each A / D conversion unit operation), designated oversampling is performed from the beginning. In a plurality of execution order entries corresponding to the ratio, AN0 is designated as the analog input number, “integration” is designated in the reset / integration field 402, and a predetermined filter coefficient is set. .

  When the conversion process shown in group 1 is performed with the configuration of the A / D control register 60d in FIG. 5 (entry format for each conversion start factor), an entry for a predetermined conversion start factor (for example, timer factor entry ADENTt is selected). In the analog input number group field 501, the bit AE0 corresponding to the analog input AN0 is set to “1” and the other bits are set to “0” to set a predetermined oversampling ratio and This can be realized by setting a filter coefficient.

  The conversion operation pattern shown in group 2 of FIG. 6 (simultaneous parallel A / D conversion processing with designated attributes for a plurality of analog inputs) is included in the configuration of the A / D control register 60 shown in FIGS. This can be realized in all except the configuration of FIG. When the conversion processing shown in group 2 is performed with the configuration of the A / D control register 60a in FIG. 2 (entry format for each analog input), a predetermined conversion start factor (for example, a timer factor is selected) as an entry for the analog input AN0. Set a conversion cycle in the timer register), set a predetermined oversampling ratio and filter coefficient, and select a predetermined conversion start factor (for example, a timer factor to select the timer register in each entry for the analog inputs AN1 to AN10. This can be realized by setting a predetermined oversampling ratio = 1 (normal A / D conversion) and a predetermined filter coefficient (arbitrary).

  In addition, when the conversion process shown in group 2 is performed with the configuration of the A / D control register 60c of FIG. 4 (A / D conversion process execution order, especially the entry format for each A / D conversion unit operation), the entry of the first step Then, AN0 is designated as the analog input number, “integration” is designated in the reset / integration field 402, a predetermined filter coefficient is set, and in the next step entry, AN1 is designated as the analog input number, and reset / “Reset” is specified in the integration field 402, a predetermined filter coefficient is set, and in the entry of the next step, AN2 is specified as the analog input number, “Reset” is specified in the reset / integration field 402, The filter coefficient is set. In the next step entry, AN0 is designated as the analog input number, and the reset / integration field 40 is set. In the next step entry, AN3 is specified as the analog input number, “Reset” is specified in the reset / integration field 402, and the predetermined filter coefficient is set. This can be realized by setting (hereinafter abbreviated).

  When the conversion process shown in group 2 is performed with the configuration of the A / D control register 60d in FIG. 5 (entry format for each conversion start factor), a predetermined conversion start factor entry (for example, timer factor entry ADENTt0 is selected). The conversion cycle is set in the register of the corresponding timer t0 among a plurality of timers), the bit AE0 corresponding to the analog input AN0 is set to “1” and the other bits are set to “0”, and a predetermined oversampling ratio and filter are set. Each coefficient corresponding to the analog inputs AN1 to AN10 is set with a coefficient and another predetermined conversion start factor entry (for example, the timer factor entry ADENTt1 is selected and the conversion cycle is set in the corresponding timer t1 register). AE1 to AE10 are set to “1” and the bit AE0 corresponding to the analog input AN0 is set to “0”. Oversampling ratio = 1 (normal A / D conversion) can be realized by setting the predetermined filter coefficients (optional).

  As specifically described above, according to the A / D converter of the present embodiment, the conversion shown in group 2 as well as the process of performing oversampling in a burst like the conversion process shown in group 1 of FIG. As in the process, oversampling is performed at a predetermined conversion period with a certain time interval for a certain analog input, and A / D conversion for another analog input is sandwiched between the individual samplings to simultaneously perform A / D. It is also possible to perform conversion processing.

  Also, according to the purpose of control, the resolution of A / D conversion can be improved by performing burst oversampling on a single analog input channel as appropriate as in the group 1 conversion process. In addition, A / D conversion processing with A / D conversion resolution required for each input can be realized by appropriately selecting an oversampling ratio. In particular, by performing oversampling while maintaining a certain time interval over the entire control frame as in the conversion processing of group 2 above, the Nyquist frequency can be increased by taking advantage of the oversampling characteristics. The requirement for the characteristics of the prefilter placed in front of the vessel can be relaxed, and a simpler filter can be used.

  Since the Nyquist frequency after decimation is ½ of the sampling frequency after decimation, it is necessary to perform a filtering process for removing signal components exceeding the latter Nyquist frequency at the decimation stage. A configuration example of the filter arithmetic circuit 10 for the filtering processing is shown in FIGS.

FIG. 7 is a diagram showing a configuration of an A / D converter having a filter calculation circuit 10a as a configuration example of the filter calculation circuit 10. The filter operation circuit 10a includes a shifter 11, a shifter 12, an adder 13, and a subtracter 14, and the operation is represented by the following recurrence formula (1). First, the previous value Y _i-1 is read from the conversion result register 20, multiplied by a coefficient 2- ^m, and the input value from the A / D converter 30 multiplied by a coefficient (1-2- ^m ) is added. This calculation result Y _i is written into the conversion result register 20.

Y _i = 2 ^−m · Y _i−1 + (1-2 ^−m ) · x (1)
Where x: input value
Y _i : i-th operation result
m: Shifter shift amount (bit)
According to this configuration, although the degree of freedom of the filter coefficient is low, the multiplier that can realize the filter coefficient with a simple circuit configuration by the combination of the shifters 11 and 12 and the subtractor 14 is a factor that increases the circuit scale. Can be made unnecessary.

  FIG. 8 is a diagram showing a configuration of an A / D converter having a filter calculation circuit 10b that operates as represented by the following recurrence formula (2) as a configuration example of the filter calculation circuit 10. This is a configuration in which the coefficients are opposite to those in FIG.

Y _i = (1-2 ^−m ) · Y _i−1 +2 ^−m · x (2)
Further, FIG. 9 shows an A / D conversion having an operation represented by the following recurrence formula (3), that is, a filter arithmetic circuit 10c that operates as a moving average filter or a comb filter, as an embodiment of the filter arithmetic circuit 10. It is a figure which shows the structure of a container. This is a circuit corresponding to a special form in the recurrence formulas (1) and (2) (2 ^−m , m is an oversampling ratio). In the case of this configuration, it is not necessary to specify the filter coefficient in the A / D control register 60 in particular.

Y _i = Y _i-1 + x (3)
Next, FIG. 10 is a diagram showing a configuration of a microcomputer 100a as a microcomputer having an A / D converter in the embodiment of the present invention. The microcomputer 100 a includes the A / D converter according to the above-described embodiment, the MPU 101, the RAM 102, and the bus 103. The conversion result register 20 and the A / D control register 60 of the A / D converter are connected to the MPU 101 and the RAM 102 via the bus 103. The MPU 101 can set the A / D control register 60 via the bus 103 to control the A / D converter and read the data in the conversion result register 20 to obtain the A / D conversion result.

  In this microcomputer 100a, the MPU 101 causes the A / D converter to operate independently based on the setting of the conversion control information in the A / D control register 60 to perform a predetermined A / D conversion process. Result data can be obtained and predetermined processing can be performed.

  FIG. 11 is a diagram showing a configuration of a microcomputer 100b including a DMAC (direct memory access controller) 70 in addition to the A / D converter of the above-described embodiment as a microcomputer in the embodiment of the present invention. is there. The microcomputer 100 b has the above-described A / D converter, MPU 101, RAM 102, bus 103, and DMAC 70, and the conversion result register 20 is logically provided on the RAM 102.

  In the microcomputer 100b, the A / D conversion result data is transferred between the filter arithmetic circuit 10 and the RAM 102 by the DMAC 70. According to this configuration, since the A / D conversion result data is transferred onto the RAM 102 that can be accessed at high speed from the MPU 101, the access time to the A / D conversion result data can be shortened, and the processing performance of the entire system can be improved. Can do.

  With the configuration described above, in the microcomputer having the A / D converter and the A / D converter according to the embodiment of the present invention, the oversampling ratio is set for each analog input and the A / D required for each analog input is set. A / D conversion processing at conversion resolution can be performed. For example, various patterns of A / D conversion processing such as oversampling for a single input and A / D conversion processing with different conversion attributes for a plurality of analog inputs can be realized.

  The A / D converter and microcomputer of the present invention can be used for various control applications such as automobile control.

It is a figure which shows the basic composition of the A / D converter in embodiment of this invention. It is a figure which shows the structure of the A / D control register which has an entry for every analog input. It is a figure which shows the structure of the A / D control register which has an entry of A / D conversion process execution order. It is a figure which shows the structure of the A / D control register which has an entry for every A / D conversion process execution order, especially A / D conversion unit operation | movement. It is a figure which shows the structure of the A / D control register which has an entry for every conversion start factor. It is the figure shown about the example of A / D conversion processing operation by the A / D converter in embodiment of this invention. It is a figure which shows the structure of the A / D converter which has one structural example of a filter arithmetic circuit. It is a figure which shows the structure of the A / D converter which has another structural example of a filter arithmetic circuit. It is a figure which shows the structure of the A / D converter which has another structural example of a filter arithmetic circuit. It is a figure which shows the structure of the microcomputer in embodiment of this invention. It is a figure which shows the structure of the other microcomputer in embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10, 10a, 10b, 10c ... Filter operation circuit, 11, 12 ... Shifter, 13 ... Adder, 14 ... Subtractor, 20 ... Conversion result register, 30 ... A / D conversion part, 40 ... Multiplexer, 50 ... Control logic , 60, 60a, 60b, 60c, 60d ... A / D control register, 70 ... DMAC, 100a, 100b ... microcomputer, 101 ... MPU, 102 ... RAM, 103 ... bus, 201 ... conversion start factor field, 202, 302 502, oversampling ratio field, 203, 303, 403, 503 ... filter coefficient field, 301, 401 ... analog input number field, 402 ... reset / integration field, 501 ... analog input number group field.

Claims (10)

A plurality of analog inputs, a multiplexer that selects any one of the plurality of analog inputs, an analog / digital conversion unit that performs analog / digital conversion on the selected analog input, and analog / digital in the analog / digital conversion unit A filter operation circuit that filters the converted data, a control register that stores conversion control information, and a conversion result register that stores conversion result data;
The control register has a plurality of entries for the conversion control information, and has a field for setting an oversampling ratio for each of the entries,
An analog / digital converter that causes the analog / digital converter and the filter operation circuit to execute an analog / digital conversion process at an oversampling ratio for each analog input based on the setting of the entry. The analog / digital converter according to claim 1.
The analog / digital converter characterized in that the plurality of entries of the control register are configured as entries for each analog input. The analog / digital converter according to claim 1.
The plurality of entries in the control register are configured as entries for each execution order of analog / digital conversion processing. The analog / digital converter according to claim 1.
The plurality of entries in the control register are configured as entries for each analog / digital conversion start factor. The analog / digital converter according to claim 1.
The control register has a field for setting a filter coefficient of the filter arithmetic circuit for each entry,
An analog / digital converter that causes the filter arithmetic circuit to perform a filter process based on the setting of the filter coefficient. The analog / digital converter according to claim 5.
In the filter arithmetic circuit, the filter coefficient is
2- ^m or (1-2- ^m ) (m: integer)
An analog / digital converter characterized by having the following structure. The analog / digital converter according to claim 1.
Oversampling is performed at a specified oversampling ratio for the first analog input among the plurality of analog inputs, and at the same time, individual sampling in oversampling of the first analog input while selecting the analog input An analog / digital converter that performs analog / digital conversion on the second analog input during The analog / digital converter according to claim 1.
Of the plurality of analog inputs, the first analog input is oversampled at a specified oversampling ratio, and at the same time, the oversampling ratio different from the oversampling ratio of the first analog input is selected while selecting the analog input. An analog / digital converter characterized by oversampling the second analog input at a sampling ratio. An analog / digital converter according to any one of claims 1-7;
A microprocessing unit and a bus;
The microcomputer, wherein the control register and the conversion result register are written and read from the microprocessor unit via the bus. The microcomputer according to claim 9, wherein
A random access memory and a direct memory access controller;
The conversion result register is logically configured on the random access memory, and data is transferred between the filter operation circuit and the conversion result register on the random access memory by the direct memory access controller. Microcomputer.

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