WO2018166222A1 - 基于交错编码的高速全数字接收机校准系统及方法 - Google Patents

基于交错编码的高速全数字接收机校准系统及方法 Download PDF

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Publication number
WO2018166222A1
WO2018166222A1 PCT/CN2017/109844 CN2017109844W WO2018166222A1 WO 2018166222 A1 WO2018166222 A1 WO 2018166222A1 CN 2017109844 W CN2017109844 W CN 2017109844W WO 2018166222 A1 WO2018166222 A1 WO 2018166222A1
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Prior art keywords
transmitter
receiver
signal
baseband signal
normal
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English (en)
French (fr)
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张璋
黄博
杨宁
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Fiberhome Telecommunication Technologies Co Ltd
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Fiberhome Telecommunication Technologies Co Ltd
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Priority to BR112019005321-2A priority Critical patent/BR112019005321B1/pt
Priority to RU2019107536A priority patent/RU2704238C1/ru
Priority to MA44946A priority patent/MA44946B1/fr
Publication of WO2018166222A1 publication Critical patent/WO2018166222A1/zh
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
    • H04L1/0038—Blind format detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0046—Code rate detection or code type detection

Definitions

  • the invention relates to the field of communications, and in particular to a high-speed full digital receiver calibration system and method based on interlaced coding, which is suitable for a communication system of an all-digital receiver directly sampled by a high-speed analog-to-digital converter (ADC).
  • ADC analog-to-digital converter
  • the all-digital receiver converts the carrier signal into a digital signal with an analog-to-digital converter (ADC) at the front end of the receiver, ie at the intermediate frequency, high frequency or close to the receiving antenna.
  • ADC analog-to-digital converter
  • the subsequent functions of the receiver (such as frequency conversion, filtering and demodulation, etc.) All are realized by digital signal processing technology. It is a combination of communication technology, computer technology and large-scale digital integrated circuit technology. It has the advantages of simple system structure, small size, low cost and good versatility. Applications.
  • the sampling rate of the ADC should be greater than twice the operating bandwidth of the all-digital receiver. This means that as the bandwidth of communication systems grows, the sampling rate of ADCs will multiply, and high-speed ADCs will become more widespread in future communication systems. Limited to the speed of electronic devices, high-speed ADCs are typically implemented with multiple low-speed ( ⁇ 1GS/s or lower) ADC time-division interleaved samples, thus calibrating the gain and phase of these low-speed ADCs to coordinate their operation into an all-digital receiver An important factor in performance.
  • the receiver's ADC calibration needs to use the stable signal from the transmitter as a reference. However, the receiver does not know exactly when the remote transmitter will send a stable signal. Therefore, there are two solutions in the past: 1. Receive The machine detects the received signal. If the signal amplitude is greater than the threshold, the transmitter is considered to have issued a stable signal, and the signal is utilized. No. ADC calibration of the analog-to-digital converter of the receiver; 2. Design an analog-to-digital converter ADC calibration error computer system. When the calibration error is greater than the threshold, the calibration is considered unsuccessful and recalibrated until the calibration error is less than the threshold.
  • both methods have drawbacks in the ADC calibration of the receiver.
  • the first method when the remote transmitter is initializing, an unstable signal is also generated; the receiver mistakes the unstable signal for a stable signal, and uses the signal to perform ADC calibration of the receiver to cause reception. Machine performance is degraded.
  • the second method the computer calibration design of ADC calibration error is more difficult, and there is no general calculation method at present.
  • the object of the present invention is to overcome the deficiencies of the above background art, and to provide a high-speed full digital receiver calibration system and method based on interlaced coding, which can enable a receiver to know the working state of the transmitter and ensure that the receiver receives a stable signal. Receiver ADC calibration is performed to ensure optimal receiver performance.
  • the present invention provides a high speed all digital receiver calibration system based on interlaced coding, the system comprising a transmitter and a receiver;
  • the transmitter is configured to: select to transmit a normal encoded signal or an interlaced encoded signal according to a signal amplitude;
  • the receiver is configured to: receive a signal of the transmitter, and perform an analog-to-digital converter ADC calibration of the receiver;
  • the transmitter includes a demultiplexer, a baseband signal processor, a flipper, and a multiplexer, the demultiplexer connecting two or more baseband signal processors, the demultiplexer and a baseband signal
  • the processor converts the input serial high-speed data into parallel data and performs baseband signal processing.
  • the flipper can invert the output signal of the transmitter baseband signal processor, and the multiplexer is used to convert the parallel data into a serial high-speed baseband signal.
  • the transmitter and the receiver are both based on numbers
  • the baseband signal processing circuit of the circuit, the normal encoding and the interleaving encoding are generated by digital circuits.
  • the baseband signal transmitted by the transmitter adopts a fixed format, and when the receiver receives the signal and processes the baseband signal, the fixed format is synchronized, and the receiver checks the coding state at the receiver. Interleaved coding is identified using a pattern synchronization fixed to the baseband signal transmitted by the transmitter.
  • the receiver sequentially attempts to format the received signal by using the interlaced coding receiving mode and the normal coding receiving mode, and identifies the current transmission by being able to format in the receiving mode. Whether the encoding method of the machine is normal encoding or interlaced encoding.
  • two or more baseband signal processors of the transmitter are connected with flippers, and each baseband signal processor and a flipper connected to the baseband signal processor form a flip
  • the data output path, the switching of the flipper on each path is switched on, and the switching of the normal coded signal sequence and the interleaved coded signal sequence is performed by the baseband signal processing circuit, so that the multiplexer outputs the normal coded signal and the interlaced coded signal.
  • the flipper is activated and activated by means of software setting.
  • the flipper of the odd path is turned on, the flipper of the even path is not turned on, the multiplexer outputs the interleaved coded signal, or the flipper of the even path is turned on, and the flipper of the odd path is not When enabled, the multiplexer outputs an interleaved coded signal; for a normal coded signal, the flipper of the odd path is not turned on, the flipper of the even path is not turned on, and the multiplexer outputs a normal coded signal.
  • the invention also provides a high-speed full digital receiver calibration method based on interlaced coding, the calibration method comprising the following steps:
  • the transmitter is started. In the initial state of the transmitter, the amplitude of the signal sent by the transmitter is unstable, and the baseband signal is interlaced.
  • the transmitter enters the normal working state. Under the normal working state of the transmitter, the amplitude of the signal sent by the transmitter is stable, and the baseband signal is changed to normal coding;
  • the receiver performs digital signal processing on the received signal to obtain a demodulated baseband signal, and continuously checks whether the baseband signal is normal or interlaced;
  • the receiver finds that the baseband signal becomes normal coding, the receiver uses the signal to perform fine calibration of the analog-to-digital converter of the receiver. After the receiver's analog-to-digital converter ADC is perfectly calibrated, the receiver enters normal operation. status.
  • step A and step B the method further includes the following steps: after the initialization state is completed, the transmitter enters a short waiting state, and the transmitter sends out when the transmitter waits for a short time.
  • the signal amplitude is stable, and the baseband signal is still interlaced.
  • the transmitter After the transmitter ends the short wait state, it enters the normal working state of the transmitter.
  • the method further includes the following steps: when the amplitude of the signal received by the receiver is less than the amplitude threshold, the receiver is in a receiver signal loss state; when the receiver When detecting that the amplitude of the received signal is greater than the amplitude threshold, the receiver uses the received signal to perform coarse calibration of the analog-to-digital converter ADC of the receiver; after the rough calibration of the analog-to-digital converter ADC of the receiver is completed, the receiver enters the check code. status.
  • the invention provides a high-speed full digital receiver calibration system and method based on interlaced coding, which can enable the receiver to know the working state of the transmitter, and ensure that the receiver performs receiver ADC calibration when receiving a stable signal to ensure the receiver.
  • the performance is optimal; at the same time, it is not interfered by noise and unstable signals, avoiding the receiver repeatedly Calibrating the receiver ADC reduces the complexity of the calibration algorithm and associated control circuitry.
  • 1 is a comparison diagram of a normal encoded signal sequence and an interleaved encoded signal sequence according to an embodiment of the present invention, wherein the signal sequence has a length of 8 bits.
  • 2 is a conventional parallel digital circuit based baseband signal processing circuit in which the parallel digital circuit is two channels.
  • FIG. 3 is a schematic diagram of a two-channel baseband signal processing circuit capable of outputting a normal encoded signal sequence or an interleaved encoded signal sequence according to an embodiment of the present invention.
  • 4 is a baseband signal processing circuit capable of outputting a normal coded signal sequence or an interleaved coded signal sequence according to an embodiment of the present invention.
  • FIG. 5 is a baseband signal processing circuit capable of outputting a normal coded signal sequence or an interleaved coded signal sequence according to an embodiment of the present invention.
  • FIG. 6 is a diagram showing an operation state of a high-speed full digital receiver calibration method based on interlaced coding according to an embodiment of the present invention.
  • Embodiments of the present invention provide a high-speed full digital receiver calibration system based on interlaced coding, the system including a transmitter and a receiver;
  • the transmitter is configured to: select a normal coded signal or an interlaced coded signal according to a signal amplitude;
  • the receiver is configured to: receive a signal of the transmitter, and perform analog to digital converter ADC calibration of the receiver;
  • a demultiplexer, a baseband signal processor, a flipper, and a multiplexer are included, the demultiplexer connecting two or more baseband signal processing.
  • the demultiplexer and the baseband signal processor convert the input serial high speed data into parallel data and perform baseband signal processing, and the flipper can invert the output signal of the transmitter baseband signal processor, and the multiplexer is used Parallel data is converted to a serial high speed baseband signal.
  • both the transmitter and the receiver adopt a digital circuit based baseband signal processing circuit, and the normal coding and interlace coding conversion are generated by the digital circuit.
  • the baseband signal transmitted by the transmitter adopts a fixed format
  • the receiver synchronizes the fixed format when receiving the signal and processing the baseband signal
  • the receiver is fixed by the baseband signal transmitted by the transmitter when the receiver checks the coding state.
  • the format synchronization feature identifies interlaced codes.
  • the receiver sequentially uses the interleave coding reception mode and the normal coding reception mode to try to format the received signal, and by using which reception mode can be formatted, the synchronization is used to identify that the current transmitter coding mode is normal. Encoding is also interleaved.
  • two or more baseband signal processors of the transmitter are connected with flippers, and each baseband signal processor and the flipper connected to the baseband signal processor form a data output path.
  • the switching of the flipper on each path is switched on and off, so that the baseband signal processing circuit outputs the switching of the normal encoded signal sequence and the interleaved encoded signal sequence, so that the multiplexer outputs the normal encoded signal and the interleaved encoded signal.
  • the flipper of the odd path is turned on, the flipper of the even path is not turned on, the multiplexer outputs the interleaved coded signal, or the flipper of the even path is turned on, the flipper of the odd path is not turned on, and multiplexing
  • the device outputs an interleaved coded signal; for a normal coded signal, the flipper of the odd path is not turned on, the flipper of the even path is not turned on, and the multiplexer outputs a normal coded signal.
  • the transmitter baseband signal processor of the odd-numbered path may be connected with the transmitter flip-flop, and the transmitter flip-flop may be flipped by software; similarly, the transmitter baseband signal processing of only the even-numbered path may be used.
  • Transmitter connection flipped Set the transmitter flipper to flip through the software.
  • the normal coded signal sequence and the interlaced coded signal sequence are respectively compared.
  • the figure shows an 8-bit length normal coded signal sequence and an 8-bit length interleaved coded signal sequence, where T1, T3, T5, The T7 bit is flipped, and the meaning of the flip is that 0 becomes 1, and 1 becomes 0.
  • the existing transmitter demultiplexer 301 converts the input serial high speed data into two channels of relatively low speed parallel data, and the first transmitter baseband signal processor 302 and the second transmitter baseband signal processor 303 pair parallel data.
  • the digital signal processing is performed, and the processed parallel signal is sent to the transmitter multiplexer 304 for conversion to a serial high speed baseband signal.
  • two channels of parallel digital circuits can output a normal coded signal sequence or a baseband signal processing circuit of an interleaved coded signal sequence.
  • the flipper of the odd path is turned on, the flipper of the even path is not turned on, and the multiplexer outputs the interleaved coded signal as an example.
  • the two-channel transmitter demultiplexer 401 converts the input serial high-speed data into The two channels of relatively low speed parallel data are activated by software to activate the two-channel first transmitter flip 405 in the two-channel first transmitter baseband signal processor 402, and the two-pass first transmitter baseband signal processor 402 The output signal is flipped.
  • the meaning of flipping is that 0 becomes 1, and 1 becomes 0.
  • the two-pass second transmitter baseband signal processor 403 also includes a two-channel second transmitter flip 406.
  • the two-channel first transmitter flip 405 is turned on, and the two-channel second transmitter flip 406 is not turned on.
  • the two-channel transmitter multiplexer 404 output signal will be an interlaced coded signal; the two-channel first transmitter flip 405 is not turned on.
  • the two-pass second transmitter flip 406 is not turned on, and the two-pass transmitter multiplexer 404 output signal will be a normal encoded signal.
  • the flipper of the even path is turned on, the flipper of the odd path is not turned on, and the multiplexer also outputs the interleaved coded signal.
  • an embodiment is provided for eight channels of parallel digital circuits.
  • a baseband signal processing circuit that outputs a normal encoded signal sequence or an interleaved encoded signal sequence.
  • the flipper of the odd path is turned on, the flipper of the even path is not turned on, and the multiplexer outputs the interleaved coded signal as an example.
  • the eight-channel transmitter demultiplexer 501 converts the input serial high-speed data into Eight channels of relatively low speed parallel data are activated by software to activate an eight-channel first transmitter flip 504 in the eight-channel first transmitter baseband signal processor 503 to activate an eight-channel third transmitter baseband signal processor 507.
  • the eight-channel third transmitter flip 508 activates an eight-channel fifth transmitter flip 512 in the eight-channel fifth transmitter baseband signal processor 511 to activate eight of the eight-channel seventh transmitter baseband signal processor 515
  • the output signal of the transmitter baseband signal processor 515 is inverted, the eight-channel second transmitter baseband signal processor 505, the eight-channel fourth transmitter baseband signal processor 509, and eight A sixth transmitter channel baseband signal processor 513, the output signal of the eighth passage eight transmitter baseband signal processor 517 is not inverted.
  • the meaning of flipping is that 0 becomes 1, and 1 becomes 0.
  • the eight-channel first transmitter flip 504, the eight-channel third transmitter flip 508, the eight-channel fifth transmitter flip 512, the eight-channel seventh transmitter flip 516, and the eight-channel second transmitter flip are turned on.
  • an eight-channel fourth transmitter flip 510, an eight-channel sixth transmitter flip 514, an eight-channel eighth transmitter flip 518, and an eight-channel transmitter multiplexer 502 output signal will be an interlaced coded signal;
  • the flipper of the even path is turned on, the flipper of the odd path is not turned on, and the multiplexer also outputs the interleaved coded signal.
  • the eight-channel first transmitter flip 504, the eight-channel third transmitter flip 508, the eight-channel fifth transmitter flip 512, the eight-channel seventh transmitter flip 516, and the eight-channel second transmitter are not turned on.
  • a flip 506, an eight-channel fourth transmitter flip 510, An eight-pass sixth transmitter flip 514, an eight-way eighth transmitter flip 518, and an eight-channel transmitter multiplexer 502 output signal will be the normal encoded signal.
  • a parallel digital circuit of 2n channels which can output a normal coded signal sequence or a baseband signal processing circuit of an interleaved coded signal sequence.
  • the flipper of the odd path is turned on, the flipper of the even path is not turned on, and the multiplexer outputs the interleaved coded signal as an example.
  • the 2n path transmitter demultiplexer 601 converts the input serial high speed data into 2n channels of relatively low speed parallel data, activated by software, activate 2n path first transmitter baseband flip 604 in 2n path first transmitter baseband signal processor 603, activate 2n path third transmitter baseband signal processor 607
  • 2n path transmitter multiplexer 602 output signal will be interlaced coded signal; similarly, The flipper of the even path is turned on, the flipper of the odd path is not turned on, and the multiplexer also outputs the interleaved coded signal.
  • Transmitter flipping of odd-numbered paths such as 2n path first transmitter flip 604, 2n path third transmitter flip 608, 2n path 2n-1 transmitter flip 612
  • the transmitter flipper of the even path of the 2n path second transmitter flip 606, 2n path 4th transmitter flip 610, 2n path 2n transmitter flip 614, etc., is not turned on, and the output signal will be a normal coded signal.
  • an embodiment of the present invention further provides a high-speed full digital receiver calibration method based on interlaced coding, where the calibration method includes the following steps:
  • the transmitter starts at time t0, and the transmitter initialization state 101 is between time t0 and time t2.
  • the amplitude of the signal sent by the transmitter is unstable, and the baseband signal is interlaced.
  • the transmitter is initialized at time t2, and the transmitter waits for state 102 temporarily between time t2 and time t3.
  • the amplitude of the signal sent by the transmitter is stable, and the baseband signal still uses interlaced coding;
  • the transmitter ends the transient waiting state 102 of the transmitter at time t3, and enters the normal working state 103 of the transmitter. Under the normal working state 103 of the transmitter, the amplitude of the signal sent by the transmitter is stable, and the baseband signal is changed to normal coding;
  • the receiver When the amplitude of the signal received by the receiver is less than the amplitude threshold, the receiver is in the receiver signal loss state 104; when the receiver detects that the amplitude of the received signal is greater than the amplitude threshold at time t1, it is considered that the transmitter has entered a transmitter initialization state 101, using the received signal for receiver ADC coarse calibration 105;
  • the receiver After the receiver ADC coarse calibration 105 is completed, the receiver enters the receiver to check the coding state 106.
  • the receiver checks the coding state 106 the receiver performs digital signal processing on the received signal to obtain the demodulated baseband signal. And constantly checking whether the baseband signal is normal or interlaced;
  • the receiver finds that the baseband signal has become normal coding at time t3, indicating that the remote transmitter has entered the normal working state 103 of the transmitter, and a stable signal is sent, and the receiver uses the signal to perform the precision calibration of the receiver ADC 107. In the receiver ADC fine school After the quasi 107 is completed, the receiver enters the normal operating state 108.

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Abstract

本发明公开了一种基于交错编码的高速全数字接收机校准系统及方法，涉及通信领域。该系统包括发射机和接收机，发射机包括解复用器、基带信号处理器、翻转器和复用器；该校准方法如下步骤：发射机启动，在发射机初始化状态下，基带信号采用交错编码；发射机进入正常工作状态，在发射机正常工作状态下，基带信号改为正常编码；接收机对所接收到的信号进行数字信号处理，获得解调后的基带信号，并不断地检查基带信号是正常编码还是交错编码；在接收机的模拟数字转换器ADC精校准完成之后，接收机进入正常工作状态；本发明能够使得接收机获知发射机的工作状态，保证接收机性能达到最佳。

Description

基于交错编码的高速全数字接收机校准系统及方法 技术领域
本发明涉及通信领域，具体涉及一种基于交错编码的高速全数字接收机校准系统及方法，适用于采用高速模拟数字转换器(ADC)直接采样的全数字接收机的通信系统。
背景技术
全数字接收机是在接收机前端即中频、高频或靠近接收天线的地方用模拟数字转换器(ADC)将载波信号转换为数字信号，接收机后续的功能(如下变频、滤波和解调等)全部用数字信号处理技术实现，它是通信技术、计算机技术和大规模数字集成电路技术结合的产物，具有系统结构简单，体积小，成本低，通用性好的优点，获得了越来越广泛的应用。
根据带通采样定律，ADC的采样率应该大于全数字接收机工作带宽的2倍。这意味着，随着通信系统带宽的增长，ADC的采样率也会成倍地增长，未来的通信系统中高速ADC将越来越广泛。限于电子器件的速率，高速ADC通常采用多个低速(<1GS/s或更低)ADC分时交织采样来实现，因此校准这些低速ADC的增益和相位，使其协调工作成为影响全数字接收机性能的重要因素。
接收机的ADC校准需要使用发射机发出的稳定的信号作为参考，然而接收机并不能确切知道处在远端的发射机什么时间会发出稳定的信号，因此以往有两种解决方法：1、接收机检测接收到信号，如果信号幅值大于门限，则认为发射机发出了稳定的信号，利用该信 号进行接收机的模拟数字转换器ADC校准；2、设计一种模拟数字转换器ADC校准误差计算机制，当校准误差大于阈值时，认为校准不成功，重新校准，直到校准误差小于阈值。
但是，上述两种方法对接收机的ADC校准均存在缺陷。第一种方法，远端的发射机正在进行初始化时，同样会发出不稳定的信号；接收机会将这一不稳定的信号误认为稳定的信号，利用该信号进行接收机的ADC校准，造成接收机性能劣化。第二种方法，ADC校准误差计算机制设计较为困难，目前还没有通用的计算方法。
发明内容
本发明的目的是为了克服上述背景技术的不足，提供一种基于交错编码的高速全数字接收机校准系统及方法，能够使得接收机获知发射机的工作状态，确保接收机在接收到稳定的信号时进行接收机ADC校准，保证接收机性能达到最佳。
本发明提供一种基于交错编码的高速全数字接收机校准系统，该系统包括发射机和接收机；
所述发射机用于：根据信号幅值选择发射正常编码信号或交错编码信号；
所述接收机用于：接收发射机的信号，并进行接收机的模拟数字转换器ADC校准；
所述发射机包括解复用器、基带信号处理器、翻转器和复用器，所述解复用器连接两个或两个以上的基带信号处理器，所述解复用器和基带信号处理器将输入的串行高速数据转换成并行数据，并进行基带信号处理，翻转器能够将发射机基带信号处理器的输出信号翻转，复用器用于将并行数据转换成串行高速基带信号。
在上述技术方案的基础上，所述发射机和接收机均采用基于数字 电路的基带信号处理电路，正常编码和交错编码的变换由数字电路产生。
在上述技术方案的基础上，所述发射机发射的基带信号采用固定的格式，接收机在接受信号并处理基带信号时，对该固定的格式进行同步，接收机在接收机检查编码状态下，利用与发射机发射的基带信号固定的格式同步这一特性对交错编码进行识别。
在上述技术方案的基础上，所述接收机依次使用交错编码接收模式和正常编码接收模式尝试对接收到的信号进行格式同步，通过在采用何种接收模式下能够格式，来同步来识别当前发射机的编码方式是正常编码还是交错编码。
在上述技术方案的基础上，所述发射机的两个或两个以上的基带信号处理器内均连接有翻转器，每个基带信号处理器和与该基带信号处理器连接的翻转器形成一个数据输出的通路，每个通路上的翻转器开启和不开启的切换，实现基带信号处理电路输出正常编码信号序列和交错编码信号序列的切换，从而使复用器输出正常编码信号和交错编码信号。
在上述技术方案的基础上，所述翻转器通过软件设置的方式激活开启。
在上述技术方案的基础上，对于交错编码信号，奇数通路的翻转器开启，偶数通路的翻转器不开启，复用器输出交错编码信号，或者偶数通路的翻转器开启，奇数通路的翻转器不开启，复用器输出交错编码信号；对于正常编码信号，奇数通路的翻转器不开启，偶数通路的翻转器不开启，复用器输出正常编码信号。
本发明还提供一种基于交错编码的高速全数字接收机校准方法，该校准方法包括如下步骤：
A、发射机启动，在发射机初始化状态下，发射机发出的信号幅值不稳定，基带信号采用交错编码；
B、发射机进入正常工作状态，在发射机正常工作状态下，发射机发出的信号幅值稳定，基带信号改为正常编码；
C、接收机对接收到的信号进行数字信号处理，获得解调后的基带信号，并不断地检查基带信号是正常编码还是交错编码；
D、当接收机发现基带信号变为正常编码时，接收机利用该信号进行接收机的模拟数字转换器ADC精校准，在接收机的模拟数字转换器ADC精校准完成之后，接收机进入正常工作状态。
在上述技术方案的基础上，所述步骤A和步骤B之间，还包括如下步骤：发射机在初始化状态完成后，发射机进入短暂等待状态，在发射机短暂等待状态下，发射机发出的信号幅值稳定，基带信号仍然采用交错编码，发射机结束短暂等待状态后，进入发射机正常工作状态。
在上述技术方案的基础上，所述步骤B和步骤C之间，还包括如下步骤：当接收机接收到的信号幅值小于幅值门限时，接收机处于接收机信号丢失状态；当接收机检测到接收信号幅值大于幅值门限时，接收机利用接收到的信号进行接收机的模拟数字转换器ADC粗校准；在接收机的模拟数字转换器ADC粗校准完毕后，接收机进入检查编码状态。
与现有技术相比，本发明的优点如下：
本发明提供的一种基于交错编码的高速全数字接收机校准系统及方法，能够使得接收机获知发射机的工作状态，确保接收机在接收到稳定的信号时进行接收机ADC校准，保证接收机性能达到最佳；同时也不会受到噪声和不稳定信号的干扰，避免了接收机反复多次地 对接收机ADC进行校准，降低了校准算法和相关控制电路的复杂度。
而且，因为发射机和接收机都是基于数字电路的，正常编码和交错编码的变换由数字电路实现非常简单，不需要增加任何硬件，软件复杂度的增加也可以忽略不计。
附图说明
图1为本发明实施例正常编码信号序列和交错编码信号序列对比图，其中信号序列长度为8比特长度。
图2为一种现有的基于并行数字电路的基带信号处理电路，其中并行数字电路为两通道。
图3为本发明实施例两通道的可输出正常编码信号序列或交错编码信号序列的基带信号处理电路。
图4为本发明实施例八通道的可输出正常编码信号序列或交错编码信号序列的基带信号处理电路。
图5为本发明实施例2n通道的可输出正常编码信号序列或交错编码信号序列的基带信号处理电路。
图6为本发明实施例基于交错编码的高速全数字接收机校准方法的工作状态图。
图中，101-发射机初始化状态，102-发射机短暂等待状态，103-发射机正常工作状态，104-接收机信号丢失状态，105-接收机ADC粗校准，106-接收机检查编码状态，107-接收机ADC精校准，108-接收机正常工作状态，301-发射机解复用器，302-第一发射机基带信号处理器，303-第二发射机基带信号处理器，304-发射机复用器，401-两通路发射机解复用器，402-两通路第一发射机基带信号处理器，403-两通路第二发射机基带信号处理器，404-两通路发射机复用器，405-两通路第一发射机翻转器，406-两通路第二发射机翻转器，501- 八通路发射机解复用器，502-八通路发射机复用器，503-八通路第一发射机基带信号处理器，504-八通路第一发射机翻转器，505-八通路第二发射机基带信号处理器，506-八通路第二发射机翻转器，507-八通路第三发射机基带信号处理器，508-八通路第三发射机翻转器，509-八通路第四发射机基带信号处理器，510-八通路第四发射机翻转器，511-八通路第五发射机基带信号处理器，512-八通路第五发射机翻转器，513-八通路第六发射机基带信号处理器，514-八通路第六发射机翻转器，515-八通路第七发射机基带信号处理器，516-八通路第七发射机翻转器，517-八通路第八发射机基带信号处理器，518-八通路第八发射机翻转器，601-2n通路发射机解复用器，602-2n通路发射机复用器，603-2n通路第一发射机基带信号处理器，604-2n通路第一发射机翻转器，605-2n通路第二发射机基带信号处理器，606-2n通路第二发射机翻转器，607-2n通路第三发射机基带信号处理器，608-2n通路第三发射机翻转器，609-2n通路第四发射机基带信号处理器，610-2n通路第四发射机翻转器，611-2n通路第2n-1发射机基带信号处理器，612-2n通路第2n-1发射机翻转器，613-2n通路第2n发射机基带信号处理器，614-2n通路第2n发射机翻转器。
具体实施方式
下面结合附图及具体实施例对本发明作进一步的详细描述。
本发明实施例提供一种基于交错编码的高速全数字接收机校准系统，该系统包括发射机和接收机；
所述发射机用于：根据信号幅值选择发射正常编码信号或交错编码信号；所述接收机用于：接收发射机的信号，并进行接收机的模拟数字转换器ADC校准；所述发射机包括解复用器、基带信号处理器、翻转器和复用器，所述解复用器连接两个或两个以上的基带信号处理 器，所述解复用器和基带信号处理器将输入的串行高速数据转换成并行数据，并进行基带信号处理，翻转器能够将发射机基带信号处理器的输出信号翻转，复用器用于将并行数据转换成串行高速基带信号。
其中，发射机和接收机均采用基于数字电路的基带信号处理电路，正常编码和交错编码的变换由数字电路产生。发射机发射的基带信号采用固定的格式，接收机在接受信号并处理基带信号时，对该固定的格式进行同步，接收机在接收机检查编码状态下，利用与发射机发射的基带信号固定的格式同步这一特性对交错编码进行识别。
其中，所述接收机依次使用交错编码接收模式和正常编码接收模式尝试对接收到的信号进行格式同步，通过在采用何种接收模式下能够格式，来同步来识别当前发射机的编码方式是正常编码还是交错编码。
实际操作时，所述发射机的两个或两个以上的基带信号处理器内均连接有翻转器，每个基带信号处理器和与该基带信号处理器连接的翻转器形成一个数据输出的通路，每个通路上的翻转器开启和不开启的切换，实现基带信号处理电路输出正常编码信号序列和交错编码信号序列的切换，从而使复用器输出正常编码信号和交错编码信号。
实际操作时，对于交错编码信号，奇数通路的翻转器开启，偶数通路的翻转器不开启，复用器输出交错编码信号，或者偶数通路的翻转器开启，奇数通路的翻转器不开启，复用器输出交错编码信号；对于正常编码信号，奇数通路的翻转器不开启，偶数通路的翻转器不开启，复用器输出正常编码信号。
可以想到的是，实际应用中，也可以仅奇数通路的发射机基带信号处理器连接有发射机翻转器，通过软件设置发射机翻转器翻转；同样，也可以仅偶数通路的发射机基带信号处理器连接有发射机翻转 器，通过软件设置发射机翻转器翻转。
参见图1所示，分别为正常编码信号序列和交错编码信号序列对比，图中示出了一个8比特长度的正常编码信号序列，8比特长度的交错编码信号序列，其中T1、T3、T5、T7比特被翻转了，翻转的含义是0变成1，1变成0。
参见图2所示，示出了常用的基于并行数字电路的基带信号处理电路。现有的发射机解复用器301将输入的串行高速数据转换成两个通道较为低速的并行数据，第一发射机基带信号处理器302和第二发射机基带信号处理器303对并行数据进行数字信号处理，处理完成的并行信号送入发射机复用器304，转换成串行高速基带信号。
参见图3所示，提供一种实施例为两个通道的并行数字电路，可输出正常编码信号序列或交错编码信号序列的基带信号处理电路。在本实施例中，以奇数通路的翻转器开启，偶数通路的翻转器不开启，复用器输出交错编码信号为例，两通路发射机解复用器401将输入的串行高速数据转换成两个通道较为低速的并行数据，通过软件设置，激活两通路第一发射机基带信号处理器402中的两通路第一发射机翻转器405，将两通路第一发射机基带信号处理器402的输出信号翻转。翻转的含义是0变成1，1变成0。两通路第二发射机基带信号处理器403也包含有两通路第二发射机翻转器406。开启两通路第一发射机翻转器405，不开启两通路第二发射机翻转器406，两通路发射机复用器404输出信号将是交错编码信号；不开启两通路第一发射机翻转器405，不开启两通路第二发射机翻转器406，两通路发射机复用器404输出信号将是正常编码信号。同理，偶数通路的翻转器开启，奇数通路的翻转器不开启，复用器同样输出交错编码信号。
参见图4所示，提供一种实施例为八个通道的并行数字电路，可 输出正常编码信号序列或交错编码信号序列的基带信号处理电路。在本实施例中，以奇数通路的翻转器开启，偶数通路的翻转器不开启，复用器输出交错编码信号为例，八通路发射机解复用器501将输入的串行高速数据转换成八个通道较为低速的并行数据，通过软件设置，激活八通路第一发射机基带信号处理器503中的八通路第一发射机翻转器504，激活八通路第三发射机基带信号处理器507中的八通路第三发射机翻转器508，激活八通路第五发射机基带信号处理器511中的八通路第五发射机翻转器512，激活八通路第七发射机基带信号处理器515中的八通路第七发射机翻转器516，将八通路第一发射机基带信号处理器503、八通路第三发射机基带信号处理器507、八通路第五发射机基带信号处理器511、八通路第七发射机基带信号处理器515的输出信号翻转，八通路第二发射机基带信号处理器505、八通路第四发射机基带信号处理器509、八通路第六发射机基带信号处理器513、八通路第八发射机基带信号处理器517的输出信号不翻转。翻转的含义是0变成1，1变成0。
开启八通路第一发射机翻转器504、八通路第三发射机翻转器508、八通路第五发射机翻转器512、八通路第七发射机翻转器516，不开启八通路第二发射机翻转器506、八通路第四发射机翻转器510、八通路第六发射机翻转器514、八通路第八发射机翻转器518，八通路发射机复用器502输出信号将是交错编码信号；同理，偶数通路的翻转器开启，奇数通路的翻转器不开启，复用器同样输出交错编码信号。
不开启八通路第一发射机翻转器504、八通路第三发射机翻转器508、八通路第五发射机翻转器512、八通路第七发射机翻转器516，不开启八通路第二发射机翻转器506、八通路第四发射机翻转器510、 八通路第六发射机翻转器514、八通路第八发射机翻转器518，八通路发射机复用器502输出信号将是正常编码信号。
参见图5所示，提供一种实施例为2n个通道的并行数字电路，可输出正常编码信号序列或交错编码信号序列的基带信号处理电路。在本实施例中，以奇数通路的翻转器开启，偶数通路的翻转器不开启，复用器输出交错编码信号为例，2n通路发射机解复用器601将输入的串行高速数据转换成2n个通道较为低速的并行数据，通过软件设置，激活2n通路第一发射机基带信号处理器603中的2n通路第一发射机翻转器604，激活2n通路第三发射机基带信号处理器607中的2n通路第三发射机翻转器608，依次类推，激活奇数通路的发射机翻转器，激活2n通路第2n-1发射机基带信号处理器611中的2n通路第2n-1发射机翻转器612，将2n通路第一发射机基带信号处理器603、2n通路第三发射机基带信号处理器607、2n通路第2n-1发射机基带信号处理器611等奇数通路的输出信号翻转，2n通路第二发射机基带信号处理器605、2n通路第四发射机基带信号处理器609、2n通路第2n发射机基带信号处理器613等偶数通路的输出信号不翻转。翻转的含义是0变成1，1变成0。
开启2n通路第一发射机翻转器604、2n通路第三发射机翻转器608、2n通路第2n-1发射机翻转器612等奇数通路的发射机翻转器，不开启2n通路第二发射机翻转器606、2n通路第四发射机翻转器610、2n通路第2n发射机翻转器614等偶数通路的发射机翻转器，2n通路发射机复用器602输出信号将是交错编码信号；同理，偶数通路的翻转器开启，奇数通路的翻转器不开启，复用器同样输出交错编码信号。
不开启2n通路第一发射机翻转器604、2n通路第三发射机翻转器608、2n通路第2n-1发射机翻转器612等奇数通路的发射机翻转 器，不开启2n通路第二发射机翻转器606、2n通路第四发射机翻转器610、2n通路第2n发射机翻转器614等偶数通路的发射机翻转器，输出信号将是正常编码信号。
参见图6所示，本发明实施例还提供一种基于交错编码的高速全数字接收机校准方法，该校准方法包括以下步骤：
S1、发射机在t0时刻启动，t0时刻与t2时刻之间为发射机初始化状态101，在发射机初始化状态101下，发射机发出的信号幅值不稳定，基带信号采用交错编码；
S2、发射机在t2时刻初始化完成，t2时刻与t3时刻之间为发射机短暂等待状态102，在发射机短暂等待状态102下，发射机发出的信号幅值稳定，基带信号仍然采用交错编码；
S3、发射机在t3时刻结束发射机短暂等待状态102，进入发射机正常工作状态103，在发射机正常工作状态103下，发射机发出的信号幅值稳定，基带信号改为正常编码；
S4、当接收机接收到的信号幅值小于幅值门限，接收机处于接收机信号丢失状态104；当接收机在t1时刻检测到接收信号幅值大于幅值门限，认为此时发射机已经进入了发射机初始化状态101，利用接收到的信号进行接收机ADC粗校准105；
S5、接收机ADC粗校准105完毕后，接收机进入接收机检查编码状态106，在接收机检查编码状态106下，接收机对所接收到的信号进行数字信号处理，获得解调后的基带信号，并不断地检查基带信号是正常编码还是交错编码；
S6、接收机在t3时刻发现基带信号变为了正常编码，说明此时远端的发射机已经进入发射机正常工作状态103，发出了稳定信号，接收机利用该信号进行接收机ADC精校准107，在接收机ADC精校 准107完成之后，接收机进入正常工作状态108。
本领域的技术人员可以对本发明实施例进行各种修改和变型，倘若这些修改和变型在本发明权利要求及其等同技术的范围之内，则这些修改和变型也在本发明的保护范围之内。
说明书中未详细描述的内容为本领域技术人员公知的现有技术。

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  1. 一种基于交错编码的高速全数字接收机校准系统，其特征在于：该系统包括发射机和接收机；
    所述发射机用于：根据信号幅值选择发射正常编码信号或交错编码信号；
    所述接收机用于：接收发射机的信号，并进行接收机的模拟数字转换器ADC校准；
    所述发射机包括解复用器、基带信号处理器、翻转器和复用器，所述解复用器连接两个或两个以上的基带信号处理器，所述解复用器和基带信号处理器将输入的串行高速数据转换成并行数据，并进行基带信号处理，翻转器能够将发射机基带信号处理器的输出信号翻转，复用器用于将并行数据转换成串行高速基带信号。
  2. 如权利要求1所述的基于交错编码的高速全数字接收机校准系统，其特征在于：所述发射机和接收机均采用基于数字电路的基带信号处理电路，正常编码和交错编码的变换由数字电路产生。
  3. 如权利要求2所述的基于交错编码的高速全数字接收机校准系统，其特征在于：所述发射机发射的基带信号采用固定的格式，接收机在接受信号并处理基带信号时，对该固定的格式进行同步，接收机在接收机检查编码状态下，利用与发射机发射的基带信号固定的格式同步这一特性对交错编码进行识别。
  4. 如权利要求3所述的基于交错编码的高速全数字接收机校准系统，其特征在于：所述接收机依次使用交错编码接收模式和正常编码接收模式尝试对接收到的信号进行格式同步，通过在采用何种接收模 式下能够格式，来同步来识别当前发射机的编码方式是正常编码还是交错编码。
  5. 如权利要求1-4中任一项所述的基于交错编码的高速全数字接收机校准系统，其特征在于：所述发射机的两个或两个以上的基带信号处理器内均连接有翻转器，每个基带信号处理器和与该基带信号处理器连接的翻转器形成一个数据输出的通路，每个通路上的翻转器开启和不开启的切换，实现基带信号处理电路输出正常编码信号序列和交错编码信号序列的切换，从而使复用器输出正常编码信号和交错编码信号。
  6. 如权利要求5所述的基于交错编码的高速全数字接收机校准系统，其特征在于：所述翻转器通过软件设置的方式激活开启。
  7. 如权利要求6所述的基于交错编码的高速全数字接收机校准系统，其特征在于：
    对于交错编码信号，奇数通路的翻转器开启，偶数通路的翻转器不开启，复用器输出交错编码信号，或者偶数通路的翻转器开启，奇数通路的翻转器不开启，复用器输出交错编码信号；
    对于正常编码信号，奇数通路的翻转器不开启，偶数通路的翻转器不开启，复用器输出正常编码信号。
  8. 一种用于权利要求1所述的基于交错编码的高速全数字接收机校准系统的方法，其特征在于，包括如下步骤：
    A、发射机启动，在发射机初始化状态下，发射机发出的信号幅值不稳定，基带信号采用交错编码；
    B、发射机进入正常工作状态，在发射机正常工作状态下，发射 机发出的信号幅值稳定，基带信号改为正常编码；
    C、接收机对接收到的信号进行数字信号处理，获得解调后的基带信号，并不断地检查基带信号是正常编码还是交错编码；
    D、当接收机发现基带信号变为正常编码时，接收机利用该信号进行接收机的模拟数字转换器ADC精校准，在接收机的模拟数字转换器ADC精校准完成之后，接收机进入正常工作状态。
  9. 如权利要求8所述的基于交错编码的高速全数字接收机校准方法，其特征在于：所述步骤A和步骤B之间，还包括如下步骤：发射机在初始化状态完成后，发射机进入短暂等待状态，在发射机短暂等待状态下，发射机发出的信号幅值稳定，基带信号仍然采用交错编码，发射机结束短暂等待状态后，进入发射机正常工作状态。
  10. 如权利要求8或9所述的基于交错编码的高速全数字接收机校准方法，其特征在于：所述步骤B和步骤C之间，还包括如下步骤：当接收机接收到的信号幅值小于幅值门限时，接收机处于接收机信号丢失状态；当接收机检测到接收信号幅值大于幅值门限时，接收机利用接收到的信号进行接收机的模拟数字转换器ADC粗校准；在接收机的模拟数字转换器ADC粗校准完毕后，接收机进入检查编码状态。
PCT/CN2017/109844 2017-03-15 2017-11-08 基于交错编码的高速全数字接收机校准系统及方法 Ceased WO2018166222A1 (zh)

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