WO2018166157A1 - 阵列基板、阵列基板的制造方法以及显示装置 - Google Patents

阵列基板、阵列基板的制造方法以及显示装置 Download PDF

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WO2018166157A1
WO2018166157A1 PCT/CN2017/102015 CN2017102015W WO2018166157A1 WO 2018166157 A1 WO2018166157 A1 WO 2018166157A1 CN 2017102015 W CN2017102015 W CN 2017102015W WO 2018166157 A1 WO2018166157 A1 WO 2018166157A1
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array substrate
electrode
layer
organic light
resistance
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PCT/CN2017/102015
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English (en)
French (fr)
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许名宏
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/759,707 priority Critical patent/US20190363144A9/en
Publication of WO2018166157A1 publication Critical patent/WO2018166157A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/17—Carrier injection layers
    • H10K50/171—Electron injection layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present disclosure relates to the field of display technology. More specifically, it relates to an array substrate, a method of manufacturing an array substrate, and a display device.
  • OLED display devices Compared with other types of display devices (for example, liquid crystal display units), organic light-emitting display devices (OLED display devices) have been widely studied as next-generation displays due to their advantages such as thinness, low power consumption, high contrast, and high color gamut. Get a preliminary application. Another advantage of OLED display devices over liquid crystal display devices is that they do not require backlighting. However, there is a problem of IR drop in OLED display devices.
  • Embodiments of the present disclosure provide an array substrate, a method of fabricating an array substrate, and a display device capable of solving at least the problem of a voltage drop in a prior art such as an OLED device.
  • a first aspect of the present disclosure provides an array substrate, the array substrate comprising: a substrate substrate; a pixel defining layer having a plurality of protrusions disposed on the substrate substrate, wherein the array substrate a region between the protrusions is a pixel region; a first electrode disposed on the base substrate in the pixel region; an organic light-emitting layer disposed on the first electrode; disposed at the organic a second electrode on the light emitting layer, the second electrode having a top surface on the bump a first portion thereon, a second portion in the pixel region, and a third portion on a side surface of the protrusion; the first surface disposed on at least one of the protrusion and the second electrode A resistance reduction portion between the first portions.
  • the array substrate further includes: a buffer layer disposed between the organic light emitting layer and the second electrode, wherein the buffer layer covers a top surface of the organic light emitting layer, a convex side surface, an upper surface of the resistance reducing portion, and a top surface of the protrusion not covered by the resistance reducing portion.
  • At least a portion of a projection of a top surface of the resistance reduction portion on a plane of a bottom surface of the resistance reduction portion exceeds an extension of a bottom surface of the resistance reduction portion.
  • the cross-sectional shape of the reduced resistance portion is an inverted trapezoid.
  • the pixel region includes sub-pixels having a long side and a short side, the resistance reducing portion extending in a direction parallel to a short side of the sub-pixel.
  • the resistivity reduction portion has a resistivity that is less than a resistivity of the second electrode.
  • the resistance reduction portion includes a first layer, a third layer, and a second layer disposed between the first layer and the third layer, wherein the first layer includes a transparent layer a conductive oxide; the second layer comprising at least one of the following materials: aluminum, silver, copper; the third layer comprising at least one of the following materials: molybdenum, titanium, indium tin oxide, indium zinc oxide.
  • the resistance reduction portion comprises a nano metal material.
  • the first electrode comprises indium tin oxide
  • the organic light emitting layer includes at least one of the following materials: a fluorescent substance, a phosphorescent substance, and a quantum dot substance;
  • the buffer layer includes at least one of the following materials: an organic small molecule, an aromatic compound; and
  • the second electrode includes Indium zinc oxide;
  • the pixel definition layer comprises a polymer.
  • the thickness of the reduced resistance portion ranges from about 100 to 600 nm; the thickness of the buffer layer ranges from about 10 to 20 nm; and the thickness of the second electrode ranges from about 70 to 300 nm. .
  • Another object of the present disclosure is to provide a display device.
  • a second aspect of the present disclosure provides a display device including the above array substrate.
  • Still another object of the present disclosure is to provide a method of fabricating an array substrate.
  • a third aspect of the present disclosure provides a method of fabricating an array substrate, comprising: forming a pixel defining layer having a plurality of protrusions on a substrate substrate, wherein the array substrate is located between the protrusions a region is a pixel region; a resistance reduction portion is formed on a top surface of at least one of the protrusions; a first electrode is formed on the base substrate in the pixel region; and an organic light is formed on the first electrode Forming a second electrode on the organic light-emitting layer, the second electrode having a first portion on a top surface of the protrusion, a second portion in the pixel region, and a bump in the The third part on the side surface.
  • the manufacturing method further includes: forming a buffer layer between the organic light emitting layer and the second electrode, wherein the buffer layer covers a top surface of the organic light emitting layer, the a convex side surface, an upper surface of the resistance reducing portion, and a top surface of the protrusion not covered by the resistance reducing portion.
  • forming the resistance reduction portion includes forming the resistance reduction portion by using at least two layers of materials, wherein an etching rate of the upper layer material of the at least two layers of material is less than an etching of the underlying material speed.
  • forming the resistance reduction portion includes forming the resistance reduction portion by printing a nano metal material.
  • FIG. 1 is a schematic diagram of an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of an array substrate in accordance with an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of an array substrate in accordance with an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a display device in accordance with an embodiment of the present disclosure.
  • the terms “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom” and The derivative should refer to the public text.
  • the terms “overlay”, “on top of”, “positioned on” or “positioned on top of” mean that a first element, such as a first structure, exists in a second element, such as a second structure. Above, wherein an intermediate element such as an interface structure may exist between the first element and the second element.
  • the term “contacting” means connecting a first element such as a first structure and a second element such as a second structure, with or without other elements at the interface of the two elements.
  • FIG. 1 is a schematic diagram of an array substrate in accordance with an embodiment of the present disclosure.
  • the array substrate includes: a base substrate 10; a pixel defining layer 11 having a plurality of protrusions PRN disposed on the base substrate 10, wherein a region between the protrusions of the array substrate is a pixel region a first electrode 12 disposed on the base substrate in the pixel region PR, an organic light-emitting layer 13 disposed on the first electrode 12, and a second electrode 14 disposed on the organic light-emitting layer 13.
  • Second electrode 14 There is a first portion 141 on the raised top surface, a second portion 142 in the pixel region, and a third portion 143 on the raised side surface.
  • the array substrate further includes a resistance reduction portion 15 disposed between the top surface of the at least one protrusion and the first portion of the second electrode.
  • the resistance reducing portion 15 By providing the resistance reducing portion 15, the voltage drop caused by the second electrode during current transmission can be reduced. This is because the resistance reducing portion forms a composite electrode with the first portion of the second electrode to reduce the electric resistance with respect to the current in the extending direction parallel to the top surface of the substrate substrate.
  • the first electrode 12 when used for a display device such as a display panel, can be used as a pixel electrode, and the second electrode 14 can be used as a main electrode.
  • An array substrate comprising: a pixel defining layer having a plurality of protrusions disposed on a substrate, wherein a region between the protrusions of the array substrate is a pixel region; and a substrate disposed in the pixel region a first electrode; an organic light emitting layer disposed on the first electrode; a second electrode disposed on the organic light emitting layer, the second electrode having a first portion on a top surface of the bump, and a second portion in the pixel region a portion and a third portion on the convex side surface; a resistance reduction portion disposed between the top surface of the at least one of the protrusions and the first portion of the second electrode, capable of reducing a current transfer process
  • the voltage drop caused by the second electrode in the middle improves the display performance.
  • the array substrate may further include a buffer layer 16 disposed between the organic light-emitting layer 13 and the second electrode 14, wherein the buffer layer 16 covers the organic light-emitting layer 13.
  • the top surface, the side surface of the bump PRN, the upper surface of the resistance reducing portion 15, and the top surface of the bump PRN which are not covered by the resistance reducing portion.
  • the projection of the top surface of the resistance reduction portion on the plane of the bottom surface of the resistance reduction portion covers and exceeds the extent of the bottom surface of the resistance reduction portion. This causes at least a portion of the side surface of the resistance reducing portion to form a buffer layer without shielding the buffer layer due to the shielding effect of the top surface, thereby enabling the resistance reduction portion to be in better electrical contact with the second electrode.
  • FIG. 3 is a schematic diagram of an array substrate in accordance with an embodiment of the present disclosure. As shown in FIG. 3, the cross-sectional shape of the electric resistance reduction portion 5 is an inverted trapezoid.
  • FIG. 4 is a schematic diagram of an array substrate in accordance with an embodiment of the present disclosure.
  • the resistance reduction portion is more clearly shown, and is filled with a filling pattern different from that of the previous figure.
  • the pixel region includes an array of sub-pixels PU having long sides and short sides, and the resistance reducing portion 15 extends in a direction parallel to the short sides of the sub-pixels. Since the pitch between the short sides of the adjacent sub-pixels is larger than the pitch between the long sides of the sub-pixels, the resistance reducing portion 15 to this arrangement can reduce the influence on the aperture ratio. It can be understood that the position and the number of the resistance reducing portions can also be differently set according to actual needs.
  • the resistance reduction portion may be set to have a resistivity lower than that of the second electrode.
  • the resistance reduction portion may include a first layer, a third layer, and a second layer disposed between the first layer and the third layer, wherein the first layer includes transparent conductive such as ITO
  • the second layer comprises at least one of the following materials: aluminum, silver, copper; and the third layer comprises at least one of the following materials: molybdenum, titanium, indium tin oxide, indium zinc oxide.
  • the resistance reduction portion may comprise a nano metal material.
  • the first electrode includes indium tin oxide.
  • the organic light-emitting layer may include at least one of the following materials: a fluorescent substance, a phosphorescent substance, a quantum dot substance such as a CdSe quantum dot.
  • the buffer layer may include at least one of the following materials: an organic small molecule, an aromatic compound.
  • the second electrode may include indium zinc oxide (IZO).
  • the pixel definition layer can include a polymer. It can be understood that the electron injection layer, the electron transport layer, the hole transport layer and the hole transport layer may be separately disposed on both sides of the organic light-emitting layer, which will not be redundantly described herein.
  • the thickness of the reduced resistance portion may range from about 100 to 600 nm.
  • the thickness of the buffer layer can range from about 10-20 nm.
  • the thickness of the second electrode may range from about 70 to 300 nm.
  • FIG. 5 is a schematic diagram of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure. As shown in FIG. 5, a method of fabricating an array substrate according to an embodiment of the present disclosure includes:
  • FIG. 6 is a schematic diagram of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure.
  • a method of fabricating an array substrate according to an embodiment of the present disclosure includes: S8, a buffer layer formed between the organic light-emitting layer and the second electrode, wherein The buffer layer covers a top surface of the organic light-emitting layer, a convex side surface, an upper surface of the reduced resistance portion, and a raised top surface not covered by the resistance reduction portion.
  • forming the resistance reduction portion may include setting the sectional shape of the resistance reduction portion to an inverted trapezoid.
  • the pixel region includes sub-pixels having a long side and a short side, and forming the resistance reducing portion includes: providing the resistance reducing portion in a direction parallel to a short side of the sub-pixel. This can reduce the effect on the aperture ratio.
  • the resistance reduction portion may be used to form the resistance reduction portion, wherein the etching speed of the upper layer material of the at least two layers of material is less than the etching speed of the underlying material, so that the resistance reduction portion cross section may be made
  • the shape has a shape such as an inverted trapezoid or the like.
  • the resistance reduction portion may include a first layer, a third layer, and a second layer disposed between the first layer and the third layer, wherein the first layer includes transparent conductive oxidation such as ITO
  • the second layer comprises at least one of the following materials: aluminum, silver, copper; and the third layer comprises at least one of the following materials: molybdenum, titanium, indium tin oxide, indium zinc oxide.
  • the reduced resistance portion can be formed by printing a nanomaterial.
  • the resistance reduction portion may include a nano metal material.
  • the resistance reduction portion can be formed by printing nano silver or other nano metal material.
  • the first electrode includes indium tin oxide.
  • the organic light emitting layer may include at least one of the following materials Species: Fluorescent substances, phosphorescent substances, quantum dot materials such as CdSe quantum dots.
  • the buffer layer may include at least one of the following materials: an organic small molecule, an aromatic compound.
  • the second electrode may include indium zinc oxide (IZO).
  • the pixel definition layer can include a polymer. It can be understood that the electron injection layer, the electron transport layer, the hole transport layer and the hole transport layer may be separately disposed on both sides of the organic light-emitting layer, which will not be redundantly described herein.
  • the organic light emitting material can be formed by a method such as ink jet printing.
  • a buffer layer may be provided by thermal evaporation.
  • the second electrode can be formed by sputtering.
  • the second electrode and the resistance reduction portion may be connected to an access point of the power source (eg, the electroluminescent device power source negative ELVSS).
  • Embodiments of the present disclosure also provide a display device and a method of fabricating the display device. Embodiments of the present disclosure also provide a display device including the array substrate as described above.
  • the display device according to the embodiment of the present disclosure may be a device having a display function, such as a display panel, a display, a television, a tablet, a mobile phone, a navigator, etc., which is not limited in this disclosure.
  • FIG. 7 is a schematic illustration of a display device of one embodiment of the present disclosure.
  • a display device according to an embodiment of the present disclosure includes an array substrate 1000 according to the present disclosure.
  • the array substrate may be an array substrate as described above.
  • the array substrate 1000 can include an array substrate as shown in FIG.

Abstract

一种阵列基板及其制造方法以及显示装置。所述阵列基板包括衬底基板（10）；设置在所述衬底基板（10）上的具有多个凸起的像素定义层（11），其中，所述阵列基板（10）的位于所述凸起之间的区域为像素区；设置在所述像素区中的所述衬底基板（10）上的第一电极（12）；设置在所述第一电极（12）上的有机发光层（13）；设置在所述有机发光层（13）上的第二电极（14），所述第二电极（14）具有在所述凸起的顶表面上的第一部分（141）、在所述像素区中的第二部分（142）和在所述凸起的侧表面上的第三部分（143）；设置在至少一个所述凸起的顶表面与所述第二电极（14）的所述第一部分（141）之间的电阻减小部（15）。

Description

阵列基板、阵列基板的制造方法以及显示装置
相关申请的交叉引用
本申请要求于2017年03月14日递交的中国专利申请第201710150107.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开文本涉及显示技术领域。更具体地，涉及一种阵列基板、阵列基板的制造方法以及显示装置。
背景技术
相比于其它类型的显示器件(例如，液晶显示单元)，有机发光显示器件(OLED显示器件)因其轻薄、低功耗、高对比度、高色域等优点，作为下一代显示器被广泛研究并得到初步应用。相比于液晶显示器件，OLED显示器件的另一个优势是，其不需要背光照明。然而，OLED显示器件中存在IR压降(IR-drop)的问题。
发明内容
本公开文本的实施例提供一种阵列基板、阵列基板的制造方法以及显示装置，至少能够解决现有技术中的诸如OLED器件存在电压压降的问题。
本公开文本的一个目的在于提供一种阵列基板。
本公开文本的第一方面提供了一种阵列基板，所述阵列基板包括：衬底基板；设置在所述衬底基板上的具有多个凸起的像素定义层，其中，所述阵列基板的位于所述凸起之间的区域为像素区；设置在所述像素区中的所述衬底基板上的第一电极；设置在所述第一电极上的有机发光层；设置在所述有机发光层上的第二电极，所述第二电极具有在所述凸起的顶表面 上的第一部分、在所述像素区中的第二部分和在所述凸起的侧表面上的第三部分；设置在至少一个所述凸起的顶表面与所述第二电极的所述第一部分之间的电阻减小部。
在一个实施例中，所述阵列基板还包括：设置在所述有机发光层和所述第二电极之间的缓冲层，其中，所述缓冲层覆盖所述有机发光层的顶表面、所述凸起的侧表面、所述电阻减小部的上表面和所述凸起的未被所述电阻减小部覆盖的顶表面。
在一个实施例中，所述电阻减小部的顶表面在所述电阻减小部的底表面所在平面上的投影的至少一部分超过所述电阻减小部的底表面的延伸范围。
在一个实施例中，所述电阻减小部的截面形状为倒置的梯形。
在一个实施例中，所述像素区包括具有长边和短边的子像素，所述电阻减小部沿着平行于子像素的短边的方向而延伸。
在一个实施例中，所述电阻减小部的电阻率小于所述第二电极的电阻率。
在一个实施例中，所述电阻减小部包括第一层、第三层和设置在所述第一层和所述第三层之间的第二层，其中，所述第一层包括透明导电氧化物；所述第二层包括下列材料的至少一种：铝，银，铜；所述第三层包括下列材料的至少一种：钼，钛，氧化铟锡，氧化铟锌。
在一个实施例中，所述电阻减小部包括纳米金属材料。
在一个实施例中，所述第一电极包括氧化铟锡；
所述有机发光层包括下列材料的至少一种：萤光物质，磷光物质，量子点物质；所述缓冲层包括下列材料的至少一种:有机小分子，芳香族化合物；所述第二电极包括氧化铟锌；所述像素定义层包括聚合物。
在一个实施例中，所述电阻减小部的厚度的范围约为100-600nm；所述缓冲层的厚度的范围约为10-20nm；所述第二电极的厚度的范围约为70-300nm。
本公开文本的另一个目的在于提供一种显示装置。
本公开文本的第二方面提供了一种显示装置，所述显示装置包括上述的阵列基板。
本公开文本的又一个目的在于提供一种阵列基板的制造方法。
本公开文本的第三方面提供了一种阵列基板的制造方法，包括：在衬底基板上形成具有多个凸起的像素定义层，其中，所述阵列基板的位于所述凸起之间的区域为像素区；在至少一个所述凸起的顶表面上形成电阻减小部；在所述像素区中的所述衬底基板上形成第一电极；在所述第一电极上形成有机发光层；在所述有机发光层上形成第二电极，所述第二电极具有在所述凸起的顶表面上的第一部分、在所述像素区中的第二部分和在所述凸起的侧表面上的第三部分。
在一个实施例中，所述制造方法还包括：形成在所述有机发光层和所述第二电极之间的缓冲层，其中，所述缓冲层覆盖所述有机发光层的顶表面、所述凸起的侧表面、所述电阻减小部的上表面和所述凸起的未被所述电阻减小部覆盖的顶表面。
在一个实施例中，形成所述电阻减小部包括：采用至少两层材料来形成所述电阻减小部，其中，所述至少两层材料的上层材料的刻蚀速度小于下层材料的刻蚀速度。
在一个实施例中，形成所述电阻减小部包括：通过打印纳米金属材料来形成所述电阻减小部。
附图说明
为了更清楚地说明本公开文本的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开文本的一些实施例，而非对本公开文本的限制，其中：
图1为根据本公开文本的实施例的阵列基板的示意图；
图2为根据本公开文本的实施例的阵列基板的示意图；
图3为根据本公开文本的实施例的阵列基板的示意图；
图4为根据本公开文本的实施例的阵列基板的示意图；
图5为根据本公开文本的实施例的阵列基板的制造方法的示意图；
图6为根据本公开文本的实施例的阵列基板的制造方法的示意图；
图7根据本公开文本的实施例的显示装置的示意图。
具体实施方式
为了使本公开文本的实施例的目的、技术方案和优点更加清楚，下面将接合附图，对本公开文本的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其他实施例，也都属于本公开文本保护的范围。
当介绍本公开文本的元素及其实施例时，除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素。
出于下文表面描述的目的，如其在附图中被标定方向那样，术语“上”、“下”、“左”、“右”“垂直”、“水平”、“顶”、“底”及其派生词应涉及公开文本。术语“上覆”、“在……顶上”、“定位在……上”或者“定位在……顶上”意味着诸如第一结构的第一要素存在于诸如第二结构的第二要素上，其中，在第一要素和第二要素之间可存在诸如界面结构的中间要素。术语“接触”意味着连接诸如第一结构的第一要素和诸如第二结构的第二要素，而在两个要素的界面处可以有或者没有其它要素。
图1为根据本公开文本的实施例的阵列基板的示意图。如图1所示，阵列基板包括：衬底基板10；设置在衬底基板10上的具有多个凸起PRN的像素定义层11，其中，阵列基板的位于凸起之间的区域为像素区PR；设置在像素区PR中的衬底基板上的第一电极12；设置在第一电极12上的有机发光层13；设置在有机发光层13上的第二电极14。第二电极14 具有在凸起的顶表面上的第一部分141、在像素区中的第二部分142和在凸起的侧表面上的第三部分143。阵列基板还包括设置在至少一个凸起的顶表面与第二电极的第一部分之间的电阻减小部15。
通过设置电阻减小部15，可以减小电流传输过程中第二电极所造成的电压压降。这是由于电阻减小部与第二电极的第一部分形成复合电极，以对于沿平行于衬底基板的顶表面的延伸方向的电流而言，减小其电阻。
可以理解，在用于诸如显示面板的显示装置时，第一电极12可以被用作像素电极，第二电极14可以被用作主电极。
通过这样的阵列基板，其包括设置在衬底基板上的具有多个凸起的像素定义层，其中，阵列基板的位于凸起之间的区域为像素区；设置在像素区中的衬底基板上的第一电极；设置在第一电极上的有机发光层；设置在有机发光层上的第二电极，第二电极具有在凸起的顶表面上的第一部分、在像素区中的第二部分和在凸起的侧表面上的第三部分；设置在至少一个所述凸起的顶表面与所述第二电极的所述第一部分之间的电阻减小部，能够减小电流传输过程中第二电极所造成的电压压降，提高显示性能。
图2为根据本公开文本的实施例的阵列基板的示意图。如图2所示，除了图1所示的结构之外，阵列基板还可以包括设置在有机发光层13和第二电极14之间的缓冲层16，其中，缓冲层16覆盖有机发光层13的顶表面、凸起PRN的侧表面、电阻减小部15的上表面和凸起PRN的未被电阻减小部覆盖的顶表面。通过设置缓冲层16，可以使得有机发光层与第二电极有更好的注入特性。
在一个实施例中，电阻减小部的顶表面在电阻减小部的底表面所在平面上的投影覆盖并超过电阻减小部的底表面的延伸范围。这使得在形成缓冲层时电阻减小部的侧面的至少一部分因顶表面的遮蔽作用而没有覆盖缓冲层，从而使电阻减小部能够与第二电极更好地电接触。
图3为根据本公开文本的实施例的阵列基板的示意图。如图3所示，电阻减小部5的截面形状为倒置的梯形。
图4为根据本公开文本的实施例的阵列基板的示意图。在图4中，为 了更清楚的示出电阻减小部，将其以与前图不同的填充图案来填充。如图4所示，该像素区包括具有长边和短边的子像素PU的阵列，电阻减小部15沿着平行于子像素的短边的方向而延伸。由于相邻子像素的短边之间的间距大于子像素的长边之间的间距，因此，电阻减小部15到该设置能够降低对开口率的影响。可以理解，电阻减少部的位置和数目也可以根据实际需要而不同地设置。
考虑到导电性，可以将电阻减小部设置为其电阻率小于第二电极的电阻率。
在一种实施方式中，电阻减小部可以包括第一层、第三层和设置在第一层和所述第三层之间的第二层，其中，第一层包括诸如ITO的透明导电氧化物；第二层包括下列材料的至少一种：铝，银，铜；第三层包括下列材料的至少一种：钼，钛，氧化铟锡，氧化铟锌。在一种实施方式中，电阻减小部可以包括纳米金属材料。
第一电极包括可以氧化铟锡。有机发光层可以包括下列材料的至少一种：萤光物质，磷光物质，诸如CdSe量子点的量子点物质。缓冲层可以包括下列材料的至少一种:有机小分子、芳香族化合物。第二电极可以包括氧化铟锌(IZO)。像素定义层可以包括聚合物。可以理解，在有机发光层的两侧还可以分别设置电子注入层、电子传输层、空穴传输层和空穴传输层，对此，本文不再冗述。
电阻减小部的厚度的范围可以约为100-600nm。缓冲层的厚度的范围可以约为10-20nm。第二电极的厚度的范围可以约为70-300nm。
图5为根据本公开文本的实施例的阵列基板的制造方法的示意图。如图5所示，根据本公开文本的实施例的阵列基板的制造方法包括：
S1、在衬底基板上形成具有多个凸起的像素定义层，其中，阵列基板的位于所述凸起之间的区域为像素区；
S3、在至少一个凸起的顶表面上形成电阻减小部；
S5、在像素区中的衬底基板上形成第一电极；
S7、在第一电极上形成有机发光层；
S9、在有机发光层上形成第二电极，第二电极具有在所述凸起的顶表面上的第一部分、在像素区中的第二部分和在凸起的侧表面上的第三部分。
图6为根据本公开文本的实施例的阵列基板的制造方法的示意图。如图6所示，除了图5所示的步骤之外，根据本公开文本的实施例的阵列基板的制造方法包括：S8、形成在有机发光层和第二电极之间的缓冲层，其中，缓冲层覆盖有机发光层的顶表面、凸起的侧表面、电阻减小部的上表面和凸起的未被电阻减小部覆盖的顶表面。
在一个实施例中，电阻减小部的顶表面在电阻减小部的底表面所在平面上的投影的至少一部分超过电阻减小部的底表面的延伸范围。这使得在形成缓冲层时电阻减小部的侧面的至少一部分因顶表面的遮蔽作用而没有覆盖缓冲层，从而使电阻减小部能够与第二电极更好地电接触。在一个实施例中，形成电阻减小部可以包括将电阻减小部的截面形状设置为倒置的梯形。
像素区包括素具有长边和短边的子像素，形成所述电阻减小部包括：沿着平行于子像素的短边的方向而设置所述电阻减小部。这能够降低对开口率的影响。
在一种实施方式中，可以采用至少两层材料来形成电阻减小部，其中，该至少两层材料的上层材料的刻蚀速度小于下层材料的刻蚀速度，从而可以使得电阻减小部截面形状具有诸如倒置的梯形等的形状。在该种情况下，电阻减小部可以包括第一层、第三层和设置在第一层和所述第三层之间的第二层，其中，第一层包括诸如ITO的透明导电氧化物；第二层包括下列材料的至少一种：铝，银，铜；第三层包括下列材料的至少一种：钼，钛，氧化铟锡，氧化铟锌。
在一种实施方式中，可以通过打印纳米材料来形成电阻减小部。在该种情况下，电阻减小部可以包括纳米金属材料。例如，可以通过打印纳米银或其它纳米金属材料来形成电阻减小部。
第一电极包括可以氧化铟锡。有机发光层可以包括下列材料的至少一 种：萤光物质，磷光物质，诸如CdSe量子点的量子点物质。缓冲层可以包括下列材料的至少一种:有机小分子、芳香族化合物。第二电极可以包括氧化铟锌(IZO)。像素定义层可以包括聚合物。可以理解，在有机发光层的两侧还可以分别设置电子注入层、电子传输层、空穴传输层和空穴传输层，对此，本文不再冗述。
有机发光材料可以采用诸如喷墨打印(ink jet printing)的方法来形成。为了与第二电极有更好的注入特性，可以采用热蒸镀的方式来设置缓冲层。第二电极可以采用溅射的方式来形成。第二电极和电阻减小部可以被连接到电源的接入点(例如，电致发光器件电源负极ELVSS)。
本公开文本的实施例还提供了一种显示装置和显示装置的制造方法。本公开文本的实施例还提供了一种显示装置，包括如上所述的阵列基板。根据本公开文本的实施例的显示装置可以为显示面板、显示器、电视机、平板电脑、手机、导航仪等具有显示功能的设备，本公开文本对此不做限定。
图7本公开文本的一个实施例的显示装置的示意图。如图7所示，根据本公开文本的实施例的显示装置包括根据本公开文本的阵列基板1000。阵列基板可以是如上述所述的阵列基板。例如，阵列基板1000可以包括如图1‐4中所示的阵列基板。
已经描述了某特定实施例，这些实施例仅通过举例的方式展现，而且不旨在限制本公开文本的范围。事实上，本文所描述的新颖实施例可以以各种其它形式来实施；此外，可在不脱离本公开文本的精神下，做出以本文所描述的实施例的形式的各种省略、替代和改变。所附权利要求以及它们的等价物旨在覆盖落在本公开文本范围和精神内的此类形式或者修改。

Claims (15)

  1. 一种阵列基板，包括：衬底基板；
    设置在所述衬底基板上的具有多个凸起的像素定义层，其中，所述阵列基板的位于所述凸起之间的区域为像素区；
    设置在所述像素区中的所述衬底基板上的第一电极；
    设置在所述第一电极上的有机发光层；
    设置在所述有机发光层上的第二电极，所述第二电极具有在所述凸起的顶表面上的第一部分、在所述像素区中的第二部分和在所述凸起的侧表面上的第三部分；
    设置在至少一个所述凸起的顶表面与所述第二电极的所述第一部分之间的电阻减小部。
  2. 根据权利要求1所述的阵列基板，还包括：设置在所述有机发光层和所述第二电极之间的缓冲层，其中，所述缓冲层覆盖所述有机发光层的顶表面、所述凸起的侧表面、所述电阻减小部的上表面和所述凸起的未被所述电阻减小部覆盖的顶表面。
  3. 根据权利要求2所述的阵列基板，其中，所述电阻减小部的顶表面在所述电阻减小部的底表面所在平面上的投影的至少一部分超过所述电阻减小部的底表面的延伸范围。
  4. 根据权利要求3所述的阵列基板，其中，所述电阻减小部的截面形状为倒置的梯形。
  5. 根据权利要求1-4中任一项所述的阵列基板，其中，所述像素区包括具有长边和短边的子像素，所述电阻减小部沿着平行于子像素的短边的方向而延伸。
  6. 根据权利要求1-4中任一项所述的阵列基板，其中，所述电阻减小部的电阻率小于所述第二电极的电阻率。
  7. 根据权利要求6所述的阵列基板，其中，所述电阻减小部包括第一层、第三层和设置在所述第一层和所述第三层之间的第二层，其中，所述第一层包括透明导电氧化物；
    所述第二层包括下列材料的至少一种：铝，银，铜；
    所述第三层包括下列材料的至少一种：钼，钛，氧化铟锡，氧化铟锌。
  8. 根据权利要求6所述的阵列基板，其中，所述电阻减小部包括纳米金属材料。
  9. 根据权利要求2-4中任一项所述的阵列基板，其中，所述第一电极包括氧化铟锡；
    所述有机发光层包括下列材料的至少一种：萤光物质，磷光物质，量子点物质；
    所述缓冲层包括下列材料的至少一种:有机小分子，芳香族化合物；
    所述第二电极包括氧化铟锌；
    所述像素定义层包括聚合物。
  10. 根据权利要求9所述的阵列基板，其中，所述电阻减小部的厚度的范围约为100-600nm；
    所述缓冲层的厚度的范围约为10-20nm；
    所述第二电极的厚度的范围约为70-300nm。
  11. 一种显示装置，包括根据权利要求1-10中任一项所述的阵列基板。
  12. 一种阵列基板的制造方法，包括：在衬底基板上形成具有多个凸起的像素定义层，其中，所述阵列基板的位于所述凸起之间的区域为像素区；
    在至少一个所述凸起的顶表面上形成电阻减小部；
    在所述像素区中的所述衬底基板上形成第一电极；
    在所述第一电极上形成有机发光层；
    在所述有机发光层上形成第二电极，所述第二电极具有在所述凸起的顶表面上的第一部分、在所述像素区中的第二部分和在所述凸起的侧表面上的第三部分。
  13. 根据权利要求12所述的阵列基板的制造方法，所述制造方法还包括：形成在所述有机发光层和所述第二电极之间的缓冲层，其中，所述缓冲层覆盖所述有机发光层的顶表面、所述凸起的侧表面、所述电阻减小部 的上表面和所述凸起的未被所述电阻减小部覆盖的顶表面。
  14. 根据权利要求12或13所述的阵列基板的制造方法，其中，形成所述电阻减小部包括：采用至少两层材料来形成所述电阻减小部，其中，所述至少两层材料的上层材料的刻蚀速度小于下层材料的刻蚀速度。
  15. 根据权利要求12或13所述的阵列基板的制造方法，其中，形成所述电阻减小部包括：通过打印纳米金属材料来形成所述电阻减小部。
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