WO2018153084A1 - 显示基板、显示装置及其驱动方法 - Google Patents

显示基板、显示装置及其驱动方法 Download PDF

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Publication number
WO2018153084A1
WO2018153084A1 PCT/CN2017/103089 CN2017103089W WO2018153084A1 WO 2018153084 A1 WO2018153084 A1 WO 2018153084A1 CN 2017103089 W CN2017103089 W CN 2017103089W WO 2018153084 A1 WO2018153084 A1 WO 2018153084A1
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Prior art keywords
pixel
sub
common electrode
line
lines
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English (en)
French (fr)
Inventor
戴珂
江鹏
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Publication of WO2018153084A1 publication Critical patent/WO2018153084A1/zh
Priority to US16/162,521 priority Critical patent/US10698282B2/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display substrate, a display device, and a driving method thereof.
  • TFT Thin Film Transistor
  • the thin film transistor is turned on or off by gate line control.
  • the pixel voltage is transmitted to the corresponding pixel through the data line.
  • the pixel charging rate is defined as the ratio of the pixel voltage of the pixel to the voltage written on the data line.
  • the pixel voltage is related to the charging time, the TFT turn-on current, and the like.
  • the pixel is designed as a 1G2D structure, and there are one gate line between adjacent two rows of pixels, and two data lines between adjacent two columns of pixels; the same row of pixels are connected with the same gate line, different rows of pixels and different gate lines connection.
  • the pixels in the same column are connected to different data lines, so that the time of the thin film transistors corresponding to the two rows of pixels can be opened by the gate lines, and the adjacent two rows of pixels are charged by different data lines, and the charging time is doubled.
  • the adjacent two gate lines give the same timing, in the design, there are two independent gate lines.
  • the gate lines occupy a certain space, the pixel opening area is compressed, and the aperture ratio is lowered. At the same time, the number of gate lines is large, resulting in an increase in the number of gate drive chips, an increase in cost, and a disadvantage of achieving a narrow bezel.
  • the present disclosure provides a display substrate, a display device, and a driving method thereof for improving pixel aperture ratio and reducing a frame.
  • an embodiment of the present disclosure provides a display substrate including a plurality of gate lines and a plurality of data lines, wherein the gate lines and the data lines are cross-distributed to define a plurality of sub-pixel regions, wherein adjacent two There are two rows of sub-pixel regions between the gate lines, two data lines are disposed between adjacent two columns of sub-pixel regions, each sub-pixel region includes a thin film transistor, and one thin film transistor corresponding to one data line is respectively located in one of the gates Thin film transistors of adjacent two rows of sub-pixel regions on both sides of the line are connected to the gate line, and thin film transistors respectively located in adjacent two rows of sub-pixel regions on both sides of the gate line are connected to corresponding data lines.
  • the display substrate further includes a first common electrode line parallel to the gate line, the first common electrode line being disposed between two rows of sub-pixel regions between adjacent two gate lines.
  • the display substrate further includes a second common electrode line parallel to the data line, wherein the second common electrode line is disposed between each pair of at least two pairs of adjacent two columns of sub-pixel regions.
  • the number of sub-pixel regions between any two adjacent second common electrode lines is s, and s is a positive integer.
  • the spacing between any two adjacent second common electrode lines is substantially the same.
  • the number of sub-pixel regions in the same row between any two adjacent second common electrode lines is greater than or equal to two.
  • the second common electrode line is located between two data lines of adjacent two columns of sub-pixel regions.
  • the first common electrode line and the gate line have the same layer structure.
  • the second common electrode line and the data line are in the same layer structure, and the first common electrode line and the second common electrode line are cross-distributed.
  • an insulating layer is disposed between the first common electrode line and the second common electrode line, and the insulating layer is provided with a via hole corresponding to a position where the first common electrode line and the second common electrode line intersect.
  • the first common electrode line and the second common electrode line are electrically connected through the via.
  • one of the sub-pixel regions is thin
  • the film transistor is connected to a data line on one side of the column of sub-pixel regions
  • the thin film transistor of the other sub-pixel region is connected to a data line on the other side of the column of sub-pixel regions.
  • a display device including the display substrate as described above is also provided in the embodiment of the present disclosure.
  • a driving method of a display device as described above is also provided in the embodiment of the present disclosure, including:
  • the thin film transistors of the adjacent two rows of sub-pixel regions located on both sides of the gate line are simultaneously turned on by one gate line; the pixel voltage is transmitted to the thin film transistors of the two rows of sub-pixel regions through the data lines.
  • the display device when displaying one frame of the screen, includes a plurality of first sub-pixel regions, and an electric field formed by the pixel voltages transmitted to the plurality of first sub-pixel regions is capable of driving liquid crystal molecules to be deflected;
  • the number of pixel voltages having the first polarity is the same as the number of pixel voltages having the second polarity, the first polarity and the second polarity The opposite polarity of sex.
  • the absolute value of the pixel voltage having the first polarity is the same as the absolute value of the pixel voltage having the second polarity.
  • the display device when displaying one frame of picture, includes a first pixel region and a second pixel region; and the first group of pixel voltages transmitted to the plurality of sub-pixel regions of the first pixel region includes n a first pixel voltage of a first polarity and m second pixel voltages having a second polarity, a pixel voltage of the first group of pixel voltages being in one-to-one correspondence with a plurality of sub-pixel regions of the first pixel region;
  • the first pixel region includes a first red pixel region, a first green pixel region, and a first blue pixel region
  • the first group of pixel voltages includes positiveness provided to the first red pixel region Red pixel voltage, a negative green pixel voltage supplied to the first green pixel region, and a positive blue pixel voltage supplied to the first blue pixel region
  • the second pixel region includes a second a red pixel region, a second green pixel region, and a second blue pixel region, the second set of pixel voltages including a positive red pixel voltage supplied to the second red pixel region, provided to the second green pixel A negative green pixel voltage of the region and a positive blue pixel voltage supplied to the second blue pixel region.
  • the absolute values of the red pixel voltage, the green pixel voltage, and the blue pixel voltage are the same.
  • two rows of sub-pixel regions are arranged between two adjacent gate lines, and two adjacent sub-pixel regions on both sides of one gate line share one gate line, thereby halving the number of gate lines and increasing pixels. Open area to increase the aperture ratio.
  • the halving of the number of gate lines reduces the number of gate drive chips or gate drive circuits, reduces the cost, and facilitates the implementation of a narrow bezel.
  • the charging time of one row of sub-pixel regions is doubled, sufficient charging time is provided, thereby increasing the pixel charging rate and improving the display quality.
  • FIG. 1 is a schematic structural view of a display substrate in an embodiment of the present disclosure
  • FIG. 2 is a schematic structural view of a display substrate in an embodiment of the present disclosure
  • FIG. 3 is a schematic structural view of a display substrate in an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram showing a polarity distribution of pixel voltages transmitted to all sub-pixel regions when a frame is displayed in an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram showing the distribution of a first pixel repeating unit and a second pixel repeating unit when a frame is displayed in an embodiment of the present disclosure.
  • a display substrate including a plurality of gate lines 10 and a plurality of data lines 20, and the gate lines 10 and the data lines 20 are cross-distributed to define a plurality of sub-pixel regions 100.
  • Each sub-pixel region 100 includes a thin film transistor 1 and a thin film crystal
  • the gate electrode of the tube 1 is integrally formed with the gate line 10, and the source electrode 2 is connected to the data line 20, and the corresponding thin film transistor 1 is turned on or off by the gate line 10.
  • Thin film transistors 1 of adjacent two rows of sub-pixel regions 100 respectively located on one side of one gate line 10 are connected to the gate line 10, and thin film transistors 1 and data are located in adjacent two rows of sub-pixel regions on both sides of one gate line 10.
  • the lines 20 are connected one by one so that when the thin film transistors 1 of the adjacent two rows of sub-pixel regions are opened by the gate lines 10, the data lines 20 transmit pixel voltages to the source electrodes 2 of the corresponding thin film transistors 1.
  • the display substrate may be an array substrate of a liquid crystal display device, a display substrate of an organic electroluminescence display device, or a display substrate of another display device using a thin film transistor as a driving device.
  • the angle between the substantially extended directions of the gate lines and the data lines is greater than zero, and cross distribution is achieved.
  • the sub-pixel regions located in the same row are distributed on the same line parallel to the gate lines, and the sub-pixel regions located in the same column are distributed on the same line parallel to the data lines, wherein the same row of sub-pixel regions may be distributed in the same line Lines of straight lines, broken lines, or other shapes may be distributed on the same line of straight lines, broken lines, or other shapes, and are not limited herein.
  • connection of the thin film transistor to the gate line means that the gate electrode of the thin film transistor is connected to the gate line
  • the connection of the thin film transistor and the data line means that the source electrode of the thin film transistor is connected to the data line.
  • two data lines are disposed between adjacent two columns of sub-pixel regions in the extending direction of the data lines 20. 20.
  • the number of data lines 20 is made to coincide with the number of adjacent two rows of sub-pixel regions. Specifically, it may be: in two adjacent sub-pixel regions 100 in the same column, wherein the thin film transistor 1 of one sub-pixel region 100 is connected to the data line 20 on one side of the column sub-pixel region, and the thin film transistor of the other sub-pixel region 100 1 is connected to the data line 20 located on the other side of the sub-pixel area of the column.
  • the display substrate includes, in addition to the gate line 10 and the data line 20, other signal lines, such as a common electrode line, which is disposed in the display area for providing a reference voltage.
  • the common electrode line includes a plurality of first common electrode lines 30 and a plurality of second common electrode lines 31.
  • the first common electrode line 30 is parallel to the gate line 10 and is disposed between the two rows of sub-pixel regions 100 between the two gate lines 10 due to the fact that between the two rows of sub-pixel regions between the two gate lines 10 A gate line is provided. Therefore, the manner in which the first common electrode line 30 is disposed between the two rows of sub-pixel regions 100 between the two gate lines 10 does not occupy the pixel opening region, which is advantageous for increasing the aperture ratio.
  • the second common electrode line 31 is substantially parallel or parallel to the data line 20, and a second common electrode line 31 is disposed between at least partially adjacent two columns of sub-pixel regions 100. Alternatively, the second common electrode line 31 is disposed only between the partially adjacent two columns of sub-pixel regions 100 to reduce the influence on the aperture ratio.
  • the uniformity of the common electrode line resistance can be improved, which is advantageous for improving the stability of the signal on the common electrode line.
  • the specific principle is that during the display process, the gate line, the data line, and the display electrode and the common electrode line form a coupling capacitor. When the signal on the gate line, the data line, and the display electrode changes, the signal of the common electrode line is changed. During the recovery process of the signal on the common electrode line, the uniformity of the resistance of the common electrode line is better, and the recovery speed is faster, which can improve the stability of the signal on the common electrode line.
  • the first common electrode line 30 may have the same layer structure as the gate line 10 and be made of the same gate metal layer.
  • the second common electrode line 31 may have the same layer structure as the data line 20 and be made of the same source/drain metal layer.
  • An insulating layer (not shown) is disposed between the first common electrode line 30 and the second common electrode line 31.
  • a plurality of via holes may be disposed at positions where the insulating layer corresponds to the intersection of the first common electrode line 30 and the second common electrode line 31, and the first common electrode line 30 and the second common electrode line 31 pass the plurality of The electrical connection of the vias and the multi-point connection can further improve the uniformity of the common electrode line resistance.
  • the display substrate can also be provided to include only the first common electrode line 30 or the second common electrode line 31.
  • the plurality of second common electrode lines 31 are disposed at equal intervals in the embodiment to improve the uniformity of the common electrode line resistance.
  • the number of sub-pixel regions 100 between any two adjacent second common electrode lines 31 is s, and s is a positive integer.
  • the display substrate of the present embodiment is taken as an example of the array substrate of the liquid crystal display device.
  • Body includes:
  • the gate lines 10 and the data lines 20 are cross-distributed, defining a plurality of sub-pixel regions 100, and two rows of sub-pixel regions between adjacent two gate lines 10, There are two data lines 20 between adjacent two columns of sub-pixel regions;
  • the common electrode line includes a plurality of first common electrode lines 30 and a plurality of second common electrode lines 31.
  • the first common electrode lines 30 are parallel to the gate lines 10 and are disposed in two rows of sub-pixels between the two gate lines 10. Between the regions; the second common electrode line 31 is parallel to the data line 20, and is disposed between the two adjacent columns of sub-pixel regions 100 by the second common electrode line 31;
  • An insulating layer between the first common electrode line 30 and the second common electrode line 31, and a via hole is disposed at a position where the insulating layer corresponds to the intersection of the first common electrode line 30 and the second common electrode line 31, and the first common electrode
  • the line 30 and the second common electrode line 31 are electrically connected through the via hole;
  • Each sub-pixel region 100 includes:
  • the thin film transistor 1 the gate electrode of the thin film transistor 1 located in the adjacent two rows of sub-pixel regions on both sides of one gate line 10 is connected to the gate line 10; in the adjacent two sub-pixel regions in the same column, one of the sub-pixel regions
  • the source electrode 2 of the thin film transistor 1 of 100 is connected to the data line 20 on the side of the column sub-pixel region, the source electrode 2 of the thin film transistor 1 of the other sub-pixel region 100, and the data line 20 on the other side of the column sub-pixel region connection.
  • a pixel electrode 4 connected to the drain electrode 3 of the thin film transistor 1;
  • a passivation layer (not shown) located between the thin film transistor 1 and the pixel electrode 4.
  • each sub-pixel region 100 of the array substrate further includes:
  • the common electrode 5 is connected to the common electrode line.
  • An intermediate insulating layer (not shown) between the pixel electrode 4 and the common electrode 5.
  • the thin film transistor 1 may be a top gate thin film transistor, a bottom gate thin film transistor, or the like.
  • the positional relationship of the pixel electrode 4, the common electrode 5, and the thin film transistor 1 is set as needed, and will not be enumerated here.
  • a display device and a driving method thereof are provided.
  • the display device adopts the display substrate in the first embodiment, and the aperture ratio is improved because the number of gate lines is halved.
  • the number of gate lines Halving reduces the number of gate drive chips or gate drive circuits, reduces cost, and facilitates the implementation of narrow bezels.
  • the thin film transistor of one row of sub-pixel regions can open the charging time of two rows of sub-pixels, sufficient charging time is provided, thereby increasing the pixel charging rate and improving the display quality.
  • the display device may be a liquid crystal display device, an organic electroluminescence display device, or the like.
  • the driving method of the above display device includes:
  • the thin film transistors of the adjacent two rows of sub-pixel regions located on both sides of the gate line are simultaneously turned on by one gate line, and then the pixel voltages are transmitted to the thin film transistors of the two rows of sub-pixel regions through the data lines one by one.
  • the above driving method simultaneously opens the thin film transistors of the adjacent two rows of sub-pixel regions located on both sides of the gate line through one gate line, so that the charging time of the sub-pixel region is doubled, providing sufficient charging time, thereby improving the pixels of the sub-pixel region.
  • the charging rate improves the display quality.
  • the display electrode is connected to the drain electrode of the thin film transistor, and the pixel voltage transmitted on the data line is transmitted to the display through the thin film transistor.
  • the display electrode is a pixel electrode.
  • the display electrode is an anode of an organic light emitting diode.
  • the common electrode line is for providing a reference voltage, for example, for providing a reference voltage to a common electrode of the liquid crystal display device, and a reference voltage for a cathode of the organic light emitting diode of the organic electroluminescence display device.
  • the common electrode line includes a plurality of first common electrode lines parallel to the gate lines, and the first common electrode lines and the gate lines are in the same layer structure, and the first common electrode lines are disposed at Between the two rows of sub-pixel regions between two adjacent gate lines, the pixel opening area is not occupied, which is advantageous for increasing the aperture ratio.
  • the gate line, the data line, and the display electrode and the common electrode line form a coupling capacitor.
  • the signal on the gate line, the data line, and the display electrode changes, the signal of the common electrode line is changed.
  • the signal on the gate line, the data line, and the display electrode changes, the signal of the common electrode line is changed.
  • the signal on the display electrodes of the red sub-pixel and the blue sub-pixel are both positive, the signal on the corresponding common electrode line is pulled to the positive polarity, and when the green sub-pixel G is The signal on the display electrode is negative polarity, and the signal on the corresponding common electrode line is pulled to the negative polarity.
  • the signal on the common electrode line is pulled more toward the positive polarity, so that the phase For the reference voltage, the signal on the common electrode line is a large positive polarity voltage, and the stability is poor, resulting in an increase in the driving voltage of the green sub-pixel, and the driving voltage of the red sub-pixel and the blue sub-pixel is reduced, and the picture is generated. green.
  • the first way is to reduce the coupling capacitance
  • the second way is to neutralize the signal on the common electrode line to the positive polarity pull and the negative polarity pull in one frame display, to ensure the balance of the signal on the common electrode line and maintain the reference voltage.
  • the second method is preferably used to overcome the problem that the stability of the signal on the common electrode line is not good.
  • the display device when displaying one frame of the screen, the display device includes a plurality of first In the sub-pixel region, among the pixel voltages transmitted to all of the first sub-pixel regions, the number of pixel voltages having the first polarity is the same as the number of pixel voltages having the second polarity, the first polarity and the first The polarities of the two polarities are opposite, and the absolute value of the pixel voltage having the first polarity is the same as the absolute value of the pixel voltage having the second polarity, which is used to form an electric field that drives the deflection of the liquid crystal molecules, thereby
  • the data line and the display electrode pull and neutralize the signal on the common electrode line to ensure the balance of the signal on the common electrode line and maintain the reference voltage.
  • the driving electric field formed by the corresponding pixel voltage except for the other sub-pixel regions of the first sub-pixel region cannot drive the liquid crystal molecules to be deflected.
  • the first sub-pixel region displays 255 gray scales, and other sub-pixel regions at the first pixel region display 0 gray scale.
  • the display device is in a normally dark mode, and when displaying one frame of the screen, the display device includes a first pixel region and a second pixel region, and transmits the first group of pixel voltages to the first pixel region.
  • the display device Providing a pixel voltage of the first group of pixel voltages to the sub-pixel regions of the first pixel region, the pixel voltages of the first group of pixel voltages being in one-to-one correspondence with the sub-pixel regions of the first pixel region, the first group of pixels
  • the voltage includes n first pixel voltages having a first polarity and m second pixel voltages having a second polarity;
  • the second group of pixel voltages includes p third pixel voltages having a first polarity and q fourth pixel voltages having a second polarity;
  • n+p m+q
  • n, m, p, q are positive integers.
  • the first pixel region and the second pixel region are bright pixel regions, and absolute values of all pixel voltages in the first group of pixel voltages are the same and absolute values of all pixel voltages in the second group of pixel voltages the same.
  • the above embodiment can realize the number of pixel voltages having the first polarity among the pixel voltages transmitted to all the bright sub-pixel regions (the corresponding pixel voltage forms the electric field for driving the liquid crystal molecules to deflect) when displaying one frame of the picture.
  • the number of pixel voltages having the second polarity is the same, and the absolute values of all the pixel voltages are the same, so that the data lines and the display electrodes are pulled and neutralized by the signals on the common electrode lines to ensure the balance of the signals on the common electrode lines. Maintain at the reference voltage.
  • the liquid crystal molecules are not deflected and are in a dark state.
  • each of the pixel regions of the display device includes a red pixel region, a green pixel region, and a blue pixel region.
  • a first set of pixel voltages are transmitted to the first pixel region, the first set of pixel voltages including a positive red pixel voltage, a negative green pixel voltage, and a positive blue pixel voltage.
  • the absolute value of the voltage and the blue pixel voltage are the same.
  • the pixel area of the display device may be further divided into a first pixel repeating unit a and a second when displayed on one frame.
  • the pixel repeating unit b, the number of positive pixel voltages in the first pixel repeating unit a is the same as the number of negative polarity pixel voltages in the second pixel repeating unit b, and the negative pixel voltages in the first pixel repeating unit a
  • the number is the same as the number of positive polarity pixel voltages in the second pixel repeating unit b, and the absolute value of the negative polarity pixel voltage and the positive polarity pixel voltage are the same.
  • the number of the first pixel repeating unit a and the second pixel repeating unit b may be set to be the same, and the interval is set to achieve the pulling neutralization of the signals on the common electrode line.
  • a positive polarity pixel voltage and a negative polarity pixel voltage are used to form an electric field that drives liquid crystal molecule deflection, for example, in FIGS. 4 and 5, positive polarity
  • the sub-pixel area corresponding to the pixel voltage and the negative polarity pixel voltage displays 255 gray scales.
  • the other sub-pixel regions of the first pixel repeating unit a and the second pixel repeating unit b display 0 gray scale.

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Abstract

一种显示基板、显示装置及其驱动方法，其中显示基板包括多条栅线（10）和多条数据线（20），多条栅线（10）和多条数据线（20）交叉分布；其中相邻两条栅线（10）之间具有两行子像素区域（100），相邻两列子像素区域（100）之间设置有两条数据线（20），每一子像素区域（100）包括一个薄膜晶体管（1），一个薄膜晶体管（1）对应一条数据线（20），分别位于一条栅线（10）两侧的相邻两行子像素区域（100）的薄膜晶体管（1）与栅线（10）连接，且分别位于一条栅线（10）两侧的相邻两行子像素区域（100）的薄膜晶体管（1）与对应的数据线（20）连接。

Description

显示基板、显示装置及其驱动方法
相关申请的交叉引用
本申请要求于2017年2月21日提交中国专利局、申请号为201710092874.8的优先权，其全部内容据此通过引用并入本申请。
技术领域
本公开涉及显示技术领域，特别是涉及一种显示基板、显示装置及其驱动方法。
背景技术
在平板显示技术领域，薄膜晶体管(Thin Film Transistor，简称TFT)具有体积小、功耗低、制造成本相对较低等优点，被作为驱动器件广泛应用在平板显示技术中。
对于薄膜晶体管显示器件，通过栅线控制打开或关闭薄膜晶体管。在薄膜晶体管打开时，通过数据线向对应的像素传输像素电压。像素充电率定义为像素的像素电压与数据线上写入的电压比值。像素电压与充电时间、TFT开启电流等相关。以120Hz显示器件(分辨率为3840*2160)为例，每一行的充电时间为t＝1/120/2220(60行Blank区)＝3.7us，在3.7us内，非晶硅薄膜晶体管的载流子迁移率较低，短时间内无法将像素电位充饱，导致像素电压小于数据线上写入的电压。
现有将像素设计成1G2D结构，相邻两行像素之间具有一条栅线，相邻两列像素之间具有两条数据线；同一行像素与同一栅线连接，不同行像素与不同栅线连接。对于相邻两行像素，位于同一列的像素与不同数据线连接，从而通过栅线可以打开2行像素对应的薄膜晶体管的时间，由不同数据线给相邻两行像素充电，充电时间翻倍，以达到液晶翻转所需求的电位。但是，相邻两条栅线虽然给的是相同的时序，在设计中为两根独立的栅线，由于栅线占用一定的空间，压缩了像素开口区，降低了开口率。同时，栅线的根数较多，导致栅极驱动芯片数量增加，成本上升，而且不利于实现窄边框。
发明内容
本公开提供一种显示基板、显示装置及其驱动方法，用以提高像素开口率，减小边框。
为解决上述技术问题，本公开实施例中提供一种显示基板，包括多条栅线和多条数据线，所述栅线和所述数据线交叉分布，限定多个子像素区域，其中相邻两条栅线之间具有两行子像素区域，相邻两列子像素区域之间设置有两条数据线，每一子像素区域包括一个薄膜晶体管，一个薄膜晶体管对应一条数据线分别位于一条所述栅线两侧的相邻两行子像素区域的薄膜晶体管与该栅线连接，且分别位于一条所述栅线两侧的相邻两行子像素区域的薄膜晶体管与对应的数据线连接。
可选地，该显示基板还包括与所述栅线平行的第一公共电极线，所述第一公共电极线设置在位于相邻两条栅线之间的两行子像素区域之间。
可选地，该显示基板还包括与所述数据线平行的第二公共电极线，其中在至少两对相邻的两列子像素区域的每一对之间设置有所述第二公共电极线。
可选地，任意相邻的两条第二公共电极线之间的子像素区域的个数均为s，s为正整数。
可选地，任意相邻的两条第二公共电极线之间的间距大致相同。
可选地，任意相邻的两条第二公共电极线之间的位于同一行的子像素区域的个数大于或等于2。
可选地，所述第二公共电极线位于相邻两列子像素区域的两条数据线之间。
可选地，所述第一公共电极线与所述栅线为同层结构。
可选地，所述第二公共电极线与所述数据线为同层结构，所述第一公共电极线和第二公共电极线交叉分布。
可选地，所述第一公共电极线和第二公共电极线之间具有绝缘层，所述绝缘层对应所述第一公共电极线和第二公共电极线交叉的位置设置有过孔，所述第一公共电极线和第二公共电极线通过所述过孔电性连接。
可选地，位于同一列的相邻两个子像素区域中，其中一个子像素区域的薄 膜晶体管与位于该列子像素区域一侧的数据线连接，另一个子像素区域的薄膜晶体管与位于该列子像素区域另一侧的数据线连接。
本公开实施例中还提供一种显示装置，包括如上所述的显示基板。
本公开实施例中还提供一种如上所述的显示装置的驱动方法，包括：
通过一条栅线同时打开位于该栅线两侧的相邻两行子像素区域的薄膜晶体管；通过数据线向该两行子像素区域的薄膜晶体管传输像素电压。
可选地，在显示一帧画面时，所述显示装置包括多个第一子像素区域，向所述多个第一子像素区域传输的像素电压形成的电场能够驱动液晶分子偏转；以及在向所述多个第一子像素区域传输的像素电压中，具有第一极性的像素电压的个数与具有第二极性的像素电压的个数相同，所述第一极性和第二极性的极性相反。进一步地，具有第一极性的像素电压的绝对值与具有第二极性的像素电压的绝对值相同。
可选地，在显示一帧画面时，所述显示装置包括为第一像素区域和第二像素区域；向所述第一像素区域的多个子像素区域传输的第一组像素电压包括n个具有第一极性的第一像素电压和m个具有第二极性的第二像素电压，所述第一组像素电压中的像素电压与所述第一像素区域的多个子像素区域一一对应；向所述第二像素区域的多个子像素区域传输的第二组像素电压包括p个具有第一极性的第三像素电压和q个具有第二极性的第四像素电压，所述第二组像素电压中的像素电压与所述第二像素区域的多个子像素区域一一对应；其中n+p＝m+q，n、m、p、q为正整数。
可选地，所述第一像素区域包括第一红色像素区域、第一绿色像素区域和第一蓝色像素区域，所述第一组像素电压包括提供给所述第一红色像素区域的正性的红色像素电压、提供给所述第一绿色像素区域的负性的绿色像素电压和提供给所述第一蓝色像素区域的正性的蓝色像素电压；所述第二像素区域包括第二红色像素区域、第二绿色像素区域和第二蓝色像素区域，所述第二组像素电压包括提供给所述第二红色像素区域的正性的红色像素电压、提供给所述第二绿色像素区域的负性的绿色像素电压和提供给所述第二蓝色像素区域的正性的蓝色像素电压。进一步地，所述红色像素电压、所述绿色像素电压和所述蓝色像素电压的绝对值相同。
本公开的上述技术方案的有益效果如下：
上述技术方案中，相邻两条栅线之间具有两行子像素区域，位于一条栅线两侧的相邻两行子像素区域共用一条栅线，从而使得栅线的数量减半，增加像素开口区，提升开口率。同时，栅线数量的减半减少了栅极驱动芯片或栅极驱动电路的个数，降低了成本，并有利于实现窄边框。另外，由于一行子像素区域的充电时间翻倍，提供充足的充电时间，从而提高像素充电率，提升显示质量。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1表示本公开实施例中显示基板的结构示意图；
图2表示本公开实施例中显示基板的结构示意图；
图3表示本公开实施例中显示基板的结构示意图；
图4表示本公开实施例中一帧画面显示时向所有子像素区域传输的像素电压的极性分布示意图；
图5表示本公开实施例中一帧画面显示时第一像素重复单元和第二像素重复单元的分布示意图。
具体实施方式
下面将结合附图和实施例，对本公开的具体实施方式作进一步详细描述。以下实施例用于说明本公开，但不用来限制本公开的范围。
实施例一
结合图1和图3所示，本实施例中提供一种显示基板，包括多条栅线10和多条数据线20，栅线10和数据线20交叉分布，限定多个子像素区域100。相邻两条栅线10之间具有两行子像素区域100，相邻两列子像素区域100之间具有两条数据线20。每一子像素区域100包括一个薄膜晶体管1，薄膜晶体 管1的栅电极与栅线10一体成型，源电极2与数据线20连接，通过栅线10打开或关闭对应的薄膜晶体管1。
分别位于一条栅线10两侧的相邻两行子像素区域100的薄膜晶体管1与该栅线10连接，且位于一条栅线10两侧的相邻两行子像素区域的薄膜晶体管1与数据线20一一对应连接，从而通过栅线10打开该相邻两行子像素区域的薄膜晶体管1时，数据线20向对应的薄膜晶体管1的源电极2传输像素电压。
本公开的技术方案中，相邻两条栅线之间具有两行子像素区域，位于一条栅线两侧的相邻两行子像素区域共用一条栅线，从而使得栅线的数量减半，增加像素开口区，提升开口率。同时，栅线数量的减半减少了栅极驱动芯片或栅极驱动电路的个数，降低了成本，并有利于实现窄边框。另外，由于一行子像素区域的充电时间翻倍，提供充足的充电时间，从而提高像素充电率，提升显示质量。
所述显示基板可以为液晶显示装置的阵列基板，也可以为有机电致发光显示装置的显示基板，或其它以薄膜晶体管作为驱动器件的显示装置的显示基板。
需要说明的是，本公开实施例中，栅线和数据线的大致延伸方向之间的夹角大于零，实现交叉分布。位于同一行的子像素区域分布在与栅线平行的同一条线上，位于同一列的子像素区域分布在与数据线平行的同一条线上，其中，同一行子像素区域可以分布在同一条直线、折线或其他形状的线上，同一列子像素区域可以分布在同一条直线、折线或其他形状的线上，在此不作限定。
本公开实施例中，薄膜晶体管与栅线连接是指：薄膜晶体管的栅电极与栅线连接，薄膜晶体管与数据线连接是指：薄膜晶体管的源电极与数据线连接。
为了实现相邻两行子像素区域的薄膜晶体管1与数据线20一一对应连接，本实施例中，在数据线20的延伸方向上，在相邻两列子像素区域之间设置两条数据线20，使数据线20的数量与相邻两行子像素区域的个数一致。具体可以为：位于同一列的相邻两个子像素区域100中，其中一个子像素区域100的薄膜晶体管1与位于该列子像素区域一侧的数据线20连接，另一个子像素区域100的薄膜晶体管1与位于该列子像素区域另一侧的数据线20连接。
所述显示基板除了栅线10和数据线20，还包括其他信号线，例如：公共电极线，所述公共电极线设置在显示区域，用于提供基准电压。
本实施例中，结合图2和图3所示，公共电极线包括多条第一公共电极线30和多条第二公共电极线31。第一公共电极线30与栅线10平行，设置在位于两条栅线10之间的两行子像素区域100之间，由于位于两条栅线10之间的两行子像素区域之间未设置有栅线，因此，将第一公共电极线30设置在位于两条栅线10之间的两行子像素区域100之间的方式，不会占用像素开口区，有利于提升开口率。
第二公共电极线31与数据线20大致平行或平行，在至少部分相邻的两列子像素区域100之间设置有第二公共电极线31。可选的，仅在部分相邻的两列子像素区域100之间设置有第二公共电极线31，以减小对开口率的影响。
通过设置交叉分布的第一公共电极线30和第二公共电极线31，可以提高公共电极线电阻的均一性，有利于提高公共电极线上信号的稳定性。具体的原理为：在显示过程中，栅线、数据线和显示用电极与公共电极线均会形成耦合电容。在栅线、数据线和显示用电极上的信号变化时，会拉动公共电极线的信号发生变化。公共电极线上的信号在拉动后的恢复过程中，公共电极线的电阻均一性越好，恢复速度越快，能够提高公共电极线上信号的稳定性。
其中，第一公共电极线30可以与栅线10为同层结构，由同一栅金属层制得。第二公共电极线31可以与数据线线20为同层结构，由同一源漏金属层制得。第一公共电极线30和第二公共电极线31之间具有绝缘层(图中未示意出)。
进一步地，还可以在所述绝缘层对应第一公共电极线30和第二公共电极线31交叉的位置设置多个过孔，第一公共电极线30和第二公共电极线31通过所述多个过孔电性连接，多点连接的方式能够进一步提升公共电极线电阻的均一性。
容易想到的是，也可以设置所述显示基板仅包括第一公共电极线30或第二公共电极线31。
当所述显示基板包括第二公共电极线31时，本实施例中设置多条第二公共电极线31等间距设置，提高公共电极线电阻的均一性。具体可以为：任意相邻的两条第二公共电极线31之间的子像素区域100的个数均为s，s为正整数。
如图3所示，以液晶显示装置的阵列基板为例，本实施例中的显示基板具 体包括：
多条平行的栅线10和多条平行的数据线20，栅线10和数据线20交叉分布，限定多个子像素区域100，相邻两条栅线10之间具有两行子像素区域，相邻两列子像素区域之间具有两条数据线20；
公共电极线，包括多条第一公共电极线30和多条第二公共电极线31，第一公共电极线30与栅线10平行，设置在位于两条栅线10之间的两行子像素区域之间；第二公共电极线31与数据线20平行，仅在部分相邻的两列子像素区域100之间设置由第二公共电极线31；
位于第一公共电极线30和第二公共电极线31之间的绝缘层，在所述绝缘层对应第一公共电极线30和第二公共电极线31交叉的位置设置过孔，第一公共电极线30和第二公共电极线31通过所述过孔电性连接；
每一子像素区域100包括：
薄膜晶体管1，位于一条栅线10两侧的相邻两行子像素区域的薄膜晶体管1的栅电极与该栅线10连接；位于同一列的相邻两个子像素区域中，其中一个子像素区域100的薄膜晶体管1的源电极2与位于该列子像素区域一侧的数据线20连接，另一个子像素区域100的薄膜晶体管1的源电极2与位于该列子像素区域另一侧的数据线20连接。
像素电极4，与薄膜晶体管1的漏电极3连接；
位于薄膜晶体管1和像素电极4之间的钝化层(图中未示意出)。
对于横向电场型液晶显示装置，所述阵列基板的每一子像素区域100还包括：
公共电极5，与公共电极线连接。
位于像素电极4和公共电极5之间的中间绝缘层(图中未示意出)。
其中，薄膜晶体管1可以为顶栅型薄膜晶体管、底栅型薄膜晶体管等。根据需要设置像素电极4、公共电极5和薄膜晶体管1的位置关系，在此不再一一列举。
实施例二
本实施例中提供一种显示装置及其驱动方法。所述显示装置采用实施例一中的显示基板，由于栅线的数量减半，从而提升了开口率。同时，栅线数量的 减半减少了栅极驱动芯片或栅极驱动电路的个数，降低了成本，并有利于实现窄边框。另外，由于一行子像素区域的薄膜晶体管可以打开两行子像素的充电时间，提供充足的充电时间，从而提高像素充电率，提升显示质量。
其中，所述显示装置可以为液晶显示装置、有机电致发光显示装置等。
上述显示装置的驱动方法包括：
通过一条栅线同时打开位于该栅线两侧的相邻两行子像素区域的薄膜晶体管，然后通过数据线一一对应向该两行子像素区域的薄膜晶体管传输像素电压。
上述驱动方法通过一条栅线同时打开位于该栅线两侧的相邻两行子像素区域的薄膜晶体管，使得子像素区域的充电时间翻倍，提供足够的充电时间，从而提高子像素区域的像素充电率，提升显示质量。
对于显示装置，不仅包括栅线和数据线，还包括用于显示用电极和公共电极线，所述显示用电极与薄膜晶体管的漏电极连接，数据线上传输的像素电压通过薄膜晶体管传输至显示用电极，形成实现显示的驱动电场。例如：对于液晶显示装置，所述显示用电极为像素电极。对于有机电致发光显示装置，所述显示用电极为有机发光二极管的阳极。
所述公共电极线用于提供基准电压，例如：用于为液晶显示装置的公共电极提供基准电压，为有机电致发光显示装置的有机发光二极管的阴极提供基准电压。
本实施例中，所述公共电极线包括多条与栅线平行的第一公共电极线，且所述第一公共电极线与栅线为同层结构，且所述第一公共电极线设置在位于相邻两条栅线之间的两行子像素区域之间，不会占用像素开口区，有利于提升开口率。
在显示过程中，栅线、数据线和显示用电极与公共电极线均会形成耦合电容。在栅线、数据线和显示用电极上的信号变化时，会拉动公共电极线的信号发生变化。例如：在显示一帧画面时，当红色子像素和蓝色子像素的显示用电极上的信号均为正极性时，对应的公共电极线上的信号向正极性拉动，当绿色子像素G的显示用电极上的信号为负极性，对应的公共电极线上的信号向负极性拉动。整个显示屏来看，公共电极线上的信号向正极性拉动较多，从而相 对于基准电压，公共电极线上的信号为较大的正极性电压，稳定性较差，导致绿色子像素的驱动电压增大，而红色子像素和蓝色子像素的驱动电压变小，画面发绿。
具体可以采用以下两种方式来克服公共电极线上信号的稳定性不好的问题：
第一种方式是降低耦合电容；
第二种方式是在一帧画面显示时，公共电极线上的信号向正极性的拉动和向负极性的拉动中和，保证公共电极线上信号的平衡，维持在基准电压。
当采用第一种方式时，需要增加公共电极线与栅线、数据线、显示用电极之间的距离，不利于实现高分辨率。
因此，本实施例中，优选采用第二种方式来克服公共电极线上信号的稳定性不好的问题，则上述驱动方法中：在显示一帧画面时，所述显示装置包括多个第一子像素区域，向所有第一子像素区域传输的像素电压中，具有第一极性的像素电压的个数与具有第二极性的像素电压的个数相同，所述第一极性和第二极性的极性相反，且具有第一极性的像素电压的绝对值与具有第二极性的像素电压的绝对值相同，所述像素电压用于形成驱动液晶分子偏转的电场，从而使得数据线和显示用电极对公共电极线上的信号拉动中和，保证公共电极线上信号的平衡，维持在基准电压。需要说明的是，在显示一帧画面时，除第一子像素区域的其它子像素区域，其对应的像素电压形成的驱动电场不能够驱动液晶分子偏转。例如：对于常暗模式的显示装置，所述第一子像素区域显示255灰阶，处第一像素区域的其他子像素区域显示0灰阶。
需要说明的是，本实施例中由于栅线和公共电极线之间间隔一行子像素区域，所以栅线对公共电极线上的信号的拉动可忽略。
在一个具体的实施方式中，所述显示装置为常暗模式，在显示一帧画面时，所述显示装置包括第一像素区域和第二像素区域，向第一像素区域传输第一组像素电压，将第一组像素电压中的像素电压提供给第一像素区域的子像素区域，第一组像素电压中的像素电压与第一像素区域的子像素区域一一对应，所述第一组像素电压包括n个具有第一极性的第一像素电压和m个具有第二极性的第二像素电压；
向第二像素区域传输第二组像素电压，将第二组像素电压中的像素电压提供给第二像素区域的子像素区域，第二组像素电压中的像素电压与第二像素区域的子像素区域一一对应，所述第二组像素电压包括p个具有第一极性的第三像素电压和q个具有第二极性的第四像素电压；
其中，n+p＝m+q，n、m、p、q为正整数。所述第一像素区域和第二像素区域为亮态像素区域，且所述第一组像素电压中的所有像素电压的绝对值相同以及所述第二组像素电压中的所有像素电压的绝对值相同。
上述具体实施方式能够实现在显示一帧画面时向所有亮态子像素区域(对应的像素电压形成驱动液晶分子偏转的电场)传输的像素电压中，具有第一极性的像素电压的个数与具有第二极性的像素电压的个数相同，且所有像素电压的绝对值相同，从而使得数据线和显示用电极对公共电极线上的信号拉动中和，保证公共电极线上信号的平衡，维持在基准电压。对于显示装置的暗态子像素区域，液晶分子未发生偏转，为暗态。
以所述显示装置的每一像素区域包括红色像素区域、绿色像素区域和蓝色像素区域为例，上述具体实施方式具体为：
在显示一帧画面时，向第一像素区域传输第一组像素电压，所述第一组像素电压包括正性的红色像素电压、负性的绿色像素电压和正性的蓝色像素电压。向第二像素区域传输第二组像素电压，所述第二组像素电压包括负性的红色像素电压、正性的绿色像素电压和负性的蓝色像素电压，其中，红色像素电压、绿色像素电压和蓝色像素电压的绝对值相同。
作为一个具体的实施方式，结合图4和图5所示，对于常暗模式的显示装置，在一帧画面显示时，还可以将显示装置的像素区域分为第一像素重复单元a和第二像素重复单元b，第一像素重复单元a中正极性的像素电压个数与第二像素重复单元b中负极性的像素电压个数相同，且第一像素重复单元a中负极性的像素电压个数与第二像素重复单元b中正极性的像素电压个数相同，且负极性的像素电压和正极性的像素电压的绝对值相同。对于每一行像素区域，可以设置第一像素重复单元a和第二像素重复单元b的个数相同，间隔设置，以达到对公共电极线上的信号的拉动中和。其中，正极性的像素电压和负极性的像素电压用于形成驱动液晶分子偏转的电场，例如：图4和图5中，正极性 的像素电压和负极性的像素电压对应的子像素区域显示255灰阶。而对于第一像素重复单元a和第二像素重复单元b的其它子像素区域显示0灰阶。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开技术原理的前提下，还可以做出若干改进和替换，这些改进和替换也应视为本公开的保护范围。

Claims (18)

  1. 一种显示基板，包括多条栅线和多条数据线，所述多条栅线和所述多条数据线交叉分布，其中，
    相邻两条栅线之间具有两行子像素区域，相邻两列子像素区域之间设置有两条数据线；
    每一子像素区域包括一个薄膜晶体管，一个薄膜晶体管对应一条数据线；
    分别位于一条所述栅线两侧的相邻两行子像素区域的薄膜晶体管与该栅线连接，且分别位于一条所述栅线两侧的相邻两行子像素区域的薄膜晶体管与对应的数据线连接。
  2. 根据权利要求1所述的显示基板，其中还包括与所述栅线平行的第一公共电极线，所述第一公共电极线设置在位于相邻两条栅线之间的两行子像素区域之间。
  3. 根据权利要求1或2所述的显示基板，还包括与所述数据线平行的第二公共电极线，其中在至少两对相邻的两列子像素区域的每一对之间设置有所述第二公共电极线。
  4. 根据权利要求3所述的显示基板，其中，任意相邻的两条第二公共电极线之间的子像素区域的个数均为s，s为正整数。
  5. 根据权利要求3或4所述的显示基板，其中，任意相邻的两条第二公共电极线之间的间距大致相同。
  6. 根据权利要求3-5任一项所述的显示基板，其中，任意相邻的两条第二公共电极线之间的位于同一行的子像素区域的个数大于或等于2。
  7. 根据权利要求3-6任一项所述的显示基板，其中，所述第二公共电极线位于相邻两列子像素区域的两条数据线之间。
  8. 根据权利要求2-7任一项所述的显示基板，其中，所述第一公共电极线与所述栅线为同层结构。
  9. 根据权利要求8所述的显示基板，其中，所述第二公共电极线与所述数据线为同层结构，所述第一公共电极线和第二公共电极线交叉分布。
  10. 根据权利要求9所述的显示基板，其中，所述第一公共电极线和第二公共电极线之间具有绝缘层，所述绝缘层对应所述第一公共电极线和第二公共 电极线交叉的位置设置有过孔，所述第一公共电极线和第二公共电极线通过所述过孔电性连接。
  11. 根据权利要求1-10任一项所述的显示基板，其中，位于同一列的相邻两个子像素区域中，其中一个子像素区域的薄膜晶体管与位于该列子像素区域一侧的数据线连接，另一个子像素区域的薄膜晶体管与位于该列子像素区域另一侧的数据线连接。
  12. 一种显示装置，包括权利要求1-11任一项所述的显示基板。
  13. 一种如权利要求12所述的显示装置的驱动方法，包括：
    通过一条栅线同时打开位于该栅线两侧的相邻两行子像素区域的薄膜晶体管；
    通过数据线向该两行子像素区域的薄膜晶体管传输像素电压。
  14. 根据权利要求13所述的驱动方法，其中在显示一帧画面时，所述显示装置包括多个第一子像素区域，向所述多个第一子像素区域传输的像素电压形成的电场能够驱动液晶分子偏转；以及在向所述多个第一子像素区域传输的像素电压中，具有第一极性的像素电压的个数与具有第二极性的像素电压的个数相同，所述第一极性和第二极性的极性相反。
  15. 根据权利要求14所述的驱动方法，其中，具有第一极性的像素电压的绝对值与具有第二极性的像素电压的绝对值相同。
  16. 根据权利要求13所述的驱动方法，其中在显示一帧画面时，所述显示装置包括为第一像素区域和第二像素区域；
    向所述第一像素区域的多个子像素区域传输的第一组像素电压包括n个具有第一极性的第一像素电压和m个具有第二极性的第二像素电压，所述第一组像素电压中的像素电压与所述第一像素区域的多个子像素区域一一对应；
    向所述第二像素区域的多个子像素区域传输的第二组像素电压包括p个具有第一极性的第三像素电压和q个具有第二极性的第四像素电压，所述第二组像素电压中的像素电压与所述第二像素区域的多个子像素区域一一对应；
    其中n+p＝m+q，n、m、p、q为正整数。
  17. 根据权利要求16所述的驱动方法，其中所述第一像素区域包括第一红色像素区域、第一绿色像素区域和第一蓝色像素区域，所述第一组像素电压 包括提供给所述第一红色像素区域的正性的红色像素电压、提供给所述第一绿色像素区域的负性的绿色像素电压和提供给所述第一蓝色像素区域的正性的蓝色像素电压；
    所述第二像素区域包括第二红色像素区域、第二绿色像素区域和第二蓝色像素区域，所述第二组像素电压包括提供给所述第二红色像素区域的正性的红色像素电压、提供给所述第二绿色像素区域的负性的绿色像素电压和提供给所述第二蓝色像素区域的正性的蓝色像素电压。
  18. 根据权利要求17所述的驱动方法，其中所述红色像素电压、所述绿色像素电压和所述蓝色像素电压的绝对值相同。
PCT/CN2017/103089 2017-02-21 2017-09-25 显示基板、显示装置及其驱动方法 Ceased WO2018153084A1 (zh)

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