WO2018152888A1 - 一种ltps制程中的tft器件的分布结构 - Google Patents

一种ltps制程中的tft器件的分布结构 Download PDF

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WO2018152888A1
WO2018152888A1 PCT/CN2017/076582 CN2017076582W WO2018152888A1 WO 2018152888 A1 WO2018152888 A1 WO 2018152888A1 CN 2017076582 W CN2017076582 W CN 2017076582W WO 2018152888 A1 WO2018152888 A1 WO 2018152888A1
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data line
tft device
pixels
tft
row
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陈辰
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to a structure of a TFT in the field of liquid crystal display, and more particularly to a structure of a TFT fabricated in LTPS.
  • the aperture ratio is something that every product design team must consider when designing each product.
  • the aperture ratio refers to the wiring portion and transistor portion (usually hidden by a black matrix) that removes each sub-pixel.
  • the panel such as the signal traces for the LCD source driver chip and the gate driver chip, as well as the TFT itself, as well as the storage capacitors for storing voltage.
  • these places are also unable to display the correct gray scale because the light passing through these places is not controlled by voltage, so they need to be shielded by a black matrix to avoid interference with other light-transmitting areas.
  • the ratio of the effective light-transmitting area to the entire area is called the aperture ratio.
  • Various factors such as the pixel design of the pixel (Pixel) Pixel display or the television image, and the placement of various metal wires greatly affect the aperture ratio of the final product.
  • the data lines include the first data line 21 and the second data line 22 .
  • the two adjacent pixels of each column are connected to the first data 21 through the U-shaped TFT1, and the TFT2 is connected to the first data line 21, and the two-pixel TFTs of the adjacent columns corresponding to the two pixels respectively and the second data
  • the line 22 is connected, and the first data line and the second data line voltage may be positive, and the realistic mode is face inversion or frame inversion;
  • the voltages of the first data line and the second data line may be opposite, one being positive and one negative, such that pixels of adjacent columns are positively charged and one column is negative. This display mode is called column inversion.
  • the object of the present invention is to overcome the shortcomings of the prior art that the effect of realizing the dot inversion is high, and the product has low competitiveness in the market, and design a TFT distribution mode with low power consumption and increased aperture ratio.
  • the display effect of dot inversion is realized in the display mode of column inversion.
  • a distribution structure of a TFT device in an LTPS process wherein a pair of mutually parallel data lines are disposed between the pixel of the i-th row and the pixel of the i+1th row;
  • Each pair of data lines includes a first data line and a second data line
  • the adjacent two pixels of the i-th row are respectively connected to the first data line and the second data line through a corresponding U-shaped TFT structure;
  • the two pixels corresponding to the two adjacent pixels in the i+1th row are respectively connected to the second data line and the first data line through the TFTs of the corresponding U-shaped structure;
  • the U-shaped TFT of the ith row of pixels is opposite to the U-shaped TFT opening of the corresponding i+1th row of pixels, and is staggered;
  • the TFT device is turned on by a gate line.
  • the distributed structure of the TFT device in the LTPS process wherein: the source of the U-shaped TFT device is connected to a corresponding data line.
  • the distributed structure of the TFT device in the LTPS process wherein: the first data line voltage is positive and the second data line voltage is negative.
  • the distributed structure of the TFT device in the LTPS process wherein: the pixel electrode of the U-shaped TFT device connected to the first data line is negative, and the pixel electrode of the U-shaped TFT connected to the second data line is positive .
  • each of the gate lines is S
  • the pattern surrounds two pixels between each adjacent two pairs of data lines per column.
  • each of the pixels is provided with a black matrix
  • the gate line is horizontally overlapped with a black matrix disposed between each pair of data lines
  • the gate lines coincide in a vertical direction with a black matrix disposed between two pairs of adjacent data lines and perpendicular to the two pairs of data lines.
  • the distributed structure of the TFT device in the LTPS process wherein the gate line is disposed between the double data line layer and the semiconductor layer where the TFT device is located.
  • each of the pixels corresponds to a U-shaped TFT device.
  • each of the TFT devices in the (i+1) th row controls a pixel of the TFT device of the i-th row corresponding thereto.
  • each of the columns of the TFT devices is electrically connected to a gate line.
  • the invention has the following advantages: the U-shaped TFTs are mutually arranged, which can effectively increase the aperture ratio of the product;
  • the signal given to the first data line in the first frame is a negative value
  • the signal given to the first data line in the second frame is a positive value
  • the display mode of the column inversion is adopted, but the polarity between the adjacent two pixels is On the contrary, the display effect of dot inversion is obtained, thereby improving the display quality of the product. In this way, dot inversion can be realized in the case of column inversion, thereby saving power consumption of the product.
  • FIG. 1 is a schematic diagram showing the distribution of TFTs in a conventional LTPS process.
  • FIG. 2 is a schematic view showing the distribution of TFTs in the LTPS process of the present invention.
  • Figure 3 is a cross-sectional view showing the distribution of TFTs in the LTPS process of the present invention.
  • FIG. 2 is a schematic view showing the distribution of TFTs in the LTPS process of the present invention, including a plurality of rows of pixels, wherein i A pair of parallel data lines are disposed between the row pixel and the i+1th row pixel; the data line includes a first data line 21 and a second data line 22; adjacent to the i-th row and the i+1th row
  • the pixels 10 and 20 are respectively connected to the first data line 21 and the second data line 22 through the U-shaped TFT devices 1' and 2', respectively; the i+1 row and the two pixels 30 corresponding to the two adjacent pixels 10 and 20 and 40 is respectively connected to the second data line 22 and the first data line 21 through the U-shaped TFT devices 1 and 2; the U-shaped TFT device 1 of the i-th row of pixels and the i+1-th row pixel corresponding thereto
  • the U-shaped TFT device 1 has opposite openings and is alternately arranged.
  • the U-shaped TFT device 1 includes a drain 11 and a source 12, and the source 12 is connected to a data line.
  • the drain 11 is used to pass a signal to the inside of the pixel.
  • the present invention will have two U-shaped TFT devices.
  • the openings are relatively staggered, and the source end of the U-shaped TFT device is disposed in the opening of the U-shaped TFT device, so that the area of the inner portion of the opening of the U-shaped TFT device can be effectively utilized, and the U-shaped TFT device occupies other pixels.
  • the area of the light portion to increase the aperture ratio of the product.
  • the TFT device is turned on by the gate line 3, and the gate line is used to turn on the TFT device to make the TFT exhibit conductivity.
  • each TFT device in each column is turned on by a gate line, and each TFT device is A gate line is connected.
  • the voltage of the first data line 21 is positive, and the voltage of the second data line 22 is negative.
  • the pixel of the pixel 10 in which the U-shaped TFT device 1 connected to the first data line 21 is located is positive, and the electrode of the pixel 30 in which the U-shaped TFT device 1' is connected to the second data line 22 is negative.
  • the pixel 20 adjacent to the pixel 10, the U-shaped TFT device 2 connected to the first data line 21, the electrode of the pixel 20 being negative, and the pixel of the U-shaped TFT device 2' connected to the second data line 22 40 electrodes are positive.
  • the electrode of pixel 50 is positive and the electrode of pixel 60 is negative.
  • the pixel 10 is controlled by the U-shaped TFT device 1'
  • the pixel 20 is controlled by the U-shaped TFT device 2'
  • the pixel 30 is controlled by the U-shaped TFT device 1
  • the pixel 40 is controlled by the U-shaped TFT device 2 That is, the pixel of the i-th row is controlled by the U-shaped TFT device located in the pixel of the i+1th row, and the pixel of the i+1th row is controlled by the U-shaped TFT device located in the pixel of the i-th row.
  • the signal given to the first data line in the first frame is a negative value
  • the signal given to the first data line in the second frame is a positive value, that is, a display mode in which column inversion is employed, but adjacent to each of the first data lines
  • the polarity between the two pixels is opposite, that is, the dot inversion display effect is obtained, thereby improving the display quality of the product.
  • the voltage of the first data line 21 can also be set to be negative, and the voltage of the second data line is set to positive 22, then the pixel electrode of the U-shaped TFT device connected to the first data line is positive, and the second The pixel electrode of the U-shaped TFT device to which the data line is connected is negative, that is, the voltage polarity of any one of the pixels is opposite to the polarity of the adjacent upper, lower, left and right pixel voltages.
  • This design has a dot-reversed display effect, which improves the display quality of the product.
  • BM strip black matrix
  • the gate lines 3 are arranged in which the black matrices coincide
  • the portion can reduce the light transmission area of the pixel occupied by the gate line during the arrangement process, and affect the aperture ratio.
  • the gate line 3 is S-shaped to surround each column of pixels.
  • the gate lines 3 are disposed in a horizontal direction and a vertical direction, wherein the gate lines 3 coincide in a horizontal direction with a black matrix disposed between the two data lines, and the gate lines 3 are disposed adjacent to each other in the vertical direction
  • the black matrix on the vertical sides of the two pixels between the two pairs of data lines coincide. That is, each of the gate lines 3 respectively surrounds two adjacent sides of each pixel of each column. This arrangement effectively reduces the light transmission area occupied by the gate lines and increases the aperture ratio of the product.
  • a cross-sectional view of a distribution of TFTs in the LTPS process of the present invention includes a first ITO 111, a passivation layer 112, a second ITO 113, and a flat layer 114 on a glass plate 121 disposed in this order from top to bottom.
  • the data line layer 115, the insulating layer 117, and the dielectric layer 116 may be disposed according to different products.
  • the data line layer 115 is respectively opposite to the polysilicon layer 120, the flat layer 114, and the first ITO layer 111 and the second ITO layer 113. contact.
  • the gate line 119 layer is disposed between the data line layer 115 and the semiconductor layer 120. And not in contact with the data line 115 and the semiconductor layer 120.
  • the gate line opening around the pixel between each adjacent two pairs of data lines is opposite.
  • Each of the pixels functions by one TFT device, and two opposite U-shaped TFTs each occupy one pixel.
  • each of the TFT devices in the (i+1) th row controls a pixel of the TFT device of the i-th row corresponding thereto. That is, the TFT device 1' controls the pixel 10, the TFT device 1 controls the pixel 30, the TFT device 2' controls the pixel 20, and the TFT device 2 controls the pixel 40...
  • each of the columns of the TFT devices is electrically connected to a gate line.

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Abstract

一种LTPS制程中的TFT器件的分布结构，第i行像素和第i+1行像素之间设有一对相互平行的数据线；所述数据线包括第一数据线和第二数据线；第i行相邻两像素分别通过U字型结构的TFT器件分别连接第一数据线和第二数据线；第i+1行与上述两相邻像素对应的两像素分别通过U字形结构的TFT器件分别与第二数据线和第一数据线连接；所述第i行像素的U字型TFT器件与与之对应的第i+1行像素的U字型TFT器件开口相对，交错设置。通过U字型TFT器件相互交叉设置，可以有效增加了产品的开口率，使用这种方式可以在列反转的情况下实现点反转，节省产品的功耗。

Description

一种LTPS制程中的TFT器件的分布结构
相关申请的交叉引用
本申请要求享有于2017年2月22日提交的名称为“一种LTPS制程中的TFT器件的分布结构”的中国专利申请2017100961479的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示领域里的一种TFT的结构，具体是关于一种在LTPS制成中的TFT的结构。
背景技术
在显示面板的制造中，开口率是每一个产品设计团队在设计每一款的产品时必须考虑的事情，开口率指除去每一个次像素的配线部、晶体管部(通常采用黑色矩阵隐藏)后的光线通过部分的面积和每一个次像素整体的面积之间的比例。开口率越高，光线通过的效率越高。当光线经由背光板发射出来时，并不是所有的光线都能穿过面板，比如给LCD source驱动芯片及gate驱动芯片用的信号走线，以及TFT本身，还有储存电压用的储存电容等。这些地方除了不完全透光外，也由于经过这些地方的光线不受电压控制，而无法显示正确的灰阶，所以都需利用黑矩阵(black matrix)加以遮蔽，以免干扰其它透光区域。而有效的透光区域与全部面积的比例就称之为开口率。像素(Pixel)Pixel显示器或电视机图象的)象素的图案设计、各类金属线的放置等各类因素都会极大的影响最终产品的开口率。
如图1所示，为传统LTPS工艺中TFT的形状及布局，相邻两列像素之间设有两个相互平行的数据线，所述数据线包括第一数据线21和第二数据线22，每列相邻两像素分别通过U字型TFT1与第一数据相连21，TFT2与第一数据线21相连，与上述两像素相对应的相邻列的两像素的TFT，分别与第二数据线22连接，所述第一数据线与第二数据线电压可以为正，这种现实模式为面反转或帧反转； 所述第一数据线和第二数据线的电压可以相反，一个为正一个未负，这样相邻两列的像素一列为正电，一列为负电，这种显示模式叫做列反转。
此外，在显示面板的制造中，由于在画面切换时使用点反转的方式画面闪烁的现象表现最为轻微，因此在图像显示方式上人们更倾向于这种方式，但是为实现点反转的效果面板的功耗非常高，从而降低了产品在市场中的竞争性，因此一般产品中使用功耗较小的列反转的反转模式进行显示。
发明内容
本发明的目的在于：克服现有技术中实现点反转的效果面板的功耗高，产品在市场中的竞争性低的缺点，设计一种低功耗，增加开口率的TFT分布方式，在列反转的显示模式下实现点反转的显示效果。
本发明的目的及解决其技术问题是采用以下技术方案实现的：
一种LTPS制程中的TFT器件的分布结构，第i行像素和第i+1行像素之间设有一对相互平行的数据线；
所述每对数据线包括第一数据线和第二数据线；
第i行相邻两像素分别通过相应的U字型的TFT结构连接第一数据线和第二数据线；
第i+1行与上述两相邻像素对应的两像素分别通过相应的U字形结构的TFT分别与第二数据线和第一数据线连接；
所述第i行像素的U字型TFT和与之对应的第i+1行像素的U字型TFT开口相对，交错设置；
所述TFT器件由栅极线导通。
所述的LTPS制程中的TFT器件的分布结构，其中：所述U字型TFT器件的源极和与之对应的数据线相连。
所述的LTPS制程中的TFT器件的分布结构，其中：所述第一数据线电压为正，第二数据线电压为负。
所述的LTPS制程中的TFT器件的分布结构，其中：与第一数据线连接的U字型TFT器件所在像素电极为负，与第二数据线连接的U字型TFT所在的像素电极为正。
所述的LTPS制程中的TFT器件的分布结构，其中：所述的每根栅极线呈S 型环绕每列每相邻两对数据线之间的两个像素。
所述的LTPS制程中的TFT器件的分布结构，其中：所述每个像素四周设置有黑色矩阵，所述栅极线在水平方向上与设置在每对数据线之间的黑色矩阵重合，所述栅极线在垂直方向上与设置在两对相邻数据线之间且垂直于两对数据线的黑色矩阵重合。
所述的LTPS制程中的TFT器件的分布结构，其中：所述栅极线设置在双数据线层与TFT器件所在的半导体层之间。
所述的LTPS制程中的TFT器件的分布结构，其中：所述每个像素分别对应一个U字型TFT器件。
所述的LTPS制程中的TFT器件的分布结构，其中：所述第i+1行每个TFT器件控制与之对应的第i行的TFT器件所在的像素。
所述的LTPS制程中的TFT器件的分布结构，其中：所述的每列TFT器件分别与一根栅极线导通连接。
本发明具有以下优点：通过U字型TFT相互交叉设置，可以有效增加了产品的开口率；
第一帧给予第一数据线的信号为负值，第二帧给予第一数据线的信号为正值，采用了列反转的显示模式，但相邻的两个像素之间的极性均相反，即得到了点反转的显示效果，从而提升了产品的显示品质，使用这种方式可以在列反转的情况下实现点反转，节省产品的功耗。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1是传统LTPS制程中的TFT的分布方式示意图。
图2是本发明LTPS制程中的TFT的分布示意图。
图3是本发明LTPS制程中的TFT的分布剖面图。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例。
具体实施方式
下面将结合附图对本发明作进一步说明。
图2是本发明LTPS制程中的TFT的分布示意图，包括多行像素，其中第i 行像素和第i+1行像素之间设有一对相互平行的数据线；所述数据线包括第一数据线21和第二数据线22；第i行与第i+1行间相邻两像素10和20分别通过U字型TFT器件1’与2’分别连接第一数据线21和第二数据线22；第i+1行与上述两相邻像素10和20对应的两像素30和40分别通过U字形TFT器件1与2分别与第二数据线22和第一数据线21连接；所述第i行像素的U字型TFT器件1与与之对应的第i+1行像素的U字型TFT器件1开口相对，交错设置。
所述U字型TFT器件1包括漏极11和源极12，所述源极12与数据线相连。所述漏极11用于把信号传递至像素内部。
由于U字型结构的TFT在开口内侧的部分无法透光，在传统的TFT设置中，并没有有效的利用起这个部分，导致显示面板开口率不佳，本发明将两个U字型TFT器件的开口相对交错设置，将U字型TFT器件的源极一端设置在U型TFT器件的开口内，可有效利用U字型TFT器件开口内侧部分的面积，减少U字型TFT器件占有像素其他透光部分的面积，以增加产品的开口率。
所述TFT器件由栅极线3导通，栅极线用于导通TFT器件，使TFT发挥导电性能，其中，每列每个TFT器件由一根栅极线导通，每个TFT器件与一根栅极线连接。
所述第一数据线21电压为正，第二数据线22电压为负。
与第一数据线21连接的U字型TFT器件1所在像素10电极为正，与第二数据线22连接的U字型TFT器件1’所在的像素30电极为负。
与像素10相邻的像素20，其与第一数据线21连接的U字型TFT器件2，像素20的电极为负，与第二数据线22连接的U字型TFT器件2’所在的像素40电极为正。
以此类推，像素50的电极为正，像素60的电极为负。
其中，像素10是由U字型TFT器件1’控制，像素20是由U字型TFT器件2’控制；像素30由U字型TFT器件1控制，像素40由U字型TFT器件2控制，即第i行的像素是由位于第i+1行像素内的U字型TFT器件控制的，第i+1行像素则是由位于第i行像素内的U字型TFT器件控制的。
即第一帧给予第一数据线的信号为负值，第二帧给予第一数据线的信号为正值，即采用了列反转的显示模式，但每个第一数据线上相邻的两个像素之间的极性均相反，即得到了点反转的显示效果，从而提升了产品的显示品质。
所述的第一数据线21电压也可设置为负，第二数据线的电压设置为正22，那么与第一数据线连接的U字型TFT器件所在的像素电极则为正，与第二数据线连接的U字型TFT器件所在的像素电极则为负，即任意一个像素的电压极性与其相邻的上、下、左、右像素电压极性都相反。这样的设计，得到了点反转的显示效果，从而提升了产品的显示品质。
在每个像素的四周，还设置有条形的黑色矩阵(BM；black Matrix)用于遮挡光线，因此在LTPS制程中的TFT设计过程中，将栅极线3布置在于所述黑色矩阵相重合的部位，能够减少栅极线在布置过程中占用像素透光面积，影响开口率。
所述栅极线3呈S型环绕每列像素。栅极线3呈水平方向和竖直方向设置，其中，栅极线3在水平方向上与设置在两数据线之间的黑色矩阵重合，栅极线3在竖直方向上与设置在相邻两对数据线之间的两个像素的垂直边上的黑色矩阵重合。即所述每根栅极线3分别环绕每列每个像素的两个相邻边。这样设置有效减少栅极线占用像素的透光面积，增加产品的开口率。
如图3所示，为本发明LTPS制程中的TFT的分布的剖面图，包括由上至下依次设置的玻璃板121上的第一ITO111、钝化层112、第二ITO113、平坦层114、数据线层115、介电层116、栅极线119、绝缘层117、TFT半导体层120以及缓冲层118。其中，数据线层115、绝缘层117和介电层116可根据不同产品的需要进行设置，数据线层115分别与多晶硅层120、平坦层114和第一ITO层111和第二ITO层113相接触。
所述栅极线119层设置在数据线层115与半导体层120之间。且不与数据线115和半导体层120相接触。
围绕每相邻两对数据线之间的像素的栅极线开口相反。
所述每个像素分别由一个TFT器件发挥作用，两个相对的U字型TFT各自占有1个像素。
所述的LTPS制程中的TFT器件的分布结构，其中：所述第i+1行每个TFT器件控制与之对应的第i行的TFT器件所在的像素。即：TFT器件1’控制像素10，TFT器件1控制像素30，TFT器件2’控制像素20，TFT器件2控制像素40……
所述的LTPS制程中的TFT器件的分布结构，其中：所述的每列TFT器件分别与一根栅极线导通连接。
虽然已经参考优选实施例对本发明进行了描述，但在不脱离本发明的范围的情况下，可以对其进行各种改进并且可以用等效物替换其中的部件。尤其是，只要不存在结构冲突，各个实施例中所提到的各项技术特征均可以任意方式组合起来。本发明并不局限于文中公开的特定实施例，而是包括落入权利要求的范围内的所有技术方案。

Claims (10)

  1. 一种LTPS制程中的TFT器件的分布结构，其特征在于：第i行像素和第i+1行像素之间设有一对相互平行的数据线；
    所述每对数据线包括第一数据线和第二数据线；
    第i行相邻两像素分别通过相应的U字型的TFT结构连接第一数据线和第二数据线；
    第i+1行与上述两相邻像素对应的两像素分别通过相应的U字形结构的TFT分别与第二数据线和第一数据线连接；
    所述第i行像素的U字型TFT和与之对应的第i+1行像素的U字型TFT开口相对，交错设置；
    所述TFT器件由栅极线导通。
  2. 根据权利要求1所述的LTPS制程中的TFT器件的分布结构，其特征在于：所述U字型TFT器件的源级和与之对应的数据线相连。
  3. 根据权利要求1所述的LTPS制程中的TFT器件的分布结构，其特征在于：所述第一数据线电压为正，第二数据线电压为负。
  4. 根据权利要求3所述的LTPS制程中的TFT器件的分布结构，其特征在于：与第一数据线连接的U字型TFT器件所在像素电极为负，与第二数据线连接的U字型TFT所在的像素电极为正。
  5. 根据权利要求1所述的LTPS制程中的TFT器件的分布结构，其特征在于：所述的每根栅极线呈S型环绕每列每相邻两对数据线之间的两个像素。
  6. 根据权利要求5所述的LTPS制程中的TFT器件的分布结构，其特征在于：所述每个像素四周设置有黑色矩阵，所述栅极线在水平方向上与设置在每对数据线之间的黑色矩阵重合，所述栅极线在垂直方向上与设置在两对相邻数据线之间且垂直于两对数据线的黑色矩阵重合。
  7. 根据权利要求6所述的LTPS制程中的TFT器件的分布结构，其特征在于：所述栅极线设置在双数据线层与TFT器件所在的半导体层之间。
  8. 根据权利要求1所述的LTPS制程中的TFT器件的分布结构，其特征在于：所述每个像素分别对应一个U字型TFT器件。
  9. 根据权利要求1所述的LTPS制程中的TFT器件的分布结构，其特征在 于：所述第i+1行每个TFT器件控制与之对应的第i行的TFT器件所在的像素。
  10. 根据权利要求1所述的LTPS制程中的TFT器件的分布结构，其特征在于：所述的每列TFT器件分别与一根栅极线导通连接。
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