WO2018152871A1 - 一种薄膜晶体管 - Google Patents

一种薄膜晶体管 Download PDF

Info

Publication number
WO2018152871A1
WO2018152871A1 PCT/CN2017/076083 CN2017076083W WO2018152871A1 WO 2018152871 A1 WO2018152871 A1 WO 2018152871A1 CN 2017076083 W CN2017076083 W CN 2017076083W WO 2018152871 A1 WO2018152871 A1 WO 2018152871A1
Authority
WO
WIPO (PCT)
Prior art keywords
light shielding
shielding layer
thin film
film transistor
layer
Prior art date
Application number
PCT/CN2017/076083
Other languages
English (en)
French (fr)
Inventor
韩约白
虞晓江
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US15/522,841 priority Critical patent/US20180301532A1/en
Publication of WO2018152871A1 publication Critical patent/WO2018152871A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present invention relates to the field of thin film transistors, and in particular to a light shielding layer of a low temperature polysilicon panel.
  • a top gate structure is often used, that is, a metal film as a shading layer (SL) is first formed on the surface of the glass.
  • a metal film as a shading layer (SL) is first formed on the surface of the glass.
  • the polysilicon layer has a certain inclination angle (ie, slope) at the edge of the light shielding layer, the damage of the polysilicon layer is easily caused in the process of Excimer Laser Annealing (ELA), thereby affecting the electrical properties of the polysilicon layer.
  • ELA Excimer Laser Annealing
  • the characteristic that the tilt angle of the edge climbing position of the light shielding layer is too large causes the conductivity of the polysilicon layer at the edge of the light shielding layer to be abnormal.
  • the low temperature polysilicon layer can be significantly improved at the edge of the light shielding layer.
  • Conductive properties thereby reducing defects such as bright and dark spots.
  • the patent document CN201410837376.8 provides a technical solution for providing a light shielding layer in a low temperature polysilicon thin film transistor, and does not provide a technical solution for improving the conductive characteristics of the edge layer (ie, polysilicon layer).
  • the present invention proposes a novel light shielding layer pattern, which can break through the limitations of the process and equipment, and more effectively improve the inclination angle of the edge climbing position of the light shielding layer, thereby improving the conductive characteristics of the polysilicon layer and improving the product. Yield.
  • the present invention provides a thin film transistor including a light shielding layer and a polysilicon layer, the light shielding layer being disposed under the polysilicon layer;
  • the included angle is an acute angle or an obtuse angle.
  • an edge of the polysilicon layer parallel to a growth direction of the polysilicon layer in a plan view is a first side, and an edge of the light shielding layer in contact with the polysilicon layer is set Second side;
  • the included angle is an angle of intersection between the first side and the second side.
  • the light shielding layer has a trapezoidal shape in plan view.
  • the light shielding layer has a parallelogram shape in plan view.
  • the edge of the light shielding layer is designed to be jagged, or the light shielding layer in plan view is directly designed into a trapezoidal shape or a parallelogram shape, so that the polysilicon layer and the light shielding layer are not vertically disposed, but have a certain angle (an acute angle). Or obtuse angle), thereby reducing the inclination angle of the polysilicon layer at the edge climbing position of the light shielding layer, and improving the conductive property of the polysilicon layer.
  • FIG. 1 is a perspective view showing a positional relationship between a polysilicon layer and a light shielding layer in the prior art
  • FIG. 2 is a schematic view showing the structure of a polysilicon layer perpendicular to a light shielding layer in a plan view in the prior art
  • FIG. 3 is a perspective view showing a positional relationship between a polysilicon layer and a light shielding layer in the present invention
  • FIG. 4 is a schematic structural view of the edge of the light shielding layer in a zigzag shape when viewed from above in the present invention
  • Figure 5 is a schematic view showing the structure of the present invention when the light shielding layer is trapezoidal in plan view;
  • Figure 6 is a schematic view showing the structure of the present invention when the light shielding layer is a parallelogram in plan view;
  • the direction of the arrow marked on the polysilicon layer 2 indicates the growth direction of the polysilicon layer 2 (which may also be referred to as the direction in which the polysilicon layer 2 extends).
  • the edge parallel to the growth direction of the polysilicon layer 2 is first set to be the first side 6, and the edge of the light shielding layer 1 in contact with the polysilicon layer 2 is the second side 7.
  • the polysilicon layer 2 is perpendicular to the light shielding layer 1 in the prior art, that is, the angle ⁇ between the first side 6 and the second side 7 is 90°.
  • the process of the light shielding layer 1 at this time causes the inclination angle of the edge climbing position 5 to be ⁇ , where the inclination angle ⁇ can be understood as the slope angle of the edge climbing position 5 of the light shielding layer 1 at the main viewing angle.
  • L is the climbing length of the growth direction of the parallel polysilicon layer 2
  • h is the thickness of the light shielding layer 1.
  • the tilt angle is large, and the polysilicon layer 2 is easily damaged during the crystallization of the excimer laser, thereby causing the conductivity of the polysilicon layer 2 at the edge climbing position 5 of the light shielding layer 1 to be abnormal.
  • the present invention provides a thin film transistor including a light shielding layer 1 and a polysilicon layer 2, the light shielding layer 1 is disposed under the polysilicon layer 2, and the light shielding layer 1 and the polysilicon layer are viewed from above.
  • the angle ⁇ existing between the two in the overhead view is an acute angle or an obtuse angle, that is, in FIG. 3, the intersection angle ⁇ of the first side 6 and the second side 7 is an acute angle or an obtuse angle.
  • the second side 7 intersecting the first side 6 in the preferred embodiment is serrated.
  • the light shielding layer 1 is trapezoidal in plan view. Wherein, the trapezoidal waist is the second side, and the upper and lower bottoms of the trapezoid are parallel to the first side.
  • the light shielding layer 1 is set to be a parallelogram in plan view. Wherein one side of the parallelogram is the second side, and the other side of the parallelogram intersecting the second side is parallel to the first side.
  • the second side of the light shielding layer 1 perpendicular to the polysilicon layer 2 is designed to be sawtooth in plan view, and the light shielding layer 1 is designed to be trapezoidal or the light shielding layer 1
  • the design is a parallelogram, the main purpose is the same, and the angle ⁇ is formed between the polysilicon layer 2 and the light shielding layer 1, and ⁇ is not equal to 90°, which is an acute angle or an obtuse angle.
  • the principle of designing ⁇ is as follows:
  • the equivalent tilt angle ⁇ is smaller than the tilt angle ⁇ in the prior art, that is, the polysilicon can be reduced.
  • the slope of the layer 2 at the edge of the light-shielding layer 1 at the climbing position 5 improves the conductive properties of the polysilicon layer 2 therein.
  • the light shielding layer 1 is a metal film.
  • the invention breaks through the limitation of the process, and adjusts the inclination of the polysilicon layer 2 relative to the light shielding layer 1 by the magnitude of the ⁇ angle, so that the polysilicon layer 2 can be reduced in a larger range.
  • the slope of the edge climbing position 5 of the layer 1 achieves the effect of improving the conductive properties of the polysilicon layer 2.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种薄膜晶体管，其中，包括遮光层（1）和多晶硅层（2），遮光层设于多晶硅层之下；俯视时遮光层与多晶硅层之间存在夹角，夹角为锐角或钝角。通过合理设计遮光层形状，突破了工艺制程的限制，可在更大的范围内减小多晶硅层在遮光层边缘爬坡位置的倾斜度，达到改善多晶硅导电特性的效果。

Description

一种薄膜晶体管
相关申请的交叉引用
本申请要求享有于2017年2月22日提交的名称为“一种薄膜晶体管”的中国专利申请CN201710096247.1的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及薄膜晶体管领域，特别地涉及一种低温多晶硅面板的遮光层。
背景技术
具有高分辨率、高迁移率和低功耗等诸多优点的低温多晶硅面板已经广泛应用在目前的平板显示产品中，例如苹果、三星、华为、小米及魅族等各大手机和平板电脑上。
但是，由于低温多晶硅器件的制程复杂，目前多采用顶栅结构，即需要在玻璃表面首先成膜一层作为遮光层(Shading Layer，SL)的金属膜。然而，由于多晶硅层在遮光层边缘爬坡位置有一定的倾斜角度(即坡度)，在准分子激光晶化(Excimer Laser Annealing，ELA)过程中容易造成多晶硅层的损伤，从而影响多晶硅层的电学特性，即遮光层边缘爬坡位置的倾斜角度过大会引起多晶硅层在遮光层边缘位置的导电性异常，通过减小遮光层边缘的倾斜角度可以明显改善低温多晶硅层在遮光层边缘爬坡处的导电特性，从而减少例如亮暗点等不良。但由于设备、制程能力的限制，无法更大限度地减小遮光层边缘的倾斜角度。
申请号CN201410837376.8专利文件提供了一种低温多晶硅薄膜晶体管中设置遮光层的技术方案，而并未提供改善有缘层(即多晶硅层)导电特性的技术方案。
因此，需要提出一种新的薄膜晶体管，使得多晶硅层在遮光层边缘爬坡的倾斜角度减小，从而改善多晶硅层的导电特性。
发明内容
针对上述问题，本发明提出了一种全新的遮光层图案，可突破制程和设备的限制，更高效地改善遮光层边缘爬坡位置的倾斜角度，从而改善了多晶硅层的导电特性，提高了产品良率。
本发明提供了一种薄膜晶体管，其中，包括遮光层和多晶硅层，所述遮光层设于所述多晶硅层之下；
俯视时所述遮光层与所述多晶硅层之间存在夹角，所述夹角为锐角或钝角。
如上所述的薄膜晶体管，其中，俯视时与所述多晶硅层的生长方向相平行的所述多晶硅层的边缘设为第一边，与所述多晶硅层相接触的所述遮光层的边缘设为第二边；
所述夹角是所述第一边与所述第二边之间的交角。
如上所述的薄膜晶体管，其中，所述第二边为锯齿状。
如上所述的薄膜晶体管，其中，俯视时所述遮光层为梯形。
如上所述的薄膜晶体管，其中，所述梯形的腰为所述第二边，所述梯形的上底和下底与所述第一边平行。
如上所述的薄膜晶体管，其中，俯视时所述遮光层为平行四边形。
如上所述的薄膜晶体管，其中，所述平行四边形的一边为所述第二边，与所述第二边相交的所述平行四边形的另一边与所述第一边平行。
如上所述的薄膜晶体管，其中，所述遮光层为金属膜。
本发明将遮光层边缘设计为锯齿状，或直接将俯视下的遮光层设计为梯形或平行四边形等形状，从而使得多晶硅层和遮光层之间不是垂直设置，而是存在一定的角度(为锐角或钝角)，从而减小了多晶硅层在遮光层边缘爬坡位置的倾斜角度，改善了多晶硅层的导电特性。
上述技术特征可以各种适合的方式组合或由等效的技术特征来替代，只要能够达到本发明的目的。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1示出了现有技术中多晶硅层与遮光层位置关系的立体图；
图2为现有技术中俯视时多晶硅层垂直于遮光层时的结构示意图；
图3示出了本发明中多晶硅层与遮光层位置关系的立体图；
图4为本发明中俯视时遮光层边缘为锯齿状时的结构示意图；
图5为本发明中俯视时遮光层为梯形时的结构示意图；
图6为本发明中俯视时遮光层为平行四边形时的结构示意图；
1-遮光层；
2-多晶硅层；
3-栅极；
4-源极。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例。
具体实施方式
下面将结合附图对本发明作进一步说明。
看图1和图3，图中多晶硅层2上标出的箭头方向表示多晶硅层2的生长方向(也可称为多晶硅层2的延伸方向)。在本发明中首先设定与多晶硅层2的生长方向相平行的边缘为第一边6，遮光层1上与多晶硅层2相接触的边缘为第二边7。
看图2中俯视视角下，现有技术中多晶硅层2与遮光层1相垂直，即第一边6与第二边7之间的夹角θ为90°。结合图1，此时遮光层1的制程使其边缘爬坡位置5的倾斜角为α，此处的倾斜角α可理解为主视视角下遮光层1的边缘爬坡位置5的坡度角。L为平行多晶硅层2的生长方向的爬坡长度，h为遮光层1的厚度，现有技术中多晶硅层2在边缘位置5的倾斜角α与L及h的三角函数关系为sin(α)＝h/L，即倾斜角α＝arcsin(h/L)。此时倾斜角较大，准分子激光晶化过程中容易引起多晶硅层2的损伤，从而导致多晶硅层2在遮光层1边缘爬坡位置5的导电性异常。
本发明为了解决上述现有技术中存在的问题，提供了一种薄膜晶体管，其中，包括遮光层1和多晶硅层2，遮光层1设在多晶硅层2之下，俯视时遮光层1与与多晶硅层2之间存在夹角θ，所述夹角θ为锐角或钝角。此时，避免使用现有技术中将遮光层1和多晶硅层2垂直设置的技术方案。而使二者之间在俯视视角下存在的夹角θ为锐角或钝角，即在图3中，第一边6和第二边7的交角θ为锐角或钝角。看图4，优选实施例中与第一边6相交的第二边7设为锯齿状。
看图5，优选实施例中俯视时遮光层1设为梯形。其中，梯形的腰为第二边，梯形的上底和下底与第一边相平行。
看图6，优选实施例中俯视时遮光层1设为平行四边形。其中，平行四边形的一边为第二边，与第二边相交的平行四边形的另一边与第一边平行。
按照本发明的技术方案，看图4、图5和图6，在俯视时当遮光层1与多晶硅层2垂直的第二边设计为锯齿状、将遮光层1设计为梯形或将遮光层1设计为平行四边形时，其主要目的是相同的，都是在多晶硅层2与遮光层1之间形成夹角θ，且θ不等于90°，为锐角或钝角，其中如此设计θ的原理如下：
看图3，相对于现有技术，此时多晶硅层2沿其生长方向的等效爬坡长度为L’＝L/sin(θ)，即第一边6的长度为L’，等效倾斜角为β，β与L’及h三者的三角函数关系为sin(β)＝h/L’＝sin(θ)×h/L＜sin(α)，即sin(β)＝sin(α)×sin(θ)，则等效倾斜角β＝arcsin(sin(α)×sin(θ))。因此，俯视时当遮光层1与多晶硅层2之间间为非垂直关系(即θ角为锐角或钝角)时，等效倾斜角β小于现有技术中的倾斜角α，即可以减小多晶硅层2在遮光层1边缘爬坡位置5处的爬坡倾斜度，从而改善多晶硅层2在此处的导电特性。
优选实施例中遮光层1为金属膜。
本发明通过合理设计遮光层1的形状，突破了工艺制程的限制，通过θ角的大小调节多晶硅层2相对于遮光层1的倾斜度，可在更大的范围内减小多晶硅层2在遮光层1的边缘爬坡位置5的倾斜度，达到改善多晶硅层2导电特性的效果。
虽然已经参考优选实施例对本发明进行了描述，但在不脱离本发明的范围的情况下，可以对其进行各种改进并且可以用等效物替换其中的部件。尤其是，只要不存在结构冲突，各个实施例中所提到的各项技术特征均可以任意方式组合起来。本发明并不局限于文中公开的特定实施例，而是包括落入权利要求的范围内的所有技术方案。

Claims (14)

  1. 一种薄膜晶体管，其中，包括遮光层和多晶硅层，所述遮光层设于所述多晶硅层之下；
    俯视时所述遮光层与所述多晶硅层之间存在夹角，所述夹角为锐角或钝角。
  2. 根据权利要求1所述的薄膜晶体管，其中，俯视时与所述多晶硅层的生长方向相平行的所述多晶硅层的边缘设为第一边，与所述多晶硅层相接触的所述遮光层的边缘设为第二边；
    所述夹角是所述第一边与所述第二边之间的交角。
  3. 根据权利要求2所述的薄膜晶体管，其中，所述遮光层为金属膜。
  4. 根据权利要求2所述的薄膜晶体管，其中，所述第二边为锯齿状。
  5. 根据权利要求4所述的薄膜晶体管，其中，所述遮光层为金属膜。
  6. 根据权利要求2所述的薄膜晶体管，其中，俯视时所述遮光层为梯形。
  7. 根据权利要求6所述的薄膜晶体管，其中，所述遮光层为金属膜。
  8. 根据权利要求6所述的薄膜晶体管，其中，所述梯形的腰为所述第二边，所述梯形的上底和下底与所述第一边平行。
  9. 根据权利要求2所述的薄膜晶体管，其中，俯视时所述遮光层为平行四边形。
  10. 根据权利要求9所述的薄膜晶体管，其中，所述遮光层为金属膜。
  11. 根据权利要求9所述的薄膜晶体管，其中，所述平行四边形的一边为所述第二边，与所述第二边相交的所述平行四边形的另一边与所述第一边平行。
  12. 根据权利要求1所述的薄膜晶体管，其中，所述遮光层为金属膜。
  13. 根据权利要求7所述的薄膜晶体管，其中，所述梯形的腰为所述第二边，所述梯形的上底和下底与所述第一边平行。
  14. 根据权利要求10所述的薄膜晶体管，其中，所述平行四边形的一边为所述第二边，与所述第二边相交的所述平行四边形的另一边与所述第一边平行。
PCT/CN2017/076083 2017-02-22 2017-03-09 一种薄膜晶体管 WO2018152871A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/522,841 US20180301532A1 (en) 2017-02-22 2017-03-09 Thin film trannsistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710096247.1A CN107046064B (zh) 2017-02-22 2017-02-22 一种薄膜晶体管
CN201710096247.1 2017-02-22

Publications (1)

Publication Number Publication Date
WO2018152871A1 true WO2018152871A1 (zh) 2018-08-30

Family

ID=59544473

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/076083 WO2018152871A1 (zh) 2017-02-22 2017-03-09 一种薄膜晶体管

Country Status (3)

Country Link
US (1) US20180301532A1 (zh)
CN (1) CN107046064B (zh)
WO (1) WO2018152871A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108198861A (zh) * 2017-12-28 2018-06-22 武汉华星光电技术有限公司 薄膜晶体管

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104102375A (zh) * 2013-04-11 2014-10-15 胜华科技股份有限公司 触控板
CN104538400A (zh) * 2014-12-16 2015-04-22 深圳市华星光电技术有限公司 一种ltps阵列基板
CN105093738A (zh) * 2015-07-29 2015-11-25 武汉华星光电技术有限公司 一种薄膜晶体管的控制电路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100671212B1 (ko) * 1999-12-31 2007-01-18 엘지.필립스 엘시디 주식회사 폴리실리콘 형성방법
US7550914B2 (en) * 2004-03-30 2009-06-23 Idemitsu Kosan Co., Ltd. Organic electroluminescence display device
CN104465673B (zh) * 2014-12-30 2018-02-23 京东方科技集团股份有限公司 阵列基板及其制造方法、以及显示装置
CN105932068A (zh) * 2016-06-30 2016-09-07 上海中航光电子有限公司 薄膜晶体管、显示面板及显示装置
CN106340249B (zh) * 2016-10-18 2020-02-21 昆山龙腾光电股份有限公司 异形显示面板及其像素结构

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104102375A (zh) * 2013-04-11 2014-10-15 胜华科技股份有限公司 触控板
CN104538400A (zh) * 2014-12-16 2015-04-22 深圳市华星光电技术有限公司 一种ltps阵列基板
CN105093738A (zh) * 2015-07-29 2015-11-25 武汉华星光电技术有限公司 一种薄膜晶体管的控制电路

Also Published As

Publication number Publication date
US20180301532A1 (en) 2018-10-18
CN107046064B (zh) 2020-01-03
CN107046064A (zh) 2017-08-15

Similar Documents

Publication Publication Date Title
KR102614464B1 (ko) 디스플레이 디바이스
US20170052418A1 (en) Array substrate, manufacturing method thereof, liquid crystal display panel and display device
CN108873422B (zh) 阵列基板、显示面板及其切割方法
KR102281848B1 (ko) 박막 트랜지스터 제조 방법과 박막 트랜지스터
TWI532154B (zh) 顯示面板及顯示裝置
US9923067B2 (en) Thin-film transistor and method for fabricating the same, array substrate and method for fabricating the same, and display device
TWI590423B (zh) 顯示裝置
US11177386B2 (en) Thin film transistor and display apparatus
KR101689462B1 (ko) 디스플레이 장치
KR101800888B1 (ko) 산화물 반도체를 포함한 박막 트랜지스터 기판
CN104733323A (zh) 一种低温多晶硅薄膜晶体管的制造方法
US20170040251A1 (en) Display substrate, manufacturing method thereof and display device
US9893165B2 (en) Method for manufacturing array substrate and manufacturing device
WO2017121073A1 (zh) Tft基板的制作方法
CN106611764B (zh) 显示设备
WO2018152871A1 (zh) 一种薄膜晶体管
KR20160043576A (ko) 액정 표시 장치 및 그 제조 방법
US9590055B2 (en) Thin film transistor, method for manufacturing the same, array substrate, and display device
WO2016029542A1 (zh) 阵列基板及显示装置
US9735278B2 (en) Array substrate, display panel and method of manufacturing thin film transistor
CN105140291B (zh) 薄膜晶体管及其制作方法、阵列基板以及显示装置
US9893205B2 (en) Thin film transistor, array substrate and liquid crystal display panel
CN108538853B (zh) 显示装置及其阵列基板
CN108663862B (zh) 显示面板
WO2016106805A1 (zh) 一种薄膜晶体管、陈列基板及显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15522841

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17897975

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17897975

Country of ref document: EP

Kind code of ref document: A1