WO2018152719A1 - 方波产生方法及方波产生电路 - Google Patents

方波产生方法及方波产生电路 Download PDF

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Publication number
WO2018152719A1
WO2018152719A1 PCT/CN2017/074531 CN2017074531W WO2018152719A1 WO 2018152719 A1 WO2018152719 A1 WO 2018152719A1 CN 2017074531 W CN2017074531 W CN 2017074531W WO 2018152719 A1 WO2018152719 A1 WO 2018152719A1
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WO
WIPO (PCT)
Prior art keywords
voltage
square wave
generating circuit
wave generating
signal
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Application number
PCT/CN2017/074531
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English (en)
French (fr)
Inventor
杨富强
杨孟达
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN202210406670.8A priority Critical patent/CN114826217B/zh
Priority to EP17898203.9A priority patent/EP3425799A4/en
Priority to PCT/CN2017/074531 priority patent/WO2018152719A1/zh
Priority to CN201780000254.5A priority patent/CN108781071B/zh
Publication of WO2018152719A1 publication Critical patent/WO2018152719A1/zh
Priority to US16/154,736 priority patent/US10622985B2/en
Priority to US16/812,349 priority patent/US10979040B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/64—Generators producing trains of pulses, i.e. finite sequences of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/02—Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform

Definitions

  • the present application relates to a square wave generating method and a square wave generating circuit, and more particularly to a square wave generating method and a square wave generating circuit capable of generating a high voltage amplitude square wave and manufacturing in a low voltage process.
  • a square wave signal with a high voltage amplitude may be required.
  • a high voltage semiconductor process is required to produce a semiconductor component having a high withstand voltage.
  • the production cost of the high voltage semiconductor process is high, and the production cost required for the electronic product to which the foregoing circuit system is applied is increased.
  • a main object of some embodiments of the present invention is to provide a square wave generating method and a square wave generating circuit which can produce a square wave having a high voltage amplitude and are manufactured in a low voltage process.
  • the present application provides a square wave generating method for applying a square wave generating circuit for generating a type of square wave signal, wherein the square wave generating circuit has a specific breakdown voltage (Breakdown Voltage).
  • the square wave generating method includes: in a first time interval, the square wave generating circuit generates the square wave signal as a first voltage; and in a second time interval, the square wave generating circuit generates the The square wave signal is a second voltage; and in the first time interval and the a transient interval between the second time intervals, the square wave generating circuit generates the square wave signal as a transient voltage, wherein the transient voltage is between the first voltage and the second voltage And a first voltage difference between the first voltage and the second voltage is greater than the specific withstand voltage.
  • a second voltage difference between the first voltage and the transient voltage is the specific withstand voltage.
  • a third voltage difference between the transient voltage and the second voltage is the specific withstand voltage.
  • the first voltage difference between the first voltage and the second voltage is twice the specific withstand voltage.
  • the transient voltage is a ground voltage.
  • the present application further provides a square wave generating circuit for generating a type of square wave signal, wherein the square wave generating circuit has a specific breakdown voltage, wherein the square wave generating circuit includes a The output end is configured to output the square wave signal; a first signal generating circuit is configured to generate a first voltage in a first time interval; and a second signal generating circuit is used in a second time interval a second voltage is generated; a first switch having one end coupled to the first signal generating circuit and the other end coupled to the output end; and a second switch coupled to the second end a signal generating circuit, the other end of which is coupled to the output end; wherein the first signal generating circuit and the second signal generating circuit generate a transient voltage in a transient interval, where the transient interval is located Between the first time interval and the second time interval; wherein, in the first time interval, the first switch is conductive, and the square wave-like signal is the first voltage; In the second time interval, The second switch is turned on, and the square wave signal is the
  • the first switch is controlled by a first control signal, in the transient section, the first switch is turned on, and the first switch is from the first signal.
  • a generating circuit passes the transient voltage to the output.
  • the second switch is controlled by a second control signal, in the transient section, the second switch is turned on, and the second switch is from the second signal A generating circuit passes the transient voltage to the output.
  • the first switch is a first MOS transistor, and a base of the first MOS transistor is coupled to a source of the first MOS transistor.
  • the first MOS transistor is a P-type MOS transistor
  • the second switch is a second MOS transistor
  • a base of the second MOS transistor is coupled to the second gold oxide A source of the half transistor
  • the second MOS transistor is an N-type MOS transistor.
  • a gate of the first MOS transistor receives a first control signal, and a gate of the second MOS transistor is coupled to a ground.
  • a gate of the second MOS transistor receives a second control signal, and a gate of the first MOS transistor is coupled to a ground.
  • the first signal generating circuit generates a first output signal, an output high level of the first output signal is a positive voltage, and an output low level of the first inverter is one Ground voltage.
  • the first signal generating circuit includes a first inverter, an output high level of the first inverter is the positive voltage, and an output of the first inverter The low level is the ground voltage.
  • the first signal generating circuit generates the first voltage as the positive voltage in the first time interval, and generates the transient voltage in the transient interval as the Ground voltage.
  • the second signal generating circuit generates a second output signal, an output high level of the second output signal is a ground voltage, and an output low level of the second inverter is one Negative voltage.
  • the second signal generating circuit includes a second inverter, an output high level of the second inverter is the ground voltage, and an output of the second inverter The low level is the negative voltage.
  • the second signal generating circuit generates the second voltage as the negative voltage in the second time interval.
  • the square wave generating circuit further includes a first protection unit and a second protection unit, the first protection unit is coupled between the first signal generation circuit and the first switch The second protection unit is coupled between the second signal generating circuit and the second switch.
  • the first protection unit includes a first N-type transistor and a first P-type transistor, the first N-type transistor and the first P-type transistor are connected to each other, and the second protection The unit includes a second N-type transistor and a second P-type transistor, and the second N-type transistor and the second P-type transistor are connected to each other.
  • a gate of the first N-type transistor receives a positive voltage
  • a gate of the first P-type transistor and a gate of the second N-type transistor are coupled to a ground.
  • a gate of the second P-type transistor receives a negative voltage.
  • the square wave generating circuit converts from a high voltage to a low voltage (or a low voltage turn)
  • the transient interval output transient voltage between the high voltage and the high voltage can output a square wave signal with a high voltage amplitude, and the manufacturing process can be completed only by using a low pressure process lower than the high voltage amplitude, which has the advantage of low production cost.
  • FIG. 1 is a schematic diagram of a square wave generating circuit according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a square wave-like signal according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a square wave generating circuit according to an embodiment of the present application.
  • FIG. 4 is a waveform diagram of a plurality of signals in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a square wave generation process according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a square wave generating circuit according to another embodiment of the present application.
  • FIG. 7 is a schematic diagram of a square wave generating circuit according to still another embodiment of the present application.
  • Fig. 8 is a waveform diagram of a plurality of signals corresponding to the square wave generating circuit of the embodiment shown in Fig. 7.
  • FIG. 9 is a schematic diagram of a square wave generating circuit according to another embodiment of the present application.
  • FIG. 10 is a schematic diagram of a square wave generating circuit according to still another embodiment of the present application.
  • FIG. 1 is a schematic diagram of a square wave generating circuit 10 according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of a class of square wave signal SSG. 2, the square wave signal SSG type having a high voltage V1 during a time interval T1 in; having a low voltage V2 T2 time interval at a time; having a transient voltage V tran in a transient time interval T tran
  • the transient voltage V tran is smaller than the high voltage V1 and greater than the low voltage V2, and the high voltage V1 and the low voltage V2 have a voltage difference ⁇ V 1,2 ;
  • the high voltage V1 and the transient voltage V tran have a voltage difference ⁇ V 1, Tran ;
  • the transient voltage V tran has a voltage difference ⁇ V 2, tran with the low voltage V2
  • the transient interval T tran is located between the time interval T1 and the time interval T2.
  • the square wave signal SSG can be approximated as a square wave signal, so it is called a square wave signal.
  • the square wave generating circuit 10 is a circuit produced by a specific process having a specific breakdown voltage BV, in other words, when the voltage across the square wave generating circuit 10 exceeds a specific withstand voltage BV, The semiconductor element inside the square wave generating circuit 10 will be broken down, causing the square wave generating circuit 10 to be damaged. Under the premise that the square wave generating circuit 10 has a specific withstand voltage BV, the square wave generating circuit 10 can generate a square wave type signal SSG whose voltage difference ⁇ V 1,2 is larger than a specific withstand voltage BV.
  • the square wave generating circuit 10 includes an output terminal No, signal generating circuits 12 and 14 and switches S1 and S2.
  • the output terminal No is used to output a square wave-like signal SSG, and the signal generating circuit 12 is used.
  • the time interval T1 to generate a high voltage V1
  • the switch S1 and the switch S2 are respectively coupled between the signal generating circuit 12 and the output terminal No and between the signal generating circuit 14 and the output terminal No.
  • the switch S1 can be in the time interval T1 and the transient interval T tran The middle is Conducted and is turned off in the time interval T2.
  • the switch S2 is open in the time interval T1 and the transient interval T tran and is turned on in the time interval T2. In this way, available at the output terminal No time interval T1, the output square wave signal SSG class high voltage V1, in the transient interval T tran class output square wave signal SSG of transient voltage V tran, and in the time interval T2,
  • the output type square wave signal SSG is a low voltage V2.
  • the square wave generating circuit 10 outputs the transient voltage V tran using the transient interval T tran from the high voltage transition V1 to the low voltage V2 (or between the low voltage V2 and the high voltage V1) to avoid the square.
  • the instantaneous voltage across the wave generating circuit 10 exceeds a specific withstand voltage BV. In this way, even in the case where the voltage difference ⁇ V 1,2 between the high voltage V1 and the low voltage V2 of the square wave signal SSG is greater than the specific withstand voltage BV, the square wave generating circuit 10 can still operate normally, without causing Breakdown and damage.
  • the voltage difference ⁇ V 1, tran between the high voltage V1 and the transient voltage V tran may be a voltage VDD
  • the voltage difference ⁇ V 2 between the transient voltage V tran and the low voltage V2 may be tran It is the voltage VDD
  • the voltage difference ⁇ V 1,2 between the high voltage V1 and the low voltage V2 can reach twice the voltage VDD.
  • a voltage difference ⁇ V between the high voltage V1 and the transient voltage V tran 1, tran can ⁇ V is the voltage difference between a specific breakdown voltage BV, transient voltage V tran embodiment and the low voltage V2 2, tran can also be a specific withstand voltage BV, and the voltage difference ⁇ V 1,2 between the high voltage V1 and the low voltage V2 can reach twice the specific withstand voltage BV.
  • FIG. 3 is a schematic diagram of a square wave generating circuit 30 according to an embodiment of the present application.
  • the square wave generating circuit 30 includes an output terminal No, signal generating circuits 32, 34, 36, switches S13, S23 and a digital control module 38.
  • the signal generating circuits 32, 34 are respectively used to implement the signal generating circuit 12 of FIG. 14.
  • the switches S13 and S23 are respectively used to implement the switches S1 and S2 in FIG. 1, and the signal generating circuit 36 can generate a control signal ctrl to control the conduction state of the switch S13.
  • the signal generating circuit 32 includes a level shifter 320 and an inverter 322.
  • the signal generating circuit 34 includes a level shifter 340 and an inverter 342.
  • the signal generating circuit 36 includes a The level shifter 360 and an inverter 362.
  • An output level of the inverter 322 is between a positive voltage AVDD and a ground voltage GND (the inverter 322 operates between the positive voltage AVDD and the ground voltage GND), and the output levels of the inverters 342, 362 are located.
  • the ground voltage GND is between a negative voltage -AVDD (the inverters 342, 362 operate between the ground voltage GND and the negative voltage -AVDD).
  • an output signal Vo 2 outputted by the inverter 322 has an output high level being a positive voltage AVDD, and the output signal Vo 2 has an output low level as a ground voltage GND; the output of the inverter 342 An output signal Vo 4 has an output high level as the ground voltage GND, the output signal Vo 4 has an output low level as a negative voltage -AVDD; and the control signal ctrl outputted by the inverter 362 has an output high level as the ground.
  • the voltage GND, the control signal ctrl has an output low level to a negative voltage -AVDD.
  • the digital control module 38 generates digital signals d 2 , d 4 , d 6 for controlling the inverters 322, 342, 362, respectively, and the level shifters 340, 342, 346 are used to output the digital control module 38.
  • the digital signal is converted to an input high level of the control inverters 322, 342, 362 (the potential can also be referred to as a level) or an input low level.
  • the square wave generating circuit 30 can be produced by a low voltage process, wherein the low voltage process refers to a semiconductor device process in which the withstand voltage BV is lower than the square wave amplitude.
  • the withstand voltage BV may be slightly higher than the voltage AVDD.
  • the switch S13 can be a Metal-Oxide-Semiconductor Field-Effect Transistor, and the switch S23 can be an N-type MOS transistor, the switch S13 and the base of the switch S23 (Bulk)
  • the source of the switch S13 is coupled to the output of the inverter 322, and the source of the switch S23 is coupled to the output of the inverter 342 to receive an output.
  • the signal Vo 2 and an output signal Vo 4 , the switch S13 and the drain of the switch S23 are all coupled to the output terminal No.
  • a gate of the switch S13 is coupled to an output of the inverter 362 to receive a control signal ctrl, and a gate of the switch S23 receives a ground voltage GND.
  • FIG. 4 is a waveform diagram of the output signals Vo 2 , Vo 4 and the control signal ctrl generated by the square wave generating circuit 30.
  • the square wave generating circuit 30 In the time interval T1, the high voltage V1 can be output as a positive voltage AVDD.
  • the signal Vo 2 is the ground voltage GND
  • the output signal Vo 4 of the inverter 342 is still the ground voltage GND
  • the inverter 362 outputs the control signal ctrl to the negative voltage -AVDD
  • the switch S13 is still on
  • the switch S23 is still open.
  • the square wave generating circuit 30 can output the transient voltage V tran to the ground voltage GND in the transient interval T tran .
  • the signal Vo 2 is the ground voltage GND
  • the inverter 342 outputs the output signal Vo 4 as the negative voltage -AVDD
  • the inverter 362 outputs the control signal ctrl to the ground voltage GND
  • the switch S13 is open and the switch S23 is turned on, therefore,
  • the wave generating circuit 30 can output the low voltage V2 to a negative voltage -AVDD in the time interval T2.
  • the square wave generating circuit 30 can generate a type of square wave signal SSG4 as shown in FIG.
  • the voltage difference ⁇ V 1, tran between the high voltage V1 (positive voltage AVDD) of the square wave signal SSG4 and the transient voltage V tran (ground voltage GND) can be the voltage AVDD
  • the transient voltage V tran The voltage difference ⁇ V 2 between the ground voltage GND) and the low voltage V2 (negative voltage -AVDD) , tran is also the voltage AVDD
  • the voltage difference ⁇ V 1,2 between the high voltage V1 and the low voltage V2 can reach the voltage AVDD 2 times larger than the specific withstand voltage BV.
  • the square wave generating circuit 30 converts the output voltage of the square wave generating circuit 30 at the output terminal No from the high voltage V1 to the transient voltage V tran by using the transient interval T tran between the time interval T1 and the time interval T2. Then, the transient voltage V tran is switched to the low voltage V2 (or is converted from the low voltage V2 to the transient voltage V tran and then converted to the high voltage V1 by the transient voltage V tran ).
  • the square wave generating circuit 30 can generate the square wave signal SSG4 having an amplitude of 2*AVDD without causing the square wave to be generated.
  • the semiconductor elements inside the circuit 30 are damaged by breakdown.
  • FIG. 5 is a schematic diagram of a square wave generation process 50 according to an embodiment of the present application.
  • the square wave generation process 50 can be performed by the square wave generation circuit 10 of FIG. 1, which includes the following steps:
  • Step 500 In the time interval T1, the square wave generating circuit 10 generates the square wave signal SSG to be the high voltage V1.
  • Step 502 The square wave generating circuit 10 generates the square wave-like signal SSG to be a low voltage V2 during the time interval T2.
  • Step 504 In the transient interval T tran between the time interval T1 and the time interval T2, the square wave generating circuit 10 generates the class-like wave signal SSG as the transient voltage V tran , wherein the transient voltage V tran is between the high voltage Between V1 and low voltage V2.
  • the square wave generating circuit of the present application can be manufactured by using a low voltage semiconductor process, and can output a square wave signal of a high amplitude.
  • the square wave generating circuit of the present application can be manufactured using a low voltage process with a withstand voltage BV of 5 volts, and the output amplitude is greater than 5 volts (example) Such as: 10 volts square wave signal.
  • a circuit system when a circuit system requires a square wave signal with a high voltage (such as 10 volts) amplitude, its square wave generation circuit can avoid the high production cost caused by the high voltage semiconductor process, and use a low voltage semiconductor process (for example, The low-voltage semiconductor process with a withstand voltage BV of 5 volts is manufactured, so that the production cost of the overall circuit system can be reduced, and the same performance can be achieved.
  • a high voltage such as 10 volts
  • a low voltage semiconductor process for example, The low-voltage semiconductor process with a withstand voltage BV of 5 volts is manufactured, so that the production cost of the overall circuit system can be reduced, and the same performance can be achieved.
  • FIG. 6 is a schematic diagram of a square wave generating circuit 60 according to another embodiment of the present application.
  • the square wave generating circuit 60 is similar to the square wave generating circuit 30, so the same components follow the same symbols.
  • the square wave generating circuit 60 further includes protection units SP2 and SP4.
  • the protection unit SP2 is coupled between the inverter 322 and the switch S13.
  • the protection unit SP2 includes a P-type MOS transistor.
  • the SP4 is coupled between the inverter 342 and the switch S23.
  • the protection unit SP4 includes a P-type MOS transistor Q P4 and an N-type MOS transistor Q N4 .
  • the transistor Q N4 and the transistor Q P4 are connected to each other, and the transistor is connected.
  • the gate of Q N4 receives the ground voltage GND, and the gate of transistor Q P4 receives the negative voltage -AVDD.
  • the protection units SP2, SP4 can be used to protect the switches S13, S23 to avoid burnout of the switches S13, S23.
  • FIG. 7 is a schematic diagram of a square wave generating circuit 70 according to an embodiment of the present application
  • FIG. 8 is an output signal Vo 2 , Vo 4 and a control signal ctrl generated by the square wave generating circuit 70.
  • the square wave generating circuit 70 is similar to the square wave generating circuit 30, so the same components follow the same symbols.
  • the gate of the switch S13 (which is a P-type MOS transistor) in the square wave generating circuit 70 receives the ground voltage GND
  • the switch S23 in the square wave generating circuit 70 (which is the N type)
  • the gate of the MOS transistor receives the control signal ctrl'.
  • the control signal ctrl' is generated by a signal generating circuit 76.
  • the signal generating circuit 76 includes an inverter 762 whose output level is at a positive voltage AVDD. Between the ground voltage GND and the ground.
  • the operation of the square wave generating circuit 70 is similar to that of the square wave generating circuit 30, and is described below.
  • the inverter 762 outputs the control signal ctrl to the ground voltage GND, the switch S13 is turned on, and the switch S23 is turned off. Therefore, the square wave generating circuit 70 can output a type of square wave signal SSG7 in the time interval T1. Positive voltage AVDD.
  • the inverter 322 In the transient interval T tran , the inverter 322 outputs the output signal Vo 2 to the ground voltage GND, the switch S13 is open, the inverter 362 outputs the control signal ctrl to the positive voltage AVDD, and the switch S23 is turned on, the square wave generating circuit 70 in the transient interval T tran can output the square wave signal SSG7 as the ground voltage GND.
  • the inverter 322 outputs the output signal Vo 2 as the ground voltage GND, the switch S13 is still open, the inverter 762 outputs the control signal ctrl to the ground voltage GND, and the switch S23 is still turned on, the square wave
  • the generating circuit 70 can output the square wave signal SSG7 to a negative voltage -AVDD in the transient interval T tran .
  • FIG. 9 is a schematic diagram of a square wave generating circuit 90 according to an embodiment of the present application.
  • the square wave generating circuit 90 is similar to the square wave generating circuits 30 and 70, so the same components follow the same symbols.
  • the square wave generating circuit 90 includes signal generating circuits 96, 98, which are used to generate control signals ctrl_P and ctrl_N, respectively, to control the conductance of the switches S13 and S23, respectively. Pass state.
  • the voltage range of the control signal ctrl_P is between the ground voltage GND and the negative voltage -AVDD
  • the voltage range of the control signal ctrl_N is between the positive voltage AVDD and the ground voltage GND.
  • the operation of the square wave generating circuit 90 is similar to that of the square wave generating circuits 30, 70, so This will not be repeated here.
  • FIG. 10 is a schematic diagram of a square wave generating circuit A0 according to an embodiment of the present application.
  • the square wave generating circuit A0 is similar to the square wave generating circuit 90, so the same components follow the same symbols.
  • the square wave generating circuit A0 includes only the signal generating circuit 98 to control the on state of the switch S23, and the gate of the switch S13 receives the ground voltage GND.
  • the operation of the square wave generating circuit A0 is similar to that of the square wave generating circuit 90, and thus will not be described again.
  • the voltage difference ⁇ V 1, tran between the high voltage V1 and the transient voltage V tran is not limited to a specific withstand voltage BV, and the voltage difference ⁇ V 1 tran between the high voltage V1 and the transient voltage V tran may be less than a specific resistance
  • the voltage difference ⁇ V 2, tran between the transient voltage V tran and the low voltage V2 may be less than the specific withstand voltage BV as long as the voltage difference ⁇ V 1,2- between the high voltage V1 and the low voltage V2 It is larger than the specific withstand voltage BV of the square wave generating circuit 10, that is, it satisfies the requirements of the present application.
  • the signal generating circuit is not limited to using the inverter to generate the high voltage V1, the transient voltage V tran and the low voltage V2, and the signal generating circuit can also use the buffer to generate the high voltage V1 and the transient voltage V tran and The low voltage V2, in which the buffer can comprise two inverters connected to each other, is also within the scope of the present application.
  • the output signal of the square wave generating circuit of the present application is inserted between the high voltage to the low voltage (or between the low voltage and the high voltage) to be inserted into the transient interval and output the transient voltage.
  • the square wave generating circuit can output a square wave signal similar to a square wave and having a high voltage amplitude, and can be manufactured only by using a low voltage process lower than the high voltage amplitude, thereby saving production cost.

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Abstract

一种方波产生方法，应用于一方波产生电路，用来产生一类方波信号，其中所述方波产生电路具有一耐压，所述方波产生方法包含有于一第一时间区间中，所述方波产生电路产生所述类方波信号为一第一电压；于一第二时间区间中，所述方波产生电路产生所述类方波信号为一第二电压；以及于所述第一时间区间与所述第二时间区间之间的一暂态区间中，所述方波产生电路产生所述类方波信号为一暂态电压，其中所述暂态电压介于所述第一电压与所述第二电压之间；其中，所述第一电压与所述第二电压之间的一第一电压差大于所述耐压。

Description

方波产生方法及方波产生电路 技术领域
本申请涉及一种方波产生方法及方波产生电路，尤其涉及一种可产生具有高压振幅方波且以低压制程制造的方波产生方法及方波产生电路。
背景技术
对特定电路系统来说，可能会需要具有高压振幅的方波信号，为了产生高压振幅的方波信号，需利用一高压半导体制程来生产具有高耐压的半导体元件。然而，高压半导体制程的生产成本较高，而导致应用前述电路系统的电子产品所需的生产成本增加。
因此，如何利用低压制程生产制造的半导体元件来产生高压振幅方波，即为业界所努力的目标之一。
发明内容
因此，本发明部分实施例主要目的即在于提供一种可产生具有高压振幅方波且以低压制程制造的方波产生方法及方波产生电路。
为了解决上述技术问题，本申请提供了一种方波产生方法，应用于一方波产生电路，用来产生一类方波信号，其中所述方波产生电路具有一特定耐压(Breakdown Voltage)，所述方波产生方法包括：在一第一时间区间，所述方波产生电路产生所述类方波信号为一第一电压；在一第二时间区间，所述方波产生电路产生所述类方波信号为一第二电压；以及于所述第一时间区间与所述 第二时间区间之间的一暂态区间，所述方波产生电路产生所述类方波信号为一暂态电压，其中所述暂态电压介于所述第一电压与所述第二电压之间；其中，所述第一电压与所述第二电压之间的一第一电压差大于所述特定耐压。
一种实施例中，所述第一电压与所述暂态电压之间的一第二电压差为所述特定耐压。
一种实施例中，所述暂态电压与所述第二电压之间的一第三电压差为所述特定耐压。
一种实施例中，所述第一电压与所述第二电压之间的所述第一电压差为所述特定耐压的2倍。
一种实施例中，所述暂态电压为一接地电压。
本申请另提供了一种方波产生电路，用来产生一类方波信号，其中所述方波产生电路具有一特定耐压(Breakdown Voltage)，其特征在于，所述方波产生电路包含有一输出端，用来输出所述类方波信号；一第一信号产生电路，用来于一第一时间区间中产生一第一电压；一第二信号产生电路，用来于一第二时间区间中产生一第二电压；一第一开关，其一端耦接于所述第一信号产生电路，另一端耦接于所述输出端；以及一第二开关，其一端耦接于所述第二信号产生电路，另一端耦接于所述输出端；其中，所述第一信号产生电路及所述第二信号产生电路于一暂态区间中产生一暂态电压，所述暂态区间位于所述第一时间区间与所述第二时间区间之间；其中，于所述第一时间区间中，所述第一开关为导通，所述类方波信号为所述第一电压；于所述第二时间区间中，所述第二开关为导通，所述类方波信号为所述第二电压，于所述暂态区间中，所述第一开关或所述第二开关为导通；其中，所述第一电压与所述第二电压之间 的一第一电压差大于所述特定耐压。
一种实施例中，所述第一开关受控于一第一控制信号，于所述于所述暂态区间中，所述第一开关导通，所述第一开关自所述第一信号产生电路将所述暂态电压传递至所述输出端。
一种实施例中，所述第二开关受控于一第二控制信号，于所述于所述暂态区间中，所述第二开关导通，所述第二开关自所述第二信号产生电路将所述暂态电压传递至所述输出端。
一种实施例中，所述第一开关为一第一金氧半晶体管，所述第一金氧半晶体管的一基极耦接于所述第一金氧半晶体管的一源极，所述第一金氧半晶体管为一P型金氧半晶体管，所述第二开关为一第二金氧半晶体管，所述第二金氧半晶体管的一基极耦接于所述第二金氧半晶体管的一源极，所述第二金氧半晶体管为一N型金氧半晶体管。
一种实施例中，所述第一金氧半晶体管的的一栅极接收一第一控制信号，所述第二金氧半晶体管的一栅极耦接于一接地端。
一种实施例中，所述第二金氧半晶体管的的一栅极接收一第二控制信号，所述第一金氧半晶体管的一栅极耦接于一接地端。
一种实施例中，所述第一信号产生电路产生一第一输出信号，第一输出信号的一输出高电平为一正电压，所述第一反相器的一输出低电平为一接地电压。
一种实施例中，所述第一信号产生电路包含一第一反相器，所述第一反相器的一输出高电平为所述正电压，所述第一反相器的一输出低电平为所述接地电压。
一种实施例中，所述第一信号产生电路于所述第一时间区间中产生所述第一电压为所述正电压，并于所述暂态区间中产生所述暂态电压为所述接地电压。
一种实施例中，所述第二信号产生电路产生一第二输出信号，第二输出信号的一输出高电平为一接地电压，所述第二反相器的一输出低电平为一负电压。
一种实施例中，所述第二信号产生电路包含一第二反相器，所述第二反相器的一输出高电平为所述接地电压，所述第二反相器的一输出低电平为所述负电压。
一种实施例中，所述第二信号产生电路于所述第二时间区间中产生所述第二电压为所述负电压。
一种实施例中，所述方波产生电路另包含一第一保护单元以及一第二保护单元，所述第一保护单元耦接于所述第一信号产生电路与所述第一开关之间，所述第二保护单元耦接于所述第二信号产生电路与所述第二开关之间。
一种实施例中，所述第一保护单元包含一第一N型晶体管以及一第一P型晶体管，所述第一N型晶体管与所述第一P型晶体管相互连接，所述第二保护单元包含一第二N型晶体管以及一第二P型晶体管，所述第二N型晶体管与所述第二P型晶体管相互连接。
一种实施例中，所述第一N型晶体管的一栅极接收一正电压，所述第一P型晶体管的一栅极以及所述第二N型晶体管的一栅极耦接于一接地端，所述第二P型晶体管的一栅极接收一负电压。
本申请提供的方波产生电路于由高电压转换至低电压之间(或低电压转 换至高电压之间)的暂态区间输出暂态电压，其可输出具有高压振幅的类方波信号，而仅利用低于高压振幅的低压制程即可完成生产制造，具有低生产成本的优点。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为本申请实施例一种方波产生电路的示意图。
图2为本申请实施例的类方波信号的示意图。
图3为本申请实施例的一种方波产生电路的示意图。
图4为本申请实施例多个信号的波形图。
图5为本申请实施例的方波产生流程的示意图。
图6为本申请另一实施例的方波产生电路的示意图。
图7为本申请又一种实施例的方波产生电路的示意图。
图8为图7所示实施例的方波产生电路对应的多个信号的波形图。
图9为本申请另一实施例的方波产生电路的示意图。
图10为本申请又一实施例的方波产生电路的示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施 例仅仅用以解释本申请，并不用于限定本申请。
请参考图1及图2，图1为本申请实施例一方波产生电路10的示意图，图2为一类方波信号SSG的示意图。如图2所示，类方波信号SSG于一时间区间T1时具有一高电压V1；于一时间区间T2时具有一低电压V2；于一暂态区间Ttran时具有一暂态电压Vtran，其中，暂态电压Vtran小于高电压V1且大于低电压V2，高电压V1与低电压V2具有一电压差ΔV1,2；高电压V1与暂态电压Vtran具有一电压差ΔV1,tran；暂态电压Vtran与低电压V2具有一电压差ΔV2,tran，另外，暂态区间Ttran位于时间区间T1与时间区间T2之间。当暂态区间Ttran相对于时间区间T1或时间区间T2为很小时(例如，当Ttran<T1*(1/100)或Ttran<T2*(1/100)时)，类方波信号SSG可近似为一方波信号，故称之为类方波信号。另一方面，方波产生电路10为利用一特定制程所生产的电路，其具有一特定耐压(Breakdown Voltage)BV，换句话说，当方波产生电路10的跨压超过特定耐压BV时，将导致方波产生电路10内部的半导体元件击穿/崩溃(Breakdown)，而导致方波产生电路10损坏。在方波产生电路10具有特定耐压BV的前提之下，方波产生电路10可产生电压差ΔV1,2大于特定耐压BV的类方波信号SSG。
另一方面，如图1所示，方波产生电路10包含一输出端No、信号产生电路12、14以及开关S1、S2，输出端No用来输出类方波信号SSG，信号产生电路12用来于时间区间T1中产生高电压V1，并于暂态区间Ttran中产生暂态电压Vtran，而信号产生电路12用来时间区间T2中产生低电压V2。开关S1以及开关S2分别耦接于信号产生电路12与输出端No之间以及信号产生电路14与输出端No之间，于一实施例中，开关S1可于时间区间T1以及暂态区间Ttran中为导通(Conducted)，并于时间区间T2为断路(Cutoff)；另外，开关S2 可于时间区间T1以及暂态区间Ttran中为断路，并于时间区间T2为导通。如此一来，输出端No可于时间区间T1中输出类方波信号SSG为高电压V1，于暂态区间Ttran中输出类方波信号SSG为暂态电压Vtran，并于时间区间T2中输出类方波信号SSG为低电压V2。也就是说，方波产生电路10利用由高电压转V1换至低电压V2之间(或低电压V2转换至高电压V1之间)之暂态区间Ttran输出暂态电压Vtran，以避免方波产生电路10的瞬间跨压超过特定耐压BV。如此一来，即使在类方波信号SSG的高电压V1与低电压V2之间的电压差ΔV1,2大于特定耐压BV的情况下，方波产生电路10仍可正常操作，不会因击穿而损坏。
于一实施例中，高电压V1与暂态电压Vtran之间的电压差ΔV1,tran可为一电压VDD，暂态电压Vtran与低电压V2之间的电压差ΔV2,tran亦可为电压VDD，而高电压V1与低电压V2之间的电压差ΔV1,2可达到电压VDD的2倍。更进一步地，于一实施例中，高电压V1与暂态电压Vtran之间的电压差ΔV1,tran可为特定耐压BV，暂态电压Vtran与低电压V2之间的电压差ΔV2,tran亦可为特定耐压BV，而高电压V1与低电压V2之间的电压差ΔV1,2可达到特定耐压BV的2倍。
关于方波产生电路10的具体电路，请参考图3，图3为本申请实施例一方波产生电路30的示意图。方波产生电路30包含有输出端No、信号产生电路32、34、36、开关S13、S23以及一数字控制模块38，信号产生电路32、34分别用来实现图1中的信号产生电路12、14，开关S13、S23分别用来实现图1中的开关S1、S2，信号产生电路36可产生一控制信号ctrl以控制开关S13的导通状态。详细来说，信号产生电路32包含一电平移位器(Level Shifter)320以及一反相器322，信号产生电路34包含一电平移位器340以及一反相器342，信号产生电路36包含一电平移位器360以及一反相器362。反相器322 的一输出电平位于一正电压AVDD与一接地电压GND之间(反相器322操作于正电压AVDD与接地电压GND之间)，反相器342、362的输出电平位于接地电压GND与一负电压－AVDD之间(反相器342、362操作于接地电压GND与负电压－AVDD之间)。换句话说，反相器322所输出的一输出信号Vo2具有一输出高电平为正电压AVDD，而输出信号Vo2具有一输出低电平为接地电压GND；反相器342所输出的一输出信号Vo4具有一输出高电平为接地电压GND，输出信号Vo4具有一输出低电平为负电压－AVDD；反相器362所输出的控制信号ctrl具有一输出高电平为接地电压GND，控制信号ctrl具有一输出低电平为负电压－AVDD。另外，数字控制模块38产生数字信号d2、d4、d6，分别用来控制反相器322、342、362，电平移位器340、342、346用来将数字控制模块38所输出的数字信号转换至控制反相器322、342、362的输入高电平(文中电位也可以称为电平)或输入低电平。另外，方波产生电路30可利用一低压制程所生产，其中低压制程是指其生产制造出的耐压BV低于方波振幅的半导体元件制程。另外，耐压BV可略高于电压AVDD。
另外，开关S13可为一P型金氧半晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor)，而开关S23可为一N型金氧半晶体管，开关S13以及开关S23的基极(Bulk)皆耦接于其源极(Source)，开关S13的源极耦接于反相器322的输出端，开关S23的源极耦接于反相器反相器342的输出端，以分别接收一输出信号Vo2以及一输出信号Vo4，开关S13以及开关S23的漏极(Drain)皆耦接于输出端No。另外，开关S13的栅极(Gate)耦接于反相器362的输出端以接收控制信号ctrl，开关S23的栅极接收接地电压GND。
方波产生电路30的运作叙述如下。请参考图4，图4为方波产生电路30所产生的输出信号Vo2、Vo4以及控制信号ctrl的波形图。于时间区间T1中，数字控制模块38产生数字信号d2、d4、d6分别为0、0、0(即d2d4d6＝000)，反相器322输出输出信号Vo2为正电压AVDD，反相器342输出输出信号Vo4为接地电压GND，反相器362输出控制信号ctrl为接地电压GND，开关S13为导通且开关S23为断路，因此，方波产生电路30于时间区间T1中可输出高电压V1为正电压AVDD。另外，于暂态区间Ttran中，数字控制模块38产生数字信号d2、d4、d6分别为1、0、1(即d2d4d6＝101)，反相器322输出输出信号Vo2为接地电压GND，反相器342输出输出信号Vo4仍为接地电压GND，反相器362输出控制信号ctrl为负电压－AVDD，开关S13仍为导通且开关S23仍为断路，因此，方波产生电路30于暂态区间Ttran中可输出暂态电压Vtran为接地电压GND。另外，于时间区间T2中，数字控制模块38产生数字信号d2、d4、d6分别为1、1、0(即d2d4d6＝110)，此时反相器322输出输出信号Vo2为接地电压GND，反相器342输出输出信号Vo4为负电压－AVDD，反相器362输出控制信号ctrl为接地电压GND，开关S13为断路且开关S23为导通，因此，方波产生电路30于时间区间T2中可输出低电压V2为负电压－AVDD。如此周而复始，方波产生电路30即可产生如图4所绘示的一类方波信号SSG4。如此一来，类方波信号SSG4的高电压V1(正电压AVDD)与暂态电压Vtran(接地电压GND)之间的电压差ΔV1,tran可为电压AVDD，而暂态电压Vtran(接地电压GND)与低电压V2(负电压－AVDD)之间的电压差ΔV2,tran亦为电压AVDD，而高电压V1与低电压V2之间的电压差ΔV1,2可达电压AVDD的2倍而大于特定耐压BV。
简言之，方波产生电路30利用时间区间T1与时间区间T2之间的暂 态区间Ttran，将方波产生电路30于输出端No的输出电压由高电压V1转换至暂态电压Vtran后再由暂态电压Vtran转换至低电压V2(或是由低电压V2转换至暂态电压Vtran后再由暂态电压Vtran转换至高电压V1)。如此一来，在方波产生电路30之特定耐压BV略高于电压AVDD的情况下，方波产生电路30可产生振幅为2*AVDD的类方波信号SSG4，而不至于使方波产生电路30内部的半导体元件因击穿而损坏。
关于方波产生电路10产生类方波信号SSG的操作方式，可进一步归纳为一方波产生流程。请参考图5，图5为本申请实施例一方波产生流程50之示意图。方波产生流程50可由图1中的方波产生电路10来执行，其包含以下步骤：
步骤500：于时间区间T1，方波产生电路10产生类方波信号SSG为高电压V1。
步骤502：于时间区间T2，方波产生电路10产生类方波信号SSG为低电压V2。
步骤504：于时间区间T1与时间区间T2之间的暂态区间Ttran，方波产生电路10产生类方波信号SSG为暂态电压Vtran，其中暂态电压Vtran介于所述高电压V1与低电压V2之间。
关于方波产生流程50的操作细节，请参考前述相关段落，于此不再赘述。
由上述可知，本申请的方波产生电路可利用低压半导体制程来生产制造，而可输出振幅为高压的(类)方波信号。举例来说，本申请的方波产生电路可利用耐压BV为5伏特的低压制程来生产制造，而输出振幅为大于5伏特(例 如：10伏特)的方波信号。换句话说，当一电路系统需要具有高压(如10伏特)振幅的方波信号时，其方波产生电路可避开利用高压半导体制程所带来的高生产成本，而使用低压半导体制程(例如具有耐压BV为5伏特的低压半导体制程)来生产制造，如此一来，可降低整体电路系统的生产成本，而可达到相同的效能。
需注意的是，前述实施例用以说明本申请之概念，本领域具通常知识者当可据以做不同之修饰，而不限于此。举例来说，请参考图6，图6为本申请另一实施例的方波产生电路60的示意图，方波产生电路60与方波产生电路30类似，故相同元件沿用相同符号。与方波产生电路30不同的是，方波产生电路60另包含保护单元SP2、SP4，保护单元SP2耦接于反相器322与开关S13之间，保护单元SP2包含一P型金氧半晶体管QP2以及一N型金氧半晶体管QN2，晶体管QN2与晶体管QP2相互连接，且晶体管QN2的栅极接收正电压AVDD，晶体管QP2的栅极接收接地电压GND，另外，保护单元SP4耦接于反相器342与开关S23之间，保护单元SP4包含一P型金氧半晶体管QP4以及一N型金氧半晶体管QN4，晶体管QN4与晶体管QP4相互连接，且晶体管QN4的栅极接收接地电压GND，晶体管QP4的栅极接收负电压－AVDD。保护单元SP2、SP4可用来保护开关S13、S23，以避免开关S13、S23烧坏。
另外，请参考图7及图8，图7为本申请实施例一方波产生电路70的示意图，图8为方波产生电路70所产生的输出信号Vo2、Vo4以及一控制信号ctrl’的波形图。方波产生电路70与方波产生电路30类似，故相同组件沿用 相同符号。与方波产生电路30不同的是，方波产生电路70中开关S13(其为P型金氧半晶体管)的栅极接收接地电压GND，而方波产生电路70中开关S23(其为N型金氧半晶体管)的栅极接收控制信号ctrl’，控制信号ctrl’由一信号产生电路76所产生，信号产生电路76包含一反相器762，反相器762的输出电平位于正电压AVDD与接地电压GND之间。
方波产生电路70的运作与方波产生电路30类似，故叙述如下。于时间区间T1中，反相器762输出控制信号ctrl为接地电压GND，开关S13为导通且开关S23为断路，因此，方波产生电路70于时间区间T1可输出一类方波信号SSG7为正电压AVDD。于暂态区间Ttran中，反相器322输出输出信号Vo2为接地电压GND，开关S13为断路，反相器362输出控制信号ctrl为正电压AVDD，开关S23为导通，方波产生电路70于暂态区间Ttran可输出类方波信号SSG7为接地电压GND。另外，于时间区间T2中，反相器322输出输出信号Vo2为接地电压GND，开关S13仍为断路，反相器762输出控制信号ctrl为接地电压GND，开关S23仍为导通，方波产生电路70于暂态区间Ttran可输出类方波信号SSG7为负电压－AVDD。
另外，请参考图9，图9为本申请实施例一方波产生电路90的示意图，方波产生电路90与方波产生电路30、70类似，故相同组件沿用相同符号。与方波产生电路30、70不同的是，方波产生电路90包含信号产生电路96、98，信号产生电路96及98分别用来产生控制信号ctrl_P及ctrl_N，以分别控制开关S13及S23的导通状态。其中，控制信号ctrl_P的电压范围介于接地电压GND与负电压－AVDD之间，控制信号ctrl_N的电压范围介于正电压AVDD与接地电压GND之间。方波产生电路90的运作与方波产生电路30、70类似，故于 此不再赘述。
另外，请参考图10，图10为本申请实施例一方波产生电路A0的示意图，方波产生电路A0与方波产生电路90类似，故相同组件沿用相同符号。方波产生电路A0仅包括信号产生电路98，以控制开关S23的导通状态，而开关S13的栅极接收接地电压GND。方波产生电路A0的运作与方波产生电路90类似，故于此不再赘述。
另外，高电压V1与暂态电压Vtran之间的电压差ΔV1,tran不限于为特定耐压BV，高电压V1与暂态电压Vtran之间的电压差ΔV1,tran可小于特定耐压BV，同样地，暂态电压Vtran与低电压V2之间的电压差ΔV2,tran亦可小于特定耐压BV，只要高电压V1与低电压V2之间的电压差ΔV1,2-大于方波产生电路10的特定耐压BV，即满足本申请的要求。
另外，信号产生电路不限于利用反相器来产生高电压V1、暂态电压Vtran以及低电压V2，信号产生电路亦可利用缓冲器(Buffer)来产生高电压V1、暂态电压Vtran以及低电压V2，其中缓冲器可包含两个反相器相互连接而成，亦属于本申请的范畴。
综上所述，本申请于方波产生电路的输出信号由高电压转换至低电压之间(或低电压转换至高电压之间)插入暂态区间并输出暂态电压，如此一来，本申请的方波产生电路可输出类似方波且具有高压振幅的类方波信号，而仅利用低于高压振幅的低压制程即可完成生产制造，进而节省生产成本。
以上所述仅为本申请的部分实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (23)

  1. 一种方波产生方法，应用于一方波产生电路，用来产生一类方波信号，其中所述方波产生电路具有一特定耐压，所述方波产生方法包括：
    在一第一时间区间，所述方波产生电路产生的类方波信号具有一第一电压；
    在一第二时间区间，所述方波产生电路产生的类方波信号具有一第二电压；以及
    在所述第一时间区间与所述第二时间区间之间的一暂态区间，所述方波产生电路产生的类方波信号具有一暂态电压，其中所述暂态电压介于所述第一电压与所述第二电压之间；
    其中，所述第一电压与所述第二电压之间形成一第一电压差，所述第一电压差大于所述特定耐压。
  2. 如权利要求1所述的方波产生方法，其中，所述第一电压与所述暂态电压之间形成一第二电压差，所述第二电压差为所述特定耐压。
  3. 如权利要求1所述的方波产生方法，其中，所述暂态电压与所述第二电压之间形成一第三电压差，所述第三电压差为所述特定耐压。
  4. 如权利要求1所述的方波产生方法，其中，所述第一电压差为所述特定耐压的2倍。
  5. 如权利要求1所述的方波产生方法，其中，所述暂态电压为一接地电压。
  6. 一种方波产生电路，用来产生一类方波信号，其中所述方波产生电路具有一特定耐压，所述方波产生电路包括：
    一输出端，用于输出所述类方波信号；
    一第一信号产生电路，用于在一第一时间区间产生一第一电压；
    一第二信号产生电路，用于在一第二时间区间产生一第二电压；
    一第一开关，其一端耦接于所述第一信号产生电路，另一端耦接于所述输出端；以及
    一第二开关，其一端耦接于所述第二信号产生电路，另一端耦接于所述输出端；其中，所述第一信号产生电路及所述第二信号产生电路于一暂态区间产生一暂态电压，所述暂态区间位于所述第一时间区间与所述第二时间区间之间；
    其中，于所述第一时间区间，所述第一开关为导通；于所述第二时间区间，所述第二开关为导通，在所述暂态区间，所述第一开关或所述第二开关为导通；其中，所述第一电压与所述第二电压之间的一第一电压差大于所述特定耐压。
  7. 如权利要求6所述的方波产生电路，其中，所述第一开关受控于一第一控制信号，在所述暂态区间，所述第一开关导通，所述第一开关自所述第一信号产生电路将所述暂态电压传递至所述输出端。
  8. 如权利要求6所述的方波产生电路，其中，所述第二开关受控于一第二控制信号，在所述暂态区间，所述第二开关导通，所述第二开关自所述第二信号产生电路将所述暂态电压传递至所述输出端。
  9. 如权利要求6所述的方波产生电路，其中，所述第一开关为一第一金氧半晶体管，所述第一金氧半晶体管的一基极耦接于所述第一金氧半晶体管的一源极，所述第一金氧半晶体管为一P型金氧半晶体管，所述第二开关为一第二金氧半晶体管，所述第二金氧半晶体管的一基极耦接于所述第二金氧半晶体管的一源极，所述第二金氧半晶体管为一N型金氧半晶体管。
  10. 如权利要求9所述的方波产生电路，其中，所述第一金氧半晶体管的的一栅极接收一第一控制信号，所述第二金氧半晶体管的一栅极耦接于一接地端。
  11. 如权利要求9所述的方波产生电路，其中，所述第二金氧半晶体管的的一栅极接收一第二控制信号，所述第一金氧半晶体管的一栅极耦接于一接地端。
  12. 如权利要求6所述的方波产生电路，其中，所述第一信号产生电路产生一第一输出信号，所述第一输出信号的一输出高电平为一正电压，所述第一反相器的一输出低电平为一接地电压。
  13. 如权利要求12所述的方波产生电路，其中，所述第一信号产生电路包含一第一反相器，所述第一反相器的一输出高电平为所述正电压，所述第一反相器的一输出低电平为所述接地电压。
  14. 如权利要求12所述的方波产生电路，其中，所述第一信号产生电路于所述第一时间区间中产生所述第一电压为所述正电压，并于所述暂态区间中产生所述暂态电压为所述接地电压。
  15. 如权利要求6所述的方波产生电路，其中，所述第二信号产生电路产生一第二输出信号，所述第二输出信号的一输出高电平为一接地电压，所述第二反相器的一输出低电平为一负电压。
  16. 如权利要求15所述的方波产生电路，其中，所述第二信号产生电路包含一第二反相器，所述第二反相器的一输出高电平为所述接地电压，所述第二反相器的一输出低电平为所述负电压。
  17. 如权利要求15所述的方波产生电路，其中，所述第二信号产生电路于所述第二时间区间中产生所述第二电压为所述负电压。
  18. 如权利要求6所述的方波产生电路，其中，所述第一电压与所述暂态电压之间的一第二电压差为所述特定耐压。
  19. 如权利要求6所述的方波产生电路，其中，所述暂态电压与所述第二电压 之间的一第三电压差为所述特定耐压。
  20. 如权利要求6所述的方波产生电路，其中，所述第一电压与所述第二电压之间的所述第一电压差为所述特定耐压的2倍。
  21. 如权利要求6所述的方波产生电路，其中，进一步包括一第一保护单元以及一第二保护单元，所述第一保护单元耦接于所述第一信号产生电路与所述第一开关之间，所述第二保护单元耦接于所述第二信号产生电路与所述第二开关之间。
  22. 如权利要求21所述的方波产生电路，其中，所述第一保护单元包括一第一N型晶体管以及一第一P型晶体管，所述第一N型晶体管与所述第一P型晶体管相互连接，所述第二保护单元包括一第二N型晶体管以及一第二P型晶体管，所述第二N型晶体管与所述第二P型晶体管相互连接。
  23. 如权利要求22所述的方波产生电路，其中，所述第一N型晶体管的一栅极接收一正电压，所述第一P型晶体管的一栅极以及所述第二N型晶体管的一栅极耦接于一接地端，所述第二P型晶体管的一栅极接收一负电压。
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CN114826217B (zh) 2023-07-07
US10979040B2 (en) 2021-04-13
EP3425799A1 (en) 2019-01-09
CN114826217A (zh) 2022-07-29
CN108781071B (zh) 2022-05-13
US20200212905A1 (en) 2020-07-02
US10622985B2 (en) 2020-04-14
CN108781071A (zh) 2018-11-09
US20190044507A1 (en) 2019-02-07
EP3425799A4 (en) 2019-05-08

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