WO2018150881A1 - Bobine d'arrêt de mode commun, composant de module, et dispositif électronique - Google Patents

Bobine d'arrêt de mode commun, composant de module, et dispositif électronique Download PDF

Info

Publication number
WO2018150881A1
WO2018150881A1 PCT/JP2018/003332 JP2018003332W WO2018150881A1 WO 2018150881 A1 WO2018150881 A1 WO 2018150881A1 JP 2018003332 W JP2018003332 W JP 2018003332W WO 2018150881 A1 WO2018150881 A1 WO 2018150881A1
Authority
WO
WIPO (PCT)
Prior art keywords
coil
layer
conductor pattern
common mode
layers
Prior art date
Application number
PCT/JP2018/003332
Other languages
English (en)
Japanese (ja)
Inventor
紀行 植木
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to JP2018568093A priority Critical patent/JP6642742B2/ja
Publication of WO2018150881A1 publication Critical patent/WO2018150881A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/09—Filters comprising mutual inductance

Definitions

  • the present invention relates to a common mode choke coil, a module component incorporating the common mode choke coil, and an electronic device including these.
  • FIG. 17A and 17B are equivalent circuit diagrams of the common mode filter described in Patent Document 1.
  • FIG. 17A and 17B are equivalent circuit diagrams of the common mode filter described in Patent Document 1.
  • the common mode filter shown in FIG. 17A includes two first coils 3, 3 and two second coils 6, 6.
  • the common mode filter includes an inductance of the second coil 6, and the first coil 3 and the second coil 6.
  • An attenuation pole is generated at a specific frequency by mutual inductance due to coupling and stray capacitance generated between the first coil 3 and the second coil 6.
  • FIG. 17 (B) is an equivalent circuit diagram of the common mode filter shown in FIG. 17 (A), particularly for common mode noise.
  • a series circuit including the second coil 6 and the stray capacitance C is connected in parallel to the first coil 3 which is the main part of the common mode choke coil. It is a structured. Therefore, the differential mode signal passes through not only the first coil 3 but also the series circuit including the second coil 6 and the stray capacitance C. As a result, the series circuit adversely affects the differential mode signal.
  • An object of the present invention is to provide a common mode choke coil that substantially eliminates the influence on the differential mode signal and widens the attenuation band of the common mode noise, a module component incorporating the common mode choke coil, and an electronic apparatus including the same. It is to provide.
  • the common mode choke coil of the present invention is configured as follows.
  • a main circuit including a first coil provided on the first signal line, and a second coil magnetically coupled to the first coil provided on a second signal line that forms a differential transmission line together with the first signal line; A third coil that is magnetically coupled to the first coil and the second coil, and a sub-circuit that includes a capacitor connected to the third coil.
  • the first coil, the second coil, and the third coil are configured in a stacked body in which a plurality of insulating base material layers are stacked and have a mounting surface.
  • the first coil and the second coil are each formed of a first coil conductor pattern and a second coil conductor pattern that are formed in the first layer of the plurality of insulating base layers and run parallel to each other.
  • the coil is composed of a third coil conductor pattern formed in the second layer of the plurality of insulating base layers and in a position overlapping the first coil conductor pattern and the second coil conductor pattern in plan view. Is done.
  • the first layer is composed of a single layer or a plurality of layers
  • the second layer is composed of a single layer or a plurality of layers and is provided on the upper layer side or the lower layer side of the first layer.
  • the sub-circuit is coupled to the main circuit, so that the attenuation band of the common mode noise is widened. Further, the sub circuit does not exist equivalently for the differential mode signal, and the sub circuit does not affect the differential mode signal.
  • the first coil conductor pattern and the second coil conductor pattern run in parallel in the same layer, and a third coil conductor pattern is provided at a position that is different from these layers and overlaps in plan view.
  • the magnetic field coupling degree between the first coil conductor pattern and the third coil conductor pattern is substantially equal to the magnetic field coupling degree between the second coil conductor pattern and the third coil conductor pattern. Furthermore, since the magnitude of these magnetic field coupling degrees is appropriately determined by the distance between the first layer and the second layer, the influence of the sub circuit on the characteristics of the main circuit can be minimized.
  • the first layer is disposed closer to the mounting surface of the laminate than the second layer. This structure suppresses the parasitic inductance and parasitic capacitance from the terminal electrode formed on the mounting surface to the first coil and the second coil, so that the attenuation of common mode noise is ensured and the differential mode signal is inserted. Loss is suppressed.
  • the third coil conductor pattern is formed in a first conductor pattern formed on a layer closer to the first layer among a plurality of layers of the second layer, and on a layer far from the first layer.
  • the capacitor includes a first conductor pattern and a second conductor pattern facing in the stacking direction, and the capacitor is formed by a capacitance generated between the first conductor pattern and the second conductor pattern.
  • a dedicated capacitor forming electrode is formed, an eddy current is generated in the capacitor forming electrode.
  • no eddy current is generated, and the first coil, the second coil, and the third coil are generated. There is no decrease in the Q value of the coil, the attenuation amount of the common mode noise is ensured, and the insertion loss of the differential mode signal is suppressed.
  • the line width of the first conductor pattern is preferably narrower than the line width of the second conductor pattern.
  • the external shape of the said 3rd coil conductor pattern is smaller than the external shape of the 1st coil conductor pattern and the 2nd coil conductor pattern.
  • the first layer includes a plurality of layers, and capacitance is formed between the first coil conductor patterns and the second coil conductor patterns formed in different layers of the first layer. It is preferable that For example, if a capacitor forming electrode connected between the first coil conductor and the second coil conductor is separately formed, an eddy current is generated in the capacitor forming electrode. No current is generated, the Q values of the first coil, the second coil, and the third coil are not lowered, the attenuation amount of the common mode noise is ensured, and the insertion loss of the differential mode signal is suppressed.
  • the module component of the present invention includes a common mode choke coil and an ESD protection element.
  • the common mode choke coil is configured as shown in (1) above, and the ESD protection element is integrated into the laminate and connected to the main circuit. With this structure, it can be handled as a single component including the ESD protection element and the common mode choke coil, and the occupied area on the circuit board is reduced.
  • the ESD protection element is disposed on the mounting surface side of the multilayer body from the common mode choke coil.
  • the module component of the present invention includes a fourth coil and a fifth coil inserted in series with the first signal line to provide the ESD protection element, and the ESD protection element includes the first protection element. It is preferable that the connection point between the four coils and the fifth coil is connected between the ground and the ground, and the fourth coil and the fifth coil are configured to make a Japanese-style connection.
  • the above configuration acts in a direction in which the inductance component generated in the ESD current path of the ESD protection element is canceled. That is, the equivalent series inductance due to the provision of the ESD protection element is suppressed, and the peak voltage during ESD protection can be further suppressed.
  • the module component of the present invention includes an ESD protection element between the first signal line and the second signal line, A fourth coil and a fifth coil inserted in series with the first signal line; a sixth coil and a seventh coil inserted in series with the second signal line;
  • the ESD protection element includes a first Zener diode, a second Zener diode, and a third Zener diode, The first Zener diode and the second Zener diode are connected in series between a connection point between the fourth coil and the fifth coil and a connection point between the sixth coil and the seventh coil.
  • the third Zener diode is connected between a connection point of the first Zener diode and the second Zener diode and a ground;
  • the fourth coil and the fifth coil are connected in a Japanese-style manner,
  • the sixth coil and the seventh coil are connected in a Japanese-style manner.
  • a configuration is preferred.
  • An electronic device of the present invention includes a common mode choke coil having a differential transmission line, and an electronic circuit connected to the differential transmission line.
  • the common mode choke coil is configured as shown in (1) above.
  • An electronic device of the present invention includes the module component according to any one of (7) to (10) above, a differential transmission line, and an electronic circuit connected to the differential transmission line.
  • a common mode choke coil that substantially eliminates the influence on the differential mode signal and widens the attenuation band of the common mode noise, a module component that incorporates the common mode choke coil, and an electronic apparatus including the same. Composed.
  • FIG. 1 is a circuit diagram of a module component 101 according to an embodiment of the present invention.
  • FIG. 2A is an equivalent circuit diagram regarding common mode noise of the common mode choke coil 10
  • FIG. 2B is an equivalent circuit diagram regarding differential mode signals of the common mode choke coil 10.
  • FIG. 3A shows the frequency characteristics of insertion loss with respect to common mode noise.
  • FIG. 3B is a diagram illustrating frequency characteristics of insertion loss of the first resonance circuit and the second resonance circuit alone.
  • FIG. 3C is a diagram illustrating the frequency characteristics of the insertion loss of the third resonance circuit.
  • FIG. 4 is a diagram illustrating frequency characteristics of reactances of the third resonance circuit, the first resonance circuit, and the second resonance circuit, and frequency characteristics of insertion loss with respect to common mode noise.
  • FIG. 1 is a circuit diagram of a module component 101 according to an embodiment of the present invention.
  • FIG. 2A is an equivalent circuit diagram regarding common mode noise of the common mode choke coil 10
  • FIG. 2B is an equivalent circuit diagram regarding differential mode signals
  • FIG. 5 is a perspective view of each conductor pattern inside the module component 101 seen through.
  • FIG. 6 is a front view seen through each conductor pattern inside the module component 101.
  • FIG. 7 is a plan view showing a conductor pattern formed on each insulating base material layer of the module component 101.
  • FIG. 8 is a block diagram of an electronic device 200 according to the present invention.
  • FIG. 9 is a circuit diagram of the module component 102 including two transient voltage suppressors.
  • FIGS. 10A and 10B are diagrams illustrating the relationship between the mutual inductance due to the coupling between the inductor La and the inductor Lb and the inductance component generated in the path of the ESD current.
  • FIG. 11 is a plan view showing a connection structure of the transient voltage suppressor 21 to the signal line.
  • FIG. 12 is a perspective view showing the internal structure of the transient voltage suppressor 21.
  • FIG. 13A is a plan view showing the configuration of the ESD protection element 1
  • FIG. 13B is a longitudinal sectional view of the ESD protection element 1.
  • FIG. 14 is a circuit diagram of the ESD protection element 1.
  • FIG. 15 is a circuit diagram of a transient voltage suppressor.
  • FIG. 16 is a plan view showing a connection structure of the matching circuit 31 and the ESD protection element 1 to the signal line.
  • FIG. 17A is an equivalent circuit diagram of the common mode filter described in Patent Document 1
  • FIG. 17B is an equivalent circuit diagram of the common mode filter, particularly for common mode noise.
  • FIG. 1 is a circuit diagram of a module component 101 according to an embodiment of the present invention.
  • the module component 101 includes a common mode choke coil 10 and a transient voltage suppressor 20.
  • the common mode choke coil 10 includes a main circuit MC and a sub circuit SC.
  • the main circuit MC is provided on a first coil L1 provided on the first signal line SL1 and a second signal line SL2 that forms a differential transmission line together with the first signal line SL1, and is magnetically coupled to the first coil L1.
  • the sub circuit SC includes a third coil L3 that is magnetically coupled to the first coil L1 and the second coil L2, and a capacitor C3 connected to the third coil L3.
  • the first coil L1 and the second coil L2 are magnetically coupled.
  • the dot marks shown in the first coil L1 and the second coil L2 indicate the polarity of mutual coupling.
  • the third coil L3 is magnetically coupled to the first coil L1 and the second coil L2, respectively.
  • the transient voltage suppressor 20 includes an ESD protection element 2 and inductors La, Lb, Lc, and Ld.
  • the inductors La and Lb are connected in series to the first signal line SL1
  • the inductors Lc and Ld are connected in series to the second signal line SL2.
  • the dot marks shown in the inductors La and Lb indicate the polarity of coupling between the inductors La and Lb.
  • the dot mark shown to the inductor Lc and the inductor Ld represents the polarity of the coupling
  • These inductors La, Lb, Lc, and Ld constitute an impedance matching circuit of the ESD protection element 2 for the differential transmission line.
  • the inductors La, Lb, Lc, and Ld correspond to “fourth coil”, “fifth coil”, “sixth coil”, and “seventh coil”, respectively, according to the present invention.
  • the ESD protection element 2 includes three Zener diodes Da, Db, Dc, and a series circuit of Zener diodes Da, Db between a connection point between the inductor La and the inductor Lb and a connection point between the inductor Lc and the inductor Ld. Is connected.
  • the Zener diodes Da and Db are connected in opposite directions, and the Zener diode Dc is connected between the connection point of the Zener diodes Da and Db and the ground.
  • the zener diodes Da, Db, and Dc correspond to “first zener diode”, “second zener diode”, and “third zener diode” according to the present invention, respectively.
  • the inductor La and the inductor Lb are connected in a Japanese-style manner. Further, the inductor Lc and the inductor Ld are connected in a Japanese-style manner.
  • an equivalent negative inductance element is connected in series to the Zener diode Da by the summing connection of the inductor La and the inductor Lb, and the equivalent series inductance of the Zener diode Da is suppressed.
  • an equivalent negative inductance element is connected in series to the Zener diode Db by the summing connection of the inductor Lc and the inductor Ld, and the equivalent series inductance of the Zener diode Db is suppressed. This effectively suppresses the peak voltage during ESD protection.
  • FIG. 2A is an equivalent circuit diagram for the common mode noise of the common mode choke coil 10
  • FIG. 2B is an equivalent circuit diagram for the differential mode signal of the common mode choke coil 10.
  • the first signal line SL1 and the second signal line SL2 constitute one differential line.
  • the first coil L1 and the second coil L2 are magnetically coupled with a polarity that cancels common mode noise propagating through the differential line. That is, the first coil L1 and the second coil L2 are differentially connected to the common mode noise, and are summed to the differential mode signal.
  • the first resonance circuit is configured by the first coil L1 and the first capacitor C1 connected in parallel to the first coil L1, and the second coil L2 and the first capacitor C1 are connected in parallel to the first coil L1.
  • a second resonance circuit is configured with the second capacitor C2.
  • a third resonance circuit is configured by a sub-circuit including a third coil L3 and a third capacitor C3.
  • the third coil L3 is magnetically coupled to the first coil L1 and the second coil L2, thereby forming a multiple resonance circuit including a first resonance circuit, a second resonance circuit, and a third resonance circuit.
  • the sub circuit SC since the first coil L1 and the second coil L2 are not coupled, there is no magnetic field coupling the first coil L1, the second coil L2, and the third coil L3. Therefore, as for the differential mode signal, as shown in FIG. 2B, the sub circuit SC does not exist equivalently, and the sub circuit SC does not influence the differential mode signal. Note that capacitors Cp1 and Cp2 shown in FIG. 2B are stray capacitances generated between the first coil L1 and the second coil L2.
  • FIG. 3A shows the frequency characteristics of insertion loss with respect to common mode noise.
  • FIG. 3B is a diagram illustrating frequency characteristics of insertion loss of the first resonance circuit and the second resonance circuit alone.
  • FIG. 3C is a diagram illustrating the frequency characteristics of the insertion loss of the third resonance circuit.
  • FIG. 4 is a diagram illustrating frequency characteristics of reactances of the third resonance circuit, the first resonance circuit, and the second resonance circuit, and frequency characteristics of insertion loss with respect to common mode noise.
  • the upper stage is a diagram illustrating frequency characteristics of reactance of the third resonance circuit, the first resonance circuit, and the second resonance circuit alone.
  • the middle stage is a diagram showing frequency characteristics of reactance in a state where the third resonance circuit is coupled to the first resonance circuit and the second resonance circuit.
  • the lower diagram shows the frequency characteristics of insertion loss with respect to common mode noise, and is the same diagram as FIG.
  • the resonance frequency of the first resonance circuit and the second resonance circuit alone is f0, and the resonance frequency of the third resonance circuit alone is f1, but these resonance circuits are coupled to each other as shown in FIG.
  • the frequencies are displaced to f01 and f11, respectively, and the frequency band between f01 and f11 is expanded.
  • common mode noise is particularly generated for a predetermined band having a frequency f01 (3 GHz) as a center frequency and a predetermined band having a frequency f11 (5 GHz) as a center frequency. Is suppressed.
  • the sub-circuit SC is coupled to the main circuit MC, so that the attenuation band of common mode noise is widened. Further, the sub circuit SC does not exist equivalently for the differential mode signal, and the sub circuit SC does not affect the differential mode signal.
  • FIG. 5 is a perspective view in which each conductor pattern inside the module component 101 is seen through.
  • FIG. 6 is a front view seen through each conductor pattern in the module component 101.
  • FIG. 7 is a plan view showing a conductor pattern formed on each insulating base material layer of the module component 101.
  • These conductor patterns are obtained by patterning Cu foil, for example.
  • the thickness of the conductor pattern is about 4 ⁇ m to 8 ⁇ m.
  • the distance between adjacent conductor patterns is about 20 ⁇ m to 40 ⁇ m.
  • the interlayer distance between conductor patterns adjacent in the stacking direction is also about 20 to 40 ⁇ m.
  • the module component 101 is configured as a laminated body 100 in which a plurality of insulating base material layers S1 to S17 are laminated.
  • the lower surface of the laminate 100 shown in FIG. 6 is a mounting surface UF for mounting the module component 101 on the circuit board.
  • These insulating base layers S1 to S17 are resin layers such as LCP (liquid crystal polymer).
  • the insulating base layer S1 is the lowermost layer, and the insulating base layer S17 is the uppermost layer.
  • Terminal electrodes P1, P2, P3, P4, and P GND are formed on the mounting surface UF of the insulating base layer (hereinafter simply “base layer”) S1.
  • base layer the insulating base layer
  • first coil conductor patterns L1a to L1e, second coil conductor patterns L2a to L2e, first coil conductor patterns L1a to L1e, an interlayer connection conductor, and a second coil conductor Interlayer connection conductors for connecting the conductor patterns L2a to L2e to each other are formed.
  • a helical first coil L1 is constituted by the first coil conductor patterns L1a to L1e and the interlayer connection conductors connecting these patterns.
  • a helical second coil L2 is configured by the second coil conductor patterns L2a to L2e and the interlayer connection conductors that connect these layers.
  • the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e are loop-shaped conductor patterns that run parallel to each other in each of the base layers S10 to S14. These base material layers S10 to S14 correspond to the “first layer” in the present invention.
  • the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e run side by side in each layer, but the relationship between the inner periphery and the outer periphery is switched for each layer. Thereby, the inductances of the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e are equalized. Further, as will be described later, the stray capacitance formed between the layers is equalized.
  • the third coil conductor patterns L3a and L3b are formed on the base material layers S15 and S16.
  • the third coil conductor patterns L3a and L3b are formed at positions overlapping the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e in plan view.
  • the base material layers S15 and S16 correspond to the “second layer” in the present invention.
  • the second layer is provided on the upper layer side of the first layer. That is, unlike the base material layers S10 to S14, the base material layers S15 and S16 are base material layers outside the range of the laminated portion of the base material layers S10 to S14.
  • first layer (S10 to S14) is arranged on the mounting surface UF side of the laminate 100 from the second layer (S15, S16).
  • second layer (S15, S16) is disposed on the upper surface TF side of the stacked body 100 from the first layer (S10 to S14).
  • the first coil conductor patterns L1a to L1e face each other in the stacking direction with one layer interposed therebetween.
  • the first coil conductor pattern L1a formed on the base material layer S10 and the first coil conductor pattern L1c formed on the base material layer S12 face each other in the stacking direction, and a stray capacitance is formed therebetween.
  • the second coil conductor pattern L2a and the second coil conductor pattern L2c face each other in the stacking direction, and a stray capacitance is formed therebetween.
  • first coil conductor pattern L1b formed on the base material layer S11 and the first coil conductor pattern L1d formed on the base material layer S13 face each other in the stacking direction, and a stray capacitance is formed therebetween.
  • second coil conductor pattern L2b and the second coil conductor pattern L2d face each other in the stacking direction, and a stray capacitance is formed therebetween.
  • the inductance components of the first coil conductor patterns L1a to L1e constitute the first coil L1 shown in FIG. 1, and the stray capacitance generated between the conductor patterns in the stacking direction causes the first capacitor C1.
  • the inductance components of the second coil conductor patterns L2a to L2e constitute the second coil L2 shown in FIG. 1, and the stray capacitance generated between the conductor patterns in the stacking direction constitutes the second capacitor C2.
  • the stray capacitances constituting the first capacitor C1 and the second capacitor C2 are constituted by stray capacitances between the conductive patterns of adjacent layers, the stray capacitance fluctuates greatly due to the misalignment in the surface direction of the base material layer.
  • the conductor patterns by causing the conductor patterns to face each other in the stacking direction with one base material layer interposed therebetween, fluctuations in stray capacitance due to the stacking error are suppressed.
  • the first conductor pattern L3a is formed on the base layer S15 on the side close to the first layer (S10 to S14) of the second layer (S15, S16).
  • the second conductor pattern L3b is formed on the base material layer S16 far from the first layer (S10 to S14).
  • the first conductor pattern L3a and the second conductor pattern L3b face each other in the stacking direction.
  • the outer peripheral end of the first conductor pattern L3a is connected to the outer peripheral end of the second conductor pattern L3b via an interlayer connection conductor.
  • the stray capacitance generated between the first conductor pattern L3a and the second conductor pattern L3b constitutes the third capacitor C3 shown in FIG.
  • the line width of the first conductor pattern L3a is about 30 ⁇ m, and the line width of the second conductor pattern L3b is about 100 ⁇ m. That is, the line width of the first conductor pattern L3a is narrower than the line width of the second conductor pattern L3b, and the first conductor pattern L3a is substantially the same as the second conductor pattern L3b over the entire length in plan view from the stacking direction. Overlap. With this structure, stray capacitance generated between the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e and the third coil conductor patterns L3a and L3b is suppressed.
  • the first coil L1 by the first coil conductor patterns L1a to L1e and the second coil L2 and the third coil L3 by the second coil conductor patterns L2a to L2e are coupled by a magnetic field and are hardly electrically coupled.
  • This electric field coupling is a coupling in which a capacitance is generated between the first coil L1 and the second coil L2 via the third coil L3, and thus has an adverse effect on the differential mode signal.
  • the first coil L1 and the second coil L2 are coupled to the third coil L3 almost only by a magnetic field, the influence of the sub circuit on the differential mode signal is suppressed. Further, even if there is a positional deviation in the surface direction between the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e, it is not easily affected.
  • the outer shapes of the third coil conductor patterns L3a and L3b are smaller than the outer shapes of the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e.
  • the outer width W3 of the third coil conductor patterns L3a and L3b is smaller than the outer width W12 of the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e.
  • the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e run in parallel in the same layer, and are in different layers and overlap with each other in plan view. Since the conductor patterns L3a and L3b are provided, the magnetic field coupling degree M2a between the first coil conductor patterns L1a to L1e and the third coil conductor patterns L3a and L3b, the second coil conductor patterns L2a to L2e, The magnetic field coupling degree M2b with the three-coil conductor patterns L3a and L3b is substantially equal. Further, the magnitudes of the magnetic field coupling degrees M2a and M2b are appropriately determined by the distance between the first layer (S10 to S14) and the second layer (S15 and S16). The influence of SC can also be suppressed to the minimum.
  • the terminal electrodes P1, P2, P3, P4 formed on the mounting surface UF.
  • the parasitic inductance and the parasitic capacitance are suppressed. Thereby, the attenuation amount of the common mode noise is ensured, and the insertion loss of the differential mode signal is suppressed.
  • the transient voltage suppressor 20 including the ESD protection element 2 and the inductors La, Lb, Lc, and Ld includes the common mode choke coil 10 including the main circuit MC and the sub circuit SC. Further, the laminated body 100 is disposed on the mounting surface UF side. With this structure, since the path length from the terminal electrode formed on the mounting surface to the transient voltage suppressor 20 is short and the parasitic component is small, the effect of suppressing the transient voltage is high.
  • flow preventing dummy patterns DP1c, DP1d, DP1e, DP1f, and DP1g are formed on the base material layers S10, S11, S12, and S13, respectively.
  • flow preventing dummy patterns DP1a, DP2a, DP3a, DP4a are formed on the base material layer S5.
  • flow preventing dummy patterns DP1b, DP2b, DP3b, DP4b are formed on the base material layer S6.
  • These dummy patterns for flow prevention disperse each conductor pattern formed on the base material layers S5, S6, S10 to S14 or the base material layers adjacent thereto uniformly within the surface of the base material layers. This suppresses the resin from flowing unevenly during the lamination heating press, and the shape of each conductor pattern is maintained as designed.
  • the unevenness on the upper surface of the laminated body is small and smooth after the heat pressing, picking up by the mounter is easy when the module component 101 is surface-mounted on the circuit board.
  • the unevenness is small and smooth on the mounting surface of the laminated body, the mounting property to the circuit board is improved.
  • the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e formed on the base material layers S10 to S14 are shifted from the center of each base material layer to the left in FIG. Therefore, flow preventing dummy patterns DP1c, DP1d, DP1e, DP1f, and DP1g are formed near the right end of each base material layer.
  • the base material layers S5 and S6 cavity openings CAa and CAb for accommodating the ESD protection element 2 (see FIG. 6) are formed, respectively.
  • the base material layer in which the cavity opening is simply formed easily extends in the X-axis direction, the Y-axis direction, or both directions.
  • the base material layers S5 and S6 have the flow preventing dummy patterns DP1a, DP2a, DP3a, DP4a, DP1b. , DP2b, DP3b, and DP4b are formed, respectively, so that the “elongation” of the base material layers S5 and S6 and the base material layers adjacent thereto is suppressed. Thereby, the shape of the cavity is maintained.
  • the anti-flow dummy patterns DP1a, DP1b, DP1c, DP1d, DP1e, DP1f, and DP1g are patterns that are long in the Y-axis direction, and therefore have an effect of suppressing the expansion in the Y-axis direction. high. Further, since the flow preventing dummy patterns DP2a, DP3a, DP4a, DP2b, DP3b, and DP4b are long patterns in the X-axis direction, the effect of suppressing the expansion in the X-axis direction is high.
  • the anti-flow dummy patterns DP1a, DP1b, DP1c, DP1d, DP1e, DP1f, DP1g, DP2a, DP3a, DP2b, DP3b extend in the peripheral direction of each base material layer. Two rows are arranged in the radial direction from the center of the material layer. Each flow prevention dummy pattern is disposed discontinuously (divided) in the peripheral direction of each base material layer.
  • the flow preventing dummy patterns DP2a, DP3a, DP2b, DP3b are shaped so that the dividing positions do not overlap in the radial direction. That is, the dividing position is dispersed. As a result, the eddy current is prevented and elongation in the X-axis direction is effectively suppressed.
  • FIG. 8 is a block diagram of an electronic device 200 according to the present invention.
  • the electronic device 200 includes a module component 101, a differential transmission line DTL, a USB connector CN, a USB device controller 201 connected to the differential transmission line DTL via the module component 101, and a CPU 202 connected to the USB device controller 201. Is provided.
  • the configuration of the module component 101 is as shown in FIGS.
  • common mode noise superimposed on the differential transmission line DTL is suppressed by the common mode choke coil 10 in the module component 101.
  • a transient voltage such as ESD entering via the USB connector CN is suppressed by the ESD protection element 2 in the module component 101, and the transient voltage applied to the USB device controller 201 is suppressed.
  • the module component 101 is connected to the differential transmission line.
  • the common mode choke coil that does not include the transient voltage suppressor 20 is configured, and the common mode choke coil is differentially connected. You may connect to a transmission line.
  • FIG. 9 is a circuit diagram of the module component 102 including two transient voltage suppressors.
  • the module component 102 includes a common mode choke coil 10 and two transient voltage suppressors 21.
  • the configuration and operation of the common mode choke coil 10 are the same as those shown in FIG.
  • the transient voltage suppressor 21 includes the ESD protection element 1 and inductors La, Lb, and ESL1.
  • the ESD protection element 1 is connected between a connection point CN1 between the inductor La and the inductor Lb and the ground.
  • the inductor ESL1 is an inductance component (equivalent series inductance) generated in the ESD current path (inductor generated between the connection point CN1 of the inductors La and Lb and the ground).
  • the inductors La and Lb are impedance matching circuits with the ESD protection element 1.
  • the inductor La and the inductor Lb are connected in a Japanese-style manner.
  • the inductors La and Lb correspond to the “fourth coil” and the “fifth coil” according to the present invention, respectively.
  • FIG. 10 (A) and 10 (B) are diagrams showing the relationship between the mutual inductance due to the coupling between the inductor La and the inductor Lb and the inductance component generated in the path of the ESD current.
  • a capacitor Cd1 is a parasitic capacitance generated in the ESD protection element 1.
  • a transformer formed by coupling the inductor La and the inductor Lb shown in FIG. 10A is represented by a T-type equivalent circuit as shown in FIG.
  • the mutual inductance ( ⁇ M) due to the coupling between the inductor La and the inductor Lb is equivalently connected in series between the connection point CN1 and the ground.
  • the mutual inductance ( ⁇ M) is a negative inductance. Therefore, the inductance component generated in the ESD current path is canceled. If the absolute value of the mutual inductance ( ⁇ M) is equal to the inductance of the inductor ESL1, the inductance component of the ESD current path is zero. This effectively suppresses the peak voltage during ESD protection.
  • the transient voltage suppressor 21 functions as a three-terminal element including the ESD protection element 1, the matching circuit for the ESD protection element 1, and the ESL cancellation circuit.
  • FIG. 11 is a plan view showing a connection structure of the transient voltage suppressor 21 to the signal line.
  • the transient voltage suppressor 21 is a rectangular parallelepiped chip component, and includes terminals Pa, Pb, and P GND on the bottom surface.
  • the substrate on which the transient voltage suppressor 21 is mounted has a signal line formed by a conductor pattern, and the terminals Pa and Pb of the transient voltage suppressor 21 are connected to the two signal lines, respectively. That is, the transient voltage suppressor 21 is mounted on the base material so as to be inserted in the middle of the signal line. Also, the base material is formed a ground electrode terminal P GND transient voltage suppressor 21 is connected to the ground electrode.
  • the terminal P GND is formed between the terminals Pa and Pb. Therefore, the transient voltage suppressor 21 is mounted so as to straddle the ground electrode.
  • the transient voltage suppressor 21 is connected (inserted) in series to the signal line, the arrangement of the conductor pattern of the signal line and the transient voltage suppressor 20 is simplified. Moreover, impedance mismatch of the signal line can be reduced.
  • FIG. 12 is a perspective view showing the internal structure of the transient voltage suppressor 21.
  • the transient voltage suppressor 21 includes the ESD protection element 1 and its redistribution layer REL.
  • the ESD protection element 1 is a semiconductor substrate on which a plurality of diode elements are formed.
  • Inductors La and Lb are formed in the redistribution layer REL of the semiconductor substrate.
  • the upper surface of the redistribution layer REL is a mounting surface of the transient voltage suppressor 21, and terminals Pa, Pb, and PGND are formed on this surface.
  • FIG. 13A is a plan view showing the configuration of the ESD protection element 1
  • FIG. 13B is a longitudinal sectional view of the ESD protection element 1.
  • FIG. FIG. 14 is a circuit diagram of the ESD protection element 1.
  • N-type epitaxial layers Nepi1 and Nepi2 are formed on a P-type semiconductor substrate Psub.
  • diodes D11 and D21 are formed between the P-type semiconductor substrate Psub and the N-type epitaxial layer Nepi1.
  • N-type epitaxial layer Nepi1 a single N-type region is formed, and a Zener diode D3 is formed between the N-type region and the P-type semiconductor substrate Psub.
  • Two P-type regions are formed in the N-type epitaxial layer Nepi2 and diodes D12 and D22 are formed between the P-type region and the N-type epitaxial layer Nepi2.
  • N-type regions are further formed in the N-type epitaxial layer Nepi2. These N-type regions act as cathode terminals of the diodes D11 and D21.
  • a trench TR for electrical insulation is formed around the N-type region formed in the N-type epitaxial layers Nepi1 and Nepi2.
  • One of the two N-type regions formed in the N-type epitaxial layer Nepi2 and one of the two P-type regions are connected by an Al wiring and used as the terminal T1.
  • the other of the two N-type regions and the other of the two P-type regions are connected by an Al-aluminum wiring and used as a terminal T2.
  • the arrow in FIG. 13B indicates the direction of current flowing through the semiconductor substrate Psub.
  • the ESD protection element 1 having the two terminals T1 and T2 is configured by the structure described above.
  • the ESD protection element needs to have a low capacity in order to pass a high-frequency signal. This is because it is necessary to increase the self-resonance frequency due to the parasitic capacitance of the ESD protection element and the equivalent series inductance (ESL) in order to pass a high-frequency signal.
  • ESD equivalent series inductance
  • a T-type matching circuit including two inductors that are coupled in a coupled manner using the capacitance of the ESD protection element 1 is configured.
  • the ESL of the ESD protection element 1 can be canceled, the self-resonance frequency of the ESD protection element 1 can be increased, and the high frequency without increasing the parasitic capacitance of the ESD protection element 1 (that is, while ensuring the ESD protection performance).
  • a signal can be passed.
  • FIG. 15 is a circuit diagram of a transient voltage suppressor. This circuit corresponds to the transient voltage suppressor 21 shown in FIG.
  • the matching circuit 31 is configured as one element in which the rewiring layer portion illustrated in FIG. 12 is independent, and includes terminals Pa, Pb, and Pc.
  • the ESD protection element 1 is configured as one element in which the semiconductor substrate 1 portion shown in FIG. 12 is independent, and includes terminals T1 and T2.
  • FIG. 16 is a plan view showing a connection structure of the matching circuit 31 and the ESD protection element 1 to the signal line.
  • both the matching circuit 31 and the ESD protection element 1 are rectangular parallelepiped chip components, and the matching circuit 31 is mounted on the base material so as to be inserted in the middle of the signal line.
  • the terminal T1 is connected to the terminal Pc of the matching circuit 31 through the conductor pattern on the base material, and the terminal T2 is connected to the ground electrode.
  • separating the ESD protection element 1 and the matching circuit 31 has an advantage that the ESD protection element 1 having desired characteristics can be selectively used.
  • the third coil described above is an example configured with a third conductor pattern formed in a plurality of second layers, but the second layer may be a single layer.
  • FIG. 6 shows an example in which the “second layer” in which the third coil L3 is formed is arranged on the upper layer side of the “first layer” in which the first coil L1 and the second coil L2 are formed.
  • the vertical relationship between the “first layer” and the “second layer” may be reversed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Filters And Equalizers (AREA)

Abstract

La présente invention concerne une bobine d'arrêt de mode commun (10) qui comprend : un circuit principal (MC) comprenant une première bobine (L1) disposée sur une première ligne de signal (SL1) et une deuxième bobine (L2) disposée sur une seconde ligne de signal (SL2) ; et un sous-circuit (SC) comprenant une troisième bobine (L3) couplée à la première bobine (L1) et à la deuxième bobine (L2) par l'intermédiaire d'un champ magnétique, et un condensateur (C3) connecté à la troisième bobine (L3). La première bobine (L1) et la deuxième bobine (L2) sont formées dans une première couche d'une pluralité de couches de substrat isolantes, et sont chacune constituées d'un premier motif conducteur de bobine et d'un deuxième motif conducteur de bobine s'étendant en parallèle. La troisième bobine (L3) est constituée d'un troisième motif conducteur de bobine qui est formé dans une seconde couche de la pluralité de couches de substrat isolantes, dans une position chevauchant le premier motif conducteur de bobine et le deuxième motif conducteur de bobine dans une vue en plan.
PCT/JP2018/003332 2017-02-14 2018-02-01 Bobine d'arrêt de mode commun, composant de module, et dispositif électronique WO2018150881A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2018568093A JP6642742B2 (ja) 2017-02-14 2018-02-01 コモンモードチョークコイル、モジュール部品および電子機器

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2017024557 2017-02-14
JP2017-024557 2017-02-14
JP2017155118 2017-08-10
JP2017-155118 2017-08-10

Publications (1)

Publication Number Publication Date
WO2018150881A1 true WO2018150881A1 (fr) 2018-08-23

Family

ID=63169857

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/003332 WO2018150881A1 (fr) 2017-02-14 2018-02-01 Bobine d'arrêt de mode commun, composant de module, et dispositif électronique

Country Status (2)

Country Link
JP (1) JP6642742B2 (fr)
WO (1) WO2018150881A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019230027A1 (fr) * 2018-05-31 2019-12-05 株式会社村田製作所 Élément d'adaptation d'impédance et dispositif de communication
JP2021005842A (ja) * 2019-06-27 2021-01-14 株式会社村田製作所 ノイズ低減回路、伝送モジュール、及び、ＳｅｒＤｅｓ回路
JP2022514606A (ja) * 2018-12-20 2022-02-14 エイブイエックス コーポレイション 少なくとも２つのビアと接続されたコンデンサを備える多層フィルタ
WO2022049927A1 (fr) * 2020-09-04 2022-03-10 株式会社村田製作所 Filtre, module de filtre et dispositif électronique

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001197665A (ja) * 2000-01-14 2001-07-19 Fuji Electric Co Ltd 入力ラインフィルタ
JP2007013723A (ja) * 2005-06-30 2007-01-18 Tdk Corp サージ吸収回路
JP2012019504A (ja) * 2010-06-07 2012-01-26 Mitsubishi Electric Corp ノイズフィルタ
WO2013136936A1 (fr) * 2012-03-16 2013-09-19 株式会社村田製作所 Bobine d'arrêt à mode commun
WO2015087794A1 (fr) * 2013-12-09 2015-06-18 株式会社村田製作所 Filtre à mode commun et filtre à mode commun à circuit de protection contre les des
WO2016067746A1 (fr) * 2014-10-30 2016-05-06 日立オートモティブシステムズ株式会社 Condensateur stratifié et dispositif de commande embarqué

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001197665A (ja) * 2000-01-14 2001-07-19 Fuji Electric Co Ltd 入力ラインフィルタ
JP2007013723A (ja) * 2005-06-30 2007-01-18 Tdk Corp サージ吸収回路
JP2012019504A (ja) * 2010-06-07 2012-01-26 Mitsubishi Electric Corp ノイズフィルタ
WO2013136936A1 (fr) * 2012-03-16 2013-09-19 株式会社村田製作所 Bobine d'arrêt à mode commun
WO2015087794A1 (fr) * 2013-12-09 2015-06-18 株式会社村田製作所 Filtre à mode commun et filtre à mode commun à circuit de protection contre les des
WO2016067746A1 (fr) * 2014-10-30 2016-05-06 日立オートモティブシステムズ株式会社 Condensateur stratifié et dispositif de commande embarqué

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019230027A1 (fr) * 2018-05-31 2019-12-05 株式会社村田製作所 Élément d'adaptation d'impédance et dispositif de communication
JP2022514606A (ja) * 2018-12-20 2022-02-14 エイブイエックス コーポレイション 少なくとも２つのビアと接続されたコンデンサを備える多層フィルタ
JP7288055B2 (ja) 2018-12-20 2023-06-06 キョーセラ・エイブイエックス・コンポーネンツ・コーポレーション 少なくとも２つのビアと接続されたコンデンサを備える多層フィルタ
JP2021005842A (ja) * 2019-06-27 2021-01-14 株式会社村田製作所 ノイズ低減回路、伝送モジュール、及び、ＳｅｒＤｅｓ回路
JP7363128B2 (ja) 2019-06-27 2023-10-18 株式会社村田製作所 ノイズ低減回路、伝送モジュール、及び、ＳｅｒＤｅｓ回路
WO2022049927A1 (fr) * 2020-09-04 2022-03-10 株式会社村田製作所 Filtre, module de filtre et dispositif électronique

Also Published As

Publication number Publication date
JPWO2018150881A1 (ja) 2019-11-07
JP6642742B2 (ja) 2020-02-12

Similar Documents

Publication Publication Date Title
US9755606B2 (en) Common mode filter and ESD-protection-circuit-equipped common mode filter
US10193336B2 (en) ESD protection circuit, differential transmission line, common mode filter circuit, ESD protection device, and composite device
JP6642742B2 (ja) コモンモードチョークコイル、モジュール部品および電子機器
JP6102871B2 (ja) コモンモードチョークコイル及び高周波電子機器
US10886730B2 (en) Filter having an ESD protection device
US10749494B2 (en) Noise filter circuit
EP2669906A1 (fr) Transformateur à base de circuit intégré
KR101422950B1 (ko) 하나의 권선으로 구현되는 직렬 인덕터 어레이 및 이를 포함하는 필터
US8421577B2 (en) Planar inductive unit and an electronic device comprising a planar inductive unit
US20040263308A1 (en) Inductor formed between two layout layers
US10950381B2 (en) Surface-mounted LC device
US9350316B1 (en) Wideband baluns and methods of their manufacture
WO2018008422A1 (fr) Inductance avec fonction de protection esd
JP6424994B1 (ja) 薄膜ｅｓｄ保護デバイス
US10004144B2 (en) Connector module
US10008757B2 (en) High-frequency module
US11870412B2 (en) Multilayer substrate, circuit device, and filter circuit substrate
US20230047936A1 (en) Filter circuit
US10911014B2 (en) Electronic component
JP2020155875A (ja) ノイズフィルタ
JP2008263074A (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18754103

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2018568093

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18754103

Country of ref document: EP

Kind code of ref document: A1