WO2018150881A1 - Common mode choke coil, module component, and electronic device - Google Patents

Abstract

A common mode choke coil (10) comprises: a main circuit (MC) including a first coil (L1) provided on a first signal line (SL1) and a second coil (L2) provided on a second signal line (SL2); and a sub-circuit (SC) comprising a third coil (L3) coupled to the first coil (L1) and the second coil (L2) via a magnetic field, and a capacitor (C3) connected to the third coil (L3). The first coil (L1) and the second coil (L2) are formed in a first layer of a plurality of insulating substrate layers, and are each configured of a first coil conductor pattern and a second coil conductor pattern running in parallel. The third coil (L3) is configured of a third coil conductor pattern which is formed in a second layer of the plurality of insulating substrate layers, in a position overlapping the first coil conductor pattern and the second coil conductor pattern in plan view.

Description

Common mode choke coil, module parts and electronic equipment

The present invention relates to a common mode choke coil, a module component incorporating the common mode choke coil, and an electronic device including these.

As an invention related to a conventional common mode choke coil, for example, a common node noise filter described in Patent Document 1 is known. 17A and 17B are equivalent circuit diagrams of the common mode filter described in Patent Document 1. FIG.

The common mode filter shown in FIG. 17A includes two first coils 3, 3 and two second coils 6, 6. The common mode filter includes an inductance of the second coil 6, and the first coil 3 and the second coil 6. An attenuation pole is generated at a specific frequency by mutual inductance due to coupling and stray capacitance generated between the first coil 3 and the second coil 6.

International Publication No. 2010/032464

FIG. 17 (B) is an equivalent circuit diagram of the common mode filter shown in FIG. 17 (A), particularly for common mode noise. As described above, in the common mode choke coil as disclosed in Patent Document 1, a series circuit including the second coil 6 and the stray capacitance C is connected in parallel to the first coil 3 which is the main part of the common mode choke coil. It is a structured. Therefore, the differential mode signal passes through not only the first coil 3 but also the series circuit including the second coil 6 and the stray capacitance C. As a result, the series circuit adversely affects the differential mode signal.

An object of the present invention is to provide a common mode choke coil that substantially eliminates the influence on the differential mode signal and widens the attenuation band of the common mode noise, a module component incorporating the common mode choke coil, and an electronic apparatus including the same. It is to provide.

(1) The common mode choke coil of the present invention is configured as follows.

A main circuit including a first coil provided on the first signal line, and a second coil magnetically coupled to the first coil provided on a second signal line that forms a differential transmission line together with the first signal line; A third coil that is magnetically coupled to the first coil and the second coil, and a sub-circuit that includes a capacitor connected to the third coil.

The first coil, the second coil, and the third coil are configured in a stacked body in which a plurality of insulating base material layers are stacked and have a mounting surface.

The first coil and the second coil are each formed of a first coil conductor pattern and a second coil conductor pattern that are formed in the first layer of the plurality of insulating base layers and run parallel to each other. The coil is composed of a third coil conductor pattern formed in the second layer of the plurality of insulating base layers and in a position overlapping the first coil conductor pattern and the second coil conductor pattern in plan view. Is done.

The first layer is composed of a single layer or a plurality of layers, and the second layer is composed of a single layer or a plurality of layers and is provided on the upper layer side or the lower layer side of the first layer.

According to the above configuration, first, the sub-circuit is coupled to the main circuit, so that the attenuation band of the common mode noise is widened. Further, the sub circuit does not exist equivalently for the differential mode signal, and the sub circuit does not affect the differential mode signal. In addition, the first coil conductor pattern and the second coil conductor pattern run in parallel in the same layer, and a third coil conductor pattern is provided at a position that is different from these layers and overlaps in plan view. Thus, the magnetic field coupling degree between the first coil conductor pattern and the third coil conductor pattern is substantially equal to the magnetic field coupling degree between the second coil conductor pattern and the third coil conductor pattern. Furthermore, since the magnitude of these magnetic field coupling degrees is appropriately determined by the distance between the first layer and the second layer, the influence of the sub circuit on the characteristics of the main circuit can be minimized.

(2) It is preferable that the first layer is disposed closer to the mounting surface of the laminate than the second layer. This structure suppresses the parasitic inductance and parasitic capacitance from the terminal electrode formed on the mounting surface to the first coil and the second coil, so that the attenuation of common mode noise is ensured and the differential mode signal is inserted. Loss is suppressed.

(3) The third coil conductor pattern is formed in a first conductor pattern formed on a layer closer to the first layer among a plurality of layers of the second layer, and on a layer far from the first layer. Preferably, the capacitor includes a first conductor pattern and a second conductor pattern facing in the stacking direction, and the capacitor is formed by a capacitance generated between the first conductor pattern and the second conductor pattern. For example, when a dedicated capacitor forming electrode is formed, an eddy current is generated in the capacitor forming electrode. However, according to the above structure, no eddy current is generated, and the first coil, the second coil, and the third coil are generated. There is no decrease in the Q value of the coil, the attenuation amount of the common mode noise is ensured, and the insertion loss of the differential mode signal is suppressed.

(4) The line width of the first conductor pattern is preferably narrower than the line width of the second conductor pattern. With this structure, the capacitance generated between the first coil and the third coil and the capacitance generated between the second coil and the third coil are suppressed. This suppresses the influence of the sub circuit on the differential mode signal. Further, even if there is a positional deviation in the surface direction between the first conductor pattern and the second conductor pattern, it is not easily affected.

(5) It is preferable that the external shape of the said 3rd coil conductor pattern is smaller than the external shape of the 1st coil conductor pattern and the 2nd coil conductor pattern. With this structure, even if the position of the third coil conductor pattern in the plane direction is shifted, the change in the degree of coupling between the third coil and the first coil and the degree of coupling between the third coil and the second coil is small. The characteristic variation is small.

(6) The first layer includes a plurality of layers, and capacitance is formed between the first coil conductor patterns and the second coil conductor patterns formed in different layers of the first layer. It is preferable that For example, if a capacitor forming electrode connected between the first coil conductor and the second coil conductor is separately formed, an eddy current is generated in the capacitor forming electrode. No current is generated, the Q values of the first coil, the second coil, and the third coil are not lowered, the attenuation amount of the common mode noise is ensured, and the insertion loss of the differential mode signal is suppressed.

(7) The module component of the present invention includes a common mode choke coil and an ESD protection element. The common mode choke coil is configured as shown in (1) above, and the ESD protection element is integrated into the laminate and connected to the main circuit. With this structure, it can be handled as a single component including the ESD protection element and the common mode choke coil, and the occupied area on the circuit board is reduced.

(8) It is preferable that the ESD protection element is disposed on the mounting surface side of the multilayer body from the common mode choke coil. With this structure, since the path length from the terminal electrode formed on the mounting surface to the ESD protection element is short and the parasitic component is small, the effect of suppressing the transient voltage is enhanced.

(9) The module component of the present invention includes a fourth coil and a fifth coil inserted in series with the first signal line to provide the ESD protection element, and the ESD protection element includes the first protection element. It is preferable that the connection point between the four coils and the fifth coil is connected between the ground and the ground, and the fourth coil and the fifth coil are configured to make a Japanese-style connection.

The above configuration acts in a direction in which the inductance component generated in the ESD current path of the ESD protection element is canceled. That is, the equivalent series inductance due to the provision of the ESD protection element is suppressed, and the peak voltage during ESD protection can be further suppressed.

(10) When the module component of the present invention includes an ESD protection element between the first signal line and the second signal line,
A fourth coil and a fifth coil inserted in series with the first signal line; a sixth coil and a seventh coil inserted in series with the second signal line;
The ESD protection element includes a first Zener diode, a second Zener diode, and a third Zener diode,
The first Zener diode and the second Zener diode are connected in series between a connection point between the fourth coil and the fifth coil and a connection point between the sixth coil and the seventh coil. ,
The third Zener diode is connected between a connection point of the first Zener diode and the second Zener diode and a ground;
The fourth coil and the fifth coil are connected in a Japanese-style manner,
The sixth coil and the seventh coil are connected in a Japanese-style manner.
A configuration is preferred.

With the above configuration, the equivalent series inductance due to the provision of the ESD protection element is suppressed, and the peak voltage during ESD protection can be further suppressed.

(11) An electronic device of the present invention includes a common mode choke coil having a differential transmission line, and an electronic circuit connected to the differential transmission line. The common mode choke coil is configured as shown in (1) above. With this structure, when the electronic circuit handles a signal over a wide band, common mode noise over the wide band is suppressed, and differential signals are input and output without affecting the differential mode signal.

(12) An electronic device of the present invention includes the module component according to any one of (7) to (10) above, a differential transmission line, and an electronic circuit connected to the differential transmission line. With this structure, when the electronic circuit handles a signal over a wide band, common mode noise over the wide band is suppressed, and differential signals are input and output without affecting the differential mode signal. Furthermore, the transient voltage applied from the outside etc. is suppressed.

According to the present invention, there is provided a common mode choke coil that substantially eliminates the influence on the differential mode signal and widens the attenuation band of the common mode noise, a module component that incorporates the common mode choke coil, and an electronic apparatus including the same. Composed.

FIG. 1 is a circuit diagram of a module component 101 according to an embodiment of the present invention. FIG. 2A is an equivalent circuit diagram regarding common mode noise of the common mode choke coil 10, and FIG. 2B is an equivalent circuit diagram regarding differential mode signals of the common mode choke coil 10. FIG. 3A shows the frequency characteristics of insertion loss with respect to common mode noise. FIG. 3B is a diagram illustrating frequency characteristics of insertion loss of the first resonance circuit and the second resonance circuit alone. FIG. 3C is a diagram illustrating the frequency characteristics of the insertion loss of the third resonance circuit. FIG. 4 is a diagram illustrating frequency characteristics of reactances of the third resonance circuit, the first resonance circuit, and the second resonance circuit, and frequency characteristics of insertion loss with respect to common mode noise. FIG. 5 is a perspective view of each conductor pattern inside the module component 101 seen through. FIG. 6 is a front view seen through each conductor pattern inside the module component 101. FIG. 7 is a plan view showing a conductor pattern formed on each insulating base material layer of the module component 101. FIG. 8 is a block diagram of an electronic device 200 according to the present invention. FIG. 9 is a circuit diagram of the module component 102 including two transient voltage suppressors. FIGS. 10A and 10B are diagrams illustrating the relationship between the mutual inductance due to the coupling between the inductor La and the inductor Lb and the inductance component generated in the path of the ESD current. FIG. 11 is a plan view showing a connection structure of the transient voltage suppressor 21 to the signal line. FIG. 12 is a perspective view showing the internal structure of the transient voltage suppressor 21. FIG. 13A is a plan view showing the configuration of the ESD protection element 1, and FIG. 13B is a longitudinal sectional view of the ESD protection element 1. FIG. 14 is a circuit diagram of the ESD protection element 1. FIG. 15 is a circuit diagram of a transient voltage suppressor. FIG. 16 is a plan view showing a connection structure of the matching circuit 31 and the ESD protection element 1 to the signal line. FIG. 17A is an equivalent circuit diagram of the common mode filter described in Patent Document 1, and FIG. 17B is an equivalent circuit diagram of the common mode filter, particularly for common mode noise.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a module component 101 according to an embodiment of the present invention. The module component 101 includes a common mode choke coil 10 and a transient voltage suppressor 20. The common mode choke coil 10 includes a main circuit MC and a sub circuit SC. The main circuit MC is provided on a first coil L1 provided on the first signal line SL1 and a second signal line SL2 that forms a differential transmission line together with the first signal line SL1, and is magnetically coupled to the first coil L1. And the second coil L2. The sub circuit SC includes a third coil L3 that is magnetically coupled to the first coil L1 and the second coil L2, and a capacitor C3 connected to the third coil L3.

As shown by a symbol M1 in FIG. 1, the first coil L1 and the second coil L2 are magnetically coupled. The dot marks shown in the first coil L1 and the second coil L2 indicate the polarity of mutual coupling. Further, as indicated by reference numerals M2a and M2b in FIG. 1, the third coil L3 is magnetically coupled to the first coil L1 and the second coil L2, respectively.

1, the transient voltage suppressor 20 includes an ESD protection element 2 and inductors La, Lb, Lc, and Ld. In the present embodiment, the inductors La and Lb are connected in series to the first signal line SL1, and the inductors Lc and Ld are connected in series to the second signal line SL2. The dot marks shown in the inductors La and Lb indicate the polarity of coupling between the inductors La and Lb. Similarly, the dot mark shown to the inductor Lc and the inductor Ld represents the polarity of the coupling | bonding of the inductor Lc and the inductor Ld. These inductors La, Lb, Lc, and Ld constitute an impedance matching circuit of the ESD protection element 2 for the differential transmission line.

The inductors La, Lb, Lc, and Ld correspond to “fourth coil”, “fifth coil”, “sixth coil”, and “seventh coil”, respectively, according to the present invention.

The ESD protection element 2 includes three Zener diodes Da, Db, Dc, and a series circuit of Zener diodes Da, Db between a connection point between the inductor La and the inductor Lb and a connection point between the inductor Lc and the inductor Ld. Is connected. The Zener diodes Da and Db are connected in opposite directions, and the Zener diode Dc is connected between the connection point of the Zener diodes Da and Db and the ground.

The zener diodes Da, Db, and Dc correspond to “first zener diode”, “second zener diode”, and “third zener diode” according to the present invention, respectively.

The inductor La and the inductor Lb are connected in a Japanese-style manner. Further, the inductor Lc and the inductor Ld are connected in a Japanese-style manner. As will be described later, an equivalent negative inductance element is connected in series to the Zener diode Da by the summing connection of the inductor La and the inductor Lb, and the equivalent series inductance of the Zener diode Da is suppressed. Similarly, an equivalent negative inductance element is connected in series to the Zener diode Db by the summing connection of the inductor Lc and the inductor Ld, and the equivalent series inductance of the Zener diode Db is suppressed. This effectively suppresses the peak voltage during ESD protection.

FIG. 2A is an equivalent circuit diagram for the common mode noise of the common mode choke coil 10, and FIG. 2B is an equivalent circuit diagram for the differential mode signal of the common mode choke coil 10. The first signal line SL1 and the second signal line SL2 constitute one differential line. The first coil L1 and the second coil L2 are magnetically coupled with a polarity that cancels common mode noise propagating through the differential line. That is, the first coil L1 and the second coil L2 are differentially connected to the common mode noise, and are summed to the differential mode signal.

As shown in FIGS. 2A and 2B, the first resonance circuit is configured by the first coil L1 and the first capacitor C1 connected in parallel to the first coil L1, and the second coil L2 and the first capacitor C1 are connected in parallel to the first coil L1. A second resonance circuit is configured with the second capacitor C2.

As for the common mode noise, as shown in FIG. 2A, a third resonance circuit is configured by a sub-circuit including a third coil L3 and a third capacitor C3. The third coil L3 is magnetically coupled to the first coil L1 and the second coil L2, thereby forming a multiple resonance circuit including a first resonance circuit, a second resonance circuit, and a third resonance circuit.

Regarding the differential mode signal, since the first coil L1 and the second coil L2 are not coupled, there is no magnetic field coupling the first coil L1, the second coil L2, and the third coil L3. Therefore, as for the differential mode signal, as shown in FIG. 2B, the sub circuit SC does not exist equivalently, and the sub circuit SC does not influence the differential mode signal. Note that capacitors Cp1 and Cp2 shown in FIG. 2B are stray capacitances generated between the first coil L1 and the second coil L2.

FIG. 3A shows the frequency characteristics of insertion loss with respect to common mode noise. FIG. 3B is a diagram illustrating frequency characteristics of insertion loss of the first resonance circuit and the second resonance circuit alone. FIG. 3C is a diagram illustrating the frequency characteristics of the insertion loss of the third resonance circuit. FIG. 4 is a diagram illustrating frequency characteristics of reactances of the third resonance circuit, the first resonance circuit, and the second resonance circuit, and frequency characteristics of insertion loss with respect to common mode noise. In FIG. 4, the upper stage is a diagram illustrating frequency characteristics of reactance of the third resonance circuit, the first resonance circuit, and the second resonance circuit alone. The middle stage is a diagram showing frequency characteristics of reactance in a state where the third resonance circuit is coupled to the first resonance circuit and the second resonance circuit. The lower diagram shows the frequency characteristics of insertion loss with respect to common mode noise, and is the same diagram as FIG.

The resonance frequency of the first resonance circuit and the second resonance circuit alone is f0, and the resonance frequency of the third resonance circuit alone is f1, but these resonance circuits are coupled to each other as shown in FIG. The frequencies are displaced to f01 and f11, respectively, and the frequency band between f01 and f11 is expanded.

In the present embodiment, as shown in FIG. 3A, common mode noise is particularly generated for a predetermined band having a frequency f01 (3 GHz) as a center frequency and a predetermined band having a frequency f11 (5 GHz) as a center frequency. Is suppressed.

By setting the resonance frequency f0 of the first resonance circuit and the second resonance circuit alone and the resonance frequency f1 of the third resonance circuit alone, center frequencies f01 and f11 in the frequency band in which the common mode noise is suppressed. Thus, a frequency band for suppressing common mode noise can be determined.

According to the present embodiment, the sub-circuit SC is coupled to the main circuit MC, so that the attenuation band of common mode noise is widened. Further, the sub circuit SC does not exist equivalently for the differential mode signal, and the sub circuit SC does not affect the differential mode signal.

FIG. 5 is a perspective view in which each conductor pattern inside the module component 101 is seen through. FIG. 6 is a front view seen through each conductor pattern in the module component 101. FIG. 7 is a plan view showing a conductor pattern formed on each insulating base material layer of the module component 101. These conductor patterns are obtained by patterning Cu foil, for example. The thickness of the conductor pattern is about 4 μm to 8 μm. The distance between adjacent conductor patterns is about 20 μm to 40 μm. The interlayer distance between conductor patterns adjacent in the stacking direction is also about 20 to 40 μm.

The module component 101 is configured as a laminated body 100 in which a plurality of insulating base material layers S1 to S17 are laminated. The lower surface of the laminate 100 shown in FIG. 6 is a mounting surface UF for mounting the module component 101 on the circuit board. These insulating base layers S1 to S17 are resin layers such as LCP (liquid crystal polymer).

In FIG. 7, the insulating base layer S1 is the lowermost layer, and the insulating base layer S17 is the uppermost layer. Terminal electrodes P1, P2, P3, P4, and P _GND are formed on the mounting surface UF of the insulating base layer (hereinafter simply “base layer”) S1. In the base material layers S10 to S14, first coil conductor patterns L1a to L1e, second coil conductor patterns L2a to L2e, first coil conductor patterns L1a to L1e, an interlayer connection conductor, and a second coil conductor Interlayer connection conductors for connecting the conductor patterns L2a to L2e to each other are formed. A helical first coil L1 is constituted by the first coil conductor patterns L1a to L1e and the interlayer connection conductors connecting these patterns. Similarly, a helical second coil L2 is configured by the second coil conductor patterns L2a to L2e and the interlayer connection conductors that connect these layers. The first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e are loop-shaped conductor patterns that run parallel to each other in each of the base layers S10 to S14. These base material layers S10 to S14 correspond to the “first layer” in the present invention. The first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e run side by side in each layer, but the relationship between the inner periphery and the outer periphery is switched for each layer. Thereby, the inductances of the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e are equalized. Further, as will be described later, the stray capacitance formed between the layers is equalized.

The third coil conductor patterns L3a and L3b are formed on the base material layers S15 and S16. The third coil conductor patterns L3a and L3b are formed at positions overlapping the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e in plan view. The base material layers S15 and S16 correspond to the “second layer” in the present invention.

The second layer is provided on the upper layer side of the first layer. That is, unlike the base material layers S10 to S14, the base material layers S15 and S16 are base material layers outside the range of the laminated portion of the base material layers S10 to S14.

Further, the first layer (S10 to S14) is arranged on the mounting surface UF side of the laminate 100 from the second layer (S15, S16). In other words, the second layer (S15, S16) is disposed on the upper surface TF side of the stacked body 100 from the first layer (S10 to S14).

The first coil conductor patterns L1a to L1e face each other in the stacking direction with one layer interposed therebetween. For example, the first coil conductor pattern L1a formed on the base material layer S10 and the first coil conductor pattern L1c formed on the base material layer S12 face each other in the stacking direction, and a stray capacitance is formed therebetween. . Similarly, the second coil conductor pattern L2a and the second coil conductor pattern L2c face each other in the stacking direction, and a stray capacitance is formed therebetween. Further, the first coil conductor pattern L1b formed on the base material layer S11 and the first coil conductor pattern L1d formed on the base material layer S13 face each other in the stacking direction, and a stray capacitance is formed therebetween. . Similarly, the second coil conductor pattern L2b and the second coil conductor pattern L2d face each other in the stacking direction, and a stray capacitance is formed therebetween.

As described above, the inductance components of the first coil conductor patterns L1a to L1e constitute the first coil L1 shown in FIG. 1, and the stray capacitance generated between the conductor patterns in the stacking direction causes the first capacitor C1. Constitute. Similarly, the inductance components of the second coil conductor patterns L2a to L2e constitute the second coil L2 shown in FIG. 1, and the stray capacitance generated between the conductor patterns in the stacking direction constitutes the second capacitor C2. To do.

Incidentally, if the stray capacitances constituting the first capacitor C1 and the second capacitor C2 are constituted by stray capacitances between the conductive patterns of adjacent layers, the stray capacitance fluctuates greatly due to the misalignment in the surface direction of the base material layer. As in the present embodiment, by causing the conductor patterns to face each other in the stacking direction with one base material layer interposed therebetween, fluctuations in stray capacitance due to the stacking error are suppressed.

Among the third coil conductor patterns L3a and L3b, the first conductor pattern L3a is formed on the base layer S15 on the side close to the first layer (S10 to S14) of the second layer (S15, S16). Of the third coil conductor patterns L3a and L3b, the second conductor pattern L3b is formed on the base material layer S16 far from the first layer (S10 to S14). The first conductor pattern L3a and the second conductor pattern L3b face each other in the stacking direction. The outer peripheral end of the first conductor pattern L3a is connected to the outer peripheral end of the second conductor pattern L3b via an interlayer connection conductor. The stray capacitance generated between the first conductor pattern L3a and the second conductor pattern L3b constitutes the third capacitor C3 shown in FIG.

The line width of the first conductor pattern L3a is about 30 μm, and the line width of the second conductor pattern L3b is about 100 μm. That is, the line width of the first conductor pattern L3a is narrower than the line width of the second conductor pattern L3b, and the first conductor pattern L3a is substantially the same as the second conductor pattern L3b over the entire length in plan view from the stacking direction. Overlap. With this structure, stray capacitance generated between the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e and the third coil conductor patterns L3a and L3b is suppressed. As a result, the first coil L1 by the first coil conductor patterns L1a to L1e and the second coil L2 and the third coil L3 by the second coil conductor patterns L2a to L2e are coupled by a magnetic field and are hardly electrically coupled. This electric field coupling is a coupling in which a capacitance is generated between the first coil L1 and the second coil L2 via the third coil L3, and thus has an adverse effect on the differential mode signal. In the present embodiment, since the first coil L1 and the second coil L2 are coupled to the third coil L3 almost only by a magnetic field, the influence of the sub circuit on the differential mode signal is suppressed. Further, even if there is a positional deviation in the surface direction between the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e, it is not easily affected.

The outer shapes of the third coil conductor patterns L3a and L3b are smaller than the outer shapes of the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e. For example, in FIG. 6, the outer width W3 of the third coil conductor patterns L3a and L3b is smaller than the outer width W12 of the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e.

As described above, the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e run in parallel in the same layer, and are in different layers and overlap with each other in plan view. Since the conductor patterns L3a and L3b are provided, the magnetic field coupling degree M2a between the first coil conductor patterns L1a to L1e and the third coil conductor patterns L3a and L3b, the second coil conductor patterns L2a to L2e, The magnetic field coupling degree M2b with the three-coil conductor patterns L3a and L3b is substantially equal. Further, the magnitudes of the magnetic field coupling degrees M2a and M2b are appropriately determined by the distance between the first layer (S10 to S14) and the second layer (S15 and S16). The influence of SC can also be suppressed to the minimum.

Further, since the first layer (S10 to S14) is arranged on the mounting surface side of the multilayer body from the second layer (S15, S16), the terminal electrodes P1, P2, P3, P4 formed on the mounting surface UF. To the first coil L1 and the second coil L2, the parasitic inductance and the parasitic capacitance are suppressed. Thereby, the attenuation amount of the common mode noise is ensured, and the insertion loss of the differential mode signal is suppressed.

As shown in FIGS. 1 and 6, the transient voltage suppressor 20 including the ESD protection element 2 and the inductors La, Lb, Lc, and Ld includes the common mode choke coil 10 including the main circuit MC and the sub circuit SC. Further, the laminated body 100 is disposed on the mounting surface UF side. With this structure, since the path length from the terminal electrode formed on the mounting surface to the transient voltage suppressor 20 is short and the parasitic component is small, the effect of suppressing the transient voltage is high.

Here, in the module component 101, a flow prevention dummy pattern that is not directly related electrically will be described. In FIG. 7, flow preventing dummy patterns DP1c, DP1d, DP1e, DP1f, and DP1g are formed on the base material layers S10, S11, S12, and S13, respectively. In addition, flow preventing dummy patterns DP1a, DP2a, DP3a, DP4a are formed on the base material layer S5. Similarly, flow preventing dummy patterns DP1b, DP2b, DP3b, DP4b are formed on the base material layer S6.

These dummy patterns for flow prevention disperse each conductor pattern formed on the base material layers S5, S6, S10 to S14 or the base material layers adjacent thereto uniformly within the surface of the base material layers. This suppresses the resin from flowing unevenly during the lamination heating press, and the shape of each conductor pattern is maintained as designed. In addition, since the unevenness on the upper surface of the laminated body is small and smooth after the heat pressing, picking up by the mounter is easy when the module component 101 is surface-mounted on the circuit board. Similarly, since the unevenness is small and smooth on the mounting surface of the laminated body, the mounting property to the circuit board is improved.

For example, the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e formed on the base material layers S10 to S14 are shifted from the center of each base material layer to the left in FIG. Therefore, flow preventing dummy patterns DP1c, DP1d, DP1e, DP1f, and DP1g are formed near the right end of each base material layer.

In addition, in the base material layers S5 and S6, cavity openings CAa and CAb for accommodating the ESD protection element 2 (see FIG. 6) are formed, respectively. The base material layer in which the cavity opening is simply formed easily extends in the X-axis direction, the Y-axis direction, or both directions. However, the base material layers S5 and S6 have the flow preventing dummy patterns DP1a, DP2a, DP3a, DP4a, DP1b. , DP2b, DP3b, and DP4b are formed, respectively, so that the “elongation” of the base material layers S5 and S6 and the base material layers adjacent thereto is suppressed. Thereby, the shape of the cavity is maintained.

Among the plurality of anti-flow dummy patterns, the anti-flow dummy patterns DP1a, DP1b, DP1c, DP1d, DP1e, DP1f, and DP1g are patterns that are long in the Y-axis direction, and therefore have an effect of suppressing the expansion in the Y-axis direction. high. Further, since the flow preventing dummy patterns DP2a, DP3a, DP4a, DP2b, DP3b, and DP4b are long patterns in the X-axis direction, the effect of suppressing the expansion in the X-axis direction is high.

Among the plurality of anti-flow dummy patterns, the anti-flow dummy patterns DP1a, DP1b, DP1c, DP1d, DP1e, DP1f, DP1g, DP2a, DP3a, DP2b, DP3b extend in the peripheral direction of each base material layer. Two rows are arranged in the radial direction from the center of the material layer. Each flow prevention dummy pattern is disposed discontinuously (divided) in the peripheral direction of each base material layer. With this structure, eddy currents are prevented from flowing through these flow preventing dummy patterns by the magnetic flux passing through the coil openings of the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e. That is, the magnetic field coupling between the first coil conductor patterns L1a to L1e and the second coil conductor patterns L2a to L2e is not inhibited.

In particular, the flow preventing dummy patterns DP2a, DP3a, DP2b, DP3b are shaped so that the dividing positions do not overlap in the radial direction. That is, the dividing position is dispersed. As a result, the eddy current is prevented and elongation in the X-axis direction is effectively suppressed.

Next, an example of the electronic device of the present invention is shown. FIG. 8 is a block diagram of an electronic device 200 according to the present invention. The electronic device 200 includes a module component 101, a differential transmission line DTL, a USB connector CN, a USB device controller 201 connected to the differential transmission line DTL via the module component 101, and a CPU 202 connected to the USB device controller 201. Is provided. The configuration of the module component 101 is as shown in FIGS.

According to this embodiment, common mode noise superimposed on the differential transmission line DTL is suppressed by the common mode choke coil 10 in the module component 101. Further, for example, a transient voltage such as ESD entering via the USB connector CN is suppressed by the ESD protection element 2 in the module component 101, and the transient voltage applied to the USB device controller 201 is suppressed.

In the example shown in FIG. 8, the module component 101 is connected to the differential transmission line. However, the common mode choke coil that does not include the transient voltage suppressor 20 is configured, and the common mode choke coil is differentially connected. You may connect to a transmission line.

Next, other configurations of the transient voltage suppressor provided in the module parts will be described.

FIG. 9 is a circuit diagram of the module component 102 including two transient voltage suppressors. The module component 102 includes a common mode choke coil 10 and two transient voltage suppressors 21. The configuration and operation of the common mode choke coil 10 are the same as those shown in FIG.

9, the transient voltage suppressor 21 includes the ESD protection element 1 and inductors La, Lb, and ESL1. The ESD protection element 1 is connected between a connection point CN1 between the inductor La and the inductor Lb and the ground. The inductor ESL1 is an inductance component (equivalent series inductance) generated in the ESD current path (inductor generated between the connection point CN1 of the inductors La and Lb and the ground). The inductors La and Lb are impedance matching circuits with the ESD protection element 1.

The inductor La and the inductor Lb are connected in a Japanese-style manner. The inductors La and Lb correspond to the “fourth coil” and the “fifth coil” according to the present invention, respectively.

10 (A) and 10 (B) are diagrams showing the relationship between the mutual inductance due to the coupling between the inductor La and the inductor Lb and the inductance component generated in the path of the ESD current. In FIG. 10A, a capacitor Cd1 is a parasitic capacitance generated in the ESD protection element 1. A transformer formed by coupling the inductor La and the inductor Lb shown in FIG. 10A is represented by a T-type equivalent circuit as shown in FIG. Thus, the mutual inductance (−M) due to the coupling between the inductor La and the inductor Lb is equivalently connected in series between the connection point CN1 and the ground. When the coupling coefficient between the inductor La and the inductor Lb is represented by k, the inductance of the inductor La is represented by La, and the inductance of the inductor Lb is represented by Lb, M = k × √ (La × Lb).

Since the inductor La and the inductor Lb are connected in a oscillating manner, the mutual inductance (−M) is a negative inductance. Therefore, the inductance component generated in the ESD current path is canceled. If the absolute value of the mutual inductance (−M) is equal to the inductance of the inductor ESL1, the inductance component of the ESD current path is zero. This effectively suppresses the peak voltage during ESD protection.

As described above, the transient voltage suppressor 21 functions as a three-terminal element including the ESD protection element 1, the matching circuit for the ESD protection element 1, and the ESL cancellation circuit.

FIG. 11 is a plan view showing a connection structure of the transient voltage suppressor 21 to the signal line. In this example, the transient voltage suppressor 21 is a rectangular parallelepiped chip component, and includes terminals Pa, Pb, and P _GND on the bottom surface. The substrate on which the transient voltage suppressor 21 is mounted has a signal line formed by a conductor pattern, and the terminals Pa and Pb of the transient voltage suppressor 21 are connected to the two signal lines, respectively. That is, the transient voltage suppressor 21 is mounted on the base material so as to be inserted in the middle of the signal line. Also, the base material is formed a ground electrode terminal P _GND transient voltage suppressor 21 is connected to the ground electrode. The terminal P _GND is formed between the terminals Pa and Pb. Therefore, the transient voltage suppressor 21 is mounted so as to straddle the ground electrode.

As shown in FIG. 11, if the transient voltage suppressor 21 is connected (inserted) in series to the signal line, the arrangement of the conductor pattern of the signal line and the transient voltage suppressor 20 is simplified. Moreover, impedance mismatch of the signal line can be reduced.

FIG. 12 is a perspective view showing the internal structure of the transient voltage suppressor 21. In FIG. 12, the thickness direction (Z-axis direction) is extended. The transient voltage suppressor 21 includes the ESD protection element 1 and its redistribution layer REL. As will be described later, the ESD protection element 1 is a semiconductor substrate on which a plurality of diode elements are formed. Inductors La and Lb are formed in the redistribution layer REL of the semiconductor substrate. The upper surface of the redistribution layer REL is a mounting surface of the transient voltage suppressor 21, and terminals Pa, Pb, and _PGND are formed on this surface.

FIG. 13A is a plan view showing the configuration of the ESD protection element 1, and FIG. 13B is a longitudinal sectional view of the ESD protection element 1. FIG. FIG. 14 is a circuit diagram of the ESD protection element 1.

In the ESD protection element 1, N-type epitaxial layers Nepi1 and Nepi2 are formed on a P-type semiconductor substrate Psub. With this structure, diodes D11 and D21 are formed between the P-type semiconductor substrate Psub and the N-type epitaxial layer Nepi1.

In the N-type epitaxial layer Nepi1, a single N-type region is formed, and a Zener diode D3 is formed between the N-type region and the P-type semiconductor substrate Psub.

Two P-type regions are formed in the N-type epitaxial layer Nepi2 and diodes D12 and D22 are formed between the P-type region and the N-type epitaxial layer Nepi2.

Two N-type regions are further formed in the N-type epitaxial layer Nepi2. These N-type regions act as cathode terminals of the diodes D11 and D21.

A trench TR for electrical insulation is formed around the N-type region formed in the N-type epitaxial layers Nepi1 and Nepi2. One of the two N-type regions formed in the N-type epitaxial layer Nepi2 and one of the two P-type regions are connected by an Al wiring and used as the terminal T1. Similarly, the other of the two N-type regions and the other of the two P-type regions are connected by an Al-aluminum wiring and used as a terminal T2.

The arrow in FIG. 13B indicates the direction of current flowing through the semiconductor substrate Psub. The ESD protection element 1 having the two terminals T1 and T2 is configured by the structure described above.

For example, when the transient voltage suppressor of this embodiment is applied to a circuit that performs high-speed data communication in accordance with the USB 3.1 Gen2 standard, the ESD protection element needs to have a low capacity in order to pass a high-frequency signal. This is because it is necessary to increase the self-resonance frequency due to the parasitic capacitance of the ESD protection element and the equivalent series inductance (ESL) in order to pass a high-frequency signal. However, there is a problem that generally low capacity capacitors have low ESD protection performance. In the present embodiment, as described above, in order to perform impedance matching, a T-type matching circuit including two inductors that are coupled in a coupled manner using the capacitance of the ESD protection element 1 is configured. As a result, the ESL of the ESD protection element 1 can be canceled, the self-resonance frequency of the ESD protection element 1 can be increased, and the high frequency without increasing the parasitic capacitance of the ESD protection element 1 (that is, while ensuring the ESD protection performance). A signal can be passed.

Next, an example in which the matching circuit 31 that performs matching with the ESD protection element 1 and cancellation of ESL and the ESD protection element 1 are configured by individual components will be described with reference to FIGS. 15 and 16.

FIG. 15 is a circuit diagram of a transient voltage suppressor. This circuit corresponds to the transient voltage suppressor 21 shown in FIG. The matching circuit 31 is configured as one element in which the rewiring layer portion illustrated in FIG. 12 is independent, and includes terminals Pa, Pb, and Pc. Further, the ESD protection element 1 is configured as one element in which the semiconductor substrate 1 portion shown in FIG. 12 is independent, and includes terminals T1 and T2.

FIG. 16 is a plan view showing a connection structure of the matching circuit 31 and the ESD protection element 1 to the signal line. In this example, both the matching circuit 31 and the ESD protection element 1 are rectangular parallelepiped chip components, and the matching circuit 31 is mounted on the base material so as to be inserted in the middle of the signal line. In the ESD protection element 1, the terminal T1 is connected to the terminal Pc of the matching circuit 31 through the conductor pattern on the base material, and the terminal T2 is connected to the ground electrode.

Thus, separating the ESD protection element 1 and the matching circuit 31 has an advantage that the ESD protection element 1 having desired characteristics can be selectively used.

<< Other embodiments >>
In FIG. 1, the module component 101 provided with the common mode choke coil 10 and the transient voltage suppressor 20 is shown, but the component of the common mode choke coil 10 alone may be similarly configured as a laminate.

The third coil described above is an example configured with a third conductor pattern formed in a plurality of second layers, but the second layer may be a single layer.

FIG. 6 shows an example in which the “second layer” in which the third coil L3 is formed is arranged on the upper layer side of the “first layer” in which the first coil L1 and the second coil L2 are formed. The vertical relationship between the “first layer” and the “second layer” may be reversed.

6 and 7 show examples in which the common mode choke coil is configured on the resin multilayer substrate, but the common mode choke coil may be configured on the ceramic multilayer substrate in the same manner.

Finally, the above-described embodiment is illustrative in all respects and not restrictive. Modifications and changes can be made as appropriate by those skilled in the art. The scope of the present invention is shown not by the above embodiments but by the claims. Furthermore, the scope of the present invention includes modifications from the embodiments within the scope equivalent to the claims.

C1 ... 1st capacitor C2 ... 2nd capacitor C3 ... 3rd capacitor CAa, CAb ... Cavity opening CN ... USB connector Da, Db, Dc ... Zener diode DP1a, DP1b, DP1c, DP1d, DP1e, DP1f, DP1g ... Flow prevention Dummy pattern DP2a, DP3a, DP4a, DP2b, DP3b, DP4b ... Dummy pattern for flow prevention DTL ... Differential transmission line L1 ... First coil L1a, L1b, L1c, L1d ... First coil conductor pattern L2 ... Second coil L2a, L2b, L2c, L2d ... 2nd coil conductor pattern L3 ... 3rd coil L3a, L3b ... 3rd coil conductor pattern L3a ... 1st conductor pattern L3b of 3rd coil conductor pattern ... 3rd coil conductor pattern Second conductor pattern La, Lb, Lc, L ... inductor MC ... main circuit _{P1, P2, P3, P4,} P GND, Pa, Pb, Pc ... terminal electrodes S1 ~ S17 ... insulating substrate layer SC ... subcircuit SL1 ... first signal line SL2 ... second signal line TF ... Upper surface UF ... Mounting surface 1, 2 ... ESD protection element 3 ... First coil 6 ... Second coil 10 ... Common mode choke coils 20, 21 ... Transient voltage suppressor 100 ... Laminate 101, 102 ... Module component 200 ... Electronics Device 201 ... USB device controller 202 ... CPU

Claims (12)

1. A main circuit including a first coil provided on the first signal line, and a second coil magnetically coupled to the first coil provided on a second signal line constituting a differential transmission line together with the first signal line; ,
   A third coil magnetically coupled to the first coil and the second coil, and a sub-circuit configured to include a capacitor connected to the third coil;
   Have
   The first coil, the second coil, and the third coil are configured as a laminate having a mounting surface in which a plurality of insulating base material layers are laminated,
   The first coil and the second coil are each formed of a first coil conductor pattern and a second coil conductor pattern that are formed in the first layer of the plurality of insulating base layers and run parallel to each other. ,
   The third coil is a third coil formed in a second layer of the plurality of insulating base layers and at a position overlapping the first coil conductor pattern and the second coil conductor pattern in plan view. Consists of conductor patterns for
   The first layer is composed of a single layer or multiple layers,
   The second layer is composed of a single layer or a plurality of layers, and is provided on the upper layer side or the lower layer side of the first layer.
   Common mode choke coil.
2. The common mode choke coil according to claim 1, wherein the first layer is disposed closer to the mounting surface of the multilayer body than the second layer.
3. The third coil conductor pattern is formed in a first conductor pattern formed on a layer closer to the first layer among a plurality of layers of the second layer, and formed on a layer far from the first layer. Including a first conductor pattern and a second conductor pattern facing in the stacking direction;
   The capacitor is constituted by a capacitance generated between the first conductor pattern and the second conductor pattern.
   The common mode choke coil according to claim 1 or 2.
4. The common mode choke coil according to claim 3, wherein a line width of the first conductor pattern is narrower than a line width of the second conductor pattern.
5. The common mode choke coil according to any one of claims 1 to 4, wherein an outer shape of the third coil conductor pattern is smaller than an outer shape of the first coil conductor pattern and the second coil conductor pattern.
6. The first layer is composed of a plurality of layers, and capacitances are formed between the first coil conductor patterns and the second coil conductor patterns formed in different layers of the first layer. The common mode choke coil according to any one of claims 1 to 5.
7. A common mode choke coil and an ESD protection element;
   The common mode choke coil is
   A main circuit including a first coil provided on the first signal line, and a second coil magnetically coupled to the first coil provided on a second signal line constituting a differential transmission line together with the first signal line; ,
   A third coil magnetically coupled to the first coil and the second coil, and a sub-circuit configured to include a capacitor connected to the third coil;
   Have
   The first coil, the second coil, and the third coil are configured as a laminate having a mounting surface in which a plurality of insulating base material layers are laminated,
   The first coil and the second coil are each formed of a first coil conductor pattern and a second coil conductor pattern that are formed in the first layer of the plurality of insulating base layers and run parallel to each other. ,
   The third coil is a third coil formed in a second layer of the plurality of insulating base layers and at a position overlapping the first coil conductor pattern and the second coil conductor pattern in plan view. Consists of conductor patterns for
   The first layer is composed of a single layer or multiple layers,
   The second layer is composed of a single layer or a plurality of layers, and is provided on the upper layer side or the lower layer side of the first layer,
   The ESD protection element is integrated into the laminate and connected to the main circuit.
   Module parts.
8. The module component according to claim 7, wherein the ESD protection element is disposed closer to the mounting surface of the multilayer body than the common mode choke coil.
9. A fourth coil and a fifth coil inserted in series with the first signal line,
   The ESD protection element is connected between a connection point between the fourth coil and the fifth coil and a ground,
   The fourth coil and the fifth coil are connected in a Japanese-style manner.
   The module component according to claim 7 or 8.
10. A fourth coil and a fifth coil inserted in series with the first signal line; a sixth coil and a seventh coil inserted in series with the second signal line;
    The ESD protection element includes a first Zener diode, a second Zener diode, and a third Zener diode,
    The first Zener diode and the second Zener diode are connected in series between a connection point between the fourth coil and the fifth coil and a connection point between the sixth coil and the seventh coil. ,
    The third Zener diode is connected between a connection point of the first Zener diode and the second Zener diode and a ground;
    The fourth coil and the fifth coil are connected in a Japanese-style manner,
    The sixth coil and the seventh coil are connected in a Japanese-style manner.
    The module component according to claim 7 or 8.
11. A common mode choke coil having a differential transmission line, and an electronic circuit connected to the differential transmission line,
    The common mode choke coil is
    A main circuit including a first coil provided on a first signal line and a second coil magnetically coupled to the first coil provided on a second signal line that constitutes the differential transmission line together with the first signal line When,
    A third coil magnetically coupled to the first coil and the second coil, and a sub-circuit configured to include a capacitor connected to the third coil;
    Have
    The first coil, the second coil, and the third coil are configured as a laminate having a mounting surface in which a plurality of insulating base material layers are laminated,
    The first coil and the second coil are each formed of a first coil conductor pattern and a second coil conductor pattern that are formed in the first layer of the plurality of insulating base layers and run parallel to each other. ,
    The third coil is a third coil formed in a second layer of the plurality of insulating base layers and at a position overlapping the first coil conductor pattern and the second coil conductor pattern in plan view. Consists of conductor patterns for
    The first layer is composed of a single layer or multiple layers,
    The second layer is composed of a single layer or a plurality of layers, and is provided on the upper layer side or the lower layer side of the first layer.
    Electronics.
12. An electronic apparatus comprising the module component according to claim 7, the differential transmission line, and an electronic circuit connected to the differential transmission line.

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