WO2019230027A1 - Impedance matching element, and communication device - Google Patents

Impedance matching element, and communication device Download PDF

Info

Publication number
WO2019230027A1
WO2019230027A1 PCT/JP2018/047441 JP2018047441W WO2019230027A1 WO 2019230027 A1 WO2019230027 A1 WO 2019230027A1 JP 2018047441 W JP2018047441 W JP 2018047441W WO 2019230027 A1 WO2019230027 A1 WO 2019230027A1
Authority
WO
WIPO (PCT)
Prior art keywords
impedance matching
terminal
matching element
type doping
region
Prior art date
Application number
PCT/JP2018/047441
Other languages
French (fr)
Japanese (ja)
Inventor
紀行 植木
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to JP2019530846A priority Critical patent/JPWO2019230027A1/en
Publication of WO2019230027A1 publication Critical patent/WO2019230027A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/866—Zener diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/28—Impedance matching networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H5/00—One-port networks comprising only passive electrical elements as network components
    • H03H5/12—One-port networks comprising only passive electrical elements as network components with at least one voltage- or current-dependent element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/18—Input circuits, e.g. for coupling to an antenna or a transmission line
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits

Definitions

  • the present invention relates to an impedance matching element for impedance matching.
  • Patent Document 1 describes an impedance matching circuit that performs impedance matching between an antenna and a high-frequency circuit.
  • Patent Document 1 discloses an impedance matching circuit using a capacitor as an example of an impedance matching circuit.
  • a capacitor used as a matching element is connected in series between the antenna and the high-frequency circuit.
  • the antenna Q is higher than when no impedance matching element is provided. This narrows the width of the band in which the antenna can communicate (a band where a predetermined gain can be obtained).
  • an object of the present invention is to provide an impedance matching element that can perform impedance matching while suppressing a reduction in the bandwidth of the antenna.
  • the impedance matching element includes a semiconductor substrate, a first terminal, and a second terminal.
  • the first terminal is formed on the semiconductor substrate and connected to the antenna.
  • the second terminal is formed on the semiconductor substrate and connected to the high frequency circuit.
  • the semiconductor substrate includes a first region and a second region.
  • the first region has a PN junction structure and has a rectifying action in which a current flows from the first terminal to the second terminal in a steady state.
  • the second region has a PN junction structure and has a rectifying action in which a current flows from the second terminal to the first terminal in a steady state.
  • the first region and the second region are connected between the first terminal and the second terminal and have a breakdown voltage in both directions.
  • the portion of the semiconductor substrate composed of the first region and the second region acts on a high-frequency signal like a capacitor whose capacitance frequency characteristics are opposite to those of a general parallel plate type capacitor. . Specifically, the higher the frequency, the lower the capacitance of this part. Therefore, it is possible to suppress the Q of the antenna from becoming higher than when a normal capacitor is used.
  • the impedance matching element of the present invention preferably has the following configuration.
  • the semiconductor substrate includes a first main surface.
  • a wiring layer is formed on the first main surface.
  • a first terminal and a second terminal are formed on the surface of the wiring layer opposite to the surface that contacts the first main surface.
  • a bidirectional Zener diode is formed using the first region and the second region.
  • a MOSFET having a bidirectional breakdown voltage is formed using the first region and the second region.
  • a transistor having a bidirectional breakdown voltage is formed using the first region and the second region.
  • any semiconductor element having bidirectional breakdown characteristics can be used as an impedance matching element.
  • impedance matching can be performed without narrowing the antenna bandwidth.
  • FIG. 1 is a block diagram showing an example of a communication device 1 including an impedance matching element 10 according to the first embodiment of the present invention.
  • FIG. 2A is a graph showing the frequency characteristics of the capacitance of the bidirectional Zener diode
  • FIG. 2B is a graph showing the frequency characteristics of the imaginary component of the bidirectional Zener diode.
  • FIG. 3A is a graph showing the frequency characteristics of the imaginary component of the impedance of an antenna, a normal capacitor, and a bidirectional Zener diode.
  • FIG. 3B shows a bidirectional Zener diode when a normal capacitor is used.
  • 6 is a graph showing the passing characteristics of the antenna when neither a normal capacitor nor a bidirectional Zener diode is used.
  • FIG. 1 is a block diagram showing an example of a communication device 1 including an impedance matching element 10 according to the first embodiment of the present invention.
  • FIG. 2A is a graph showing the frequency characteristics of the capacitance of the bidirectional Zener di
  • FIG. 4 is a graph showing pass characteristics of the bidirectional Zener diode.
  • FIG. 5 is a side sectional view of the impedance matching element 10 according to the first embodiment of the present invention.
  • FIG. 6 is a perspective view of the impedance matching element 10 according to the first embodiment of the present invention.
  • FIG. 7A is a top view of the impedance matching element 10 according to the first embodiment, and
  • FIG. 7B is a view of an intermediate position of the wiring layer 40 as viewed from the top surface side.
  • C) is a view of the first main surface of the semiconductor substrate 20.
  • FIG. 8A is a side sectional view of an impedance matching element 10A according to the second embodiment of the present invention, and FIG.
  • FIG. 8B is a diagram of the impedance matching element 10A according to the second embodiment of the present invention. It is a top view which shows the positional relationship of each component.
  • FIG. 9A is an equivalent circuit diagram of the impedance matching element 10A according to the second embodiment of the present invention
  • FIG. 9B shows the impedance matching element 10A according to the second embodiment of the present invention.
  • FIG. 9C is an equivalent circuit diagram of a first mode of signal transmission
  • FIG. 9C is an equivalent circuit diagram of a second mode of signal transmission of the impedance matching element 10A according to the second embodiment of the present invention.
  • FIG. 10A is a side cross-sectional view of the impedance matching element 10B according to the third embodiment of the present invention, and FIG.
  • FIG. 10B shows the impedance matching element 10B according to the third embodiment of the present invention. It is an equivalent circuit diagram.
  • FIG. 11A is a side cross-sectional view of an impedance matching element 10C according to the fourth embodiment of the present invention, and FIG. 11B shows an impedance matching element 10C according to the fourth embodiment of the present invention. It is an equivalent circuit diagram.
  • 12A and 12B are functional block diagrams illustrating a configuration example of the high-frequency circuit.
  • FIG. 1 is a block diagram showing an example of a communication device 1 including an impedance matching element 10 according to the first embodiment of the present invention.
  • the communication apparatus 1 includes an antenna 91, a high frequency circuit 92, and an impedance matching element 10.
  • the impedance matching element 10 includes a first terminal P11, a second terminal P12, and a bidirectional Zener diode ZD10.
  • the bidirectional Zener diode ZD10 is connected between the first terminal P11 and the second terminal P12.
  • the antenna 91 is connected to the first terminal P11.
  • the high frequency circuit 92 is connected to the second terminal P12.
  • the impedance matching element 10 is connected in series between the antenna 91 and the high frequency circuit 92.
  • the bidirectional Zener diode ZD10 has a bidirectional breakdown voltage.
  • the bidirectional Zener diode ZD10 has the following various characteristics.
  • FIG. 2A is a graph showing the frequency characteristics of the capacitance of the bidirectional Zener diode ZD10.
  • FIG. 2B is a graph showing the frequency characteristics of the imaginary component of the bidirectional Zener diode ZD10. 2A and 2B, the solid line indicates the characteristic of the bidirectional Zener diode ZD10, and the broken line indicates the characteristic of a normal capacitor.
  • the bidirectional Zener diode ZD10 has a capacitance that decreases as the frequency increases. That is, the frequency dependence of capacitance exhibits a negative characteristic.
  • the capacitance of a normal capacitor increases as the frequency increases. That is, the frequency dependency of capacitance exhibits a positive characteristic.
  • a normal capacitor is a capacitor having a configuration in which a dielectric is disposed between opposing electrodes. In particular, as shown in FIG. 2 (A), the tendency becomes large at a frequency exceeding about 700 MHz, which is currently widely used for communication.
  • the change amount of the imaginary component of the impedance between the terminals with respect to the change amount of the frequency is usually in the region where the frequency dependence of the capacitance is negative. It becomes smaller than the amount of change of the capacitor.
  • the frequency dependence of capacitance shows a negative characteristic in a region exceeding at least about 700 MHz, and the imaginary number of the impedance between terminals with respect to the amount of change in frequency. It can be seen that the component change amount is smaller than the normal capacitor change amount.
  • the relationship between the impedance characteristics of the antenna, the impedance characteristics of a normal capacitor, and the impedance characteristics of the bidirectional Zener diode ZD10 will be considered.
  • FIG. 3A is a graph showing frequency characteristics of an imaginary component of the impedance of an antenna (an antenna having no matching element (for example, an antenna element)), a normal capacitor, and a bidirectional Zener diode.
  • the solid line indicates the characteristic of the bidirectional Zener diode
  • the broken line indicates the characteristic of the normal capacitor
  • the two-dot chain line indicates the characteristic of the antenna alone.
  • the imaginary component of the antenna impedance increases as the frequency increases.
  • the imaginary number component of the normal capacitor impedance and the imaginary number component of the bidirectional Zener diode increase as the frequency increases.
  • the rate of change of the imaginary number component of the bidirectional Zener diode is smaller than the rate of change of the imaginary number component of a normal capacitor.
  • the high frequency band is preferably a frequency band of about 700 MHz or more, for example.
  • the rate of change of the imaginary component of the impedance corresponds to the height of Q. That is, if the rate of change of the imaginary number component of impedance is large, Q is high, and if the rate of change of the imaginary number component of impedance is low, Q is low.
  • the antenna Q is lower when the bidirectional Zener diode is used as the impedance matching element than when a normal capacitor is used as the impedance matching element. More strictly, the Q of the substantial antenna constituted by the antenna and the bidirectional Zener diode is lowered.
  • FIG. 3B is a graph showing the passing characteristics of the antenna when a normal capacitor is used, when a bidirectional Zener diode is used, and when neither a normal capacitor nor a bidirectional Zener diode is used.
  • the solid line indicates the characteristics when the bidirectional Zener diode is used
  • the broken line indicates the characteristics when a normal capacitor is used
  • the two-dot chain line indicates the characteristics of the antenna alone.
  • the pole at the resonance frequency is steeper than the antenna alone.
  • the bidirectional Zener diode is used, the steepness of the pole at the resonance frequency is lowered. That is, the width of the specific band is widened.
  • the bandwidth of the bandwidth is as follows when a normal capacitor is used. About 72%.
  • the width of the ratio band is about 82%. In other words, the reduction in the width of the specific band can be improved by about 10%.
  • FIG. 4 is a graph showing pass characteristics of the bidirectional Zener diode.
  • the bidirectional Zener diode can transmit a high-frequency signal with almost no attenuation in a frequency band of at least about 700 MHz.
  • the impedance matching element 10 composed of the bidirectional Zener diode ZD10 is connected between the antenna 91 and the high-frequency circuit 92, thereby matching the impedance of the antenna 91 and the impedance of the high-frequency circuit 92.
  • a reduction in the width of the communication band of the antenna 91 can be suppressed, and a high-frequency signal can be transmitted with low loss.
  • FIG. 5 is a side sectional view of the impedance matching element 10 according to the first embodiment of the present invention.
  • FIG. 6 is a perspective view of the impedance matching element 10 according to the first embodiment of the present invention. In FIG. 6, the semiconductor substrate of the impedance matching element 10 and the electrode of the wiring layer are illustrated, and the portion formed of the insulating material in the wiring layer is not illustrated.
  • FIG. 7A is a top view of the impedance matching element 10 according to the first embodiment, and FIG. 7B is a view of an intermediate position of the wiring layer 40 as viewed from the top surface side.
  • C) is a view of the first main surface of the semiconductor substrate 20.
  • the impedance matching element 10 includes a semiconductor substrate 20, an insulating film 31, and a wiring layer 40.
  • the semiconductor substrate 20 includes an Nsub layer 21, an N epilayer 22, an N-type doping unit 231, an N-type doping unit 232, a P + type doping unit 241, and a P + type doping unit 242.
  • the semiconductor substrate 20 is formed by a known semiconductor formation process.
  • the Nsub layer 21 is made of an N-type semiconductor and has a flat plate shape.
  • the N epi layer 22 is made of an N-type semiconductor.
  • the N epilayer 22 is formed on one main surface of the Nsub layer 21 by epitaxially growing an N-type semiconductor.
  • the N-type doping part 231 and the N-type doping part 232 are formed in the N epilayer 22.
  • the N-type doping unit 231 and the N-type doping unit 232 are formed by performing partial N-type carrier doping on the N epilayer 22.
  • the N-type doping part 231 and the N-type doping part 232 are formed at a height (depth) in contact with the Nsub layer 21.
  • the N-type doping part 231 and the N-type doping part 232 have a substantially rectangular parallelepiped shape.
  • the N-type doping part 231 and the N-type doping part 232 are arranged apart from each other by a predetermined distance in the X direction.
  • the P + type doping portion 241 and the P + type doping portion 242 are on the surface of the N epilayer 22 (the surface opposite to the surface in contact with the Nsub layer 21), That is, it is formed on the first main surface side of the semiconductor substrate 20.
  • the P + type doping part 241 and the P + type doping part 242 are formed by performing partial P type carrier doping on the N epilayer 22.
  • the P + type doping part 241 overlaps with the N type doping part 231 in plan view (viewed in the Z-axis direction in FIG. 5), and has a predetermined height (depth, that is, along the Z-axis direction in FIG. 5). Length).
  • the P + type doping unit 241 is joined to the N type doping unit 231.
  • a first PN junction is realized by the junction between the P + type doping unit 241 and the N type doping unit 231.
  • the PN junction corresponds to a first region having a rectifying action for flowing a current from the first terminal P11 to the second terminal P12 in a steady state.
  • the steady state means a state in which no breakdown occurs.
  • the P + type doping part 242 overlaps with the N type doping part 232 in a plan view (viewed in the Z-axis direction in FIG. 5), and has a predetermined height (depth, ie, along the Z-axis direction in FIG. 5). Length).
  • the P + type doping part 242 is joined to the N type doping part 232.
  • a second PN junction is realized by the junction between the P + type doping unit 242 and the N type doping unit 232.
  • the PN junction corresponds to a second region having a rectifying action for flowing a current from the second terminal P12 to the first terminal P11 in a steady state.
  • the N-type doping unit 231 and the N-type doping unit 232 are in contact with the Nsub layer 21, the Nsub layer 21 serves as a current path that electrically connects the first region and the second region.
  • the insulating film 31 is made of SiO 2 , SiN or the like. It is formed on the surface of the N epi layer 22.
  • the wiring conductor 321 and the wiring conductor 322 are made of a metal having high conductivity such as Al.
  • the wiring conductor 321 and the wiring conductor 322 are formed on the surface of the insulating film 31 (surface opposite to the surface in contact with the N epitaxial layer 22).
  • the wiring conductor 321 and the wiring conductor 322 are substantially rectangular in a plan view and are separated by a predetermined distance in the X direction.
  • the wiring conductor 321 overlaps the P + type doping part 241 in plan view.
  • the wiring conductor 321 is connected to the P + type doping part 241 through a via conductor that penetrates the insulating film 31.
  • the wiring conductor 322 overlaps the P + type doping part 242 in plan view.
  • the wiring conductor 322 is connected to the P + type doping part 242 through a via conductor that penetrates the insulating film 31.
  • the wiring layer 40 includes an insulating resin 41, a via conductor 421, a via conductor 422, a wiring conductor 431, a wiring conductor 432, a plating layer 441, and a plating layer 442.
  • the insulating resin 41 is made of a resin excellent in workability, such as an epoxy resin.
  • the insulating resin 41 is formed on the surface of the insulating film 31.
  • the wiring conductor 431 and the wiring conductor 432 are made of a metal having high conductivity and excellent workability, such as Cu.
  • the insulating resin 41 is disposed in the vicinity of the surface opposite to the contact surface with the insulating film 31 (the surface of the impedance matching element 10).
  • the wiring conductor 431 and the wiring conductor 432 are substantially rectangular in a plan view and are separated by a predetermined distance in the X direction.
  • the wiring conductor 431 overlaps the wiring conductor 321 in plan view.
  • the wiring conductor 431 is connected to the wiring conductor 321 via a via conductor 421 extending in the thickness direction (Z direction) of the insulating resin 41.
  • the wiring conductor 432 overlaps the wiring conductor 322 in plan view.
  • the wiring conductor 432 is connected to the wiring conductor 322 via a via conductor 422 extending in the thickness direction (Z direction) of the insulating resin 41.
  • the plating layer 441 and the plating layer 442 are formed by, for example, Ni / Au plating.
  • the plating layer 441 overlaps a part of the wiring conductor 431 and is exposed to the surface of the impedance matching element 10 through the opening 451. This exposed portion corresponds to the “first terminal” of the present invention.
  • the plated layer 442 overlaps a part of the wiring conductor 432 and is exposed to the surface of the impedance matching element 10 through the opening 452. This exposed portion corresponds to the “second terminal” of the present invention. With this configuration, the first terminal and the second terminal of the impedance matching element 10 are formed on the semiconductor substrate 20.
  • the impedance matching element 10 having the bidirectional Zener diode ZD10 having the above-described bidirectional breakdown voltage can be realized. Furthermore, the impedance matching element 10 can improve the freedom degree of arrangement
  • FIG. 1st terminal and a 2nd terminal by providing the wiring layer 40.
  • FIG. 8A is a side sectional view of an impedance matching element 10A according to the second embodiment of the present invention
  • FIG. 8B is a diagram of the impedance matching element 10A according to the second embodiment of the present invention. It is a top view which shows the positional relationship of each component.
  • FIG. 9A is an equivalent circuit diagram of the impedance matching element 10A according to the second embodiment of the present invention
  • FIG. 9B shows the impedance matching element 10A according to the second embodiment of the present invention.
  • FIG. 9C is an equivalent circuit diagram of a first mode of signal transmission
  • FIG. 9C is an equivalent circuit diagram of a second mode of signal transmission of the impedance matching element 10A according to the second embodiment of the present invention.
  • the impedance matching element 10A according to the second embodiment includes the first Compared to the impedance matching element 10 according to the embodiment, it is different in that it is constituted by more diodes.
  • the concept of the other basic configuration of the impedance matching element 10A is the same as that of the impedance matching element 10, and the description of the same part is omitted.
  • the wiring portion is not shown, but the impedance matching element 10A includes a wiring portion similar to that of the impedance matching element 10 according to the first embodiment. It is preferable.
  • the impedance matching element 10A includes a semiconductor substrate 20A and an insulating film 31.
  • the semiconductor substrate 20A includes a Psub layer 27, an N epi layer 22, an N type doping unit 23, a P + type doping unit 241A, a P + type doping unit 242A, an N + type doping unit 251A, and an N + type doping unit 252A.
  • the semiconductor substrate 20A is formed by a known semiconductor formation process.
  • the Psub layer 27 is made of a P-type semiconductor and has a flat plate shape.
  • the N epi layer 22 is made of an N-type semiconductor.
  • the N epi layer 22 is formed on one main surface of the Psub layer 27.
  • the N-type doping portion 23 is formed by being embedded in the N epi layer 22.
  • the N-type doping part 23 is in contact with the Psub layer 27.
  • the P + type doping portion 241A and the P + type doping portion 242A are formed on the surface of the N epi layer 22 (the surface opposite to the surface in contact with the Psub layer 27), that is, on the first main surface side of the semiconductor substrate 20A. .
  • the P + type doping part 241A and the P + type doping part 242A are arranged at a predetermined distance in the X direction.
  • the P + type doping part 241A and the P + type doping part 242A overlap the N type doping part 23 in a plan view of the semiconductor substrate 20A (as viewed in the Z-axis direction in FIG. 8A). However, the P + type doping part 241A and the P + type doping part 242A are separated from the N type doping part 23 in the Z direction.
  • the N + type doping portion 251A and the N + type doping portion 252A are formed on the surface of the N epi layer 22 (the surface opposite to the surface in contact with the Psub layer 27), that is, on the first main surface side of the semiconductor substrate 20A. .
  • the N + type doping part 251A and the N + type doping part 252A are arranged in a position sandwiching the P + type doping part 241A and the P + type doping part 242A in the X direction. At this time, the N + type doping unit 251A and the P + type doping unit 241A are adjacent to each other, and the N + type doping unit 252A and the P + type doping unit 242A are adjacent to each other.
  • the N + type doping part 251A and the N + type doping part 252A do not overlap the N type doping part 23 in a plan view of the semiconductor substrate 20A.
  • the trench 261 is made of an insulating material and has a frame shape surrounding the N + type doping portion 251A in plan view of the semiconductor substrate 20A. As shown in FIG. 8A, the trench 261 has a predetermined depth from the surface of the semiconductor substrate 20 ⁇ / b> A, and the tip in the depth direction reaches the inside of the Psub layer 27.
  • the trench 262 is made of an insulating material and has a frame shape surrounding the N + -type doping portion 252A in plan view of the semiconductor substrate 20A. As shown in FIG. 8A, the trench 262 has a predetermined depth from the surface of the semiconductor substrate 20 ⁇ / b> A, and the tip in the depth direction reaches the inside of the Psub layer 27.
  • the trench 263 is made of an insulating material and surrounds the N-type doping portion 23, the P + -type doping portion 241A, and the P + -type doping portion 242A in plan view of the semiconductor substrate 20A. It is out. As shown in FIG. 8A, the trench 263 has a predetermined depth from the surface of the semiconductor substrate 20A, and the tip in the depth direction reaches the inside of the Psub layer 27.
  • the insulating film 31 is made of SiO 2 , SiN or the like. It is formed on the surface of the N epi layer 22.
  • the wiring conductor 321A and the wiring conductor 322A are made of a metal having high conductivity, such as Al.
  • the wiring conductor 321 ⁇ / b> A and the wiring conductor 322 ⁇ / b> A are formed on the surface of the insulating film 31 (surface opposite to the surface in contact with the N epitaxial layer 22).
  • the wiring conductor 321A is connected to the first terminal P11, and the wiring conductor 322A is connected to the second terminal P12.
  • the wiring conductor 321A overlaps the P + type doping part 241A and the N + type doping part 251A in plan view.
  • the wiring conductor 321A is connected to the P + type doping part 241A and the N + type doping part 251A via via conductors that penetrate the insulating film 31.
  • the wiring conductor 322A overlaps the P + type doping part 242A and the N + type doping part 252A in plan view.
  • the wiring conductor 322A is connected to the P + type doping part 242A and the N + type doping part 252A through a via conductor penetrating the insulating film 31.
  • a Zener diode ZD11 in which a current flows from the Psub layer 27 to the N-type doping portion 23 in a steady state is formed by the connection portion between the Psub layer 27 and the N-type doping portion 23. . That is, the structure of the PN junction having the bidirectional breakdown voltage in the present invention is realized.
  • a diode D31 (see FIG. 9) in which a current flows from the P + type doping part 241A to the N epilayer 22 in a steady state is formed by the connection part between the P + type doping part 241A and the N epilayer 22.
  • a diode D32 (see FIG. 9) in which a current flows from the P + type doping part 242A to the N epilayer 22 in a steady state is formed by the connection part between the P + type doping part 242A and the N epilayer 22.
  • the Psub layer is overlapped with the N + type doping portion 251A in a plan view of the semiconductor substrate 20A and surrounded by the trench 261 in the connection portion between the N epi layer 22 and the Psub layer 27 (see FIG. 8B).
  • a diode D21 (see FIG. 9) in which current flows from 27 to the N-epi layer 22 is formed.
  • the Psub layer is overlapped by the portion (see FIG. 8B) that overlaps with the N + type doping portion 252A in a plan view of the semiconductor substrate 20A and is surrounded by the trench 262 in the connection portion between the N epi layer 22 and the Psub layer 27 A diode D ⁇ b> 22 in which current flows from 27 to the N epilayer 22 is formed.
  • the anode of the diode D31 is connected to the first terminal P11
  • the cathode of the diode D32 is connected to the cathode of the diode D31
  • the second terminal P12 is connected to the anode of the diode D32.
  • the cathode of the diode D21 is connected to the first terminal P11
  • the anode of the diode D22 is connected to the anode of the diode D21
  • the second terminal P12 is connected to the cathode of the diode D22.
  • the cathode of the Zener diode ZD11 is connected to the cathode of the diode D31 and the cathode of the diode D32.
  • the anode of the Zener diode ZD11 is connected to the anode of the diode D21 and the anode of the diode D22.
  • a signal transmission path is formed in which the diode D31, the Zener diode ZD11, and the diode D22 are connected in this order from the first terminal P11 to the second terminal P12.
  • the anode of the Zener diode ZD11 is on the second terminal P12 side
  • the cathode of the Zener diode ZD11 is on the first terminal P11 side.
  • the portion of the PN junction that forms the Zener diode ZD11 corresponds to the second region because current flows from the second terminal P12 to the first terminal P11 in a steady state.
  • a signal transmission path is configured in which the diode D21, the Zener diode ZD11, and the diode D32 are connected in this order from the first terminal P11 to the second terminal P12.
  • the anode of the Zener diode ZD11 is on the first terminal P11 side
  • the cathode of the Zener diode ZD11 is on the second terminal P12 side.
  • the portion of the PN junction that forms the Zener diode ZD11 corresponds to the first region because current flows from the first terminal P11 to the second terminal P12 in a steady state.
  • the impedance matching element 10A can realize a circuit configuration having a breakdown voltage bidirectionally between the first terminal P11 and the second terminal P12. Thereby, the impedance matching element 10A can have the same effects as the impedance matching element 10 according to the first embodiment.
  • FIG. 10A is a side cross-sectional view of the impedance matching element 10B according to the third embodiment of the present invention
  • FIG. 10B shows the impedance matching element 10B according to the third embodiment of the present invention. It is an equivalent circuit diagram.
  • the impedance matching element 10B according to the third embodiment is more n-type MOS-FET than the impedance matching element 10 according to the first embodiment. Is different in that a circuit configuration having a bidirectional breakdown voltage is realized.
  • the concept of the other basic configuration of the impedance matching element 10B is the same as that of the impedance matching element 10, and the description of the same part is omitted.
  • the wiring portion is not shown, but the impedance matching element 10B preferably includes a wiring portion similar to the impedance matching element 10 according to the first embodiment.
  • the impedance matching element 10B includes a semiconductor substrate 20B and an insulating film 31.
  • the semiconductor substrate 20B includes a Psub layer 27, a P well layer 28, a P + type doping unit 24B, an N + type doping unit 251B, and an N + type doping unit 252B.
  • the semiconductor substrate 20B is formed by a known semiconductor formation process.
  • the Psub layer 27 is made of a P-type semiconductor and has a flat plate shape.
  • the P well layer 28 is made of a P-type semiconductor.
  • the P well layer 28 is formed on one main surface of the Psub layer 27.
  • the P + type doping portion 24B is formed on the surface of the P well layer 28 (the surface opposite to the surface in contact with the Psub layer 27), that is, on the first main surface side of the semiconductor substrate 20B.
  • the N + type doping portion 251B and the N + type doping portion 252B are formed on the surface of the P well layer 28 (the surface opposite to the surface in contact with the Psub layer 27), that is, on the first main surface side of the semiconductor substrate 20B. .
  • the N + type doping part 251B and the N + type doping part 252B are arranged apart from each other in the X direction. Further, the N + -type doping unit 251B and the N + -type doping unit 252B are arranged apart from the P + -type doping unit 24B in the X direction. At this time, the P + type doping part 24B is not disposed between the N + type doping part 251B and the N + type doping part 252B in the X direction.
  • the insulating film 31 is made of SiO 2 , SiN or the like. It is formed on the surface of the P well layer 28.
  • the wiring conductor 321B, the wiring conductor 322B, the wiring conductor 323B, and the wiring conductor 324B are made of a metal having high conductivity, such as Al.
  • the wiring conductor 321B, the wiring conductor 322B, the wiring conductor 323B, and the wiring conductor 324B are formed on the surface of the insulating film 31 (the surface opposite to the surface in contact with the P well layer 28).
  • the wiring conductor 321B is connected to the first terminal P11, and the wiring conductor 322B is connected to the second terminal P12.
  • the wiring conductor 321B overlaps the N + type doping part 251B in plan view.
  • the wiring conductor 321B is connected to the N + type doping portion 251B through a via conductor that penetrates the insulating film 31.
  • the wiring conductor 322B overlaps the N + type doping portion 252B in plan view.
  • the wiring conductor 322B is connected to the N + type doping portion 252B through a via conductor that penetrates the insulating film 31.
  • the wiring conductor 323B overlaps with the P + type doping portion 24B in plan view.
  • the wiring conductor 323B is connected to the P + type doping part 24B through a via conductor that penetrates the insulating film 31.
  • the wiring conductor 324B is connected to the wiring conductor 323B.
  • the impedance matching element 10B is realized by an n-type MOS-FET in which the first terminal P11 and the second terminal P12 are connected to the drain and source, as shown in FIG.
  • the structure of the PN junction which forms the 2nd field is realized by the junction of P well layer 28 and N + type doping part 251B.
  • the structure of the PN junction forming the first region is realized by the junction between the P well layer 28 and the N + type doping portion 252B.
  • the impedance matching element 10B can realize a circuit configuration having a breakdown voltage in both directions between the first terminal P11 and the second terminal P12. Thereby, the impedance matching element 10B can have the same effect as the impedance matching element 10 according to the first embodiment.
  • n + type MOS-FET including the Psub layer 27, the P well layer 28, the P + type doping unit 24B, the N + type doping unit 251B, and the N + type doping unit 252B has been described.
  • the present invention is not limited to this, and various MOS-FETs can be used.
  • a p + type MOS-FET may be used instead of the n + type MOS-FET.
  • FIG. 11A is a side cross-sectional view of an impedance matching element 10C according to the fourth embodiment of the present invention
  • FIG. 11B shows an impedance matching element 10C according to the fourth embodiment of the present invention. It is an equivalent circuit diagram.
  • the impedance matching element 10C according to the fourth embodiment is compared with the impedance matching element 10 according to the first embodiment by a PNP transistor. The difference is that a circuit configuration having a bidirectional breakdown voltage is realized.
  • the concept of the other basic configuration of the impedance matching element 10C is the same as that of the impedance matching element 10, and the description of the same part is omitted.
  • the wiring portion is not shown, but the impedance matching element 10C preferably includes a wiring portion similar to the impedance matching element 10 according to the first embodiment.
  • the impedance matching element 10C includes a semiconductor substrate 20C and an insulating film 31.
  • the semiconductor substrate 20C includes a Psub layer 27, an N well layer 29, a P well layer 281C, a P well layer 282C, a P + type doping unit 241C, a P + type doping unit 242C, an N + type doping unit 251C, and an N + type doping unit 252C.
  • the semiconductor substrate 20C is formed by a known semiconductor formation process.
  • the Psub layer 27 is made of a P-type semiconductor and has a flat plate shape.
  • the N well layer 29 is made of an N type semiconductor. N well layer 29 is formed on one main surface of Psub layer 27.
  • the P well layer 281C and the P well layer 282C are formed on the surface of the N well layer 29 (the surface opposite to the surface in contact with the Psub layer 27), that is, on the first main surface side of the semiconductor substrate 20C.
  • the P + type doping part 241C is formed on the surface side of the P well layer 281C, that is, on the first main surface side of the semiconductor substrate 20C.
  • the P + type doping portion 242C is formed on the surface side of the P well layer 282C, that is, on the first main surface side of the semiconductor substrate 20C.
  • N + type doping portion 251C and N + type doping portion 252C are formed on the surface of N well layer 29 (the surface opposite to the surface in contact with Psub layer 27), that is, on the first main surface side of semiconductor substrate 20C. .
  • the N + type doping unit 251B and the N + type doping unit 252B are arranged apart from each other with the P well layer 281C and the P well layer 282C interposed therebetween in the X direction.
  • the insulating film 31 is made of SiO 2 , SiN or the like. It is formed on the surface of N well layer 29.
  • the wiring conductor 321C, the wiring conductor 322C, the wiring conductor 323C, and the wiring conductor 324C are made of a metal having high conductivity, such as Al.
  • the wiring conductor 321C, the wiring conductor 322C, the wiring conductor 323C, and the wiring conductor 324C are formed on the surface of the insulating film 31 (the surface opposite to the surface in contact with the N well layer 29).
  • the wiring conductor 321C is connected to the first terminal P11, and the wiring conductor 322C is connected to the second terminal P12.
  • the wiring conductor 321C overlaps with the P + type doping portion 241C in plan view.
  • the wiring conductor 321C is connected to the P + type doping portion 241C through a via conductor that penetrates the insulating film 31.
  • the wiring conductor 322C overlaps with the P + type doping portion 242C in plan view.
  • the wiring conductor 322C is connected to the P + type doping portion 242C through a via conductor that penetrates the insulating film 31.
  • the wiring conductor 323C and the wiring conductor 324C overlap with the N + type doping part 251C and the N + type doping part 252C, respectively, in plan view.
  • the wiring conductor 323C is connected to the N + type doping portion 251C via a via conductor that penetrates the insulating film 31, and the wiring conductor 324C is connected to the N + type doping portion 252C via a via conductor that penetrates the insulating film 31. Connected to.
  • the wiring conductor 323C and the wiring conductor 324C are connected.
  • the impedance matching element 10C is realized by a PNP transistor in which the first terminal P11 and the second terminal P12 are connected to the emitter and collector, as shown in FIG. 11B.
  • region is implement
  • the structure of the PN junction forming the second region is realized by the junction between the P well layer 282C and the N well layer 29.
  • the impedance matching element 10C can realize a circuit configuration having a breakdown voltage bidirectionally between the first terminal P11 and the second terminal P12.
  • the impedance matching element 10 ⁇ / b> C can achieve the same operational effects as the impedance matching element 10 according to the first embodiment.
  • the high frequency circuit 92 is realized, for example, by the circuit configuration shown in FIGS. 12 (A) and 12 (B).
  • FIGS. 12A and 12B are functional block diagrams illustrating a configuration example of the high-frequency circuit 92.
  • the high-frequency circuit 92 generally uses a circuit called a high-frequency front-end circuit. it can.
  • the high-frequency circuit 92 includes a switch circuit (SW circuit) 921, a transmission circuit (TX circuit) 922, and a reception circuit (RX circuit) 923.
  • the switch circuit 921 is connected to the antenna 91 via the impedance matching element of the present invention.
  • the switch circuit 921 is connected to the transmission circuit 922 and the reception circuit 923.
  • the switch circuit 921 connects the transmission circuit 922 to the antenna 91 when transmitting a high-frequency signal, and connects the reception circuit 923 to the antenna 91 when receiving a high-frequency signal.
  • the switch circuit 921 corresponds to a kind of branching circuit of the present invention.
  • the high-frequency circuit 92 includes a duplexer (DPX) 924, a power amplifier (PA) 925, and a low noise amplifier (LNA) 926.
  • the duplexer 924 is connected to the antenna 91 via the impedance matching element of the present invention.
  • the duplexer 924 is connected to the power amplifier 925 and the low noise amplifier 926.
  • the duplexer 924 corresponds to a kind of branching circuit of the present invention.
  • the power amplifier 925 is included in the transmission circuit of the present invention, and the low noise amplifier 926 is included in the reception circuit of the present invention.
  • the transmission signal is amplified by the power amplifier 925 and output to the antenna 91 via the duplexer 924.
  • a reception signal from the antenna 91 is output to the low noise amplifier 926 via the duplexer 924 and amplified by the low noise amplifier 926.

Abstract

An impedance matching element (10), provided with a semiconductor substrate (20), a first terminal (P11), and a second terminal (P12). The first terminal (P11) is formed on the semiconductor substrate (20) and is connected to the antenna (91). The second terminal (P12) is formed on the semiconductor substrate (20) and is connected to a high-frequency circuit (92). The semiconductor substrate (20) has a first region and a second region. The first region is provided with a first PN junction, and has a rectification effect of channeling a current from the first terminal (P11) to the second terminal (P12) in a steady state. The second region is provided with a second PN junction, and has a rectification effect of channeling a current from the second terminal (P12) to the first terminal (P11) in a steady state. The first region and the second region are connected between the first terminal (P11) and the second terminal (P12) and have a breakdown voltage in both directions.

Description

インピーダンス整合素子、および通信装置Impedance matching element and communication device
　本発明は、インピーダンス整合用のインピーダンス整合素子に関する。 The present invention relates to an impedance matching element for impedance matching.
　特許文献１には、アンテナと高周波回路との間のインピーダンス整合を行うインピーダンス整合回路が記載されている。 Patent Document 1 describes an impedance matching circuit that performs impedance matching between an antenna and a high-frequency circuit.
　より具体的には、特許文献１では、インピーダンス整合回路の一例として、キャパシタを用いたインピーダンス整合回路が示されている。このインピーダンス整合回路において、整合素子として用いられるキャパシタは、アンテナと高周波回路との間に、直列に接続されている。 More specifically, Patent Document 1 discloses an impedance matching circuit using a capacitor as an example of an impedance matching circuit. In this impedance matching circuit, a capacitor used as a matching element is connected in series between the antenna and the high-frequency circuit.
特開２００５－２０５９６号公報JP 2005-20596 A
　しかしながら、インピーダンス整合素子として、直列接続のキャパシタを用いた場合、インピーダンス整合素子がない場合よりも、アンテナのＱが高くなる。これにより、アンテナの通信可能な帯域（所定の利得が得られる帯域）の幅が狭くなってしまう。 However, when a series-connected capacitor is used as the impedance matching element, the antenna Q is higher than when no impedance matching element is provided. This narrows the width of the band in which the antenna can communicate (a band where a predetermined gain can be obtained).
　したがって、本発明の目的は、アンテナの帯域幅が狭くなるのを抑えつつ、インピーダンス整合を行うことができるインピーダンス整合素子を提供することにある。 Therefore, an object of the present invention is to provide an impedance matching element that can perform impedance matching while suppressing a reduction in the bandwidth of the antenna.
　この発明のインピーダンス整合素子は、半導体基板、第１端子、および、第２端子を備える。第１端子は、半導体基板上に形成され、アンテナに接続している。第２端子は、半導体基板上に形成され、高周波回路に接続している。半導体基板は、第１領域と第２領域とを備える。第１領域は、ＰＮ接合の構造を備え、定常状態において第１端子から第２端子に電流を流す整流作用を有する。第２領域は、ＰＮ接合の構造を備え、定常状態において第２端子から第１端子に電流を流す整流作用を有する。第１領域と第２領域とは、第１端子と第２端子との間に接続され、双方向にブレークダウン電圧を有する。 The impedance matching element according to the present invention includes a semiconductor substrate, a first terminal, and a second terminal. The first terminal is formed on the semiconductor substrate and connected to the antenna. The second terminal is formed on the semiconductor substrate and connected to the high frequency circuit. The semiconductor substrate includes a first region and a second region. The first region has a PN junction structure and has a rectifying action in which a current flows from the first terminal to the second terminal in a steady state. The second region has a PN junction structure and has a rectifying action in which a current flows from the second terminal to the first terminal in a steady state. The first region and the second region are connected between the first terminal and the second terminal and have a breakdown voltage in both directions.
　この構成では、半導体基板における第１領域と第２領域とからなる部分は、高周波信号に対して、一般的な平行平板型のキャパシタとはキャパシタンスの周波数特性が逆となるキャパシタのように作用する。具体的には、周波数が高くなるほど、この部分のキャパシタンスは低くなる。したがって、通常のキャパシタを用いた場合よりも、アンテナのＱが高くなることが抑制される。 In this configuration, the portion of the semiconductor substrate composed of the first region and the second region acts on a high-frequency signal like a capacitor whose capacitance frequency characteristics are opposite to those of a general parallel plate type capacitor. . Specifically, the higher the frequency, the lower the capacitance of this part. Therefore, it is possible to suppress the Q of the antenna from becoming higher than when a normal capacitor is used.
　また、この発明のインピーダンス整合素子では、次の構成であることが好ましい。半導体基板は、第１主面を備える。第１主面上には、配線層が形成されている。配線層における第１主面に当接する面と反対側の面に、第１端子および第２端子が形成されている。 Also, the impedance matching element of the present invention preferably has the following configuration. The semiconductor substrate includes a first main surface. A wiring layer is formed on the first main surface. A first terminal and a second terminal are formed on the surface of the wiring layer opposite to the surface that contacts the first main surface.
　この構成では、配線層によって、第１端子と第２端子の配置の自由度が向上する。 In this configuration, the degree of freedom of arrangement of the first terminal and the second terminal is improved by the wiring layer.
　また、この発明のインピーダンス整合素子では、一例として、第１領域と第２領域とを用いて、双方向ツェナーダイオードが形成されている。 In the impedance matching element of the present invention, as an example, a bidirectional Zener diode is formed using the first region and the second region.
　また、この発明のインピーダンス整合素子では、一例として、第１領域と第２領域とを用いて、双方向のブレークダウン電圧を有するＭＯＳＦＥＴが形成されている。 In the impedance matching element of the present invention, as an example, a MOSFET having a bidirectional breakdown voltage is formed using the first region and the second region.
　また、この発明のインピーダンス整合素子では、一例として、第１領域と第２領域とを用いて、双方向のブレークダウン電圧を有するトランジスタが形成されている。 In the impedance matching element of the present invention, as an example, a transistor having a bidirectional breakdown voltage is formed using the first region and the second region.
　このように、双方向のブレークダウン特性を有する半導体素子であれば、インピーダンス整合素子として利用することが可能である。 As described above, any semiconductor element having bidirectional breakdown characteristics can be used as an impedance matching element.
　この発明によれば、アンテナの帯域幅を狭くすることなく、インピーダンス整合を行うことができる。 According to the present invention, impedance matching can be performed without narrowing the antenna bandwidth.
図１は本発明の第１の実施形態に係るインピーダンス整合素子１０を含む通信装置１の一例を示すブロック図である。FIG. 1 is a block diagram showing an example of a communication device 1 including an impedance matching element 10 according to the first embodiment of the present invention. 図２（Ａ）は、双方向ツェナーダイオードのキャパシタンスの周波数特性を示すグラフであり、図２（Ｂ）は、双方向ツェナーダイオードの虚数成分の周波数特性を示すグラフである。FIG. 2A is a graph showing the frequency characteristics of the capacitance of the bidirectional Zener diode, and FIG. 2B is a graph showing the frequency characteristics of the imaginary component of the bidirectional Zener diode. 図３（Ａ）は、アンテナ、通常のキャパシタ、双方向ツェナーダイオードのインピーダンスの虚数成分の周波数特性を示すグラフであり、図３（Ｂ）は、通常のキャパシタを用いた場合、双方向ツェナーダイオードを用いた場合、通常のキャパシタも双方向ツェナーダイオードも用いない場合でのアンテナの通過特性を示すグラフである。FIG. 3A is a graph showing the frequency characteristics of the imaginary component of the impedance of an antenna, a normal capacitor, and a bidirectional Zener diode. FIG. 3B shows a bidirectional Zener diode when a normal capacitor is used. 6 is a graph showing the passing characteristics of the antenna when neither a normal capacitor nor a bidirectional Zener diode is used. 図４は双方向ツェナーダイオードの通過特性を示すグラフである。FIG. 4 is a graph showing pass characteristics of the bidirectional Zener diode. 図５は本発明の第１の実施形態に係るインピーダンス整合素子１０の側面断面図である。FIG. 5 is a side sectional view of the impedance matching element 10 according to the first embodiment of the present invention. 図６は本発明の第１の実施形態に係るインピーダンス整合素子１０の斜視図である。FIG. 6 is a perspective view of the impedance matching element 10 according to the first embodiment of the present invention. 図７（Ａ）は、第１の実施形態に係るインピーダンス整合素子１０の上面図であり、図７（Ｂ）は、配線層４０の途中位置を上面側から視た図であり、図７（Ｃ）は、半導体基板２０の第１主面を視た図である。FIG. 7A is a top view of the impedance matching element 10 according to the first embodiment, and FIG. 7B is a view of an intermediate position of the wiring layer 40 as viewed from the top surface side. C) is a view of the first main surface of the semiconductor substrate 20. 図８（Ａ）は、本発明の第２の実施形態に係るインピーダンス整合素子１０Ａの側面断面図であり、図８（Ｂ）は、本発明の第２の実施形態に係るインピーダンス整合素子１０Ａの各構成要素の位置関係を示す平面図である。FIG. 8A is a side sectional view of an impedance matching element 10A according to the second embodiment of the present invention, and FIG. 8B is a diagram of the impedance matching element 10A according to the second embodiment of the present invention. It is a top view which shows the positional relationship of each component. 図９（Ａ）は、本発明の第２の実施形態に係るインピーダンス整合素子１０Ａの等価回路図であり、図９（Ｂ）は、本発明の第２の実施形態に係るインピーダンス整合素子１０Ａの信号伝送の第１態様の等価回路図であり、図９（Ｃ）は、本発明の第２の実施形態に係るインピーダンス整合素子１０Ａの信号伝送の第２態様の等価回路図である。FIG. 9A is an equivalent circuit diagram of the impedance matching element 10A according to the second embodiment of the present invention, and FIG. 9B shows the impedance matching element 10A according to the second embodiment of the present invention. FIG. 9C is an equivalent circuit diagram of a first mode of signal transmission, and FIG. 9C is an equivalent circuit diagram of a second mode of signal transmission of the impedance matching element 10A according to the second embodiment of the present invention. 図１０（Ａ）は、本発明の第３の実施形態に係るインピーダンス整合素子１０Ｂの側面断面図であり、図１０（Ｂ）は、本発明の第３の実施形態に係るインピーダンス整合素子１０Ｂの等価回路図である。FIG. 10A is a side cross-sectional view of the impedance matching element 10B according to the third embodiment of the present invention, and FIG. 10B shows the impedance matching element 10B according to the third embodiment of the present invention. It is an equivalent circuit diagram. 図１１（Ａ）は、本発明の第４の実施形態に係るインピーダンス整合素子１０Ｃの側面断面図であり、図１１（Ｂ）は、本発明の第４の実施形態に係るインピーダンス整合素子１０Ｃの等価回路図である。FIG. 11A is a side cross-sectional view of an impedance matching element 10C according to the fourth embodiment of the present invention, and FIG. 11B shows an impedance matching element 10C according to the fourth embodiment of the present invention. It is an equivalent circuit diagram. 図１２（Ａ）、図１２（Ｂ）は、高周波回路の構成例を示す機能ブロック図である。12A and 12B are functional block diagrams illustrating a configuration example of the high-frequency circuit.
　以降、図を参照して幾つかの具体的な例を挙げて、本発明を実施するための複数の形態を示す。各図中には同一箇所に同一符号を付している。要点の説明又は理解の容易性を考慮して、便宜上実施形態を分けて示すが、異なる実施形態で示した構成の部分的な置換又は組み合わせが可能である。第２の実施形態以降では第１の実施形態と共通の事柄についての記述を省略し、異なる点を中心に説明を行う。特に、同様の構成による同様の作用効果については実施形態毎には逐次言及しない。 Hereinafter, several specific examples will be given with reference to the drawings to show a plurality of modes for carrying out the present invention. In each figure, the same reference numerals are assigned to the same portions. In consideration of ease of explanation or understanding of the main points, the embodiments are shown separately for convenience, but partial replacement or combination of the configurations shown in different embodiments is possible. In the second and subsequent embodiments, description of matters common to the first embodiment will be omitted, and description will be made focusing on differences. In particular, the same operation effect by the same configuration will not be sequentially described for each embodiment.
　（回路構成および特性）
　本発明の第１の実施形態に係るインピーダンス整合素子について、図を参照して説明する。図１は、本発明の第１の実施形態に係るインピーダンス整合素子１０を含む通信装置１の一例を示すブロック図である。 (Circuit configuration and characteristics)
An impedance matching element according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an example of a communication device 1 including an impedance matching element 10 according to the first embodiment of the present invention.
　通信装置１は、アンテナ９１、高周波回路９２、および、インピーダンス整合素子１０を備える。インピーダンス整合素子１０は、第１端子Ｐ１１、第２端子Ｐ１２、双方向ツェナーダイオードＺＤ１０を備える。双方向ツェナーダイオードＺＤ１０は、第１端子Ｐ１１と第２端子Ｐ１２との間に接続されている。 The communication apparatus 1 includes an antenna 91, a high frequency circuit 92, and an impedance matching element 10. The impedance matching element 10 includes a first terminal P11, a second terminal P12, and a bidirectional Zener diode ZD10. The bidirectional Zener diode ZD10 is connected between the first terminal P11 and the second terminal P12.
　アンテナ９１は、第１端子Ｐ１１に接続されている。高周波回路９２は、第２端子Ｐ１２に接続されている。言い換えれば、インピーダンス整合素子１０は、アンテナ９１と高周波回路９２との間に、直列に接続されている。 The antenna 91 is connected to the first terminal P11. The high frequency circuit 92 is connected to the second terminal P12. In other words, the impedance matching element 10 is connected in series between the antenna 91 and the high frequency circuit 92.
　双方向ツェナーダイオードＺＤ１０は、双方向のブレークダウン電圧を有する。そして、双方向ツェナーダイオードＺＤ１０は、次に示す各種の特性を有する。 The bidirectional Zener diode ZD10 has a bidirectional breakdown voltage. The bidirectional Zener diode ZD10 has the following various characteristics.
　図２（Ａ）は、双方向ツェナーダイオードＺＤ１０のキャパシタンスの周波数特性を示すグラフである。図２（Ｂ）は、双方向ツェナーダイオードＺＤ１０の虚数成分の周波数特性を示すグラフである。図２（Ａ）、図２（Ｂ）において、実線は、双方向ツェナーダイオードＺＤ１０の特性を示し、破線は、通常のキャパシタの特性を示す。 FIG. 2A is a graph showing the frequency characteristics of the capacitance of the bidirectional Zener diode ZD10. FIG. 2B is a graph showing the frequency characteristics of the imaginary component of the bidirectional Zener diode ZD10. 2A and 2B, the solid line indicates the characteristic of the bidirectional Zener diode ZD10, and the broken line indicates the characteristic of a normal capacitor.
　図２（Ａ）に示すように、双方向ツェナーダイオードＺＤ１０は、周波数が高くなるのにしたがって、キャパシタンスは小さくなる。すなわち、キャパシタンスの周波数依存性が負の特性を示す。一方、通常のキャパシタは、周波数が高くなるのにしたがって、キャパシタンスは大きくなる。すなわち、キャパシタンスの周波数依存性が正の特性を示す。なお、通常のキャパシタとは、対向電極間に誘電体を配置した構成からなるキャパシタである。特に、図２（Ａ）に示すように、現在、通信用として多く利用されている約７００ＭＨｚを超える周波数では、その傾向が大きくなる。 As shown in FIG. 2A, the bidirectional Zener diode ZD10 has a capacitance that decreases as the frequency increases. That is, the frequency dependence of capacitance exhibits a negative characteristic. On the other hand, the capacitance of a normal capacitor increases as the frequency increases. That is, the frequency dependency of capacitance exhibits a positive characteristic. A normal capacitor is a capacitor having a configuration in which a dielectric is disposed between opposing electrodes. In particular, as shown in FIG. 2 (A), the tendency becomes large at a frequency exceeding about 700 MHz, which is currently widely used for communication.
　そして、図２（Ｂ）に示すように、双方向ツェナーダイオードＺＤ１０は、キャパシタンスの周波数依存性が負の特性を示す領域では、周波数の変化量に対する端子間インピーダンスの虚数成分の変化量が、通常のキャパシタの変化量よりも小さくなる。なお、図２（Ａ）、図２（Ｂ）に示す例では、少なくとも約７００ＭＨｚを超える領域では、キャパシタンスの周波数依存性が負の特性を示しており、周波数の変化量に対する端子間インピーダンスの虚数成分の変化量が、通常のキャパシタの変化量よりも小さくなっていることが分かる。 As shown in FIG. 2B, in the bidirectional Zener diode ZD10, the change amount of the imaginary component of the impedance between the terminals with respect to the change amount of the frequency is usually in the region where the frequency dependence of the capacitance is negative. It becomes smaller than the amount of change of the capacitor. In the example shown in FIGS. 2A and 2B, the frequency dependence of capacitance shows a negative characteristic in a region exceeding at least about 700 MHz, and the imaginary number of the impedance between terminals with respect to the amount of change in frequency. It can be seen that the component change amount is smaller than the normal capacitor change amount.
　ここで、アンテナのインピーダンス特性と、通常のキャパシタのインピーダンス特性、および、双方向ツェナーダイオードＺＤ１０のインピーダンス特性との関係について考える。 Here, the relationship between the impedance characteristics of the antenna, the impedance characteristics of a normal capacitor, and the impedance characteristics of the bidirectional Zener diode ZD10 will be considered.
　図３（Ａ）は、アンテナ（整合素子を有さないアンテナ（例えば、アンテナエレメント））、通常のキャパシタ、双方向ツェナーダイオードのインピーダンスの虚数成分の周波数特性を示すグラフである。図３（Ａ）において、実線は、双方向ツェナーダイオードの特性を示し、破線は、通常のキャパシタの特性を示し、二点鎖線は、アンテナ単体の特性を示す。 FIG. 3A is a graph showing frequency characteristics of an imaginary component of the impedance of an antenna (an antenna having no matching element (for example, an antenna element)), a normal capacitor, and a bidirectional Zener diode. In FIG. 3A, the solid line indicates the characteristic of the bidirectional Zener diode, the broken line indicates the characteristic of the normal capacitor, and the two-dot chain line indicates the characteristic of the antenna alone.
　図３（Ａ）に示すように、アンテナのインピーダンスの虚数成分は、周波数が高くなるほど大きくなる。同様に、通常のキャパシタのインピーダンスの虚数成分も、双方向ツェナーダイオードの虚数成分も、周波数が高くなるほど大きくなる。 As shown in FIG. 3 (A), the imaginary component of the antenna impedance increases as the frequency increases. Similarly, the imaginary number component of the normal capacitor impedance and the imaginary number component of the bidirectional Zener diode increase as the frequency increases.
　しかしながら、図３（Ａ）に示すように、双方向ツェナーダイオードの虚数成分の変化率は、通常のキャパシタの虚数成分の変化率よりも小さい。 However, as shown in FIG. 3A, the rate of change of the imaginary number component of the bidirectional Zener diode is smaller than the rate of change of the imaginary number component of a normal capacitor.
　したがって、通常のキャパシタをインピーダンス整合素子として用いるよりも、双方向ツェナーダイオードをインピーダンス整合素子として用いる方が、高周波帯域におけるインピーダンスの虚数成分の変化率は、小さくなる。なお、高周波帯域とは、例えば約７００ＭＨｚ以上の周波数帯域であることが好ましい。 Therefore, the rate of change of the imaginary component of the impedance in the high frequency band is smaller when the bidirectional Zener diode is used as the impedance matching element than when the normal capacitor is used as the impedance matching element. The high frequency band is preferably a frequency band of about 700 MHz or more, for example.
　ここで、インピーダンスの虚数成分の変化率は、Ｑの高さに対応する。すなわち、インピーダンスの虚数成分の変化率が大きければ、Ｑは高くなり、インピーダンスの虚数成分の変化率が低ければ、Ｑは低くなる。 Here, the rate of change of the imaginary component of the impedance corresponds to the height of Q. That is, if the rate of change of the imaginary number component of impedance is large, Q is high, and if the rate of change of the imaginary number component of impedance is low, Q is low.
　この結果、双方向ツェナーダイオードをインピーダンス整合素子として用いる方が、通常のキャパシタをインピーダンス整合素子として用いるよりも、アンテナのＱは低くなる。より厳密には、アンテナと双方向ツェナーダイオードによって構成される実質的なアンテナのＱは低くなる。 As a result, the antenna Q is lower when the bidirectional Zener diode is used as the impedance matching element than when a normal capacitor is used as the impedance matching element. More strictly, the Q of the substantial antenna constituted by the antenna and the bidirectional Zener diode is lowered.
　図３（Ｂ）は、通常のキャパシタを用いた場合、双方向ツェナーダイオードを用いた場合、通常のキャパシタも双方向ツェナーダイオードも用いない場合でのアンテナの通過特性を示すグラフである。図３（Ｂ）において、実線は、双方向ツェナーダイオードを用いた場合の特性を示し、破線は、通常のキャパシタを用いた場合の特性を示し、二点鎖線は、アンテナ単体の特性を示す。 FIG. 3B is a graph showing the passing characteristics of the antenna when a normal capacitor is used, when a bidirectional Zener diode is used, and when neither a normal capacitor nor a bidirectional Zener diode is used. In FIG. 3B, the solid line indicates the characteristics when the bidirectional Zener diode is used, the broken line indicates the characteristics when a normal capacitor is used, and the two-dot chain line indicates the characteristics of the antenna alone.
　図３（Ｂ）に示すように、通常のキャパシタを用いた場合、双方向ツェナーダイオードを用いた場合の双方において、アンテナ単体よりも共振周波数での極は急峻になる。しかしながら、双方向ツェナーダイオードを用いた場合の方が、共振周波数での極の急峻度は低下する。すなわち、比帯域の幅が広くなる。 As shown in FIG. 3B, in the case of using a normal capacitor and in the case of using a bidirectional Zener diode, the pole at the resonance frequency is steeper than the antenna alone. However, when the bidirectional Zener diode is used, the steepness of the pole at the resonance frequency is lowered. That is, the width of the specific band is widened.
　例えば、図３（Ｂ）の例では、Ｓ［ｄＢ］＝－１０において、アンテナ単体での比帯域の幅を約１００％とすると、通常のキャパシタを用いた場合には、比帯域の幅は、約７２％になる。しかしながら、双方向ツェナーダイオードを用いた場合には、比帯域の幅は、約８２％になる。すなわち、比帯域の幅の減少を約１０％改善できる。 For example, in the example of FIG. 3B, when the bandwidth of the specific band of the antenna alone is about 100% at S [dB] = − 10, the bandwidth of the bandwidth is as follows when a normal capacitor is used. About 72%. However, when the bidirectional Zener diode is used, the width of the ratio band is about 82%. In other words, the reduction in the width of the specific band can be improved by about 10%.
　このように、双方向ツェナーダイオードを用いることによって、容量性のインピーダンス整合素子を接続したことによる、アンテナの通信帯域の幅の減少を抑制できる。 Thus, by using the bidirectional Zener diode, it is possible to suppress a decrease in the communication bandwidth of the antenna due to the connection of the capacitive impedance matching element.
　また、双方向ツェナーダイオードは、次に示す通過特性を有する。図４は、双方向ツェナーダイオードの通過特性を示すグラフである。 Also, the bidirectional Zener diode has the following pass characteristics. FIG. 4 is a graph showing pass characteristics of the bidirectional Zener diode.
　図４に示すように、双方向ツェナーダイオードは、少なくとも約７００ＭＨｚ以上の周波数帯域において、殆ど減衰することなく、高周波信号を伝送できる。 As shown in FIG. 4, the bidirectional Zener diode can transmit a high-frequency signal with almost no attenuation in a frequency band of at least about 700 MHz.
　以上のように、双方向ツェナーダイオードＺＤ１０からなるインピーダンス整合素子１０を、アンテナ９１と高周波回路９２との間に接続することによって、アンテナ９１のインピーダンスと、高周波回路９２のインピーダンスとを整合しながら、アンテナ９１の通信帯域の幅の減少を抑制し、且つ、高周波信号を低損失に伝送できる。 As described above, the impedance matching element 10 composed of the bidirectional Zener diode ZD10 is connected between the antenna 91 and the high-frequency circuit 92, thereby matching the impedance of the antenna 91 and the impedance of the high-frequency circuit 92. A reduction in the width of the communication band of the antenna 91 can be suppressed, and a high-frequency signal can be transmitted with low loss.
　（インピーダンス整合素子１０の具体的な構造）
　図５は、本発明の第１の実施形態に係るインピーダンス整合素子１０の側面断面図である。図６は、本発明の第１の実施形態に係るインピーダンス整合素子１０の斜視図である。図６では、インピーダンス整合素子１０の半導体基板と、配線層の電極を図示しており、配線層における絶縁性材料によって形成される部分の図示は省略している。図７（Ａ）は、第１の実施形態に係るインピーダンス整合素子１０の上面図であり、図７（Ｂ）は、配線層４０の途中位置を上面側から視た図であり、図７（Ｃ）は、半導体基板２０の第１主面を視た図である。 (Specific structure of impedance matching element 10)
FIG. 5 is a side sectional view of the impedance matching element 10 according to the first embodiment of the present invention. FIG. 6 is a perspective view of the impedance matching element 10 according to the first embodiment of the present invention. In FIG. 6, the semiconductor substrate of the impedance matching element 10 and the electrode of the wiring layer are illustrated, and the portion formed of the insulating material in the wiring layer is not illustrated. FIG. 7A is a top view of the impedance matching element 10 according to the first embodiment, and FIG. 7B is a view of an intermediate position of the wiring layer 40 as viewed from the top surface side. C) is a view of the first main surface of the semiconductor substrate 20.
　図５、図６に示すように、インピーダンス整合素子１０は、半導体基板２０、絶縁膜３１、および、配線層４０を備える。 As shown in FIGS. 5 and 6, the impedance matching element 10 includes a semiconductor substrate 20, an insulating film 31, and a wiring layer 40.
　半導体基板２０は、Ｎｓｕｂ層２１、Ｎエピ層２２、Ｎ型ドーピング部２３１、Ｎ型ドーピング部２３２、Ｐ＋型ドーピング部２４１、および、Ｐ＋型ドーピング部２４２を備える。半導体基板２０は、既知の半導体形成プロセスによって形成されている。 The semiconductor substrate 20 includes an Nsub layer 21, an N epilayer 22, an N-type doping unit 231, an N-type doping unit 232, a P + type doping unit 241, and a P + type doping unit 242. The semiconductor substrate 20 is formed by a known semiconductor formation process.
　Ｎｓｕｂ層２１は、Ｎ型の半導体からなり、平板状である。Ｎエピ層２２は、Ｎ型の半導体からなる。Ｎエピ層２２は、Ｎｓｕｂ層２１の一方主面上に、Ｎ型半導体をエピタキシャル成長させることによって形成されている。 The Nsub layer 21 is made of an N-type semiconductor and has a flat plate shape. The N epi layer 22 is made of an N-type semiconductor. The N epilayer 22 is formed on one main surface of the Nsub layer 21 by epitaxially growing an N-type semiconductor.
　図５、図６、図７（Ｃ）に示すように、Ｎ型ドーピング部２３１およびＮ型ドーピング部２３２は、Ｎエピ層２２に形成されている。Ｎ型ドーピング部２３１およびＮ型ドーピング部２３２は、Ｎエピ層２２に対して、部分的なＮ型キャリアのドーピングを行うことによって、形成されている。Ｎ型ドーピング部２３１およびＮ型ドーピング部２３２は、Ｎｓｕｂ層２１に当接する高さ（深さ）で形成されている。 As shown in FIGS. 5, 6, and 7 (C), the N-type doping part 231 and the N-type doping part 232 are formed in the N epilayer 22. The N-type doping unit 231 and the N-type doping unit 232 are formed by performing partial N-type carrier doping on the N epilayer 22. The N-type doping part 231 and the N-type doping part 232 are formed at a height (depth) in contact with the Nsub layer 21.
　Ｎ型ドーピング部２３１およびＮ型ドーピング部２３２は、略直方体形状である。Ｎ型ドーピング部２３１とＮ型ドーピング部２３２とは、Ｘ方向に所定距離で離間して配置されている。 The N-type doping part 231 and the N-type doping part 232 have a substantially rectangular parallelepiped shape. The N-type doping part 231 and the N-type doping part 232 are arranged apart from each other by a predetermined distance in the X direction.
　図５、図６、図７（Ｃ）に示すように、Ｐ＋型ドーピング部２４１およびＰ＋型ドーピング部２４２は、Ｎエピ層２２の表面（Ｎｓｕｂ層２１に当接する面と反対の面）側、すなわち、半導体基板２０の第１主面側に形成されている。Ｐ＋型ドーピング部２４１およびＰ＋型ドーピング部２４２は、Ｎエピ層２２に対して、部分的なＰ型キャリアのドーピングを行うことによって、形成されている。 As shown in FIGS. 5, 6, and 7 (C), the P + type doping portion 241 and the P + type doping portion 242 are on the surface of the N epilayer 22 (the surface opposite to the surface in contact with the Nsub layer 21), That is, it is formed on the first main surface side of the semiconductor substrate 20. The P + type doping part 241 and the P + type doping part 242 are formed by performing partial P type carrier doping on the N epilayer 22.
　Ｐ＋型ドーピング部２４１は、平面視で（図５のＺ軸方向に視て）、Ｎ型ドーピング部２３１と重なっており、所定の高さ（深さ、すなわち、図５のＺ軸方向に沿った長さ）を有する。Ｐ＋型ドーピング部２４１は、Ｎ型ドーピング部２３１に接合している。これらＰ＋型ドーピング部２４１とＮ型ドーピング部２３１との接合部によって、第１のＰＮ接合が実現される。そして、このＰＮ接合部は、定常状態において第１端子Ｐ１１から第２端子Ｐ１２に電流を流す整流作用を有する第１領域に対応する。なお、定常状態とは、ブレークダウンが生じていない状態を意味する。 The P + type doping part 241 overlaps with the N type doping part 231 in plan view (viewed in the Z-axis direction in FIG. 5), and has a predetermined height (depth, that is, along the Z-axis direction in FIG. 5). Length). The P + type doping unit 241 is joined to the N type doping unit 231. A first PN junction is realized by the junction between the P + type doping unit 241 and the N type doping unit 231. The PN junction corresponds to a first region having a rectifying action for flowing a current from the first terminal P11 to the second terminal P12 in a steady state. The steady state means a state in which no breakdown occurs.
　Ｐ＋型ドーピング部２４２は、平面視で（図５のＺ軸方向に視て）、Ｎ型ドーピング部２３２と重なっており、所定の高さ（深さ、すなわち、図５のＺ軸方向に沿った長さ）を有する。Ｐ＋型ドーピング部２４２は、Ｎ型ドーピング部２３２に接合している。これらＰ＋型ドーピング部２４２とＮ型ドーピング部２３２との接合部によって、第２のＰＮ接合が実現される。そして、このＰＮ接合部は、定常状態において第２端子Ｐ１２から第１端子Ｐ１１に電流を流す整流作用を有する第２領域に対応する。 The P + type doping part 242 overlaps with the N type doping part 232 in a plan view (viewed in the Z-axis direction in FIG. 5), and has a predetermined height (depth, ie, along the Z-axis direction in FIG. 5). Length). The P + type doping part 242 is joined to the N type doping part 232. A second PN junction is realized by the junction between the P + type doping unit 242 and the N type doping unit 232. The PN junction corresponds to a second region having a rectifying action for flowing a current from the second terminal P12 to the first terminal P11 in a steady state.
　また、Ｎ型ドーピング部２３１およびＮ型ドーピング部２３２は、Ｎｓｕｂ層２１に当接しているので、Ｎｓｕｂ層２１が、第１領域と第２領域を電気的に接続する電流経路となる。 Further, since the N-type doping unit 231 and the N-type doping unit 232 are in contact with the Nsub layer 21, the Nsub layer 21 serves as a current path that electrically connects the first region and the second region.
　そして、この構造では、第１領域のＰＮ接合部の向きと、第２領域のＰＮ接合部の向きとが逆の状態で接続される。これにより、双方向にブレークダウン電圧を有する双方向ツェナーダイオードＺＤ１０が形成される。 In this structure, the direction of the PN junction in the first region and the direction of the PN junction in the second region are connected in an opposite state. As a result, a bidirectional Zener diode ZD10 having a breakdown voltage in both directions is formed.
　絶縁膜３１は、ＳｉＯ２、ＳｉＮ等からなる。Ｎエピ層２２の表面に形成されている。 The insulating film 31 is made of SiO 2 , SiN or the like. It is formed on the surface of the N epi layer 22.
　配線導体３２１および配線導体３２２は、Ａｌ等の高い導電率を有する金属からなる。配線導体３２１および配線導体３２２は、絶縁膜３１の表面（Ｎエピ層２２に当接する面と反対側の面）に形成されている。 The wiring conductor 321 and the wiring conductor 322 are made of a metal having high conductivity such as Al. The wiring conductor 321 and the wiring conductor 322 are formed on the surface of the insulating film 31 (surface opposite to the surface in contact with the N epitaxial layer 22).
　図７（Ｃ）に示すように、配線導体３２１と配線導体３２２は、平面視において略矩形であり、Ｘ方向に所定距離で離間している。 As shown in FIG. 7C, the wiring conductor 321 and the wiring conductor 322 are substantially rectangular in a plan view and are separated by a predetermined distance in the X direction.
　配線導体３２１は、平面視において、Ｐ＋型ドーピング部２４１に重なっている。配線導体３２１は、絶縁膜３１を貫通するビア導体を介して、Ｐ＋型ドーピング部２４１に接続している。 The wiring conductor 321 overlaps the P + type doping part 241 in plan view. The wiring conductor 321 is connected to the P + type doping part 241 through a via conductor that penetrates the insulating film 31.
　配線導体３２２は、平面視において、Ｐ＋型ドーピング部２４２に重なっている。配線導体３２２は、絶縁膜３１を貫通するビア導体を介して、Ｐ＋型ドーピング部２４２に接続している。 The wiring conductor 322 overlaps the P + type doping part 242 in plan view. The wiring conductor 322 is connected to the P + type doping part 242 through a via conductor that penetrates the insulating film 31.
　配線層４０は、絶縁性樹脂４１、ビア導体４２１、ビア導体４２２、配線導体４３１、配線導体４３２、メッキ層４４１、および、メッキ層４４２を備える。 The wiring layer 40 includes an insulating resin 41, a via conductor 421, a via conductor 422, a wiring conductor 431, a wiring conductor 432, a plating layer 441, and a plating layer 442.
　絶縁性樹脂４１は、例えば、エポキシ樹脂等の加工性に優れた樹脂からなる。絶縁性樹脂４１は、絶縁膜３１の表面に形成されている。 The insulating resin 41 is made of a resin excellent in workability, such as an epoxy resin. The insulating resin 41 is formed on the surface of the insulating film 31.
　配線導体４３１および配線導体４３２は、例えば、Ｃｕ等の、高い導電率を有し、加工性に優れた金属からなる。絶縁性樹脂４１における絶縁膜３１との当接面と反対側の面（インピーダンス整合素子１０の表面）の近傍に配置されている。 The wiring conductor 431 and the wiring conductor 432 are made of a metal having high conductivity and excellent workability, such as Cu. The insulating resin 41 is disposed in the vicinity of the surface opposite to the contact surface with the insulating film 31 (the surface of the impedance matching element 10).
　図７（Ｂ）に示すように、配線導体４３１および配線導体４３２は、平面視において略矩形であり、Ｘ方向に所定距離で離間している。 As shown in FIG. 7B, the wiring conductor 431 and the wiring conductor 432 are substantially rectangular in a plan view and are separated by a predetermined distance in the X direction.
　配線導体４３１は、平面視において、配線導体３２１に重なっている。配線導体４３１は、絶縁性樹脂４１の厚み方向（Ｚ方向）に延びるビア導体４２１を介して、配線導体３２１に接続している。 The wiring conductor 431 overlaps the wiring conductor 321 in plan view. The wiring conductor 431 is connected to the wiring conductor 321 via a via conductor 421 extending in the thickness direction (Z direction) of the insulating resin 41.
　配線導体４３２は、平面視において、配線導体３２２に重なっている。配線導体４３２は、絶縁性樹脂４１の厚み方向（Ｚ方向）に延びるビア導体４２２を介して、配線導体３２２に接続している。 The wiring conductor 432 overlaps the wiring conductor 322 in plan view. The wiring conductor 432 is connected to the wiring conductor 322 via a via conductor 422 extending in the thickness direction (Z direction) of the insulating resin 41.
　メッキ層４４１、および、メッキ層４４２は、例えば、Ｎｉ／Ａｕメッキによって形成されている。 The plating layer 441 and the plating layer 442 are formed by, for example, Ni / Au plating.
　図５、図７（Ａ）に示すように、メッキ層４４１は、配線導体４３１の一部に重なっており、開口４５１によって、インピーダンス整合素子１０の表面に露出している。この露出部分が、本発明の「第１端子」に対応する。メッキ層４４２は、配線導体４３２の一部に重なっており、開口４５２によって、インピーダンス整合素子１０の表面に露出している。この露出部分が、本発明の「第２端子」に対応する。この構成により、インピーダンス整合素子１０の第１端子および第２端子は、半導体基板２０上に形成される。 As shown in FIGS. 5 and 7A, the plating layer 441 overlaps a part of the wiring conductor 431 and is exposed to the surface of the impedance matching element 10 through the opening 451. This exposed portion corresponds to the “first terminal” of the present invention. The plated layer 442 overlaps a part of the wiring conductor 432 and is exposed to the surface of the impedance matching element 10 through the opening 452. This exposed portion corresponds to the “second terminal” of the present invention. With this configuration, the first terminal and the second terminal of the impedance matching element 10 are formed on the semiconductor substrate 20.
　そして、このような構成を用いることによって、上述の双方向にブレークダウン電圧を有する双方向ツェナーダイオードＺＤ１０を有するインピーダンス整合素子１０を実現できる。さらに、インピーダンス整合素子１０は、配線層４０を備えることによって、第１端子と第２端子の配置の自由度を向上できる。 And by using such a configuration, the impedance matching element 10 having the bidirectional Zener diode ZD10 having the above-described bidirectional breakdown voltage can be realized. Furthermore, the impedance matching element 10 can improve the freedom degree of arrangement | positioning of a 1st terminal and a 2nd terminal by providing the wiring layer 40. FIG.
　次に、本発明の第２の実施形態に係るインピーダンス整合素子について、図を参照して説明する。図８（Ａ）は、本発明の第２の実施形態に係るインピーダンス整合素子１０Ａの側面断面図であり、図８（Ｂ）は、本発明の第２の実施形態に係るインピーダンス整合素子１０Ａの各構成要素の位置関係を示す平面図である。図９（Ａ）は、本発明の第２の実施形態に係るインピーダンス整合素子１０Ａの等価回路図であり、図９（Ｂ）は、本発明の第２の実施形態に係るインピーダンス整合素子１０Ａの信号伝送の第１態様の等価回路図であり、図９（Ｃ）は、本発明の第２の実施形態に係るインピーダンス整合素子１０Ａの信号伝送の第２態様の等価回路図である。 Next, an impedance matching element according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 8A is a side sectional view of an impedance matching element 10A according to the second embodiment of the present invention, and FIG. 8B is a diagram of the impedance matching element 10A according to the second embodiment of the present invention. It is a top view which shows the positional relationship of each component. FIG. 9A is an equivalent circuit diagram of the impedance matching element 10A according to the second embodiment of the present invention, and FIG. 9B shows the impedance matching element 10A according to the second embodiment of the present invention. FIG. 9C is an equivalent circuit diagram of a first mode of signal transmission, and FIG. 9C is an equivalent circuit diagram of a second mode of signal transmission of the impedance matching element 10A according to the second embodiment of the present invention.
　図８（Ａ）、図８（Ｂ）、図９（Ａ）、図９（Ｂ）、図９（Ｃ）に示すように、第２の実施形態に係るインピーダンス整合素子１０Ａは、第１の実施形態に係るインピーダンス整合素子１０と比較して、より多くのダイオードによって構成される点において異なる。インピーダンス整合素子１０Ａのその他の基本的な構成の概念は、インピーダンス整合素子１０と同様であり、同様の箇所の説明は省略する。なお、図８（Ａ）、図８（Ｂ）では、配線部の図示を省略しているが、インピーダンス整合素子１０Ａは、第１の実施形態に係るインピーダンス整合素子１０と同様の配線部を備えていることが好ましい。 As shown in FIG. 8A, FIG. 8B, FIG. 9A, FIG. 9B, and FIG. 9C, the impedance matching element 10A according to the second embodiment includes the first Compared to the impedance matching element 10 according to the embodiment, it is different in that it is constituted by more diodes. The concept of the other basic configuration of the impedance matching element 10A is the same as that of the impedance matching element 10, and the description of the same part is omitted. 8A and 8B, the wiring portion is not shown, but the impedance matching element 10A includes a wiring portion similar to that of the impedance matching element 10 according to the first embodiment. It is preferable.
　図８（Ａ）に示すように、インピーダンス整合素子１０Ａは、半導体基板２０Ａ、および、絶縁膜３１を備える。 As shown in FIG. 8A, the impedance matching element 10A includes a semiconductor substrate 20A and an insulating film 31.
　半導体基板２０Ａは、Ｐｓｕｂ層２７、Ｎエピ層２２、Ｎ型ドーピング部２３、Ｐ＋型ドーピング部２４１Ａ、Ｐ＋型ドーピング部２４２Ａ、Ｎ＋型ドーピング部２５１Ａ、および、Ｎ＋型ドーピング部２５２Ａを備える。半導体基板２０Ａは、既知の半導体形成プロセスによって形成されている。 The semiconductor substrate 20A includes a Psub layer 27, an N epi layer 22, an N type doping unit 23, a P + type doping unit 241A, a P + type doping unit 242A, an N + type doping unit 251A, and an N + type doping unit 252A. The semiconductor substrate 20A is formed by a known semiconductor formation process.
　Ｐｓｕｂ層２７は、Ｐ型の半導体からなり、平板状である。Ｎエピ層２２は、Ｎ型の半導体からなる。Ｎエピ層２２は、Ｐｓｕｂ層２７の一方主面上に形成されている。 The Psub layer 27 is made of a P-type semiconductor and has a flat plate shape. The N epi layer 22 is made of an N-type semiconductor. The N epi layer 22 is formed on one main surface of the Psub layer 27.
　Ｎ型ドーピング部２３は、Ｎエピ層２２内に埋め込まれて形成されている。Ｎ型ドーピング部２３は、Ｐｓｕｂ層２７に当接している。 The N-type doping portion 23 is formed by being embedded in the N epi layer 22. The N-type doping part 23 is in contact with the Psub layer 27.
　Ｐ＋型ドーピング部２４１ＡおよびＰ＋型ドーピング部２４２Ａは、Ｎエピ層２２の表面（Ｐｓｕｂ層２７に当接する面と反対の面）側、すなわち、半導体基板２０Ａの第１主面側に形成されている。Ｐ＋型ドーピング部２４１ＡとＰ＋型ドーピング部２４２Ａとは、Ｘ方向に所定距離で離間して配置されている。Ｐ＋型ドーピング部２４１ＡおよびＰ＋型ドーピング部２４２Ａは、半導体基板２０Ａの平面視において（図８（Ａ）のＺ軸方向に視て）、Ｎ型ドーピング部２３に重なっている。ただし、Ｐ＋型ドーピング部２４１ＡおよびＰ＋型ドーピング部２４２Ａは、Ｚ方向において、Ｎ型ドーピング部２３から離間している。 The P + type doping portion 241A and the P + type doping portion 242A are formed on the surface of the N epi layer 22 (the surface opposite to the surface in contact with the Psub layer 27), that is, on the first main surface side of the semiconductor substrate 20A. . The P + type doping part 241A and the P + type doping part 242A are arranged at a predetermined distance in the X direction. The P + type doping part 241A and the P + type doping part 242A overlap the N type doping part 23 in a plan view of the semiconductor substrate 20A (as viewed in the Z-axis direction in FIG. 8A). However, the P + type doping part 241A and the P + type doping part 242A are separated from the N type doping part 23 in the Z direction.
　Ｎ＋型ドーピング部２５１ＡおよびＮ＋型ドーピング部２５２Ａは、Ｎエピ層２２の表面（Ｐｓｕｂ層２７に当接する面と反対の面）側、すなわち、半導体基板２０Ａの第１主面側に形成されている。Ｎ＋型ドーピング部２５１ＡとＮ＋型ドーピング部２５２Ａとは、Ｘ方向において、Ｐ＋型ドーピング部２４１ＡおよびＰ＋型ドーピング部２４２Ａを挟む位置に配置されている。この際、Ｎ＋型ドーピング部２５１ＡとＰ＋型ドーピング部２４１Ａとは、隣り合い、Ｎ＋型ドーピング部２５２ＡとＰ＋型ドーピング部２４２Ａとは、隣り合う。Ｎ＋型ドーピング部２５１ＡおよびＮ＋型ドーピング部２５２Ａは、半導体基板２０Ａの平面視において、Ｎ型ドーピング部２３に重なっていない。 The N + type doping portion 251A and the N + type doping portion 252A are formed on the surface of the N epi layer 22 (the surface opposite to the surface in contact with the Psub layer 27), that is, on the first main surface side of the semiconductor substrate 20A. . The N + type doping part 251A and the N + type doping part 252A are arranged in a position sandwiching the P + type doping part 241A and the P + type doping part 242A in the X direction. At this time, the N + type doping unit 251A and the P + type doping unit 241A are adjacent to each other, and the N + type doping unit 252A and the P + type doping unit 242A are adjacent to each other. The N + type doping part 251A and the N + type doping part 252A do not overlap the N type doping part 23 in a plan view of the semiconductor substrate 20A.
　図８（Ｂ）に示すように、トレンチ２６１は、絶縁性材料からなり、半導体基板２０Ａを平面視して、Ｎ＋型ドーピング部２５１Ａを囲む枠状である。図８（Ａ）に示すように、トレンチ２６１は、半導体基板２０Ａの表面から所定の深さを有し、その深さ方向の先端は、Ｐｓｕｂ層２７の内部まで達している。 As shown in FIG. 8B, the trench 261 is made of an insulating material and has a frame shape surrounding the N + type doping portion 251A in plan view of the semiconductor substrate 20A. As shown in FIG. 8A, the trench 261 has a predetermined depth from the surface of the semiconductor substrate 20 </ b> A, and the tip in the depth direction reaches the inside of the Psub layer 27.
　図８（Ｂ）に示すように、トレンチ２６２は、絶縁性材料からなり、半導体基板２０Ａを平面視して、Ｎ＋型ドーピング部２５２Ａを囲む枠状である。図８（Ａ）に示すように、トレンチ２６２は、半導体基板２０Ａの表面から所定の深さを有し、その深さ方向の先端は、Ｐｓｕｂ層２７の内部まで達している。 As shown in FIG. 8B, the trench 262 is made of an insulating material and has a frame shape surrounding the N + -type doping portion 252A in plan view of the semiconductor substrate 20A. As shown in FIG. 8A, the trench 262 has a predetermined depth from the surface of the semiconductor substrate 20 </ b> A, and the tip in the depth direction reaches the inside of the Psub layer 27.
　図８（Ｂ）に示すように、トレンチ２６３は、絶縁性材料からなり、半導体基板２０Ａを平面視して、Ｎ型ドーピング部２３、Ｐ＋型ドーピング部２４１Ａ、および、Ｐ＋型ドーピング部２４２Ａを囲んでいる。図８（Ａ）に示すように、トレンチ２６３は、半導体基板２０Ａの表面から所定の深さを有し、その深さ方向の先端は、Ｐｓｕｂ層２７の内部まで達している。 As shown in FIG. 8B, the trench 263 is made of an insulating material and surrounds the N-type doping portion 23, the P + -type doping portion 241A, and the P + -type doping portion 242A in plan view of the semiconductor substrate 20A. It is out. As shown in FIG. 8A, the trench 263 has a predetermined depth from the surface of the semiconductor substrate 20A, and the tip in the depth direction reaches the inside of the Psub layer 27.
　絶縁膜３１は、ＳｉＯ２、ＳｉＮ等からなる。Ｎエピ層２２の表面に形成されている。 The insulating film 31 is made of SiO 2 , SiN or the like. It is formed on the surface of the N epi layer 22.
　配線導体３２１Ａおよび配線導体３２２Ａは、例えば、Ａｌ等の、高い導電率を有する金属からなる。配線導体３２１Ａおよび配線導体３２２Ａは、絶縁膜３１の表面（Ｎエピ層２２に当接する面と反対側の面）に形成されている。配線導体３２１Ａは、第１端子Ｐ１１に接続しており、配線導体３２２Ａは、第２端子Ｐ１２に接続している。 The wiring conductor 321A and the wiring conductor 322A are made of a metal having high conductivity, such as Al. The wiring conductor 321 </ b> A and the wiring conductor 322 </ b> A are formed on the surface of the insulating film 31 (surface opposite to the surface in contact with the N epitaxial layer 22). The wiring conductor 321A is connected to the first terminal P11, and the wiring conductor 322A is connected to the second terminal P12.
　配線導体３２１Ａは、平面視において、Ｐ＋型ドーピング部２４１ＡおよびＮ＋型ドーピング部２５１Ａに重なっている。配線導体３２１Ａは、絶縁膜３１を貫通するビア導体を介して、Ｐ＋型ドーピング部２４１ＡおよびＮ＋型ドーピング部２５１Ａに接続している。 The wiring conductor 321A overlaps the P + type doping part 241A and the N + type doping part 251A in plan view. The wiring conductor 321A is connected to the P + type doping part 241A and the N + type doping part 251A via via conductors that penetrate the insulating film 31.
　配線導体３２２Ａは、平面視において、Ｐ＋型ドーピング部２４２ＡおよびＮ＋型ドーピング部２５２Ａに重なっている。配線導体３２２Ａは、絶縁膜３１を貫通するビア導体を介して、Ｐ＋型ドーピング部２４２ＡおよびＮ＋型ドーピング部２５２Ａに接続している。 The wiring conductor 322A overlaps the P + type doping part 242A and the N + type doping part 252A in plan view. The wiring conductor 322A is connected to the P + type doping part 242A and the N + type doping part 252A through a via conductor penetrating the insulating film 31.
　このような構成では、Ｐｓｕｂ層２７とＮ型ドーピング部２３との接続部によって、定常状態において、Ｐｓｕｂ層２７からＮ型ドーピング部２３に電流が流れるツェナーダイオードＺＤ１１（図９参照）が形成される。すなわち、本発明のおける、双方向ブレークダウン電圧を有するＰＮ接合の構造が実現される。 In such a configuration, a Zener diode ZD11 (see FIG. 9) in which a current flows from the Psub layer 27 to the N-type doping portion 23 in a steady state is formed by the connection portion between the Psub layer 27 and the N-type doping portion 23. . That is, the structure of the PN junction having the bidirectional breakdown voltage in the present invention is realized.
　Ｐ＋型ドーピング部２４１ＡとＮエピ層２２との接続部によって、定常状態において、Ｐ＋型ドーピング部２４１ＡからＮエピ層２２に電流が流れるダイオードＤ３１（図９参照）が形成される。 A diode D31 (see FIG. 9) in which a current flows from the P + type doping part 241A to the N epilayer 22 in a steady state is formed by the connection part between the P + type doping part 241A and the N epilayer 22.
　Ｐ＋型ドーピング部２４２ＡとＮエピ層２２との接続部によって、定常状態において、Ｐ＋型ドーピング部２４２ＡからＮエピ層２２に電流が流れるダイオードＤ３２（図９参照）が形成される。 A diode D32 (see FIG. 9) in which a current flows from the P + type doping part 242A to the N epilayer 22 in a steady state is formed by the connection part between the P + type doping part 242A and the N epilayer 22.
　半導体基板２０Ａの平面視においてＮ＋型ドーピング部２５１Ａと重なり、Ｎエピ層２２とＰｓｕｂ層２７との接続部におけるトレンチ２６１に囲まれる部分（図８（Ｂ）参照）によって、定常状態において、Ｐｓｕｂ層２７からＮエピ層２２に電流が流れるダイオードＤ２１（図９参照）が形成される。 In a steady state, the Psub layer is overlapped with the N + type doping portion 251A in a plan view of the semiconductor substrate 20A and surrounded by the trench 261 in the connection portion between the N epi layer 22 and the Psub layer 27 (see FIG. 8B). A diode D21 (see FIG. 9) in which current flows from 27 to the N-epi layer 22 is formed.
　半導体基板２０Ａの平面視においてＮ＋型ドーピング部２５２Ａと重なり、Ｎエピ層２２とＰｓｕｂ層２７との接続部におけるトレンチ２６２に囲まれる部分（図８（Ｂ）参照）によって、定常状態において、Ｐｓｕｂ層２７からＮエピ層２２に電流が流れるダイオードＤ２２が形成される。 In a steady state, the Psub layer is overlapped by the portion (see FIG. 8B) that overlaps with the N + type doping portion 252A in a plan view of the semiconductor substrate 20A and is surrounded by the trench 262 in the connection portion between the N epi layer 22 and the Psub layer 27 A diode D <b> 22 in which current flows from 27 to the N epilayer 22 is formed.
　そして、このような構造によって、図９（Ａ）に示すような回路が実現される。第１端子Ｐ１１には、ダイオードＤ３１のアノードが接続され、ダイオードＤ３１のカソードには、ダイオードＤ３２のカソードが接続され、ダイオードＤ３２のアノードには、第２端子Ｐ１２が接続される。また、第１端子Ｐ１１には、ダイオードＤ２１のカソードが接続され、ダイオードＤ２１のアノードには、ダイオードＤ２２のアノードが接続され、ダイオードＤ２２のカソードには、第２端子Ｐ１２が接続される。さらに、ダイオードＤ３１のカソードとダイオードＤ３２のカソードとには、ツェナーダイオードＺＤ１１のカソードが接続される。ダイオードＤ２１のアノードとダイオードＤ２２のアノードとには、ツェナーダイオードＺＤ１１のアノードが接続される。 And such a structure realizes a circuit as shown in FIG. The anode of the diode D31 is connected to the first terminal P11, the cathode of the diode D32 is connected to the cathode of the diode D31, and the second terminal P12 is connected to the anode of the diode D32. The cathode of the diode D21 is connected to the first terminal P11, the anode of the diode D22 is connected to the anode of the diode D21, and the second terminal P12 is connected to the cathode of the diode D22. Further, the cathode of the Zener diode ZD11 is connected to the cathode of the diode D31 and the cathode of the diode D32. The anode of the Zener diode ZD11 is connected to the anode of the diode D21 and the anode of the diode D22.
　そして、この構成では、図９（Ｂ）に示す信号伝送の第１態様と、図９（Ｃ）に示す信号伝送の第２態様とが実現される。 In this configuration, the first mode of signal transmission shown in FIG. 9B and the second mode of signal transmission shown in FIG. 9C are realized.
　図９（Ｂ）に示す態様では、第１端子Ｐ１１から第２端子Ｐ１２に向けて、ダイオードＤ３１、ツェナーダイオードＺＤ１１、および、ダイオードＤ２２が、この順で接続される信号伝送経路が構成される。この際、ツェナーダイオードＺＤ１１のアノードは、第２端子Ｐ１２側となり、ツェナーダイオードＺＤ１１のカソードは、第１端子Ｐ１１側となる。この場合、ツェナーダイオードＺＤ１１を形成するＰＮ接合の部分は、定常状態で第２端子Ｐ１２から第１端子Ｐ１１に電流を流すので、第２領域に対応する。 9B, a signal transmission path is formed in which the diode D31, the Zener diode ZD11, and the diode D22 are connected in this order from the first terminal P11 to the second terminal P12. At this time, the anode of the Zener diode ZD11 is on the second terminal P12 side, and the cathode of the Zener diode ZD11 is on the first terminal P11 side. In this case, the portion of the PN junction that forms the Zener diode ZD11 corresponds to the second region because current flows from the second terminal P12 to the first terminal P11 in a steady state.
　図９（Ｃ）に示す態様では、第１端子Ｐ１１から第２端子Ｐ１２に向けて、ダイオードＤ２１、ツェナーダイオードＺＤ１１、および、ダイオードＤ３２が、この順で接続される信号伝送経路が構成される。この際、ツェナーダイオードＺＤ１１のアノードは、第１端子Ｐ１１側となり、ツェナーダイオードＺＤ１１のカソードは、第２端子Ｐ１２側となる。この場合、ツェナーダイオードＺＤ１１を形成するＰＮ接合の部分は、定常状態で第１端子Ｐ１１から第２端子Ｐ１２に電流を流すので、第１領域に対応する。 9C, a signal transmission path is configured in which the diode D21, the Zener diode ZD11, and the diode D32 are connected in this order from the first terminal P11 to the second terminal P12. At this time, the anode of the Zener diode ZD11 is on the first terminal P11 side, and the cathode of the Zener diode ZD11 is on the second terminal P12 side. In this case, the portion of the PN junction that forms the Zener diode ZD11 corresponds to the first region because current flows from the first terminal P11 to the second terminal P12 in a steady state.
　このような構成により、インピーダンス整合素子１０Ａは、第１端子Ｐ１１と第２端子Ｐ１２との間に、双方向にブレークダウン電圧を有する回路構成を実現できる。これにより、インピーダンス整合素子１０Ａは、第１の実施形態に係るインピーダンス整合素子１０と同様の作用効果を奏することができる。 With such a configuration, the impedance matching element 10A can realize a circuit configuration having a breakdown voltage bidirectionally between the first terminal P11 and the second terminal P12. Thereby, the impedance matching element 10A can have the same effects as the impedance matching element 10 according to the first embodiment.
　次に、本発明の第３の実施形態に係るインピーダンス整合素子について、図を参照して説明する。図１０（Ａ）は、本発明の第３の実施形態に係るインピーダンス整合素子１０Ｂの側面断面図であり、図１０（Ｂ）は、本発明の第３の実施形態に係るインピーダンス整合素子１０Ｂの等価回路図である。 Next, an impedance matching element according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 10A is a side cross-sectional view of the impedance matching element 10B according to the third embodiment of the present invention, and FIG. 10B shows the impedance matching element 10B according to the third embodiment of the present invention. It is an equivalent circuit diagram.
　図１０（Ａ）、図１０（Ｂ）に示すように、第３の実施形態に係るインピーダンス整合素子１０Ｂは、第１の実施形態に係るインピーダンス整合素子１０と比較して、ｎ型ＭＯＳ－ＦＥＴによって、双方向ブレークダウン電圧を有する回路構成を実現する点で異なる。インピーダンス整合素子１０Ｂのその他の基本的な構成の概念は、インピーダンス整合素子１０と同様であり、同様の箇所の説明は省略する。なお、図１０（Ａ）では、配線部の図示を省略しているが、インピーダンス整合素子１０Ｂは、第１の実施形態に係るインピーダンス整合素子１０と同様の配線部を備えていることが好ましい。 As shown in FIGS. 10A and 10B, the impedance matching element 10B according to the third embodiment is more n-type MOS-FET than the impedance matching element 10 according to the first embodiment. Is different in that a circuit configuration having a bidirectional breakdown voltage is realized. The concept of the other basic configuration of the impedance matching element 10B is the same as that of the impedance matching element 10, and the description of the same part is omitted. In FIG. 10A, the wiring portion is not shown, but the impedance matching element 10B preferably includes a wiring portion similar to the impedance matching element 10 according to the first embodiment.
　図１０（Ａ）に示すように、インピーダンス整合素子１０Ｂは、半導体基板２０Ｂ、および、絶縁膜３１を備える。 As shown in FIG. 10A, the impedance matching element 10B includes a semiconductor substrate 20B and an insulating film 31.
　半導体基板２０Ｂは、Ｐｓｕｂ層２７、Ｐウェル層２８、Ｐ＋型ドーピング部２４Ｂ、Ｎ＋型ドーピング部２５１Ｂ、および、Ｎ＋型ドーピング部２５２Ｂを備える。半導体基板２０Ｂは、既知の半導体形成プロセスによって形成されている。 The semiconductor substrate 20B includes a Psub layer 27, a P well layer 28, a P + type doping unit 24B, an N + type doping unit 251B, and an N + type doping unit 252B. The semiconductor substrate 20B is formed by a known semiconductor formation process.
　Ｐｓｕｂ層２７は、Ｐ型の半導体からなり、平板状である。Ｐウェル層２８は、Ｐ型の半導体からなる。Ｐウェル層２８は、Ｐｓｕｂ層２７の一方主面上に形成されている。 The Psub layer 27 is made of a P-type semiconductor and has a flat plate shape. The P well layer 28 is made of a P-type semiconductor. The P well layer 28 is formed on one main surface of the Psub layer 27.
　Ｐ＋型ドーピング部２４Ｂは、Ｐウェル層２８の表面（Ｐｓｕｂ層２７に当接する面と反対の面）側、すなわち、半導体基板２０Ｂの第１主面側に形成されている。 The P + type doping portion 24B is formed on the surface of the P well layer 28 (the surface opposite to the surface in contact with the Psub layer 27), that is, on the first main surface side of the semiconductor substrate 20B.
　Ｎ＋型ドーピング部２５１ＢおよびＮ＋型ドーピング部２５２Ｂは、Ｐウェル層２８の表面（Ｐｓｕｂ層２７に当接する面と反対の面）側、すなわち、半導体基板２０Ｂの第１主面側に形成されている。Ｎ＋型ドーピング部２５１ＢとＮ＋型ドーピング部２５２Ｂとは、Ｘ方向において離間して配置されている。さらに、Ｎ＋型ドーピング部２５１ＢとＮ＋型ドーピング部２５２Ｂとは、Ｘ方向において、Ｐ＋型ドーピング部２４Ｂから離間して配置されている。この際、Ｐ＋型ドーピング部２４Ｂは、Ｘ方向において、Ｎ＋型ドーピング部２５１ＢとＮ＋型ドーピング部２５２Ｂとの間に配置されていない。 The N + type doping portion 251B and the N + type doping portion 252B are formed on the surface of the P well layer 28 (the surface opposite to the surface in contact with the Psub layer 27), that is, on the first main surface side of the semiconductor substrate 20B. . The N + type doping part 251B and the N + type doping part 252B are arranged apart from each other in the X direction. Further, the N + -type doping unit 251B and the N + -type doping unit 252B are arranged apart from the P + -type doping unit 24B in the X direction. At this time, the P + type doping part 24B is not disposed between the N + type doping part 251B and the N + type doping part 252B in the X direction.
　絶縁膜３１は、ＳｉＯ２、ＳｉＮ等からなる。Ｐウェル層２８の表面に形成されている。 The insulating film 31 is made of SiO 2 , SiN or the like. It is formed on the surface of the P well layer 28.
　配線導体３２１Ｂ、配線導体３２２Ｂ、配線導体３２３Ｂ、および配線導体３２４Ｂは、例えば、Ａｌ等の、高い導電率を有する金属からなる。配線導体３２１Ｂ、配線導体３２２Ｂ、配線導体３２３Ｂ、および配線導体３２４Ｂは、絶縁膜３１の表面（Ｐウェル層２８に当接する面と反対側の面）に形成されている。配線導体３２１Ｂは、第１端子Ｐ１１に接続しており、配線導体３２２Ｂは、第２端子Ｐ１２に接続している。 The wiring conductor 321B, the wiring conductor 322B, the wiring conductor 323B, and the wiring conductor 324B are made of a metal having high conductivity, such as Al. The wiring conductor 321B, the wiring conductor 322B, the wiring conductor 323B, and the wiring conductor 324B are formed on the surface of the insulating film 31 (the surface opposite to the surface in contact with the P well layer 28). The wiring conductor 321B is connected to the first terminal P11, and the wiring conductor 322B is connected to the second terminal P12.
　配線導体３２１Ｂは、平面視において、Ｎ＋型ドーピング部２５１Ｂに重なっている。配線導体３２１Ｂは、絶縁膜３１を貫通するビア導体を介して、Ｎ＋型ドーピング部２５１Ｂに接続している。 The wiring conductor 321B overlaps the N + type doping part 251B in plan view. The wiring conductor 321B is connected to the N + type doping portion 251B through a via conductor that penetrates the insulating film 31.
　配線導体３２２Ｂは、平面視において、Ｎ＋型ドーピング部２５２Ｂに重なっている。配線導体３２２Ｂは、絶縁膜３１を貫通するビア導体を介して、Ｎ＋型ドーピング部２５２Ｂに接続している。 The wiring conductor 322B overlaps the N + type doping portion 252B in plan view. The wiring conductor 322B is connected to the N + type doping portion 252B through a via conductor that penetrates the insulating film 31.
　配線導体３２３Ｂは、平面視において、Ｐ＋型ドーピング部２４Ｂに重なっている。配線導体３２３Ｂは、絶縁膜３１を貫通するビア導体を介して、Ｐ＋型ドーピング部２４Ｂに接続している。配線導体３２４Ｂは、配線導体３２３Ｂに接続している。 The wiring conductor 323B overlaps with the P + type doping portion 24B in plan view. The wiring conductor 323B is connected to the P + type doping part 24B through a via conductor that penetrates the insulating film 31. The wiring conductor 324B is connected to the wiring conductor 323B.
　この構成により、インピーダンス整合素子１０Ｂは、図１０（Ｂ）に示すように、第１端子Ｐ１１および第２端子Ｐ１２がドレインおよびソースに接続するｎ型ＭＯＳ－ＦＥＴによって実現される。 With this configuration, the impedance matching element 10B is realized by an n-type MOS-FET in which the first terminal P11 and the second terminal P12 are connected to the drain and source, as shown in FIG.
　そして、このような構成では、Ｐウェル層２８とＮ＋型ドーピング部２５１Ｂとの接合部によって、第２領域を形成するＰＮ接合の構造が実現される。 And in such a structure, the structure of the PN junction which forms the 2nd field is realized by the junction of P well layer 28 and N + type doping part 251B.
　また、Ｐウェル層２８とＮ＋型ドーピング部２５２Ｂとの接合部によって、第１領域を形成するＰＮ接合の構造が実現される。 Also, the structure of the PN junction forming the first region is realized by the junction between the P well layer 28 and the N + type doping portion 252B.
　このような構成により、インピーダンス整合素子１０Ｂは、第１端子Ｐ１１と第２端子Ｐ１２との間に、双方向にブレークダウン電圧を有する回路構成を実現できる。これにより、インピーダンス整合素子１０Ｂは、第１の実施形態に係るインピーダンス整合素子１０と同様の作用効果を奏することができる。 With such a configuration, the impedance matching element 10B can realize a circuit configuration having a breakdown voltage in both directions between the first terminal P11 and the second terminal P12. Thereby, the impedance matching element 10B can have the same effect as the impedance matching element 10 according to the first embodiment.
　なお、上述した実施形態では、Ｐｓｕｂ層２７、Ｐウェル層２８、Ｐ＋型ドーピング部２４Ｂ、Ｎ＋型ドーピング部２５１Ｂ、および、Ｎ＋型ドーピング部２５２Ｂを備えるｎ＋型ＭＯＳ－ＦＥＴを用いた例について説明したが、これに限定されるものではなく、種々のＭＯＳ－ＦＥＴを用いることができる。ｎ＋型ＭＯＳ－ＦＥＴに代えて、ｐ＋型ＭＯＳ－ＦＥＴを用いてもよい。 In the above-described embodiment, an example using an n + type MOS-FET including the Psub layer 27, the P well layer 28, the P + type doping unit 24B, the N + type doping unit 251B, and the N + type doping unit 252B has been described. However, the present invention is not limited to this, and various MOS-FETs can be used. A p + type MOS-FET may be used instead of the n + type MOS-FET.
　次に、本発明の第４の実施形態に係るインピーダンス整合素子について、図を参照して説明する。図１１（Ａ）は、本発明の第４の実施形態に係るインピーダンス整合素子１０Ｃの側面断面図であり、図１１（Ｂ）は、本発明の第４の実施形態に係るインピーダンス整合素子１０Ｃの等価回路図である。 Next, an impedance matching element according to a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 11A is a side cross-sectional view of an impedance matching element 10C according to the fourth embodiment of the present invention, and FIG. 11B shows an impedance matching element 10C according to the fourth embodiment of the present invention. It is an equivalent circuit diagram.
　図１１（Ａ）、図１１（Ｂ）に示すように、第４の実施形態に係るインピーダンス整合素子１０Ｃは、第１の実施形態に係るインピーダンス整合素子１０と比較して、ＰＮＰ型トランジスタによって、双方向ブレークダウン電圧を有する回路構成を実現する点で異なる。インピーダンス整合素子１０Ｃのその他の基本的な構成の概念は、インピーダンス整合素子１０と同様であり、同様の箇所の説明は省略する。なお、図１１（Ａ）では、配線部の図示を省略しているが、インピーダンス整合素子１０Ｃは、第１の実施形態に係るインピーダンス整合素子１０と同様の配線部を備えていることが好ましい。 As shown in FIGS. 11A and 11B, the impedance matching element 10C according to the fourth embodiment is compared with the impedance matching element 10 according to the first embodiment by a PNP transistor. The difference is that a circuit configuration having a bidirectional breakdown voltage is realized. The concept of the other basic configuration of the impedance matching element 10C is the same as that of the impedance matching element 10, and the description of the same part is omitted. In FIG. 11A, the wiring portion is not shown, but the impedance matching element 10C preferably includes a wiring portion similar to the impedance matching element 10 according to the first embodiment.
　図１１（Ａ）に示すように、インピーダンス整合素子１０Ｃは、半導体基板２０Ｃ、および、絶縁膜３１を備える。 As shown in FIG. 11A, the impedance matching element 10C includes a semiconductor substrate 20C and an insulating film 31.
　半導体基板２０Ｃは、Ｐｓｕｂ層２７、Ｎウェル層２９、Ｐウェル層２８１Ｃ、Ｐウェル層２８２Ｃ、Ｐ＋型ドーピング部２４１Ｃ、Ｐ＋型ドーピング部２４２Ｃ、Ｎ＋型ドーピング部２５１Ｃ、および、Ｎ＋型ドーピング部２５２Ｃを備える。半導体基板２０Ｃは、既知の半導体形成プロセスによって形成されている。 The semiconductor substrate 20C includes a Psub layer 27, an N well layer 29, a P well layer 281C, a P well layer 282C, a P + type doping unit 241C, a P + type doping unit 242C, an N + type doping unit 251C, and an N + type doping unit 252C. Prepare. The semiconductor substrate 20C is formed by a known semiconductor formation process.
　Ｐｓｕｂ層２７は、Ｐ型の半導体からなり、平板状である。Ｎウェル層２９は、Ｎ型の半導体からなる。Ｎウェル層２９は、Ｐｓｕｂ層２７の一方主面上に形成されている。 The Psub layer 27 is made of a P-type semiconductor and has a flat plate shape. The N well layer 29 is made of an N type semiconductor. N well layer 29 is formed on one main surface of Psub layer 27.
　Ｐウェル層２８１ＣおよびＰウェル層２８２Ｃは、Ｎウェル層２９の表面（Ｐｓｕｂ層２７に当接する面と反対の面）側、すなわち、半導体基板２０Ｃの第１主面側に形成されている。 The P well layer 281C and the P well layer 282C are formed on the surface of the N well layer 29 (the surface opposite to the surface in contact with the Psub layer 27), that is, on the first main surface side of the semiconductor substrate 20C.
　Ｐ＋型ドーピング部２４１Ｃは、Ｐウェル層２８１Ｃの表面側、すなわち、半導体基板２０Ｃの第１主面側に形成されている。Ｐ＋型ドーピング部２４２Ｃは、Ｐウェル層２８２Ｃの表面側、すなわち、半導体基板２０Ｃの第１主面側に形成されている。 The P + type doping part 241C is formed on the surface side of the P well layer 281C, that is, on the first main surface side of the semiconductor substrate 20C. The P + type doping portion 242C is formed on the surface side of the P well layer 282C, that is, on the first main surface side of the semiconductor substrate 20C.
　Ｎ＋型ドーピング部２５１ＣおよびＮ＋型ドーピング部２５２Ｃは、Ｎウェル層２９の表面（Ｐｓｕｂ層２７に当接する面と反対の面）側、すなわち、半導体基板２０Ｃの第１主面側に形成されている。Ｎ＋型ドーピング部２５１ＢとＮ＋型ドーピング部２５２Ｂとは、Ｘ方向において、Ｐウェル層２８１ＣおよびＰウェル層２８２Ｃを挟んで、離間して配置されている。 N + type doping portion 251C and N + type doping portion 252C are formed on the surface of N well layer 29 (the surface opposite to the surface in contact with Psub layer 27), that is, on the first main surface side of semiconductor substrate 20C. . The N + type doping unit 251B and the N + type doping unit 252B are arranged apart from each other with the P well layer 281C and the P well layer 282C interposed therebetween in the X direction.
　絶縁膜３１は、ＳｉＯ２、ＳｉＮ等からなる。Ｎウェル層２９の表面に形成されている。 The insulating film 31 is made of SiO 2 , SiN or the like. It is formed on the surface of N well layer 29.
　配線導体３２１Ｃ、配線導体３２２Ｃ、配線導体３２３Ｃ、および配線導体３２４Ｃは、例えば、Ａｌ等の、高い導電率を有する金属からなる。配線導体３２１Ｃ、配線導体３２２Ｃ、配線導体３２３Ｃ、および配線導体３２４Ｃは、絶縁膜３１の表面（Ｎウェル層２９に当接する面と反対側の面）に形成されている。配線導体３２１Ｃは、第１端子Ｐ１１に接続しており、配線導体３２２Ｃは、第２端子Ｐ１２に接続している。 The wiring conductor 321C, the wiring conductor 322C, the wiring conductor 323C, and the wiring conductor 324C are made of a metal having high conductivity, such as Al. The wiring conductor 321C, the wiring conductor 322C, the wiring conductor 323C, and the wiring conductor 324C are formed on the surface of the insulating film 31 (the surface opposite to the surface in contact with the N well layer 29). The wiring conductor 321C is connected to the first terminal P11, and the wiring conductor 322C is connected to the second terminal P12.
　配線導体３２１Ｃは、平面視において、Ｐ＋型ドーピング部２４１Ｃに重なっている。配線導体３２１Ｃは、絶縁膜３１を貫通するビア導体を介して、Ｐ＋型ドーピング部２４１Ｃに接続している。 The wiring conductor 321C overlaps with the P + type doping portion 241C in plan view. The wiring conductor 321C is connected to the P + type doping portion 241C through a via conductor that penetrates the insulating film 31.
　配線導体３２２Ｃは、平面視において、Ｐ＋型ドーピング部２４２Ｃに重なっている。配線導体３２２Ｃは、絶縁膜３１を貫通するビア導体を介して、Ｐ＋型ドーピング部２４２Ｃに接続している。 The wiring conductor 322C overlaps with the P + type doping portion 242C in plan view. The wiring conductor 322C is connected to the P + type doping portion 242C through a via conductor that penetrates the insulating film 31.
　配線導体３２３Ｃおよび配線導体３２４Ｃは、平面視において、Ｎ＋型ドーピング部２５１ＣおよびＮ＋型ドーピング部２５２Ｃに、それぞれ重なっている。配線導体３２３Ｃは、絶縁膜３１を貫通するビア導体を介して、Ｎ＋型ドーピング部２５１Ｃに接続しており、配線導体３２４Ｃは、絶縁膜３１を貫通するビア導体を介して、Ｎ＋型ドーピング部２５２Ｃに接続している。配線導体３２３Ｃと配線導体３２４Ｃとは、接続されている。 The wiring conductor 323C and the wiring conductor 324C overlap with the N + type doping part 251C and the N + type doping part 252C, respectively, in plan view. The wiring conductor 323C is connected to the N + type doping portion 251C via a via conductor that penetrates the insulating film 31, and the wiring conductor 324C is connected to the N + type doping portion 252C via a via conductor that penetrates the insulating film 31. Connected to. The wiring conductor 323C and the wiring conductor 324C are connected.
　この構成により、インピーダンス整合素子１０Ｃは、図１１（Ｂ）に示すように、第１端子Ｐ１１および第２端子Ｐ１２がエミッタおよびコレクタに接続するＰＮＰ型トランジスタによって実現される。 With this configuration, the impedance matching element 10C is realized by a PNP transistor in which the first terminal P11 and the second terminal P12 are connected to the emitter and collector, as shown in FIG. 11B.
　そして、このような構成では、Ｐウェル層２８１ＣとＮウェル層２９との接合部によって、第１領域を形成するＰＮ接合の構成が実現される。 And in such a structure, the structure of the PN junction which forms a 1st area | region is implement | achieved by the junction part of P well layer 281C and the N well layer 29. FIG.
　また、Ｐウェル層２８２ＣとＮウェル層２９との接合部によって、第２領域を形成するＰＮ接合の構成が実現される。 Further, the structure of the PN junction forming the second region is realized by the junction between the P well layer 282C and the N well layer 29.
　このような構成により、インピーダンス整合素子１０Ｃは、第１端子Ｐ１１と第２端子Ｐ１２との間に、双方向にブレークダウン電圧を有する回路構成を実現できる。これにより、インピーダンス整合素子１０Ｃは、第１の実施形態に係るインピーダンス整合素子１０と同様の作用効果を奏することができる。 With such a configuration, the impedance matching element 10C can realize a circuit configuration having a breakdown voltage bidirectionally between the first terminal P11 and the second terminal P12. Thereby, the impedance matching element 10 </ b> C can achieve the same operational effects as the impedance matching element 10 according to the first embodiment.
　（高周波回路の具体例）
　なお、上述説明では、高周波回路について具体的な構成を示していないが、各実施形態の高周波回路は、例えば、次に示すような回路構成によって実現が可能である。 (Specific examples of high-frequency circuits)
In the above description, the specific configuration of the high-frequency circuit is not shown, but the high-frequency circuit of each embodiment can be realized by the following circuit configuration, for example.
　高周波回路９２は、例えば、図１２（Ａ）、図１２（Ｂ）に示す回路構成によって実現される。図１２（Ａ）、図１２（Ｂ）は、高周波回路９２の構成例を示す機能ブロック図である。 The high frequency circuit 92 is realized, for example, by the circuit configuration shown in FIGS. 12 (A) and 12 (B). FIGS. 12A and 12B are functional block diagrams illustrating a configuration example of the high-frequency circuit 92.
　なお、図１２（Ａ）、図１２（Ｂ）は、高周波回路９２の簡単な構成例を示すものであり、高周波回路９２には、一般的に、高周波フロントエンド回路と称する回路を用いることができる。 12A and 12B show a simple configuration example of the high-frequency circuit 92. The high-frequency circuit 92 generally uses a circuit called a high-frequency front-end circuit. it can.
　図１２（Ａ）に示す構成例では、高周波回路９２は、スイッチ回路（ＳＷ回路）９２１、送信回路（ＴＸ回路）９２２、および、受信回路（ＲＸ回路）９２３を備える。スイッチ回路９２１は、本発明のインピーダンス整合素子を介して、アンテナ９１に接続している。また、スイッチ回路９２１は、送信回路９２２および受信回路９２３に接続している。スイッチ回路９２１は、高周波信号の送信時には、送信回路９２２をアンテナ９１に接続し、高周波信号の受信時には、受信回路９２３をアンテナ９１に接続する。この回路において、スイッチ回路９２１が、本発明の分波回路の一種に相当する。 In the configuration example shown in FIG. 12A, the high-frequency circuit 92 includes a switch circuit (SW circuit) 921, a transmission circuit (TX circuit) 922, and a reception circuit (RX circuit) 923. The switch circuit 921 is connected to the antenna 91 via the impedance matching element of the present invention. The switch circuit 921 is connected to the transmission circuit 922 and the reception circuit 923. The switch circuit 921 connects the transmission circuit 922 to the antenna 91 when transmitting a high-frequency signal, and connects the reception circuit 923 to the antenna 91 when receiving a high-frequency signal. In this circuit, the switch circuit 921 corresponds to a kind of branching circuit of the present invention.
　図１２（Ｂ）に示す構成例では、高周波回路９２は、デュプレクサ（ＤＰＸ）９２４、パワーアンプ（ＰＡ）９２５、ローノイズアンプ（ＬＮＡ）９２６を備える。デュプレクサ９２４は、本発明のインピーダンス整合素子を介して、アンテナ９１に接続している。また、デュプレクサ９２４は、パワーアンプ９２５、および、ローノイズアンプ９２６に接続している。この回路において、デュプレクサ９２４が、本発明の分波回路の一種に相当する。パワーアンプ９２５は、本発明の送信回路に含まれ、ローノイズアンプ９２６は、本発明の受信回路に含まれている。 In the configuration example shown in FIG. 12B, the high-frequency circuit 92 includes a duplexer (DPX) 924, a power amplifier (PA) 925, and a low noise amplifier (LNA) 926. The duplexer 924 is connected to the antenna 91 via the impedance matching element of the present invention. The duplexer 924 is connected to the power amplifier 925 and the low noise amplifier 926. In this circuit, the duplexer 924 corresponds to a kind of branching circuit of the present invention. The power amplifier 925 is included in the transmission circuit of the present invention, and the low noise amplifier 926 is included in the reception circuit of the present invention.
　送信信号は、パワーアンプ９２５で増幅され、デュプレクサ９２４を介して、アンテナ９１に出力される。アンテナ９１から受信信号は、デュプレクサ９２４を介して、ローノイズアンプ９２６に出力され、ローノイズアンプ９２６で増幅される。 The transmission signal is amplified by the power amplifier 925 and output to the antenna 91 via the duplexer 924. A reception signal from the antenna 91 is output to the low noise amplifier 926 via the duplexer 924 and amplified by the low noise amplifier 926.
　なお、上述の各実施形態の説明は、すべての点で例示であって、制限的なものではない。当業者にとって変形及び変更が適宜可能である。 Note that the description of each embodiment described above is an example in all respects and is not restrictive. Modifications and changes can be appropriately made by those skilled in the art.
１：通信装置
１０、１０Ａ、１０Ｂ、１０Ｃ：インピーダンス整合素子
２０、２０Ａ、２０Ｂ、２０Ｃ：半導体基板
２１：Ｎｓｕｂ層
２２：エピ層
２３：Ｎ型ドーピング部
２４Ｂ：Ｐ＋型ドーピング部
２７：Ｐｓｕｂ層
２８：Ｐウェル層
２９：Ｎウェル層
３１：絶縁膜
４０：配線層
４１：絶縁性樹脂
９１：アンテナ
９２：高周波回路
２３１、２３２：Ｎ型ドーピング部
２４１、２４１Ａ、２４１Ｃ、２４２、２４２Ａ、２４２Ｃ：Ｐ＋型ドーピング部
２５１Ａ、２５１Ｂ、２５１Ｃ、２５２Ａ、２５２Ｂ、２５２Ｃ：Ｎ＋型ドーピング部
２６１、２６２、２６３：トレンチ
２８１Ｃ、２８２Ｃ：Ｐウェル層
３２１、３２１Ａ、３２１Ｂ、３２１Ｃ、３２２、３２２Ａ、３２２Ｂ、３２２Ｃ、３２３Ｂ、３２３Ｃ、３２４Ｂ、３２４Ｃ：配線導体
４２１、４２２：ビア導体
４３１、４３２：配線導体
４４１、４４２：メッキ層
４５１：開口
９２１：スイッチ回路
９２２：送信回路
９２３：受信回路
９２４：デュプレクサ
９２５：パワーアンプ
９２６：ローノイズアンプ
Ｐ１１：第１端子
Ｐ１２：第２端子
ＺＤ１０：双方向ツェナーダイオード
ＺＤ１１：ツェナーダイオード
Ｄ２１、Ｄ２２、Ｄ３１、Ｄ３２：ダイオード 1: Communication devices 10, 10A, 10B, 10C: Impedance matching elements 20, 20A, 20B, 20C: Semiconductor substrate 21: Nsub layer 22: Epi layer 23: N-type doping unit 24B: P + type doping unit 27: Psub layer 28 : P well layer 29: N well layer 31: Insulating film 40: Wiring layer 41: Insulating resin 91: Antenna 92: High frequency circuits 231 and 232: N- type doping parts 241, 241 A, 241 C, 242 242 A, 242 C: P + Type doping part 251A, 251B, 251C, 252A, 252B, 252C: N + type doping part 261, 262, 263: Trench 281C, 282C: P well layer 321, 321A, 321B, 321C, 322, 322A, 322B, 322C, 323B 323C, 324B, 324C: Wiring conductor 421, 422: Via conductors 431, 432: Wiring conductors 441, 442: Plating layer 451: Opening 921: Switch circuit 922: Transmission circuit 923: Reception circuit 924: Duplexer 925: Power amplifier 926: Low noise amplifier P11: First terminal P12 : Second terminal ZD10: bidirectional Zener diode ZD11: Zener diodes D21, D22, D31, D32: diodes

Claims (9)

  1. 　半導体基板と、
    　前記半導体基板上に形成され、アンテナに接続する第１端子と、
    　前記半導体基板上に形成され、高周波回路に接続する第２端子と、を備え、
    　前記半導体基板は、
    　第１のＰＮ接合を備え、定常状態において前記第１端子から前記第２端子に電流を流す整流作用を有する第１領域と、
    　第２のＰＮ接合を備え、定常状態において前記第２端子から前記第１端子に電流を流す整流作用を有する第２領域と、を有し、
    　前記第１領域と前記第２領域とは、前記第１端子と前記第２端子との間に接続され、双方向にブレークダウン電圧を有する、
    　インピーダンス整合素子。     A semiconductor substrate;
    A first terminal formed on the semiconductor substrate and connected to the antenna;
    A second terminal formed on the semiconductor substrate and connected to a high-frequency circuit,
    The semiconductor substrate is
    A first region having a first PN junction and having a rectifying action for flowing current from the first terminal to the second terminal in a steady state;
    A second region having a second PN junction and having a rectifying action for flowing current from the second terminal to the first terminal in a steady state;
    The first region and the second region are connected between the first terminal and the second terminal and have a breakdown voltage in both directions.
    Impedance matching element.
  2. 　前記半導体基板は、第１主面を備え、
    　前記第１主面上には、配線層が形成されており、
    　前記配線層における前記第１主面に当接する面と反対側の面に、前記第１端子および前記第２端子が形成されている、
    　請求項１に記載のインピーダンス整合素子。     The semiconductor substrate includes a first main surface,
    A wiring layer is formed on the first main surface,
    The first terminal and the second terminal are formed on the surface of the wiring layer opposite to the surface that contacts the first main surface.
    The impedance matching element according to claim 1.
  3. 　前記第１領域と前記第２領域とを用いて、双方向ツェナーダイオードが形成されている、
    　請求項１または請求項２に記載のインピーダンス整合素子。     A bidirectional Zener diode is formed using the first region and the second region.
    The impedance matching element according to claim 1 or 2.
  4. 　前記第１領域と前記第２領域とを用いて、前記双方向のブレークダウン電圧を有するＭＯＳＦＥＴが形成されている、
    　請求項１または請求項２に記載のインピーダンス整合素子。     A MOSFET having the bidirectional breakdown voltage is formed using the first region and the second region.
    The impedance matching element according to claim 1 or 2.
  5. 　前記第１領域と前記第２領域とを用いて、前記双方向のブレークダウン電圧を有するトランジスタが形成されている、
    　請求項１または請求項２に記載のインピーダンス整合素子。     A transistor having the bidirectional breakdown voltage is formed using the first region and the second region.
    The impedance matching element according to claim 1 or 2.
  6. 　請求項１乃至請求項５のいずれかに記載の構成を有するインピーダンス整合素子と、
    　前記高周波回路と、を備え、
    　前記高周波回路は、前記インピーダンス整合素子に接続される分波回路と、前記分波回路にそれぞれ接続される送信回路および受信回路とを備える、
    　通信装置。     An impedance matching element having the configuration according to claim 1;
    The high-frequency circuit,
    The high-frequency circuit includes a branching circuit connected to the impedance matching element, and a transmission circuit and a reception circuit connected to the branching circuit, respectively.
    Communication device.
  7. 　前記分波回路は、スイッチ回路である、
    　請求項６に記載の通信装置。     The branching circuit is a switch circuit.
    The communication apparatus according to claim 6.
  8. 　前記分波回路は、デュプレクサである、
    　請求項６に記載の通信装置。     The branching circuit is a duplexer;
    The communication apparatus according to claim 6.
  9. 　前記送信回路は、パワーアンプを含み、前記受信回路は、ローノイズアンプを含む、
    　請求項６乃至請求項８のいずれかに記載の通信装置。     The transmission circuit includes a power amplifier, and the reception circuit includes a low noise amplifier.
    The communication apparatus according to claim 6.
PCT/JP2018/047441 2018-05-31 2018-12-25 Impedance matching element, and communication device WO2019230027A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2019530846A JPWO2019230027A1 (en) 2018-05-31 2018-12-25 Impedance matching element and communication device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-104286 2018-05-31
JP2018104286 2018-05-31

Publications (1)

Publication Number Publication Date
WO2019230027A1 true WO2019230027A1 (en) 2019-12-05

Family

ID=68698745

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/047441 WO2019230027A1 (en) 2018-05-31 2018-12-25 Impedance matching element, and communication device

Country Status (2)

Country Link
JP (1) JPWO2019230027A1 (en)
WO (1) WO2019230027A1 (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004214353A (en) * 2002-12-27 2004-07-29 Nec Kansai Ltd Vertical type insulated gate field effect transistor
WO2007135821A1 (en) * 2006-05-19 2007-11-29 Murata Manufacturing Co., Ltd. Matching device, and antenna matching circuit
JP2008544494A (en) * 2005-06-08 2008-12-04 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア Linear variable voltage diode capacitor and adaptive matching network
JP2013026249A (en) * 2011-07-15 2013-02-04 Renesas Electronics Corp Bidirectional zener diode and bidirectional zener diode manufacturing method
JP2014530543A (en) * 2011-09-13 2014-11-17 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ Impedance matching circuit having multiple configurations
JP2015082699A (en) * 2013-10-21 2015-04-27 アスモ株式会社 Motor controller
WO2018066578A1 (en) * 2016-10-07 2018-04-12 株式会社村田製作所 Filter
WO2018150881A1 (en) * 2017-02-14 2018-08-23 株式会社村田製作所 Common mode choke coil, module component, and electronic device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004214353A (en) * 2002-12-27 2004-07-29 Nec Kansai Ltd Vertical type insulated gate field effect transistor
JP2008544494A (en) * 2005-06-08 2008-12-04 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア Linear variable voltage diode capacitor and adaptive matching network
WO2007135821A1 (en) * 2006-05-19 2007-11-29 Murata Manufacturing Co., Ltd. Matching device, and antenna matching circuit
JP2013026249A (en) * 2011-07-15 2013-02-04 Renesas Electronics Corp Bidirectional zener diode and bidirectional zener diode manufacturing method
JP2014530543A (en) * 2011-09-13 2014-11-17 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ Impedance matching circuit having multiple configurations
JP2015082699A (en) * 2013-10-21 2015-04-27 アスモ株式会社 Motor controller
WO2018066578A1 (en) * 2016-10-07 2018-04-12 株式会社村田製作所 Filter
WO2018150881A1 (en) * 2017-02-14 2018-08-23 株式会社村田製作所 Common mode choke coil, module component, and electronic device

Also Published As

Publication number Publication date
JPWO2019230027A1 (en) 2020-06-11

Similar Documents

Publication Publication Date Title
JP4322414B2 (en) Semiconductor device
KR100710434B1 (en) Schottky barrier diode
US7307298B2 (en) Semiconductor device
US20110316062A1 (en) Semiconductor device
US20130056730A1 (en) Semiconductor device
JP2006196802A (en) Semiconductor device and method for manufacturing the same
EP3460843B1 (en) Transistor with shield structure, packaged device, and method of manufacture
US6580107B2 (en) Compound semiconductor device with depletion layer stop region
WO2007062369A2 (en) Semiconductor device and circuit having multiple voltage controlled capacitors
JP4535668B2 (en) Semiconductor device
US6734509B2 (en) Semiconductor integrated circuit
US6891267B2 (en) Semiconductor switching circuit device
US11444078B2 (en) ESD protection element
WO2019230027A1 (en) Impedance matching element, and communication device
KR100644980B1 (en) Compound semiconductor switch circuit device
KR100620923B1 (en) Switching circuit device of compound semiconductor
JP2005353991A (en) Semiconductor device
US20210273118A1 (en) Semiconductor Device
US7750442B2 (en) High-frequency switch
WO2024062789A1 (en) Semiconductor device, method for manufacturing semiconductor device, semiconductor module, and electronic equipment
US10930747B2 (en) Semiconductor device with an encircled electrode
CN100487895C (en) Compound semiconductor device
KR100620927B1 (en) Compound semiconductor device
JP2012019221A (en) Semiconductor device
JP2012015531A (en) Semiconductor device

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2019530846

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18920417

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18920417

Country of ref document: EP

Kind code of ref document: A1