JP2004214353A - Vertical type insulated gate field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a vertical type insulated gate field effect transistor reduced in the number of manufacturing process compared with that of a conventional field effect transistor, without increasing the rate of an area occupied by the chip of a bidirectional Zener diode formed in the same chip by the shape of a diffusion layer as the protective diode of a power MOSFET. <P>SOLUTION: The vertical type insulated gate field effect transistor is provided with a P-base region 25 and, at the same time, a P-type diffusion layer 23 having a pattern area smaller than the P-base region 25, which are formed in an N<SP>-</SP>-drain region 21, and an N<SP>+</SP>-type source region 26 and, at the same time, N<SP>+</SP>-type diffusion layer 24, which are formed in the P-type diffusion layer 23, while the bidirectional Zener diode Z<SB>DG</SB>connected between the drain gates is constituted of the N<SP>-</SP>-drain region 21, the P-type diffusion layer 23, and the N<SP>+</SP>-type diffusion layer 24. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a vertical insulated gate field effect transistor, and more particularly to a power vertical insulated gate field effect transistor having a protection diode on the same chip.
[0002]
[Prior art]
Power vertical insulated gate field effect transistors (hereinafter referred to as power MOSFETs) used in motors, actuators, relays, etc. that use a coil as a load absorb the back electromotive force surge of the coil that occurs when the coil load turns off. It is commonly used with protective diodes that can be used. As this protection diode, there is a power MOSFET characterized in that a bidirectional Zener diode is inserted between a gate and a source and between a drain and a gate, respectively, and integrated on the same chip as the power MOSFET body (for example, see Patent Reference 1). A conventional power MOSFET in which a bidirectional Zener diode between a drain and a gate is formed by a diffusion layer will be described below with reference to Patent Document 1 with reference to FIGS. In the power MOSFET, a large number of parallel-connected unit cells each having a transistor function are usually arranged in a cell portion of a chip. However, in the drawings used in the description of this specification, only one cell is illustrated for convenience. Is shown.
[0003]
N ⁻ drain region 1 is formed on N ⁺ drain region 2. As a power MOSFET body, a P base region 5 is formed in an N ⁻ drain region 1, an N ⁺ source region 6 is formed in a P base region 5, and a P base region between the N ⁺ source region 6 and the N ⁻ drain region 1 is formed. A gate electrode 9 made of polysilicon is formed on region 5 with a gate insulating film 8 interposed therebetween. Di shown in FIG. 5 is a junction diode between the P base region 5 and the N ⁻ drain region 1, and Tr is a parasitic diode having the P base region 5, the N ⁺ source region 6, and the N ⁻ drain region 1 as a base, an emitter and a collector, respectively. transistors, _{R B} is a parasitic base resistance. A bidirectional Zener diode Z _GS (consisting of an N-type polysilicon film 10-1, a P ⁺ -type polysilicon film 11, and an N-type polysilicon film 10-2) is connected between the gate and the source. Between the drain and gate N ^- connects the drain region N ⁺ diffusion layer 12 formed in 1, P-type diffusion layer 3, N ⁺ consists type diffusion layer 4 bidirectional Zener diode Z _DG. The Zener diode Z _GS is formed continuously with the gate polysilicon of the main body. The Zener diode _ZDG is formed in the N ^- drain region 1 by ion implantation and pressing. In order to lower the breakdown voltage below the breakdown voltage of the FET body, an N ⁺ diffusion layer 12 of the same conductivity type as the drain region 1 and slightly higher in concentration than the drain region 1 is formed, and a Zener diode is formed therein.
[0004]
The operation of the power MOSFET having the above configuration will be described with reference to FIGS. When the gate voltage V _GS rises and the power MOSFET turns on, the drain current I _DS rises, and the drain voltage V _DS becomes V _{DS (on)} . drain voltage _{V DS} of the input voltage drops power MOSFET in the toff is begin to soaring gate voltage so as to suppress the rise of the drain voltage _{V DS} of the power MOSFET at the moment beyond the _BV ZGS _{+ BV ZDG} is applied. That is, a sufficiently large discharge current can flow even with the small power Zener diode _ZDG by using the amplifying action of the power MOSFET of the main body.
Note that the breakdown voltage _{BV ZDG} of the Zener diode _{Z DG} is designed to satisfy the following conditions.
BV _ZDG <LV _{CER −BV ZGS} ,
LV _CER ... Latchback voltage of parasitic transistor,
BV _ZGS ... breakdown voltage of Zener diode Z _GS ,
The BV _ZGS is designed to satisfy the following conditions.
V _{GS (on)} <BV _ZGS <V _{GS (max)} ,
V _{GS (on)} : gate voltage when the power MOSFET is turned on,
V _{GS (max)} …… Gate breakdown voltage
[Patent Document 1]
Japanese Patent Application Laid-Open No. 3-038881
[Problems to be solved by the invention]
In the conventional power MOSFET described above, the breakdown voltage BV _ZDG of the diffusion layer type bidirectional Zener diode Z _DG inserted between the drain and the gate for preventing the latch-back of the parasitic transistor is _reduced by the breakdown voltage BV _{DS of the} power MOSFET body. In order to further lower the impedance, the bidirectional Zener diode _ZDG is configured by forming a Zener diode in the N ⁺ diffusion layer 12 having a slightly higher concentration than the N ⁻ drain region 1. Therefore, in the manufacturing process of the power MOSFET, a step of forming the N ⁺ diffusion layer 12 is required, and there is a problem that the number of steps is increased.
The present invention has been made in view of the above problems, and an object of the present invention is to provide a vertical insulated gate field effect transistor in which the number of manufacturing steps is reduced without increasing the area of the chip of the bidirectional Zener diode _ZDG. To provide.
[0007]
[Means for Solving the Problems]
The vertical insulated gate field effect transistor of the present invention includes a low-concentration one-conductivity-type drain region, a plurality of other-conductivity-type base regions formed in the drain region, and a high-concentration one-conductivity-type source region formed in each base region. A vertical insulated gate field effect transistor having a vertical insulated gate field effect transistor body and a bidirectional Zener diode for protection formed between a drain and a gate of the transistor body and formed on the same chip as the transistor body In the transistor, the bidirectional Zener diode includes the drain region, at least one other conductivity type diffusion layer formed in the drain region with a smaller area than each base region at the same time as the base region, and the other conductivity type diffusion layer A high concentration one conductivity type diffusion layer formed simultaneously with the source region.
In the vertical insulated gate field effect transistor, the other conductivity type diffusion layer is connected to the gate via a first resistor formed on the same chip as the transistor body, and the other conductivity type diffusion layer is A second resistor formed on the same chip as the transistor body is connected to a connection point between the layer and the first resistor, or an external second resistor is connected.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
An N-channel power MOSFET according to one embodiment of the present invention will be described below with reference to FIGS. An N ⁻ drain region 21 is formed on the N ⁺ drain region 22. A P base region 25 is formed in the N ⁻ drain region 21 and an N ⁺ source region 26 is formed in the P base region 25 to constitute a power MOSFET body. Also, N ^- P base region 25 simultaneously with the P base region 25 than the pattern area is small P-type diffusion layer 23, and the P-type diffusion layer ^{N +} -type diffusion layer at the same time as the ^{N +} source region 26 in 23 in the drain region 21 24 is formed, a bidirectional Zener diode _{Z DG} is connected between the drain and gate, N ^- constitutes a drain region 21, P-type diffusion layer 23, ^{N +} -type diffusion layer 24. At this time, the breakdown voltage of the Zener diode _ZDG is lower than the breakdown voltage of the FET body because the pattern area of the P-type diffusion layer 23 is smaller than that of the P base region 25. Further, a P well 27 is formed in the N ⁻ drain region 21 at a position directly below a gate pad (not shown). Then, on the P base region 25 between the N ⁺ source region 26 and the N ⁻ drain region 21 and on the P type diffusion layer 23 between the N ⁺ type diffusion layer 24 and the N ⁻ drain region 21 via the gate insulating film 28. A gate electrode 29 made of polysilicon is formed. A bidirectional Zener diode Z _GS (comprising an N-type polysilicon film 30-1, a P ⁺ -type polysilicon film 31, and an N-type polysilicon film 30-2) is connected between the gate and the source.
[0009]
The power MOSFET of this embodiment has the following configuration in addition to the above configuration. Between the connection point between the N ⁺ type diffusion layer 24 and the N type polysilicon film 30-2 and the gate electrode 29, a built-in first resistor 32 made of a diffusion layer or a polysilicon film (not shown as a diffusion layer or a polysilicon film). Zu) are connected. A built-in second resistor 33 (diffusion layer or polysilicon) formed of a diffusion layer or a polysilicon film is provided between a connection point between the N ⁺ type diffusion layer 24 and the N-type polysilicon film 30-2 and a gate pad (not shown). (Not shown as a silicon film). Note that the second resistor 33 may be an external resistor.
[0010]
Resistance R ₂ of the second resistor 33, also a pattern area of the P-type diffusion layer 23 of the Zener diode Z _DG is made smaller than the area of the P base region 25, is set to an appropriate value to allow a surge absorber. That is, in the power MOSFET having the above structure, by setting the resistance value R ₂ of the second resistor 33 to a proper value, if the L load back electromotive force from the drain side is applied, the Zener diode Z _DG is FET body Breakdown _occurs at a breakdown voltage _BVZDG lower than the breakdown voltage, and a current at that time generates a voltage higher than the threshold voltage of the FET main body in the second resistor 33, and the voltage is applied to the gate of the FET main body, and the FET main body is turned on. Then, the L load back electromotive force is absorbed. For example, in 2V threshold voltage of the FET body, when the current capacity of the Zener diode _{Z DG} and 1 .mu.A, the resistance value _{R 2} of the second resistor 33 becomes 2 M [Omega.
[0011]
With the above configuration, the resistance value of the second resistor R2 is set to an appropriate value, and the pattern area of the P-type diffusion layer 23 is made smaller than that of the P base region 25. cell unit with (FET body) 41 and the gate pad portion 42, as shown and a Zener diode _{Z DG,} and a second resistor R2, which is formed of a polysilicon film between gate pad portion 42 and the Zener diode _{Z DG,} chip area Power MOSFET can be manufactured without increasing the power MOSFET in comparison with the related art. Further, since the P-type diffusion layer 23 and the N ⁺ -type diffusion layer 24 forming the Zener diode _ZDG are formed simultaneously with the P base region 25 and the N ⁺ source region 26 of the FET main body, the power MOSFET can be manufactured in a smaller number of steps than before. Can be manufactured.
[0012]
【The invention's effect】
As described above, according to the present invention, the bidirectional Zener diode between the drain and the gate is provided with a high-concentration one-conductivity-type drain region and at least one other drain region formed at the same time as the base region with a smaller area than each base region. A vertical-type insulated-gate field-effect transistor is used without increasing the chip area, as it is composed of a conductive-type diffusion layer and a high-concentration one-conductivity-type diffusion layer formed simultaneously with the source region in the other-type diffusion layer. Can be manufactured with fewer steps.
[Brief description of the drawings]
FIG. 1 is a sectional view of a main part of a power MOSFET according to an embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of the power MOSFET of FIG.
FIG. 3 is a schematic plan view of the power MOSFET of FIG. 1;
FIG. 4 is a sectional view of a main part of a conventional power MOSFET.
5 is an equivalent circuit diagram of the power MOSFET of FIG.
6 is an equivalent circuit diagram when the power MOSFET of FIG. 4 is driven by a coil load.
FIG. 7 is a timing chart when the power MOSFET of FIG. 4 is driven by a coil load.
[Explanation of symbols]
Reference numeral 21 N ^- drain region 22 N ⁺ drain region 23 P-type diffusion layer 24 N ⁺ -type diffusion layer 25 P base region 26 N ⁺ source region 27 P well 28 gate insulating film 29 gate electrode 30 first resistor 31 second resistor

Claims (2)

A vertical insulated gate field effect transistor body having a low concentration one conductivity type drain region, a plurality of other conductivity type base regions formed in the drain region, and a high concentration one conductivity type source region formed in each base region, and a transistor A vertical insulated gate field effect transistor having a protective bidirectional Zener diode connected between the drain and the gate of the transistor body, which is formed of a diffusion layer on the same chip as the body,
The bidirectional Zener diode includes: a drain region; at least one other conductivity type diffusion layer formed in the drain region with a smaller area than each base region at the same time as the base region; and a source region in the other conductivity type diffusion layer. A vertical insulated gate field effect transistor having a high concentration one conductivity type diffusion layer formed at the same time. The other conductivity type diffusion layer is connected to the gate via a first resistor formed on the same chip as the transistor body, and the transistor is connected to a connection point between the other conductivity type diffusion layer and the first resistor. 2. The vertical insulated gate field effect transistor according to claim 1, wherein a second resistor formed on the same chip as the main body is connected or an external second resistor is connected.

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