WO2018146799A1 - Semiconductor device and electrical power conversion device - Google Patents

Semiconductor device and electrical power conversion device Download PDF

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Publication number
WO2018146799A1
WO2018146799A1 PCT/JP2017/004973 JP2017004973W WO2018146799A1 WO 2018146799 A1 WO2018146799 A1 WO 2018146799A1 JP 2017004973 W JP2017004973 W JP 2017004973W WO 2018146799 A1 WO2018146799 A1 WO 2018146799A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
lead frame
metal foil
laminated sheet
insulating sheet
Prior art date
Application number
PCT/JP2017/004973
Other languages
French (fr)
Japanese (ja)
Inventor
穂隆 六分一
健 開田
山本　圭
清文 北井
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to CN201780085650.2A priority Critical patent/CN110268518B/en
Priority to PCT/JP2017/004973 priority patent/WO2018146799A1/en
Priority to JP2017559719A priority patent/JP6279186B1/en
Publication of WO2018146799A1 publication Critical patent/WO2018146799A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a transfer mold type semiconductor device provided with a sealing resin.
  • the lead frame In a conventional semiconductor device provided with a sealing resin like the transfer mold type semiconductor device described above, a lead frame on which a semiconductor element is mounted so as to ensure insulation performance by suppressing partial discharge at the end of the insulating sheet; In order to maintain a creepage distance from the high thermal conductive insulating sheet, the lead frame has a structure bent inside the sealing resin.
  • the bent lead frame has a shape in which the space between the frame patterns is widened, which may lead to an increase in the size of the entire lead frame, and in turn, an increase in the size of the semiconductor device and the entire semiconductor module using the semiconductor device. is there.
  • a structure for projecting terminals for external connection from three or more sides of a semiconductor device is used, there is a possibility that interference between lead frames may occur due to bending, and there is a possibility that the lead frame pattern is limited. .
  • the present invention provides a semiconductor device that can be reduced in size while suppressing the occurrence of partial discharge at the end face of the insulating sheet and increasing the creepage distance between the insulating sheet and the lead frame to maintain the insulating performance. For the purpose.
  • the semiconductor device includes a laminated sheet, a lead frame, a semiconductor element, and a sealing housing.
  • the laminated sheet is obtained by laminating a conductor layer and an insulating layer.
  • the lead frame is disposed on the laminated sheet.
  • the semiconductor element is disposed on the lead frame.
  • the sealing housing is made of resin and seals the semiconductor element, a part of the lead frame, and a part of the laminated sheet.
  • An opening that exposes a part of the back surface opposite to the front surface facing the lead frame in the laminated sheet is formed in the sealing housing.
  • the sealing housing includes a rib portion that surrounds the opening and protrudes in a direction perpendicular to the back surface of the laminated sheet.
  • the end portion of the conductor layer located at a part of the outer peripheral portion exposed from the opening is embedded in the sealed casing.
  • a power conversion device includes the above-described semiconductor device, a main conversion circuit that converts and outputs input power, and a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit; Is provided.
  • the rib portion that secures the creepage distance between the lead frame located outside the sealing housing and the laminated sheet exposed from the opening is formed, a sufficient creepage distance is maintained.
  • the size of the semiconductor device in plan view can be reduced.
  • the end portion of the conductor layer of the laminated sheet is embedded in the sealed casing, the partial discharge start voltage at the end portion of the conductor layer is increased. As a result, the insulation performance of the semiconductor device is improved.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a partial cross-sectional schematic diagram of the semiconductor device shown in FIG. 1.
  • FIG. 2 is a schematic perspective view seen from the surface side of the semiconductor device shown in FIG. 1.
  • FIG. 2 is a schematic perspective view seen from the back side of the semiconductor device shown in FIG. 1.
  • FIG. 2 is a schematic diagram showing a relationship between a lead frame and a laminated sheet in the semiconductor device shown in FIG. 1.
  • 2 is a flowchart showing a method for manufacturing the semiconductor device shown in FIG. It is a cross-sectional schematic diagram of the semiconductor device which concerns on Embodiment 2 of this invention.
  • FIG. 11 is a partial schematic cross-sectional view of the semiconductor device shown in FIG. 10. It is a block diagram which shows the structure of the power conversion system which concerns on Embodiment 5 of this invention.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention.
  • 2 is a schematic partial sectional view of the semiconductor device of FIG. 1
  • FIG. 3 is a schematic perspective view of the semiconductor device of FIG.
  • FIG. 4 is a schematic perspective view of the semiconductor device of FIG. 1 viewed from the insulating sheet 3b side (back side) with a metal foil as a laminated sheet.
  • FIG. 5 is a schematic diagram showing the relationship between the lead frame and the laminated sheet in the semiconductor device shown in FIG.
  • the semiconductor device 10 mainly includes a lead frame 1, an insulating sheet 3b with metal foil, a power element 5 as a semiconductor element, a wire 6 as a conductive wire, and a resin casing 7 as a sealing casing.
  • the lead frame 1 includes a wiring part for mounting the power element 5 and an external terminal part 12 exposed from the resin casing 7.
  • the power element 5 is mounted on the wiring part, and the back electrode of the power element 5 is connected to the wiring part with solder or the like. Further, the wires 6 are connected between the power elements 5 and between the surface electrode of the power element 5 and the wiring portion.
  • the lead frame 1 is electrically connected to the electrode of the power element 5.
  • the insulating sheet 3b with metal foil is a laminated sheet in which the insulating sheet 3 is laminated on the metal foil 4.
  • a lead frame 1 is disposed on the insulating sheet 3.
  • a power element 5 is disposed on the lead frame 1.
  • the resin casing 7 is formed so as to seal a part of the lead frame 1, the power element 5, the wire 6, and the insulating sheet 3b with metal foil.
  • a part of the bottom face part 20 which is the surface of the metal foil 4 of the insulating sheet 3b with metal foil is exposed from the resin casing 7.
  • the outer peripheral edge of the insulating sheet 3b with metal foil is embedded in the resin casing 7.
  • casing 7 is arrange
  • the external terminal unit 12 has a plurality of terminals connected to an external device or the like. Each terminal of the external terminal portion 12 is bent into an L shape outside the resin casing 7 and exposed from the resin casing 7.
  • FIG. 3 shows an example in which the external terminal portion 12 protrudes from the resin casing 7 from three directions of the semiconductor device 10.
  • the external terminal portion 12 may be formed so as to protrude from the resin casing 7 in one direction or in two different directions.
  • the external terminal portion 12 which is an example of a configuration that makes it difficult to design the frame pattern of the lead frame 1, protrudes in two directions, the half that forms the stepped portion 8 of the lead frame 1 as shown in FIGS. 1 and 2.
  • the merit of the punching process becomes particularly remarkable.
  • the step 8 equivalent to the half blanking process may be formed by bending the lead frame 1. In this case, the lead frame 1 is bent so as not to affect the distance between the patterns of the lead frame 1 due to the bending process or to prevent pattern interference.
  • the insulating sheet 3b with metal foil includes the insulating sheet 3 that is an insulating layer having high heat dissipation and the metal foil 4.
  • the insulating sheet 3 insulates the lead frame 1 from the metal foil 4.
  • the heat generated by the power element 5 is radiated to the metal foil 4 through the insulating sheet 3.
  • a thermosetting resin such as an epoxy resin is used.
  • a high thermal conductive filler such as silica, alumina, boron nitride or the like is mixed therein.
  • the metal foil 4 a high thermal conductive member such as a copper plate, an aluminum plate, or a copper foil is used.
  • the thickness of the metal foil 4 may be thin, it is preferably 0.03 mm or more and 0.40 mm or less so as to have a self-supporting property.
  • the lower limit of the thickness of the metal foil 4 may be 0.05 mm, 0.10 mm, 0.15 mm, or 0.20 mm.
  • the upper limit of the thickness of the metal foil 4 may be 0.35 mm, 0.30 mm, or 0.25 mm.
  • the lead frame 1 is formed by forming a pattern by press molding a copper plate or an aluminum plate.
  • a stepped portion 8 having a height (for example, 0.3 mm) that is half the thickness of the lead frame (for example, 0.6 mm) is formed by half blanking.
  • the stepped portion 8 can be formed in the lead frame 1 by stopping the movement of the processing tool in the middle of the thickness direction of the lead frame 1 in a process such as a punch press.
  • the thickness of the lead frame 1 can be set to any thickness as long as it can be processed by press molding, and may be greater than 0.6 mm, for example.
  • the height of the stepped portion 8 of the lead frame 1 may be, for example, 0.1 mm or more.
  • a part of the resin casing 7 is filled between the lead frame 1 and the insulating sheet 3 in a gap that is located between the lead frame 1 and the insulating sheet 3 and that is continuous with the stepped portion 8 without generation of voids.
  • the height of the stepped portion 8 is desirably 0.1 mm or more and half or less of the thickness of the lead frame 1.
  • FIG. 3 and 4 show a configuration in which the external terminal portion 12 of the lead frame 1 is bent so as to extend in a direction intersecting the upper surface of the resin casing 7, FIG. 1 and FIG.
  • the bent shape of the external terminal portion 12 of the lead frame 1 is not shown.
  • the power element 5 is, for example, a diode used in a converter unit that converts input AC power into DC power, or a bipolar transistor, IGBT (Insulated Gate Bipolar Transistor), MOSFET (Metal Oxide Semiconductor) that is used in an inverter unit that converts DC power into AC power. It may be a Field Effect Transistor (GFT), a Gate Turn-Off thyristor (GTO), or the like.
  • GFT Field Effect Transistor
  • GTO Gate Turn-Off thyristor
  • Resin casing 7 may be formed of a thermosetting resin such as epoxy.
  • the resin casing 7 is resin-molded at a high temperature using techniques such as transfer molding, injection molding, and compression molding.
  • the resin casing 7 ensures insulation between members disposed inside the resin casing 7.
  • the resin casing 7 seals the power element 5 so that one surface (the bottom surface portion 20 which is an exposed surface) of the insulating sheet 3b with metal foil and a part of the lead frame 1 (the external terminal portion 12) are exposed.
  • the resin housing 7 includes the rib portion 2. In the resin casing 7 including the rib portion 2, the end portion of the insulating sheet 3b with metal foil is embedded in the inside.
  • the rib portion 2 is formed to protrude from the bottom surface portion 20 in a direction perpendicular to the bottom surface portion 20.
  • the rib part 2 is formed so that the end part 14 of the metal foil is buried inside.
  • the rib portion 2 is provided so as to protrude to the side opposite to the direction of the stepped portion 8 of the lead frame 1 with the bottom surface portion 20 (exposed surface) of the insulating sheet 3b with metal foil as a reference surface.
  • the rib portion 2 is formed so as to fill the entire periphery of the insulating sheet 3b with metal foil. If it says from a different viewpoint, the rib part 2 is formed along the outer periphery in the planar view of the semiconductor device 10. As shown in FIG.
  • the shape of the semiconductor device 10 in plan view is a polygonal shape (for example, a square shape)
  • the rib portions 2 along adjacent sides of the polygonal shape are connected.
  • angular part which is a boundary part of the said adjacent edge is improved by connecting between the parts along an adjacent edge
  • the bending rigidity of the semiconductor device 10 in the counter electrode direction (for example, three opposing corner directions) is improved.
  • the rib portion 2 it is possible to ensure a creepage distance between the external terminal portion 12 of the lead frame 1 and the metal foil 4. For this reason, since it is not necessary to increase the size of the semiconductor device in order to ensure the creepage distance between the external terminal portion 12 and the metal foil 4 without forming the rib portion 2, the size of the semiconductor device can be reduced. Realized.
  • the corners of the rib portion 2 may be R-shaped or tapered.
  • the distance L1 between the end 13 and the end 14 of the metal foil 4 is, for example, 1.0 mm, and the distance between the end 14 of the metal foil 4 made of copper or the like and the bottom surface 15 of the rib 2 in the vertical direction.
  • L2 is 3.0 mm.
  • the distance L1 between the end 13 and the end 14 of the metal foil 4 is desirably 0.2 mm or more.
  • the distance L2 in the vertical direction between the copper foil end portion 14 and the bottom surface 15 of the rib portion 2 is preferably 0.2 mm or more.
  • the stepped portion 8 of the lead frame 1 is preferably located inside the end portion 14 of the metal foil 4.
  • the areas of the insulating sheet 3 and the metal foil 4 are preferably the same, but may be different.
  • the distance L3 between the stepped portion 8 and the end 14 of the metal foil 4 may be, for example, 0.2 mm or more, 0.3 mm or more, or 0.5 mm or more. Further, the upper limit of the distance L3 may be 3.0 mm or 2.0 mm.
  • the insulating sheet 3 and the metal foil 4 may be deformed in the vertical direction with respect to the upper surface of the resin casing 7 which is the upper surface of the semiconductor device. Even in this case, the distance L1 between the end portion 14 of the metal foil 4 and the end portion 13 where the rib is formed and the distance L2 between the end portion 14 and the bottom surface 15 of the rib portion 2 are each 0.2 mm or more. It is desirable.
  • the lead frame 1 may be in contact with the insulating sheet 3 deformed to the lead frame 1 side at a position outside the step portion 8 of the lead frame 1. On the other hand, the end 14 of the metal foil 4 is not allowed to contact the lead frame 1.
  • FIG. 1 shows an example in which the stepped portion 8 is provided inside the end surface of the lead frame 1 that contacts the insulating sheet 3.
  • a semiconductor device 10 includes an insulating sheet 3b with a metal foil as a laminated sheet, a lead frame 1, a power element 5 as a semiconductor element, and a resin casing 7 as a sealing casing.
  • the insulating sheet 3b with metal foil is obtained by laminating a metal foil 4 as a conductor layer and an insulating sheet 3 as an insulating layer.
  • the lead frame 1 is disposed on the insulating sheet 3b with metal foil.
  • the power element 5 is disposed on the lead frame 1.
  • the resin casing 7 is made of resin and seals the power element 5, part of the lead frame 1, and part of the insulating sheet 3b with metal foil.
  • the resin casing 7 has an opening that exposes a part of the back surface opposite to the front surface facing the lead frame 1 in the insulating sheet 3b with metal foil.
  • the resin casing 7 includes a rib portion 2 that surrounds the opening and protrudes in a direction perpendicular to the bottom surface portion 20 as the back surface of the insulating sheet 3b with metal foil.
  • the end portion 14 of the metal foil 4 located on the outer periphery of a part of the bottom surface portion 20 exposed from the opening 17 is embedded in the resin casing 7.
  • the rib portion 2 that secures the creeping distance between the lead frame 1 located outside the resin casing 7 and the insulating sheet 3b with the metal foil exposed from the opening is sufficiently formed.
  • the size of the semiconductor device 10 in plan view can be reduced while maintaining a large creepage distance.
  • the end portion 14 of the metal foil 4 of the insulating sheet 3b with the metal foil is embedded in the resin casing 7, the partial discharge start voltage at the end portion 14 of the metal foil 4 increases. As a result, the insulation performance of the semiconductor device 10 can be improved and the reliability thereof can be improved.
  • the rib portion 2 includes a side wall that forms the inner peripheral surface of the opening.
  • the end 13 of the side wall on the side of the insulating sheet 3b with metal foil is located on the inner peripheral side from the end 14 of the metal foil 4.
  • the distance L1 between the end 13 on the side wall and the end 14 of the metal foil 4 is 0.2 mm or more. In this case, the partial discharge start voltage at the end 14 of the metal foil 4 can be made sufficiently high.
  • the resin casing 7 is a molded body formed using a transfer molding method.
  • the end portion 14 of the metal foil 4 of the insulating sheet 3b with the metal foil is disposed in the region where the resin casing 7 is formed inside the mold for forming the resin casing 7 in the transfer molding method.
  • a structure in which the end 14 of the metal foil 4 is embedded in the resin casing 7 can be easily obtained.
  • the shape of the resin casing 7 in plan view is a polygonal shape including a first side extending in the left-right direction of the paper surface in FIG. 3 and a second side extending in a direction different from the first side on the outer periphery. It is.
  • the shape of the resin casing 7 in plan view may be a quadrangular shape as shown in FIG.
  • the lead frame 1 includes a first external terminal portion 12 protruding outward from the first side of the resin housing 7 and a second external terminal portion 12 protruding outward from the second side of the resin housing 7.
  • the configuration in which the rib portion 2 and the end portion 14 of the metal foil 4 according to the present disclosure are embedded in the resin casing 7 does not interfere with each other in either the first side or the second side of the resin casing 7. Since it can be formed, the configuration according to the present disclosure can be easily applied to the semiconductor device 10 including the first and second external terminal portions 12 as described above.
  • the lead frame 1 has a step 8 formed on the insulating sheet 3b with metal foil in a direction away from the insulating sheet 3b with metal foil.
  • the height G of the stepped portion 8 is less than the thickness of the lead frame 1. In this case, the occurrence of a problem that the lead frame 1 is broken at the stepped portion 8 can be suppressed.
  • the lead frame 1 includes a first portion that overlaps the opening 17 in a plan view and a second portion that continues to the first portion and overlaps the end portion 14 of the metal foil 4.
  • a step portion 8 is formed in the first portion so that the second portion is spaced from the end portion 14 of the metal foil 4.
  • the second portion of the lead frame 1 is disposed with a space between the end portion 14 of the metal foil 4, the second portion of the lead frame 1 is disposed between the end portion 14 of the metal foil 4.
  • a part of the resin casing 7 can be arranged. As a result, the end 14 of the metal foil 4 can be reliably embedded in the resin casing 7.
  • the lead frame 1 includes a mounting portion on which the power element 5 is mounted and an outer peripheral portion located on the outer peripheral side from the mounting portion. In a direction perpendicular to the surface of the insulating sheet with metal foil 3b, the distance L8 from the insulating sheet with metal foil 3b to the surface of the mounting portion is smaller than the distance L9 from the insulating sheet with metal foil 3b to the surface of the outer peripheral portion. .
  • the distance L10 between the surface of the mounting portion and the surface of the outer peripheral portion is less than the thickness of the lead frame 1 in the direction perpendicular to the surface of the insulating sheet 3b with metal foil.
  • a step portion 8 or a bent portion 9 shown in FIG. When formed, the deformation amount of the lead frame 1 at the stepped portion 8 and the bent portion 9 can be made less than the thickness of the lead frame 1. For this reason, generation
  • the amount of deformation in the thickness direction of the insulating sheet 3b with metal foil is 0.3 mm or less. In this case, the possibility that the metal foil 4 constituting the insulating sheet 3b with metal foil and the outer peripheral portion of the lead frame 1 come into contact with each other can be reduced.
  • the power element 5 is made of a wide band gap semiconductor material. In this case, it is possible to obtain the semiconductor device 10 that can operate at a higher temperature and has a higher withstand voltage than the case where the power element 5 is formed of silicon.
  • the wide band gap semiconductor material includes one selected from the group consisting of silicon carbide (SiC), gallium nitride (GaN), and diamond.
  • the semiconductor device 10 includes the power element 5 as a semiconductor element, the insulating sheet 3b with a metal foil as a laminated sheet that dissipates heat from the power element 5, and the electrode of the power element 5.
  • a lead frame 1 electrically connected to the substrate, and a resin casing 7 as a sealing casing for sealing the power element 5 so that one surface of the insulating sheet 3b with metal foil and a part of the lead frame 1 are exposed. Is provided.
  • a part of the power element 5 and the lead frame 1 is disposed inside, and one surface of the metal foil 4 is exposed at the bottom surface portion 20.
  • the resin casing 7 of the semiconductor device 10 includes a rib portion 2 provided so as to protrude from the bottom surface portion 20 in a vertical direction.
  • the end portion 14 of the metal foil 4 is embedded in the rib portion 2.
  • the semiconductor device 10 according to the first embodiment has a structure in which the rib portion 2 is provided so as to protrude in the vertical direction from the bottom surface portion 20 and the end portion 14 of the metal foil 4 is embedded in the rib portion 2. It is possible to suppress the electric field strength at the end portion 14 of the metal foil 4 while securing the creeping distance between the external terminal portion 12 and the metal foil 4. As a result, the semiconductor device 10 can be downsized and the partial discharge start voltage can be improved.
  • FIG. 6 is a flowchart showing a manufacturing method of the semiconductor device shown in FIG. A method of manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIG.
  • a preparation step (S10) is performed as shown in FIG.
  • components that constitute the semiconductor device 10, such as the metal foil 4, the power element 5, and the lead frame 1 on which the semi-cured insulating sheets are laminated, are prepared.
  • the power element 5 is mounted at a predetermined position on the lead frame 1 and connects the electrode of the power element 5 and the lead frame 1 using a wire 6.
  • a resin casing forming step (S20) is performed.
  • a metal foil 4 in which a semi-cured insulating sheet is laminated is placed inside a mold for transfer molding the resin casing 7.
  • the lead frame 1 is installed on the metal foil 4 on which the semi-cured insulating sheets are laminated.
  • a power element 5 and wires 6 are mounted on the lead frame 1 in advance.
  • the positioning of the metal foil 4 with respect to the mold for forming the resin casing 7 is performed by arranging two movable pins on the side surface of the corner of the metal foil 4 and arranging these movable pins on the metal foil 4 4. It is carried out by adjusting the position of the movable pin by installing it at the deviation of one corner. A movable pin is installed in the position which forms the rib part 2 (refer FIG. 1) in a metal mold
  • the metal foil 4 is disposed so that the end portion 14 of the metal foil 4 is not in contact with the mold. In this state, resin is injected into the mold. As a result, the end portion 14 of the metal foil 4 has a structure embedded in the rib portion 2, and an improvement in insulation is expected.
  • the resin is cured by the resin filling pressure and the resin temperature in the mold to form the resin casing 7, and at the same time, semi-cured insulation via the lead frame 1 is performed.
  • the sheet is cured while being pressed against the metal foil 4 to form an insulating sheet 3 (see FIG. 1). Thereby, the insulation and heat dissipation of the insulating sheet 3 are improved.
  • the semi-cured insulating sheet is cured first to become the insulating sheet 3, and the lead frame 1 and the insulating sheet 3 are in close contact with each other. Deteriorates. As a result, the heat dissipation and insulation of the semiconductor layer may deteriorate.
  • a post-processing step (S30) is performed.
  • the semiconductor device including the cured resin casing 7 is taken out from the inside of the mold.
  • necessary post-processing such as processing on the external terminal portion 12 of the lead frame 1 is performed. In this way, the semiconductor device shown in FIGS. 1 to 4 can be obtained.
  • FIG. 7 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention.
  • the semiconductor device shown in FIG. 7 basically has the same configuration as that of the semiconductor device shown in FIGS. 1 to 4, but the shape of the lead frame 1 is different from that of the semiconductor device shown in FIGS. Yes. That is, in the semiconductor device shown in FIG. 7, the shape of the step of the lead frame 1 is different from that of the semiconductor device shown in FIGS.
  • a frame bent portion also referred to as a bent portion 9 is formed instead of the stepped portion 8 (see FIG. 2).
  • the gap between the lead frame 1 and the insulating sheet 3 (also referred to as the height G of the stepped portion 8) is set to 0.3 mm.
  • the bent portion 9 includes a portion inclined with respect to the surface of the insulating sheet 3.
  • the horizontal length L4 of the inclined portion is, for example, 0.3 mm.
  • the angle ⁇ between the inclined portion and the insulating sheet 3 is, for example, 45 °.
  • the angle ⁇ may be less than 45 °, but in that case, the size of the semiconductor device tends to increase.
  • the height G may be 0.1 mm or more as in the first embodiment.
  • FIG. 8 is a schematic perspective view of a semiconductor device according to the third embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional view of the semiconductor layer shown in FIG. 8 corresponds to FIG. 3, and FIG. 9 corresponds to FIG.
  • the semiconductor device shown in FIGS. 8 and 9 basically has the same configuration as the semiconductor device shown in FIGS. 1 to 4, but at least one through hole 11 is formed in the central portion of the semiconductor device 10. Is different.
  • a through hole 11 that penetrates the resin casing 7 and the insulating sheet 3 b with metal foil is formed.
  • the insulating sheet 3b with metal foil used in the present embodiment may be provided with a hole 16 to be the through hole 11 that penetrates the insulating sheet 3 and the metal foil 4 when molded by punching or the like.
  • the position of the through hole 11 in the semiconductor device 10 can be set to an arbitrary position.
  • the through hole 11 may be formed at a position close to the center of the resin casing 7 in plan view as shown in FIG. You may form the through-hole 11 in.
  • one of the plurality of through holes 11 is arranged at the center of the resin casing 7, and the other through holes 11 are arranged on the outer peripheral portion of the resin casing 7. Also good. Further, all of the plurality of through holes 11 may be arranged on the outer peripheral portion of the resin casing 7 in plan view.
  • a through hole 11 reaching the portion is formed.
  • the inner wall of the through hole 11 is constituted by a part of the resin casing 7.
  • the resin casing 7 includes an inner peripheral rib portion 27 that surrounds the inner peripheral end 23 of the metal foil 4 in the insulating sheet 3b with the metal foil facing the inner wall of the through hole 11.
  • the inner peripheral rib portion 27 includes an outer peripheral side wall facing the rib portion 2.
  • the end of the outer peripheral side wall on the side of the insulating sheet with metal foil 3 b is located on the outer peripheral side of the inner peripheral end 23 of the metal foil 4.
  • the distance L7 between the end portion on the outer peripheral side wall and the inner peripheral end portion 23 of the metal foil 4 is 0.2 mm or more.
  • the distance L5 to the surface is 0.2 mm or more.
  • the bottom surface 15 that is the surface in the direction perpendicular to the bottom surface portion 20 that is the back surface of the insulating sheet 3b with the metal foil in the inner peripheral rib portion 27, and the metal foil
  • the distance L6 between the inner peripheral side end portion 4 of 4 is 0.2 mm or more.
  • FIG. 10 is a schematic cross-sectional view of a semiconductor device according to the fourth embodiment of the present invention.
  • 11 is a partial schematic cross-sectional view of the semiconductor device shown in FIG. 10 corresponds to FIG. 1, and FIG. 11 is a schematic partial sectional view of the semiconductor device showing the vicinity of the through hole 11 in FIG.
  • the semiconductor device shown in FIGS. 10 and 11 basically has the same configuration as the semiconductor device shown in FIGS. 8 and 9, but the metal foil 4 facing the through hole 11 is one of the resin casings 7.
  • the semiconductor device shown in FIGS. 8 and 9 is different from the semiconductor device shown in FIGS. That is, in the semiconductor device shown in FIGS.
  • the inner peripheral rib portion 27 in which a part of the resin casing 7 protrudes from the bottom surface portion 20 is formed around the through hole 11 in the central portion of the bottom surface portion 20.
  • the inner peripheral side end 23 of the metal foil 4 is not exposed on the inner peripheral surface of the through hole 11.
  • the distance L5 between the inner peripheral end 23 of the metal foil 4 and the inner wall of the through hole 11 can be set to 0.2 mm or more, for example.
  • the distance L6 between the back surface which is the surface facing the surface of the metal foil 4 in the inner peripheral rib portion 27 and the metal foil 4 can also be set to 0.2 mm or more, for example.
  • the distance L7 between the end on the metal foil 4 side and the inner peripheral side end 23 of the metal foil 4 on the outer peripheral side wall located on the opposite side of the through hole 11 of the inner peripheral rib portion 27 is also, for example, 0. It can be 2 mm or more.
  • the inner peripheral rib portion 27 of the semiconductor device described above can be formed, for example, by adjusting the shape of a mold for forming the resin casing 7 as described below. That is, the periphery of the region where the through hole 11 is to be formed is dug deeper than the surface of the mold that contacts the bottom surface portion 20 of the semiconductor device. If it does in this way, the edge part by the side of the through-hole 11 of the insulating sheet 3b with metal foil will be covered with a part of resin housing 7 by introduce
  • Embodiment 5 the semiconductor device according to Embodiments 1 to 4 described above is applied to a power conversion device.
  • the present invention is not limited to a specific power converter, hereinafter, a case where the present invention is applied to a three-phase inverter will be described as a fifth embodiment.
  • FIG. 12 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.
  • the power conversion system shown in FIG. 12 includes a power supply 100, a power conversion device 200, and a load 300.
  • the power source 100 is a DC power source and supplies DC power to the power conversion device 200.
  • the power source 100 can be composed of various types, for example, can be composed of a direct current system, a solar battery, a storage battery, or can be composed of a rectifier circuit or an AC / DC converter connected to the alternating current system. Also good.
  • the power supply 100 may be configured by a DC / DC converter that converts DC power output from the DC system into predetermined power.
  • the power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts the DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. As shown in FIG. 12, the power conversion device 200 converts a DC power into an AC power and outputs the main conversion circuit 201, and a control circuit 203 outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. And.
  • the load 300 is a three-phase electric motor that is driven by AC power supplied from the power conversion device 200.
  • the load 300 is not limited to a specific application, and is an electric motor mounted on various electric devices.
  • the load 300 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.
  • the main conversion circuit 201 includes a switching element and a free wheel diode (not shown). When the switching element switches, the main conversion circuit 201 converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300.
  • the main conversion circuit 201 is a two-level three-phase full bridge circuit, and includes six switching elements and respective switching elements. It can be composed of six anti-parallel diodes.
  • the semiconductor device according to any of Embodiments 1 to 4 described above is applied to at least one of the switching elements and the free-wheeling diodes of main conversion circuit 201.
  • the six switching elements are connected in series for each of the two switching elements to constitute upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit.
  • the output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.
  • the main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element.
  • the drive circuit may be built in the semiconductor module 202, or a drive circuit may be provided separately from the semiconductor module 202. The structure provided may be sufficient.
  • the drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201. Specifically, in accordance with a control signal from the control circuit 203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element.
  • the drive signal When the switching element is maintained in the ON state, the drive signal is a voltage signal (ON signal) that is equal to or higher than the threshold voltage of the switching element, and when the switching element is maintained in the OFF state, the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element.
  • Signal (off signal) When the switching element is maintained in the ON state, the drive signal is a voltage signal (ON signal) that is equal to or higher than the threshold voltage of the switching element, and when the switching element is maintained in the OFF state, the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element.
  • Signal (off signal) When the switching element is maintained in the ON state, the drive signal is a voltage signal (ON signal) that is equal to or higher than the threshold voltage of the switching element, and when the switching element is maintained in the OFF state, the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element.
  • Signal (off signal) When the switching element is maintained in the ON state,
  • the control circuit 203 controls the switching element of the main conversion circuit 201 so that desired power is supplied to the load 300. Specifically, based on the power to be supplied to the load 300, the time (ON time) during which each switching element of the main converter circuit 201 is to be turned on is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the ON time of the switching element in accordance with the voltage to be output. Then, a control command (control signal) is supplied to the drive circuit included in the main conversion circuit 201 so that an ON signal is output to the switching element that should be turned on at each time point and an OFF signal is output to the switching element that should be turned off. Is output. In accordance with this control signal, the drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.
  • the semiconductor module according to the first to fourth embodiments is applied as the switching element and the free wheel diode of the main conversion circuit 201, the insulation performance is maintained and the reliability is improved. In addition, it is possible to realize a power converter that can be reduced in size.
  • the present invention is not limited to this, and can be applied to various power conversion devices.
  • a two-level power converter is used.
  • a three-level or multi-level power converter may be used.
  • the present invention is applied to a single-phase inverter. You may apply.
  • the present invention can be applied to a DC / DC converter or an AC / DC converter.
  • the power conversion device to which the present invention is applied is not limited to the case where the load described above is an electric motor.
  • the power source of an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system It can also be used as a device, and can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.
  • Example 2 In order to confirm the effect of the present invention, a sample of an example of the present invention and a sample of a comparative example were prepared, and a partial discharge start voltage was measured for each sample.
  • Sample No. Seven types of semiconductor device samples 1 to 7 were prepared. Sample No. Nos. 1 to 5 correspond to the examples of the present invention. 6 and 7 correspond to comparative examples.
  • Each sample basically has the same configuration as that of the semiconductor device according to the first embodiment of the present invention, and the planar shape of the semiconductor device, the material and thickness of the lead frame, the type and number of power elements, and the like are common.
  • the insulating sheet 3b with metal foil a copper foil having a thickness of 0.1 mm as the metal foil 4 and a high thermal conductive filler made of silica in an epoxy resin are mixed, and the insulating sheet 3 having a thickness of 0.2 mm. Is used.
  • the planar shape of the insulating sheet 3b with metal foil is a quadrangular shape having a length of 60 mm and a width of 45 mm.
  • the lead frame was made of copper having a thickness of 0.6 mm.
  • a MOSFET is used as the power element 5.
  • Epoxy resin was used as the material of the resin casing 7.
  • the planar shape of the resin casing 7 is a quadrangular shape having a length of 70 mm and a width of 55 mm.
  • the sample 1 has basically the same configuration as the semiconductor device according to the first embodiment described above, the distance L1 is 1.0 mm, the distance L2 is 3.0 mm, and the height G of the step portion 8 is 0.3 mm. It was said.
  • Sample No. 2 has basically the same configuration as the semiconductor device according to the second embodiment described above, the distance L1 is 1.0 mm, the distance L2 is 3.0 mm, and the height G of the bent portion 9 is 0.1 mm. It was said.
  • Sample No. 3 has basically the same configuration as the semiconductor device according to Embodiment 3 described above, the distance L1 is 1.0 mm, the distance L2 is 3.0 mm, and the height G of the stepped portion 8 is 0.3 mm. The diameter of the through hole 11 formed in the center was 6 mm.
  • Sample No. 4 has basically the same configuration as the semiconductor device according to Embodiment 4 described above, the distance L1 is 1.0 mm, the distance L2 is 3.0 mm, and the height G of the stepped portion 8 is 0.3 mm.
  • the diameter of the through hole 11 formed in the center is 6 mm, the distance L5 in FIG. 11 is 3 mm, the distance L6 is 3 mm, and the distance L7 is 3 mm.
  • Sample No. 5 has basically the same configuration as the semiconductor device according to the first embodiment described above, the distance L1 is 0.2 mm, the distance L2 is 0.2 mm, and the height G of the step portion 8 is 0.3 mm. It was said.
  • Sample No. 6 has basically the same configuration as the semiconductor device according to the first embodiment described above, the distance L1 is 0.19 mm, the distance L2 is 3.0 mm, and the height G of the step portion 8 is 0.3 mm. It was said.
  • Sample No. 7 has basically the same configuration as the semiconductor device according to the first embodiment described above, the distance L1 is 1.0 mm, the distance L2 is 0.19 mm, and the height G of the step portion 8 is 0.3 mm. It was said.
  • ⁇ Test method> Each sample was subjected to an insulation test. Specifically, a voltage of 2 kV assuming a rated operating voltage was applied between the terminals, and whether or not partial discharge occurred at the end of the metal foil 4 was confirmed.
  • sample No. which is a comparative example.
  • sample No. which is a comparative example.
  • 6 and 7 the occurrence of partial discharge was observed under the above conditions.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

Provided is a semiconductor device which can be miniaturized while maintaining insulating performance. This semiconductor device (10) is provided with: a metal foil-attached insulating sheet (3b) as a laminated sheet; a lead frame (1), a power element as a semiconductor element; and a resin case (7) as an encapsulation case. The resin case (7) is made of a resin and seals the power element, a portion of the lead frame (1), and a portion of the metal foil-attached insulating sheet (3b). The resin case (7) has an opening part (17) which, in the metal foil-attached insulating sheet (3b), exposes a portion of a rear surface on the reverse side of the surface facing the lead frame (1). The resin case (7) includes a rib part (2) which surrounds the opening part and protrudes in a direction perpendicular to a bottom surface part (20) as the rear surface of the metal foil-attached insulating sheet (3b). In the metal foil-attached insulating sheet (3b), an end section (14) of a metal foil (4) located at a portion of an outer peripheral section of the bottom surface part (20), exposed from the opening part (17) is embedded in the resin case (7).

Description

半導体装置および電力変換装置Semiconductor device and power conversion device
　この発明は、半導体装置に関するものであり、より特定的には封止樹脂を備えるトランスファーモールド型半導体装置に関する。 The present invention relates to a semiconductor device, and more particularly to a transfer mold type semiconductor device provided with a sealing resin.
　従来、封止樹脂をトランスファーモールド法により形成したトランスファーモールド型半導体装置が知られている。トランスファーモールド型半導体装置は、高い生産性と信頼性を有することから、その開発が盛んに行われている。トランスファーモールド型半導体装置では、絶縁と放熱の役割を、放熱用の金属層と絶縁層とが積層された高熱伝導絶縁シート（以下、絶縁シートとも呼ぶ）が担うものがある（たとえば、特開２０１４－７２３０５号公報（以下、特許文献１と呼ぶ）および国際公開番号ＷＯ２０１２／０５３２０５号（以下、特許文献２と呼ぶ）参照）。 Conventionally, a transfer mold type semiconductor device in which a sealing resin is formed by a transfer mold method is known. Since transfer mold type semiconductor devices have high productivity and reliability, they have been actively developed. Some transfer mold type semiconductor devices play a role of insulation and heat dissipation by a high heat conductive insulating sheet (hereinafter also referred to as an insulating sheet) in which a metal layer for heat dissipation and an insulating layer are laminated (for example, Japanese Patent Application Laid-Open No. 2014-2012). -72305 gazette (hereinafter referred to as Patent Document 1) and International Publication No. WO2012 / 053205 (hereinafter referred to as Patent Document 2).
特開２０１４－７２３０５号公報JP 2014-72305 A ＷＯ２０１２／０５３２０５WO2012 / 053205
　上述したトランスファーモールド型半導体装置のように封止樹脂を備えた従来の半導体装置においては、絶縁シートの端部における部分放電を抑制して絶縁性能を確保できるよう、半導体素子を搭載したリードフレームと高熱伝導絶縁シートとの沿面距離を保つために、リードフレームが封止樹脂の内部で曲げられた構造を有している。曲げ加工が施されたリードフレームは、フレームパターン同士の間隔が広げられる形になり、リードフレーム全体の大型化、ひいては半導体装置や当該半導体装置を用いた半導体モジュール全体の大型化を招く可能性がある。また、半導体装置の３辺以上から外部接続用の端子を出す構造とした場合、曲げ加工によりリードフレーム同士の干渉が発生する可能性があり、リードフレームのパターンに制限が発生する可能性がある。 In a conventional semiconductor device provided with a sealing resin like the transfer mold type semiconductor device described above, a lead frame on which a semiconductor element is mounted so as to ensure insulation performance by suppressing partial discharge at the end of the insulating sheet; In order to maintain a creepage distance from the high thermal conductive insulating sheet, the lead frame has a structure bent inside the sealing resin. The bent lead frame has a shape in which the space between the frame patterns is widened, which may lead to an increase in the size of the entire lead frame, and in turn, an increase in the size of the semiconductor device and the entire semiconductor module using the semiconductor device. is there. In addition, when a structure for projecting terminals for external connection from three or more sides of a semiconductor device is used, there is a possibility that interference between lead frames may occur due to bending, and there is a possibility that the lead frame pattern is limited. .
　本発明においては、絶縁シートの端面における部分放電の発生を抑制するとともに絶縁シートとリードフレームとの間の沿面距離を大きくして絶縁性能を維持しつつ、小型化が可能な半導体装置を提供することを目的とする。 The present invention provides a semiconductor device that can be reduced in size while suppressing the occurrence of partial discharge at the end face of the insulating sheet and increasing the creepage distance between the insulating sheet and the lead frame to maintain the insulating performance. For the purpose.
　本開示に従った半導体装置は、積層シートと、リードフレームと、半導体素子と、封止筐体とを備える。積層シートは導体層と絶縁層とを積層したものである。リードフレームは、積層シート上に配置される。半導体素子は、リードフレーム上に配置される。封止筐体は、樹脂製であって、半導体素子、リードフレームの一部、積層シートの一部を封止するものである。封止筐体には、積層シートにおいてリードフレームと対向する表面と反対側の裏面の一部を露出する開口部が形成される。封止筐体は、開口部を囲み積層シートの裏面に対して垂直な方向に突出するリブ部を含む。積層シートにおいて開口部から露出する一部の外周部に位置する導体層の端部は封止筐体中に埋設されている。 The semiconductor device according to the present disclosure includes a laminated sheet, a lead frame, a semiconductor element, and a sealing housing. The laminated sheet is obtained by laminating a conductor layer and an insulating layer. The lead frame is disposed on the laminated sheet. The semiconductor element is disposed on the lead frame. The sealing housing is made of resin and seals the semiconductor element, a part of the lead frame, and a part of the laminated sheet. An opening that exposes a part of the back surface opposite to the front surface facing the lead frame in the laminated sheet is formed in the sealing housing. The sealing housing includes a rib portion that surrounds the opening and protrudes in a direction perpendicular to the back surface of the laminated sheet. In the laminated sheet, the end portion of the conductor layer located at a part of the outer peripheral portion exposed from the opening is embedded in the sealed casing.
　本開示に従った電力変換装置は、上記半導体装置を有し、入力される電力を変換して出力する主変換回路と、主変換回路を制御する制御信号を主変換回路に出力する制御回路とを備える。 A power conversion device according to the present disclosure includes the above-described semiconductor device, a main conversion circuit that converts and outputs input power, and a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit; Is provided.
　上記によれば、封止筐体の外側に位置するリードフレームと開口部から露出する積層シートとの間の沿面距離を確保するリブ部が形成されているので、十分な沿面距離を維持しつつ半導体装置の平面視でのサイズを小さくできる。さらに、積層シートの導体層の端部が封止筐体中に埋設されている事により、導体層の端部における部分放電開始電圧が上昇する。この結果、半導体装置の絶縁性能が向上する。 According to the above, since the rib portion that secures the creepage distance between the lead frame located outside the sealing housing and the laminated sheet exposed from the opening is formed, a sufficient creepage distance is maintained. The size of the semiconductor device in plan view can be reduced. Furthermore, since the end portion of the conductor layer of the laminated sheet is embedded in the sealed casing, the partial discharge start voltage at the end portion of the conductor layer is increased. As a result, the insulation performance of the semiconductor device is improved.
本発明の実施の形態１に係る半導体装置の断面模式図である。1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention. 図１に示した半導体装置の部分断面模式図である。FIG. 2 is a partial cross-sectional schematic diagram of the semiconductor device shown in FIG. 1. 図１に示した半導体装置の表面側から見た斜視模式図である。FIG. 2 is a schematic perspective view seen from the surface side of the semiconductor device shown in FIG. 1. 図１に示した半導体装置の裏面側から見た斜視模式図である。FIG. 2 is a schematic perspective view seen from the back side of the semiconductor device shown in FIG. 1. 図１に示した半導体装置におけるリードフレームと積層シートとの関係を示す模式図である。FIG. 2 is a schematic diagram showing a relationship between a lead frame and a laminated sheet in the semiconductor device shown in FIG. 1. 図１に示した半導体装置の製造方法を示すフローチャートである。2 is a flowchart showing a method for manufacturing the semiconductor device shown in FIG. 本発明の実施の形態２に係る半導体装置の断面模式図である。It is a cross-sectional schematic diagram of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る半導体装置の斜視模式図である。It is a perspective schematic diagram of the semiconductor device which concerns on Embodiment 3 of this invention. 図８に示した半導体層の断面模式図である。It is a cross-sectional schematic diagram of the semiconductor layer shown in FIG. 本発明の実施の形態４に係る半導体装置の断面模式図である。It is a cross-sectional schematic diagram of the semiconductor device which concerns on Embodiment 4 of this invention. 図１０に示した半導体装置の部分断面模式図である。FIG. 11 is a partial schematic cross-sectional view of the semiconductor device shown in FIG. 10. 本発明の実施の形態５に係る電力変換システムの構成を示すブロック図である。It is a block diagram which shows the structure of the power conversion system which concerns on Embodiment 5 of this invention.
　以下、図面を参照しながら本発明の実施の形態について説明する。以下の図面において同一または相当する部分には同一の参照番号を付し、その説明は繰り返さない。また、図１を含め、以下の図面では各構成部材の大きさの関係が実際のものとは異なる場合がある。さらに、明細書全文に表わされている構成要素の形態は、あくまでも例示であって、これらの記載に限定されるものではない。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. Moreover, in the following drawings including FIG. 1, the relationship of the size of each component may be different from the actual one. Furthermore, the forms of the constituent elements shown in the entire specification are merely examples, and are not limited to these descriptions.
　実施の形態１．
　＜半導体装置の構成＞
　図１は、本発明の実施の形態１に係る半導体装置の断面図である。図２は図１の半導体装置の部分断面模式図であり、図３は図１の半導体装置を表面側から見た斜視模式図である。図４は図１の半導体装置を積層シートとしての金属箔付き絶縁シート３ｂ側（裏面側）から見た斜視模式図である。図５は、図１に示した半導体装置におけるリードフレームと積層シートとの関係を示す模式図である。半導体装置１０は、リードフレーム１、金属箔付き絶縁シート３ｂ、半導体素子としてのパワー素子５、導電線としてのワイヤ６、封止筐体としての樹脂筐体７を主に備える。 Embodiment 1 FIG.
<Configuration of semiconductor device>
FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention. 2 is a schematic partial sectional view of the semiconductor device of FIG. 1, and FIG. 3 is a schematic perspective view of the semiconductor device of FIG. FIG. 4 is a schematic perspective view of the semiconductor device of FIG. 1 viewed from the insulating sheet 3b side (back side) with a metal foil as a laminated sheet. FIG. 5 is a schematic diagram showing the relationship between the lead frame and the laminated sheet in the semiconductor device shown in FIG. The semiconductor device 10 mainly includes a lead frame 1, an insulating sheet 3b with metal foil, a power element 5 as a semiconductor element, a wire 6 as a conductive wire, and a resin casing 7 as a sealing casing.
　リードフレーム１は、パワー素子５を実装する配線部と、樹脂筐体７から露出した部分の外部端子部１２とを含む。配線部にはパワー素子５が搭載され、パワー素子５の裏面電極が半田などで当該配線部に接続される。また、複数のパワー素子５間、およびパワー素子５の表面電極と配線部との間はワイヤ６により接続される。リードフレーム１は、パワー素子５の電極に電気的に接続される。 The lead frame 1 includes a wiring part for mounting the power element 5 and an external terminal part 12 exposed from the resin casing 7. The power element 5 is mounted on the wiring part, and the back electrode of the power element 5 is connected to the wiring part with solder or the like. Further, the wires 6 are connected between the power elements 5 and between the surface electrode of the power element 5 and the wiring portion. The lead frame 1 is electrically connected to the electrode of the power element 5.
　金属箔付き絶縁シート３ｂは、金属箔４上に絶縁シート３が積層された積層シートである。絶縁シート３上にリードフレーム１が配置されている。リードフレーム１上にパワー素子５が配置されている。樹脂筐体７は、リードフレーム１の一部、パワー素子５、ワイヤ６、金属箔付き絶縁シート３ｂを封止するように形成されている。なお、金属箔付き絶縁シート３ｂの金属箔４の表面である底面部２０の一部は樹脂筐体７から露出している。金属箔付き絶縁シート３ｂの外周端部は樹脂筐体７の内部に埋設されている。また、金属箔付き絶縁シート３ｂの外周部下には、樹脂筐体７のリブ部２が配置されている。 The insulating sheet 3b with metal foil is a laminated sheet in which the insulating sheet 3 is laminated on the metal foil 4. A lead frame 1 is disposed on the insulating sheet 3. A power element 5 is disposed on the lead frame 1. The resin casing 7 is formed so as to seal a part of the lead frame 1, the power element 5, the wire 6, and the insulating sheet 3b with metal foil. In addition, a part of the bottom face part 20 which is the surface of the metal foil 4 of the insulating sheet 3b with metal foil is exposed from the resin casing 7. The outer peripheral edge of the insulating sheet 3b with metal foil is embedded in the resin casing 7. Moreover, the rib part 2 of the resin housing | casing 7 is arrange | positioned under the outer peripheral part of the insulating sheet 3b with metal foil.
　外部端子部１２は、外部の機器等に接続する複数の端子を有する。外部端子部１２の各端子は、樹脂筐体７の外部においてＬ形状に曲げられて、樹脂筐体７より露出されている。図３では、半導体装置１０の３方向から外部端子部１２が樹脂筐体７より突出している例を示した。なお、外部端子部１２は、樹脂筐体７から１方向、あるいは互いに異なる２方向に突出するように形成されていてもよい。リードフレーム１のフレームパターンの設計が困難になる構成の一例である外部端子部１２が２方向に突出する構成において、図１および図２に示すようなリードフレーム１の段差部８を形成する半抜き加工のメリットが特に顕著になる。ただし、リードフレーム１の曲げ加工により半抜き加工と同等の段差部８を形成しても良い。この場合、曲げ加工によるリードフレーム１のパターン間の距離に影響が出ない、あるいはパターンの干渉が発生しないようにリードフレーム１の曲げ加工を実施する。 The external terminal unit 12 has a plurality of terminals connected to an external device or the like. Each terminal of the external terminal portion 12 is bent into an L shape outside the resin casing 7 and exposed from the resin casing 7. FIG. 3 shows an example in which the external terminal portion 12 protrudes from the resin casing 7 from three directions of the semiconductor device 10. Note that the external terminal portion 12 may be formed so as to protrude from the resin casing 7 in one direction or in two different directions. In the configuration in which the external terminal portion 12, which is an example of a configuration that makes it difficult to design the frame pattern of the lead frame 1, protrudes in two directions, the half that forms the stepped portion 8 of the lead frame 1 as shown in FIGS. 1 and 2. The merit of the punching process becomes particularly remarkable. However, the step 8 equivalent to the half blanking process may be formed by bending the lead frame 1. In this case, the lead frame 1 is bent so as not to affect the distance between the patterns of the lead frame 1 due to the bending process or to prevent pattern interference.
　金属箔付き絶縁シート３ｂは、放熱性の高い絶縁層である絶縁シート３と、金属箔４とを含む。絶縁シート３はリードフレーム１と金属箔４とを絶縁する。パワー素子５が発生させた熱は絶縁シート３を介して金属箔４に放熱される。絶縁シート３の材料としては、エポキシ樹脂などの熱硬化性樹脂が用いられる。また、絶縁シート３では、その内部にシリカやアルミナ、窒化ホウ素などの高熱伝導性フィラーが混入されている。 The insulating sheet 3b with metal foil includes the insulating sheet 3 that is an insulating layer having high heat dissipation and the metal foil 4. The insulating sheet 3 insulates the lead frame 1 from the metal foil 4. The heat generated by the power element 5 is radiated to the metal foil 4 through the insulating sheet 3. As a material of the insulating sheet 3, a thermosetting resin such as an epoxy resin is used. Further, in the insulating sheet 3, a high thermal conductive filler such as silica, alumina, boron nitride or the like is mixed therein.
　金属箔４としては、銅板、アルミ板、銅箔など高熱伝導部材が用いられる。金属箔４の厚みは薄くても良いが、自己支持性があるように０．０３ｍｍ以上０．４０ｍｍ以下であることが望ましい。金属箔４の厚みの下限は０．０５ｍｍでもよく、０．１０ｍｍでもよく、０．１５ｍｍでもよく、０．２０ｍｍでもよい。金属箔４の厚みの上限は、０．３５ｍｍでもよく、０．３０ｍｍでもよく、０．２５ｍｍでもよい。 As the metal foil 4, a high thermal conductive member such as a copper plate, an aluminum plate, or a copper foil is used. Although the thickness of the metal foil 4 may be thin, it is preferably 0.03 mm or more and 0.40 mm or less so as to have a self-supporting property. The lower limit of the thickness of the metal foil 4 may be 0.05 mm, 0.10 mm, 0.15 mm, or 0.20 mm. The upper limit of the thickness of the metal foil 4 may be 0.35 mm, 0.30 mm, or 0.25 mm.
　リードフレーム１は、銅板やアルミ板をプレス成形することによりパターン形成されることで形成される。リードフレーム１では、上記パターンの形成後、半抜き加工によりリードフレームの厚み（たとえば０．６ｍｍ）の半分の高さ（たとえば０．３ｍｍ）の段差部８が形成されている。半抜き加工では、パンチプレス等の工程で、リードフレーム１の厚み方向に対して途中で加工工具の移動を止めることで、リードフレーム１に段差部８を形成することができる。リードフレーム１の厚みは、プレス成型によって加工することができれば任意の厚みとすることができ、たとえば０．６ｍｍより厚くても良い。リードフレーム１の段差部８の高さは、たとえば０．１ｍｍ以上としてもよい。この場合、樹脂筐体７の一部が、リードフレーム１と絶縁シート３との間に位置し段差部８に連なる隙間にボイドの発生なく充填される。また、リードフレーム１の厚みの半分よりも大きく半抜き加工を行うと、リードフレーム１の切断、あるいはリードフレーム１の強度の不足による不良などが発生する恐れがある。そのため、段差部８の高さは０．１ｍｍ以上リードフレーム１の厚みの半分以下とすることが望ましい。 The lead frame 1 is formed by forming a pattern by press molding a copper plate or an aluminum plate. In the lead frame 1, after the pattern is formed, a stepped portion 8 having a height (for example, 0.3 mm) that is half the thickness of the lead frame (for example, 0.6 mm) is formed by half blanking. In the half punching process, the stepped portion 8 can be formed in the lead frame 1 by stopping the movement of the processing tool in the middle of the thickness direction of the lead frame 1 in a process such as a punch press. The thickness of the lead frame 1 can be set to any thickness as long as it can be processed by press molding, and may be greater than 0.6 mm, for example. The height of the stepped portion 8 of the lead frame 1 may be, for example, 0.1 mm or more. In this case, a part of the resin casing 7 is filled between the lead frame 1 and the insulating sheet 3 in a gap that is located between the lead frame 1 and the insulating sheet 3 and that is continuous with the stepped portion 8 without generation of voids. Further, if the half-cutting process is performed to be larger than half the thickness of the lead frame 1, there is a possibility that the lead frame 1 is cut or defective due to insufficient strength of the lead frame 1. Therefore, the height of the stepped portion 8 is desirably 0.1 mm or more and half or less of the thickness of the lead frame 1.
　なお、図３および図４では、リードフレーム１の外部端子部１２が、樹脂筐体７の上面と交差する方向に伸びるように屈曲されている構成が示されているが、図１、図２および図５では当該リードフレーム１の外部端子部１２の屈曲形状の図示は省略されている。 3 and 4 show a configuration in which the external terminal portion 12 of the lead frame 1 is bent so as to extend in a direction intersecting the upper surface of the resin casing 7, FIG. 1 and FIG. In FIG. 5 and FIG. 5, the bent shape of the external terminal portion 12 of the lead frame 1 is not shown.
　パワー素子５は、たとえば入力交流電力を直流電力に変換するコンバータ部に用いるダイオード、あるいは直流電力を交流電力に変換するインバータ部に用いるバイポーラトランジスタ、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）、ＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）、ＧＴＯ（Ｇａｔｅ　Ｔｕｒｎ－Ｏｆｆ　ｔｈｙｒｉｓｔｏｒ）等であってもよい。 The power element 5 is, for example, a diode used in a converter unit that converts input AC power into DC power, or a bipolar transistor, IGBT (Insulated Gate Bipolar Transistor), MOSFET (Metal Oxide Semiconductor) that is used in an inverter unit that converts DC power into AC power. It may be a Field Effect Transistor (GFT), a Gate Turn-Off thyristor (GTO), or the like.
　樹脂筐体７は、エポキシなどの熱硬化性樹脂により形成されてもよい。この場合、樹脂筐体７は、トランスファー成型、射出成形、コンプレッション成型などの手法を用い、高温下で樹脂成形される。樹脂筐体７は、樹脂筐体７の内部に配置した部材間の絶縁性を確保する。樹脂筐体７は、金属箔付き絶縁シート３ｂの一面（露出面である底面部２０）およびリードフレーム１の一部（外部端子部１２）が露出するようにパワー素子５を封止している。樹脂筐体７は、リブ部２を含む。リブ部２を含む樹脂筐体７では、金属箔付き絶縁シート３ｂの端部が内部に埋設された状態となっている。リブ部２は、底面部２０から当該底面部２０に対して垂直な方向に突出して形成されている。 Resin casing 7 may be formed of a thermosetting resin such as epoxy. In this case, the resin casing 7 is resin-molded at a high temperature using techniques such as transfer molding, injection molding, and compression molding. The resin casing 7 ensures insulation between members disposed inside the resin casing 7. The resin casing 7 seals the power element 5 so that one surface (the bottom surface portion 20 which is an exposed surface) of the insulating sheet 3b with metal foil and a part of the lead frame 1 (the external terminal portion 12) are exposed. . The resin housing 7 includes the rib portion 2. In the resin casing 7 including the rib portion 2, the end portion of the insulating sheet 3b with metal foil is embedded in the inside. The rib portion 2 is formed to protrude from the bottom surface portion 20 in a direction perpendicular to the bottom surface portion 20.
　リブ部２は、金属箔の端部１４が内部に埋まるように形成されている。リブ部２は、金属箔付き絶縁シート３ｂの底面部２０（露出面）を基準面として、リードフレーム１の段差部８の方向とは反対側に突出して設けられる。リブ部２は金属箔付き絶縁シート３ｂの全周囲を埋めるように形成されている。異なる観点から言えば、リブ部２は半導体装置１０の平面視における外周に沿って形成されている。図４に示すように、半導体装置１０の平面視における形状が多角形状（たとえば四角形状）であるときに、当該多角形状の隣接する辺に沿ったリブ部２は繋がった状態である。リブ部２では、隣接する辺に沿った部分の間をつなげることで、当該隣接する辺の境界部である角部でのリブ部２の剛性が向上されている。この結果、半導体装置１０の対極方向（たとえば対向する３つの角方向）における曲げ剛性を向上させている。 The rib part 2 is formed so that the end part 14 of the metal foil is buried inside. The rib portion 2 is provided so as to protrude to the side opposite to the direction of the stepped portion 8 of the lead frame 1 with the bottom surface portion 20 (exposed surface) of the insulating sheet 3b with metal foil as a reference surface. The rib portion 2 is formed so as to fill the entire periphery of the insulating sheet 3b with metal foil. If it says from a different viewpoint, the rib part 2 is formed along the outer periphery in the planar view of the semiconductor device 10. As shown in FIG. 4, when the shape of the semiconductor device 10 in plan view is a polygonal shape (for example, a square shape), the rib portions 2 along adjacent sides of the polygonal shape are connected. In the rib part 2, the rigidity of the rib part 2 in the corner | angular part which is a boundary part of the said adjacent edge is improved by connecting between the parts along an adjacent edge | side. As a result, the bending rigidity of the semiconductor device 10 in the counter electrode direction (for example, three opposing corner directions) is improved.
　また、リブ部２が形成されることにより、リードフレーム１の外部端子部１２と金属箔４との間の沿面距離を確保する事ができる。このため、リブ部２を形成せずに外部端子部１２と金属箔４との間の沿面距離を確保するため半導体装置を大型化する、といった対応が不要になるため、半導体装置の小型化が実現される。なお、樹脂筐体７を成形する際に使用する金型の離型性を向上させるため、リブ部２の角部をＲ形状またはテーパ形状としてもよい。 Further, by forming the rib portion 2, it is possible to ensure a creepage distance between the external terminal portion 12 of the lead frame 1 and the metal foil 4. For this reason, since it is not necessary to increase the size of the semiconductor device in order to ensure the creepage distance between the external terminal portion 12 and the metal foil 4 without forming the rib portion 2, the size of the semiconductor device can be reduced. Realized. In addition, in order to improve the mold release property of the metal mold used when the resin casing 7 is molded, the corners of the rib portion 2 may be R-shaped or tapered.
　図２において、半導体装置の底面部２０におけるリブ形成位置である端部１３は、金属箔４の端部１４よりも内周側に位置する。端部１３と金属箔４の端部１４との間の距離Ｌ１はたとえば１．０ｍｍであり、銅などからなる金属箔４の端部１４とリブ部２の底面１５との垂直方向での距離Ｌ２は３．０ｍｍである。端部１３と金属箔４の端部１４との距離Ｌ１は０．２ｍｍ以上であることが望ましい。また、銅箔端部１４とリブ部２の底面１５との垂直方向での距離Ｌ２は０．２ｍｍ以上であることが望ましい。これらを満たす場合において、金属箔４の端部１４における電界強度緩和の効果があり、当該端部１４での部分放電開始電圧の向上が見込まれる。この結果、半導体装置１０の絶縁性を向上させることができる。 In FIG. 2, the end portion 13, which is a rib forming position in the bottom surface portion 20 of the semiconductor device, is located on the inner peripheral side with respect to the end portion 14 of the metal foil 4. The distance L1 between the end 13 and the end 14 of the metal foil 4 is, for example, 1.0 mm, and the distance between the end 14 of the metal foil 4 made of copper or the like and the bottom surface 15 of the rib 2 in the vertical direction. L2 is 3.0 mm. The distance L1 between the end 13 and the end 14 of the metal foil 4 is desirably 0.2 mm or more. Further, the distance L2 in the vertical direction between the copper foil end portion 14 and the bottom surface 15 of the rib portion 2 is preferably 0.2 mm or more. In the case where these are satisfied, there is an effect of relaxing the electric field strength at the end portion 14 of the metal foil 4, and an improvement in the partial discharge start voltage at the end portion 14 is expected. As a result, the insulating property of the semiconductor device 10 can be improved.
　また、図５に示すように、リードフレーム１の段差部８は金属箔４の端部１４より内側に位置することが好ましい。絶縁シート３と金属箔４の面積は同一であることが望ましいが、異なっていても良い。段差部８と金属箔４の端部１４との間の距離Ｌ３はたとえば０．２ｍｍ以上でもよく、０．３ｍｍ以上でもよく、０．５ｍｍ以上でもよい。また、距離Ｌ３の上限は３．０ｍｍでもよく、２．０ｍｍでもよい。 Further, as shown in FIG. 5, the stepped portion 8 of the lead frame 1 is preferably located inside the end portion 14 of the metal foil 4. The areas of the insulating sheet 3 and the metal foil 4 are preferably the same, but may be different. The distance L3 between the stepped portion 8 and the end 14 of the metal foil 4 may be, for example, 0.2 mm or more, 0.3 mm or more, or 0.5 mm or more. Further, the upper limit of the distance L3 may be 3.0 mm or 2.0 mm.
　また、絶縁シート３と金属箔４とは半導体装置の上面となる樹脂筐体７の上面に対し、垂直方向に変形していてもよい。この場合においても、金属箔４の端部１４とリブ形成位置である端部１３との間の距離Ｌ１および端部１４とリブ部２の底面１５との距離Ｌ２がそれぞれ０．２ｍｍ以上であることが望ましい。このとき、リードフレーム１の段差部８よりも外側の位置で、リードフレーム１側に変形された絶縁シート３とリードフレーム１が接触していても構わない。一方、金属箔４の端部１４がリードフレーム１と接触することは許容されない。絶縁シート３とリードフレーム１とが接触している場合、絶縁シート３は底面部２０から垂直方向に０．３ｍｍだけ変位するように変形している。絶縁シート３の変形を抑制するためには、金属箔４の端部１４の位置が、図２に示したリブ部２の底面１５の中央より内周側に配置される（あるいは、距離Ｌ１が底面１５の長さの２分の１以下となる）ようにすることが効果的である。なお、図１では、リードフレーム１において絶縁シート３と接触する端面より内側に段差部８を設けた例を示した。この段差部８と絶縁シート３と間の隙間に樹脂筐体７が充填されることで、樹脂筐体７の厚さ分だけリードフレーム１と金属箔付き絶縁シート３ｂとの間の絶縁距離を確保している。 Further, the insulating sheet 3 and the metal foil 4 may be deformed in the vertical direction with respect to the upper surface of the resin casing 7 which is the upper surface of the semiconductor device. Even in this case, the distance L1 between the end portion 14 of the metal foil 4 and the end portion 13 where the rib is formed and the distance L2 between the end portion 14 and the bottom surface 15 of the rib portion 2 are each 0.2 mm or more. It is desirable. At this time, the lead frame 1 may be in contact with the insulating sheet 3 deformed to the lead frame 1 side at a position outside the step portion 8 of the lead frame 1. On the other hand, the end 14 of the metal foil 4 is not allowed to contact the lead frame 1. When the insulating sheet 3 and the lead frame 1 are in contact, the insulating sheet 3 is deformed so as to be displaced by 0.3 mm from the bottom surface portion 20 in the vertical direction. In order to suppress the deformation of the insulating sheet 3, the position of the end portion 14 of the metal foil 4 is arranged on the inner peripheral side from the center of the bottom surface 15 of the rib portion 2 shown in FIG. It is effective to make it less than half the length of the bottom surface 15). FIG. 1 shows an example in which the stepped portion 8 is provided inside the end surface of the lead frame 1 that contacts the insulating sheet 3. By filling the gap between the step portion 8 and the insulating sheet 3 with the resin casing 7, the insulation distance between the lead frame 1 and the insulating sheet 3 b with the metal foil is increased by the thickness of the resin casing 7. Secured.
　＜半導体装置の作用効果＞
　本開示に従った半導体装置１０は、積層シートとしての金属箔付き絶縁シート３ｂと、リードフレーム１と、半導体素子としてのパワー素子５と、封止筐体としての樹脂筐体７とを備える。金属箔付き絶縁シート３ｂは導体層としての金属箔４と絶縁層としての絶縁シート３とを積層したものである。リードフレーム１は、金属箔付き絶縁シート３ｂ上に配置される。パワー素子５は、リードフレーム１上に配置される。樹脂筐体７は、樹脂製であって、パワー素子５、リードフレーム１の一部、金属箔付き絶縁シート３ｂの一部を封止するものである。樹脂筐体７には、金属箔付き絶縁シート３ｂにおいてリードフレーム１と対向する表面と反対側の裏面の一部を露出する開口部が形成される。樹脂筐体７は、開口部を囲み金属箔付き絶縁シート３ｂの裏面としての底面部２０に対して垂直な方向に突出するリブ部２を含む。金属箔付き絶縁シート３ｂにおいて開口部１７から露出する底面部２０の一部の外周部に位置する金属箔４の端部１４は樹脂筐体７中に埋設されている。 <Operational effect of semiconductor device>
A semiconductor device 10 according to the present disclosure includes an insulating sheet 3b with a metal foil as a laminated sheet, a lead frame 1, a power element 5 as a semiconductor element, and a resin casing 7 as a sealing casing. The insulating sheet 3b with metal foil is obtained by laminating a metal foil 4 as a conductor layer and an insulating sheet 3 as an insulating layer. The lead frame 1 is disposed on the insulating sheet 3b with metal foil. The power element 5 is disposed on the lead frame 1. The resin casing 7 is made of resin and seals the power element 5, part of the lead frame 1, and part of the insulating sheet 3b with metal foil. The resin casing 7 has an opening that exposes a part of the back surface opposite to the front surface facing the lead frame 1 in the insulating sheet 3b with metal foil. The resin casing 7 includes a rib portion 2 that surrounds the opening and protrudes in a direction perpendicular to the bottom surface portion 20 as the back surface of the insulating sheet 3b with metal foil. In the insulating sheet with metal foil 3 b, the end portion 14 of the metal foil 4 located on the outer periphery of a part of the bottom surface portion 20 exposed from the opening 17 is embedded in the resin casing 7.
　このようにすれば、樹脂筐体７の外側に位置するリードフレーム１と開口部から露出する金属箔付き絶縁シート３ｂとの間の沿面距離を確保するリブ部２が形成されているので、十分な沿面距離を維持しつつ半導体装置１０の平面視でのサイズを小さくできる。さらに、金属箔付き絶縁シート３ｂの金属箔４の端部１４が樹脂筐体７中に埋設されている事により、金属箔４の端部１４における部分放電開始電圧が上昇する。この結果、半導体装置１０の絶縁性能が向上し、その信頼性を向上させることができる。 In this case, the rib portion 2 that secures the creeping distance between the lead frame 1 located outside the resin casing 7 and the insulating sheet 3b with the metal foil exposed from the opening is sufficiently formed. The size of the semiconductor device 10 in plan view can be reduced while maintaining a large creepage distance. Furthermore, since the end portion 14 of the metal foil 4 of the insulating sheet 3b with the metal foil is embedded in the resin casing 7, the partial discharge start voltage at the end portion 14 of the metal foil 4 increases. As a result, the insulation performance of the semiconductor device 10 can be improved and the reliability thereof can be improved.
　上記半導体装置１０において、リブ部２は、開口部の内周面を構成する側壁を含む。側壁における金属箔付き絶縁シート３ｂ側の端部１３は、金属箔４の端部１４より内周側に位置する。側壁における端部１３と、金属箔４の端部１４との間の距離Ｌ１は０．２ｍｍ以上である。この場合、金属箔４の端部１４における部分放電開始電圧を十分高くすることができる。 In the semiconductor device 10, the rib portion 2 includes a side wall that forms the inner peripheral surface of the opening. The end 13 of the side wall on the side of the insulating sheet 3b with metal foil is located on the inner peripheral side from the end 14 of the metal foil 4. The distance L1 between the end 13 on the side wall and the end 14 of the metal foil 4 is 0.2 mm or more. In this case, the partial discharge start voltage at the end 14 of the metal foil 4 can be made sufficiently high.
　上記半導体装置１０では、リブ部２において金属箔付き絶縁シート３ｂの裏面である底面部２０に対して垂直な方向における表面である底面１５と、金属箔４の端部１４との間の距離Ｌ２は０．２ｍｍ以上である。この場合、金属箔４の端部１４における部分放電開始電圧を十分高くすることができる。 In the semiconductor device 10, the distance L <b> 2 between the bottom surface 15 that is the surface in the direction perpendicular to the bottom surface portion 20 that is the back surface of the insulating sheet 3 b with the metal foil in the rib portion 2 and the end portion 14 of the metal foil 4. Is 0.2 mm or more. In this case, the partial discharge start voltage at the end 14 of the metal foil 4 can be made sufficiently high.
　上記半導体装置１０において、樹脂筐体７は、トランスファーモールド法を用いて形成された成形体である。この場合、トランスファーモールド法において樹脂筐体７を形成するための金型の内部で、樹脂筐体７が形成される領域内に金属箔付き絶縁シート３ｂの金属箔４の端部１４を配置したうえで樹脂筐体７となる樹脂を金型内に導入することにより、金属箔４の端部１４が樹脂筐体７の内部に埋設された構造を容易に得ることができる。 In the semiconductor device 10, the resin casing 7 is a molded body formed using a transfer molding method. In this case, the end portion 14 of the metal foil 4 of the insulating sheet 3b with the metal foil is disposed in the region where the resin casing 7 is formed inside the mold for forming the resin casing 7 in the transfer molding method. In addition, by introducing the resin that becomes the resin casing 7 into the mold, a structure in which the end 14 of the metal foil 4 is embedded in the resin casing 7 can be easily obtained.
　上記半導体装置１０において、樹脂筐体７を平面視した場合の形状は、図３における紙面の左右方向に延びる第１辺および当該第１辺と異なる方向に延びる第２辺を外周に含む多角形状である。たとえば、樹脂筐体７の平面視における形状は図３に示すような四角形状でもよい。リードフレーム１は、樹脂筐体７の第１辺から外側に突出する第１外部端子部１２と、樹脂筐体７の第２辺から外側に突出する第２外部端子部１２とを含む。 In the semiconductor device 10, the shape of the resin casing 7 in plan view is a polygonal shape including a first side extending in the left-right direction of the paper surface in FIG. 3 and a second side extending in a direction different from the first side on the outer periphery. It is. For example, the shape of the resin casing 7 in plan view may be a quadrangular shape as shown in FIG. The lead frame 1 includes a first external terminal portion 12 protruding outward from the first side of the resin housing 7 and a second external terminal portion 12 protruding outward from the second side of the resin housing 7.
　本開示に係るリブ部２や金属箔４の端部１４を樹脂筐体７中に埋設した構成は、樹脂筐体７の第１辺および第２辺のいずれの方向においても互いに干渉することなく形成可能であるため、上記のような第１および第２外部端子部１２を含む半導体装置１０においても本開示に係る構成を容易に適用できる。 The configuration in which the rib portion 2 and the end portion 14 of the metal foil 4 according to the present disclosure are embedded in the resin casing 7 does not interfere with each other in either the first side or the second side of the resin casing 7. Since it can be formed, the configuration according to the present disclosure can be easily applied to the semiconductor device 10 including the first and second external terminal portions 12 as described above.
　上記半導体装置１０において、リードフレーム１は、金属箔付き絶縁シート３ｂ上において金属箔付き絶縁シート３ｂから離れる方向に段差部８が形成されている。段差部８の高さＧはリードフレーム１の厚み未満である。この場合、リードフレーム１が段差部８で破断するといった問題の発生を抑制できる。 In the semiconductor device 10, the lead frame 1 has a step 8 formed on the insulating sheet 3b with metal foil in a direction away from the insulating sheet 3b with metal foil. The height G of the stepped portion 8 is less than the thickness of the lead frame 1. In this case, the occurrence of a problem that the lead frame 1 is broken at the stepped portion 8 can be suppressed.
　上記半導体装置１０において、リードフレーム１は、平面視において開口部１７と重なる第１部分と、第１部分に連なり金属箔４の端部１４と重なる第２部分とを含む。リードフレーム１において、第２部分が金属箔４の端部１４と間隔を隔てて配置するように、第１部分には段差部８が形成されている。 In the semiconductor device 10, the lead frame 1 includes a first portion that overlaps the opening 17 in a plan view and a second portion that continues to the first portion and overlaps the end portion 14 of the metal foil 4. In the lead frame 1, a step portion 8 is formed in the first portion so that the second portion is spaced from the end portion 14 of the metal foil 4.
　この場合、リードフレーム１の第２部分が金属箔４の端部１４との間に間隔を隔てて配置されるので、リードフレーム１の第２部分と金属箔４の端部１４との間に樹脂筐体７の一部を配置することができる。この結果、金属箔４の端部１４を確実に樹脂筐体７の内部に埋設された状態とすることができる。 In this case, since the second portion of the lead frame 1 is disposed with a space between the end portion 14 of the metal foil 4, the second portion of the lead frame 1 is disposed between the end portion 14 of the metal foil 4. A part of the resin casing 7 can be arranged. As a result, the end 14 of the metal foil 4 can be reliably embedded in the resin casing 7.
　上記半導体装置１０において、リードフレーム１は、パワー素子５が実装された実装部分と、実装部分より外周側に位置する外周部分とを含む。金属箔付き絶縁シート３ｂの表面に対して垂直な方向において、金属箔付き絶縁シート３ｂから実装部分の表面までの距離Ｌ８は、金属箔付き絶縁シート３ｂから外周部分の表面までの距離Ｌ９より小さい。 In the semiconductor device 10, the lead frame 1 includes a mounting portion on which the power element 5 is mounted and an outer peripheral portion located on the outer peripheral side from the mounting portion. In a direction perpendicular to the surface of the insulating sheet with metal foil 3b, the distance L8 from the insulating sheet with metal foil 3b to the surface of the mounting portion is smaller than the distance L9 from the insulating sheet with metal foil 3b to the surface of the outer peripheral portion. .
　上記半導体装置１０では、金属箔付き絶縁シート３ｂの表面に対して垂直な方向において、実装部分の表面と外周部分の表面との間の距離Ｌ１０はリードフレーム１の厚み未満である。この場合、実装部分の表面と外周部分の表面との間で金属箔付き絶縁シート３ｂからの高さの差を形成するためリードフレームに段差部８や後述する図７に示した屈曲部９を形成したときに、当該段差部８や屈曲部９でのリードフレーム１の変形量を当該リードフレーム１の厚み未満とすることができる。このため、段差部８や屈曲部９においてリードフレーム１が過度に変形することで破損する、といった問題の発生を抑制できる。 In the semiconductor device 10, the distance L10 between the surface of the mounting portion and the surface of the outer peripheral portion is less than the thickness of the lead frame 1 in the direction perpendicular to the surface of the insulating sheet 3b with metal foil. In this case, in order to form a height difference from the insulating sheet 3b with the metal foil between the surface of the mounting portion and the surface of the outer peripheral portion, a step portion 8 or a bent portion 9 shown in FIG. When formed, the deformation amount of the lead frame 1 at the stepped portion 8 and the bent portion 9 can be made less than the thickness of the lead frame 1. For this reason, generation | occurrence | production of the problem that the lead frame 1 is damaged by deform | transforming excessively in the level | step-difference part 8 or the bending part 9 can be suppressed.
　上記半導体装置１０において、金属箔付き絶縁シート３ｂの厚み方向における変形量は０．３ｍｍ以下である。この場合、金属箔付き絶縁シート３ｂを構成する金属箔４とリードフレーム１の外周部とが接触する可能性を低減できる。 In the semiconductor device 10, the amount of deformation in the thickness direction of the insulating sheet 3b with metal foil is 0.3 mm or less. In this case, the possibility that the metal foil 4 constituting the insulating sheet 3b with metal foil and the outer peripheral portion of the lead frame 1 come into contact with each other can be reduced.
　上記半導体装置１０において、パワー素子５は、ワイドバンドギャップ半導体材料により構成されている。この場合、珪素によりパワー素子５を構成する場合に比べて、より高温での動作が可能で耐圧も高い半導体装置１０を得ることができる。 In the semiconductor device 10, the power element 5 is made of a wide band gap semiconductor material. In this case, it is possible to obtain the semiconductor device 10 that can operate at a higher temperature and has a higher withstand voltage than the case where the power element 5 is formed of silicon.
　上記半導体装置１０において、ワイドバンドギャップ半導体材料は、炭化珪素（ＳｉＣ）、窒化ガリウム（ＧａＮ）、ダイヤモンドからなる群から選択される１種を含む。 In the semiconductor device 10, the wide band gap semiconductor material includes one selected from the group consisting of silicon carbide (SiC), gallium nitride (GaN), and diamond.
　以上のように、実施の形態１の半導体装置１０は、半導体素子としてのパワー素子５と、パワー素子５からの熱を放熱する積層シートとしての金属箔付き絶縁シート３ｂと、パワー素子５の電極に電気的に接続されたリードフレーム１と、金属箔付き絶縁シート３ｂの一面及びリードフレーム１の一部が露出するようにパワー素子５を封止する封止筐体としての樹脂筐体７とを備える。半導体装置１０の樹脂筐体７は、パワー素子５及びリードフレーム１の一部が内部に配置されると共に、底面部２０において金属箔４の一面が露出する。また、半導体装置１０の樹脂筐体７は、底面部２０から垂直な方向に突出して設けられたリブ部２を備える。金属箔４の端部１４はリブ部２に包埋されている。実施の形態１の半導体装置１０は、底面部２０から垂直な方向に突出して設けられたリブ部２を備えるとともに、金属箔４の端部１４がリブ部２に包埋された構造を持つため、外部端子部１２と金属箔４との沿面距離を確保しつつ、金属箔４の端部１４における電界強度を抑制することが可能である。この結果、半導体装置１０の小型化と部分放電開始電圧の向上とが可能となる。 As described above, the semiconductor device 10 according to the first embodiment includes the power element 5 as a semiconductor element, the insulating sheet 3b with a metal foil as a laminated sheet that dissipates heat from the power element 5, and the electrode of the power element 5. A lead frame 1 electrically connected to the substrate, and a resin casing 7 as a sealing casing for sealing the power element 5 so that one surface of the insulating sheet 3b with metal foil and a part of the lead frame 1 are exposed. Is provided. In the resin casing 7 of the semiconductor device 10, a part of the power element 5 and the lead frame 1 is disposed inside, and one surface of the metal foil 4 is exposed at the bottom surface portion 20. Further, the resin casing 7 of the semiconductor device 10 includes a rib portion 2 provided so as to protrude from the bottom surface portion 20 in a vertical direction. The end portion 14 of the metal foil 4 is embedded in the rib portion 2. The semiconductor device 10 according to the first embodiment has a structure in which the rib portion 2 is provided so as to protrude in the vertical direction from the bottom surface portion 20 and the end portion 14 of the metal foil 4 is embedded in the rib portion 2. It is possible to suppress the electric field strength at the end portion 14 of the metal foil 4 while securing the creeping distance between the external terminal portion 12 and the metal foil 4. As a result, the semiconductor device 10 can be downsized and the partial discharge start voltage can be improved.
　＜半導体装置の製造方法＞
　図６は、図１に示した半導体装置の製造方法を示すフローチャートである。図６を参照しながら図１に示した半導体装置の製造法を説明する。 <Method for Manufacturing Semiconductor Device>
FIG. 6 is a flowchart showing a manufacturing method of the semiconductor device shown in FIG. A method of manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIG.
　まず、図１に示すように準備工程（Ｓ１０）を実施する。この工程（Ｓ１０）では、金属箔付き絶縁シート３ｂとなるべき、半硬化の絶縁シートが積層された金属箔４、パワー素子５、リードフレーム１など半導体装置１０を構成する部品を準備する。また、パワー素子５はリードフレーム１上の所定の位置に搭載されるとともに、ワイヤ６を用いてパワー素子５の電極とリードフレーム１との間を接続する。 First, a preparation step (S10) is performed as shown in FIG. In this step (S10), components that constitute the semiconductor device 10, such as the metal foil 4, the power element 5, and the lead frame 1 on which the semi-cured insulating sheets are laminated, are prepared. The power element 5 is mounted at a predetermined position on the lead frame 1 and connects the electrode of the power element 5 and the lead frame 1 using a wire 6.
　次に、樹脂筐体形成工程（Ｓ２０）を実施する。この工程（Ｓ２０）では、樹脂筐体７をトランスファーモールド成形するための金型の内部に、半硬化の絶縁シートが積層された金属箔４を配置する。また、半硬化の絶縁シートが積層された金属箔４の上に、リードフレーム１を設置する。なお、リードフレーム１上には予めパワー素子５やワイヤ６などが実装されている。 Next, a resin casing forming step (S20) is performed. In this step (S20), a metal foil 4 in which a semi-cured insulating sheet is laminated is placed inside a mold for transfer molding the resin casing 7. Moreover, the lead frame 1 is installed on the metal foil 4 on which the semi-cured insulating sheets are laminated. A power element 5 and wires 6 are mounted on the lead frame 1 in advance.
　このとき、樹脂筐体７を形成するための金型に対する金属箔４の位置決めは、可動ピンを金属箔４の角部の側面に２本ずつ配置し、これらの可動ピンを金属箔４の４つ角のそれずれに設置して当該可動ピンの位置を調整することにより実施する。可動ピンは、金型におけるリブ部２（図１参照）を形成する位置に設置される。これにより、金型に樹脂筐体７となるべき樹脂が注入されたときの樹脂圧力で、金属箔４の位置ずれを抑制する。金型においてリブ部２を形成するべき領域において、金属箔４の端部１４は金型と接しない状態となるように、金属箔４が配置される。この状態で金型内部に樹脂を注入する。この結果、金属箔４の端部１４はリブ部２内部に埋設された構造となり、絶縁性の向上が見込まれる。 At this time, the positioning of the metal foil 4 with respect to the mold for forming the resin casing 7 is performed by arranging two movable pins on the side surface of the corner of the metal foil 4 and arranging these movable pins on the metal foil 4 4. It is carried out by adjusting the position of the movable pin by installing it at the deviation of one corner. A movable pin is installed in the position which forms the rib part 2 (refer FIG. 1) in a metal mold | die. Thereby, the position shift of the metal foil 4 is suppressed by the resin pressure when the resin to be the resin casing 7 is injected into the mold. In the region where the rib portion 2 is to be formed in the mold, the metal foil 4 is disposed so that the end portion 14 of the metal foil 4 is not in contact with the mold. In this state, resin is injected into the mold. As a result, the end portion 14 of the metal foil 4 has a structure embedded in the rib portion 2, and an improvement in insulation is expected.
　上述した樹脂筐体形成工程（Ｓ２０）では、金型内での樹脂充填圧と樹脂温度とにより、樹脂を硬化して樹脂筐体７を形成すると同時に、リードフレーム１を介して半硬化の絶縁シートを金属箔４に押しつけながら硬化させて絶縁シート３（図１参照）としている。これにより、絶縁シート３の絶縁性と放熱性を向上させている。なお、樹脂筐体７を構成する樹脂の硬化時間と、絶縁シート３となるべき半硬化の絶縁シートの硬化時間とを合わせることが好ましい。樹脂筐体７を構成する樹脂の硬化時間が半硬化の絶縁シートの硬化時間より長くなると、半硬化の絶縁シートが先に硬化して絶縁シート３となり、リードフレーム１と絶縁シート３との密着が劣化する。この結果、半導体層の放熱性や絶縁性が劣化する場合がある。 In the resin casing forming step (S20) described above, the resin is cured by the resin filling pressure and the resin temperature in the mold to form the resin casing 7, and at the same time, semi-cured insulation via the lead frame 1 is performed. The sheet is cured while being pressed against the metal foil 4 to form an insulating sheet 3 (see FIG. 1). Thereby, the insulation and heat dissipation of the insulating sheet 3 are improved. In addition, it is preferable to match | combine the hardening time of the resin which comprises the resin housing | casing 7, and the hardening time of the semi-hardened insulating sheet which should become the insulating sheet 3. FIG. When the curing time of the resin constituting the resin casing 7 is longer than the curing time of the semi-cured insulating sheet, the semi-cured insulating sheet is cured first to become the insulating sheet 3, and the lead frame 1 and the insulating sheet 3 are in close contact with each other. Deteriorates. As a result, the heat dissipation and insulation of the semiconductor layer may deteriorate.
　次に、後処理工程（Ｓ３０）を実施する。この工程（Ｓ３０）では、金型内部から硬化した樹脂筐体７を含む半導体装置を取り出す。そして、リードフレーム１の外部端子部１２に対する加工など、必要な後処理を実施する。このようにして、図１～図４に示した半導体装置を得ることができる。 Next, a post-processing step (S30) is performed. In this step (S30), the semiconductor device including the cured resin casing 7 is taken out from the inside of the mold. Then, necessary post-processing such as processing on the external terminal portion 12 of the lead frame 1 is performed. In this way, the semiconductor device shown in FIGS. 1 to 4 can be obtained.
　実施の形態２．
　＜半導体装置の構成＞
　図７は、本発明の実施の形態２に係る半導体装置の断面模式図である。図７に示した半導体装置は、基本的には図１～図４に示した半導体装置と同様の構成を備えるが、リードフレーム１の形状が図１～図４に示した半導体装置と異なっている。すなわち、図７に示した半導体装置では、リードフレーム１の段差の形状が図１～図４に示した半導体装置と異なる。図７に示した半導体装置では、段差部８（図２参照）ではなくフレーム屈曲部（屈曲部９とも呼ぶ）を形成している。また、リードフレーム１と絶縁シート３のギャップ（段差部８の高さＧとも呼ぶ）を０．３ｍｍとしている。屈曲部９は絶縁シート３の表面に対して傾斜した部分を含む。傾斜した部分の横方向の長さＬ４はたとえば０．３ｍｍである。また、当該傾斜した部分と絶縁シート３との間の角度θはたとえば４５°である。角度θは４５°未満でもよいが、その場合、半導体装置のサイズが大きくなる傾向になる。高さＧは、実施の形態１と同様に０．１ｍｍ以上であれば良い。 Embodiment 2. FIG.
<Configuration of semiconductor device>
FIG. 7 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention. The semiconductor device shown in FIG. 7 basically has the same configuration as that of the semiconductor device shown in FIGS. 1 to 4, but the shape of the lead frame 1 is different from that of the semiconductor device shown in FIGS. Yes. That is, in the semiconductor device shown in FIG. 7, the shape of the step of the lead frame 1 is different from that of the semiconductor device shown in FIGS. In the semiconductor device shown in FIG. 7, a frame bent portion (also referred to as a bent portion 9) is formed instead of the stepped portion 8 (see FIG. 2). The gap between the lead frame 1 and the insulating sheet 3 (also referred to as the height G of the stepped portion 8) is set to 0.3 mm. The bent portion 9 includes a portion inclined with respect to the surface of the insulating sheet 3. The horizontal length L4 of the inclined portion is, for example, 0.3 mm. Further, the angle θ between the inclined portion and the insulating sheet 3 is, for example, 45 °. The angle θ may be less than 45 °, but in that case, the size of the semiconductor device tends to increase. The height G may be 0.1 mm or more as in the first embodiment.
　＜半導体装置の作用効果＞
　上記のような半導体装置によれば、実施の形態１に係る半導体装置と同様の効果を得られるとともに、リードフレーム１において当該リードフレーム１の厚みを実質的に維持しながら屈曲させた屈曲部９を設けているので、リードフレーム１が当該屈曲部９において破断する可能性を低減できる。 <Operational effect of semiconductor device>
According to the semiconductor device as described above, the same effect as that of the semiconductor device according to the first embodiment can be obtained, and the bent portion 9 bent in the lead frame 1 while substantially maintaining the thickness of the lead frame 1. Therefore, the possibility that the lead frame 1 breaks at the bent portion 9 can be reduced.
　実施の形態３．
　＜半導体装置の構成＞
　図８は、本発明の実施の形態３に係る半導体装置の斜視模式図である。図９は、図８に示した半導体層の断面模式図である。なお、図８は図３に対応し、図９は図１に対応する。図８および図９に示した半導体装置は、基本的には図１～図４に示した半導体装置と同様の構成を備えるが、半導体装置１０の中央部に少なくとも１つの貫通孔１１が形成されている点が異なる。図８および図９に示した半導体装置では、図９に示すように樹脂筐体７と金属箔付き絶縁シート３ｂとを貫通する貫通孔１１が形成されている。本実施の形態で使用する金属箔付き絶縁シート３ｂは、打ち抜き等で成型される際に絶縁シート３および金属箔４を貫通する、上記貫通孔１１となるべき穴１６を設けてもよい。 Embodiment 3 FIG.
<Configuration of semiconductor device>
FIG. 8 is a schematic perspective view of a semiconductor device according to the third embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of the semiconductor layer shown in FIG. 8 corresponds to FIG. 3, and FIG. 9 corresponds to FIG. The semiconductor device shown in FIGS. 8 and 9 basically has the same configuration as the semiconductor device shown in FIGS. 1 to 4, but at least one through hole 11 is formed in the central portion of the semiconductor device 10. Is different. In the semiconductor device shown in FIGS. 8 and 9, as shown in FIG. 9, a through hole 11 that penetrates the resin casing 7 and the insulating sheet 3 b with metal foil is formed. The insulating sheet 3b with metal foil used in the present embodiment may be provided with a hole 16 to be the through hole 11 that penetrates the insulating sheet 3 and the metal foil 4 when molded by punching or the like.
　半導体装置１０における貫通孔１１の位置は、任意の位置とすることができる。たとえば、貫通孔１１が１つである場合、図８に示すように平面視における樹脂筐体７の中央に近い位置に貫通孔１１を形成してもよいが、樹脂筐体７の端部周辺に貫通孔１１を形成してもよい。また、複数の貫通孔１１を形成する場合、複数の貫通孔１１のうちの１つを樹脂筐体７の中央に配置し、他の貫通孔１１を樹脂筐体７の外周部に配置してもよい。また、複数の貫通孔１１のすべてを樹脂筐体７の平面視における外周部に配置してもよい。 The position of the through hole 11 in the semiconductor device 10 can be set to an arbitrary position. For example, when there is one through hole 11, the through hole 11 may be formed at a position close to the center of the resin casing 7 in plan view as shown in FIG. You may form the through-hole 11 in. Further, when forming a plurality of through holes 11, one of the plurality of through holes 11 is arranged at the center of the resin casing 7, and the other through holes 11 are arranged on the outer peripheral portion of the resin casing 7. Also good. Further, all of the plurality of through holes 11 may be arranged on the outer peripheral portion of the resin casing 7 in plan view.
　＜半導体装置の作用効果＞
　上記半導体装置１０において、金属箔付き絶縁シート３ｂの表面に対して垂直な方向における樹脂筐体７の上面から、開口部１７において露出する金属箔付き絶縁シート３ｂの裏面である底面部２０の一部にまで到達する貫通孔１１が形成されている。また、上記半導体装置１０において、貫通孔１１の内壁は樹脂筐体７の一部により構成されている。樹脂筐体７は、貫通孔１１の内壁に面する金属箔付き絶縁シート３ｂにおける金属箔４の内周側端部２３を囲む内周側リブ部２７を含む。内周側リブ部２７は、リブ部２に面する外周側側壁を含む。外周側側壁における金属箔付き絶縁シート３ｂ側の端部は、金属箔４の内周側端部２３より外周側に位置する。外周側側壁における端部と、金属箔４の内周側端部２３との間の距離Ｌ７は０．２ｍｍ以上である。 <Operational effect of semiconductor device>
In the semiconductor device 10, the bottom surface 20, which is the back surface of the insulating sheet 3 b with metal foil exposed from the opening 17, from the top surface of the resin casing 7 in a direction perpendicular to the surface of the insulating sheet 3 b with metal foil. A through hole 11 reaching the portion is formed. In the semiconductor device 10, the inner wall of the through hole 11 is constituted by a part of the resin casing 7. The resin casing 7 includes an inner peripheral rib portion 27 that surrounds the inner peripheral end 23 of the metal foil 4 in the insulating sheet 3b with the metal foil facing the inner wall of the through hole 11. The inner peripheral rib portion 27 includes an outer peripheral side wall facing the rib portion 2. The end of the outer peripheral side wall on the side of the insulating sheet with metal foil 3 b is located on the outer peripheral side of the inner peripheral end 23 of the metal foil 4. The distance L7 between the end portion on the outer peripheral side wall and the inner peripheral end portion 23 of the metal foil 4 is 0.2 mm or more.
　上記半導体装置１０において、金属箔付き絶縁シート３ｂにおける金属箔４の内周側端部２３から内周側リブ部２７の表面までの距離、および内周側端部２３から貫通孔１１の内壁の表面までの距離Ｌ５はいずれも０．２ｍｍ以上である。また、異なる観点から言えば、上記半導体装置１０では、内周側リブ部２７において金属箔付き絶縁シート３ｂの裏面である底面部２０に対して垂直な方向における表面である底面１５と、金属箔４の内周側端部２３との間の距離Ｌ６は０．２ｍｍ以上である。 In the semiconductor device 10, the distance from the inner peripheral side end 23 of the metal foil 4 to the surface of the inner peripheral side rib 27 in the insulating sheet 3 b with the metal foil, and the inner wall of the through hole 11 from the inner peripheral side end 23. The distance L5 to the surface is 0.2 mm or more. From a different point of view, in the semiconductor device 10, the bottom surface 15 that is the surface in the direction perpendicular to the bottom surface portion 20 that is the back surface of the insulating sheet 3b with the metal foil in the inner peripheral rib portion 27, and the metal foil The distance L6 between the inner peripheral side end portion 4 of 4 is 0.2 mm or more.
　このようにすれば、実施の形態１に示した半導体装置１０と同様の効果を得られるとともに、金属箔４の内周側端部２３における部分放電開始電圧を高めることができ、半導体装置１０の絶縁性能を向上させることができる。 In this way, the same effect as that of the semiconductor device 10 shown in the first embodiment can be obtained, and the partial discharge start voltage at the inner peripheral end 23 of the metal foil 4 can be increased. Insulation performance can be improved.
　実施の形態４．
　＜半導体装置の構成＞
　図１０は、本発明の実施の形態４に係る半導体装置の断面模式図である。図１１は、図１０に示した半導体装置の部分断面模式図である。なお、図１０は図１に対応し、図１１は図１の貫通孔１１近傍を示した半導体装置の部分断面模式図である。図１０および図１１に示した半導体装置は、基本的には図８および図９に示した半導体装置と同様の構成を備えるが、貫通孔１１に面する金属箔４が樹脂筐体７の一部である内周側リブ部２７に埋設された状態となっている点が図８および図９に示した半導体装置と異なっている。すなわち、図１０および図１１に示した半導体装置では、底面部２０の中央部において貫通孔１１の周囲に、樹脂筐体７の一部が底面部２０から突出した内周側リブ部２７が形成されている。金属箔４の内周側端部２３は貫通孔１１の内周面に露出していない。 Embodiment 4 FIG.
<Configuration of semiconductor device>
FIG. 10 is a schematic cross-sectional view of a semiconductor device according to the fourth embodiment of the present invention. 11 is a partial schematic cross-sectional view of the semiconductor device shown in FIG. 10 corresponds to FIG. 1, and FIG. 11 is a schematic partial sectional view of the semiconductor device showing the vicinity of the through hole 11 in FIG. The semiconductor device shown in FIGS. 10 and 11 basically has the same configuration as the semiconductor device shown in FIGS. 8 and 9, but the metal foil 4 facing the through hole 11 is one of the resin casings 7. The semiconductor device shown in FIGS. 8 and 9 is different from the semiconductor device shown in FIGS. That is, in the semiconductor device shown in FIGS. 10 and 11, the inner peripheral rib portion 27 in which a part of the resin casing 7 protrudes from the bottom surface portion 20 is formed around the through hole 11 in the central portion of the bottom surface portion 20. Has been. The inner peripheral side end 23 of the metal foil 4 is not exposed on the inner peripheral surface of the through hole 11.
　図１１に示すように、金属箔４の内周側端部２３と貫通孔１１の内壁との間の距離Ｌ５はたとえば０．２ｍｍ以上とすることができる。また、内周側リブ部２７において金属箔４の表面と対向する表面である裏面と金属箔４との間の距離Ｌ６もたとえば０．２ｍｍ以上とすることができる。また、内周側リブ部２７の貫通孔１１と反対側に位置する外周側側壁における金属箔４側の端部と金属箔４の内周側端部２３との間の距離Ｌ７もたとえば０．２ｍｍ以上とすることができる。 As shown in FIG. 11, the distance L5 between the inner peripheral end 23 of the metal foil 4 and the inner wall of the through hole 11 can be set to 0.2 mm or more, for example. Moreover, the distance L6 between the back surface which is the surface facing the surface of the metal foil 4 in the inner peripheral rib portion 27 and the metal foil 4 can also be set to 0.2 mm or more, for example. The distance L7 between the end on the metal foil 4 side and the inner peripheral side end 23 of the metal foil 4 on the outer peripheral side wall located on the opposite side of the through hole 11 of the inner peripheral rib portion 27 is also, for example, 0. It can be 2 mm or more.
　上述した半導体装置の内周側リブ部２７は、たとえば下記のように樹脂筐体７を形成するための金型の形状を調整することで形成できる。すなわち、当該金型において半導体装置の底面部２０と接触する表面よりも、貫通孔１１が形成されるべき領域の周囲が深く掘り込んでおく。このようにすれば、当該金型の内部に樹脂筐体７となるべき樹脂を導入することで、金属箔付き絶縁シート３ｂの貫通孔１１側の端部を樹脂筐体７の一部により覆うことができる。 The inner peripheral rib portion 27 of the semiconductor device described above can be formed, for example, by adjusting the shape of a mold for forming the resin casing 7 as described below. That is, the periphery of the region where the through hole 11 is to be formed is dug deeper than the surface of the mold that contacts the bottom surface portion 20 of the semiconductor device. If it does in this way, the edge part by the side of the through-hole 11 of the insulating sheet 3b with metal foil will be covered with a part of resin housing 7 by introduce | transducing resin which should become the resin housing 7 in the inside of the said metal mold | die. be able to.
　＜半導体装置の作用効果＞
　このような構成の半導体装置１０では、実施の形態３に示した半導体装置１０と同様の効果を得られるとともに、貫通孔１１の付近の金属箔付き絶縁シート３ｂの端部が樹脂筐体７で覆われていることで、リードフレーム１が貫通孔１１の近くまで延びている場合においても部分放電開始電圧の低下を抑制する事ができる。 <Operational effect of semiconductor device>
In the semiconductor device 10 having such a configuration, the same effect as that of the semiconductor device 10 shown in the third embodiment can be obtained, and the end portion of the insulating sheet 3b with the metal foil in the vicinity of the through hole 11 is a resin casing 7. By being covered, even when the lead frame 1 extends to the vicinity of the through hole 11, it is possible to suppress a decrease in the partial discharge start voltage.
　実施の形態５．
　本実施の形態は、上述した実施の形態１～実施の形態４に係る半導体装置を電力変換装置に適用したものである。本発明は特定の電力変換装置に限定されるものではないが、以下、実施の形態５として、三相のインバータに本発明を適用した場合について説明する。 Embodiment 5 FIG.
In this embodiment, the semiconductor device according to Embodiments 1 to 4 described above is applied to a power conversion device. Although the present invention is not limited to a specific power converter, hereinafter, a case where the present invention is applied to a three-phase inverter will be described as a fifth embodiment.
　図１２は、本実施の形態にかかる電力変換装置を適用した電力変換システムの構成を示すブロック図である。 FIG. 12 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.
　図１２に示す電力変換システムは、電源１００、電力変換装置２００、負荷３００から構成される。電源１００は、直流電源であり、電力変換装置２００に直流電力を供給する。電源１００は種々のもので構成することが可能であり、例えば、直流系統、太陽電池、蓄電池で構成することができるし、交流系統に接続された整流回路やＡＣ／ＤＣコンバータで構成することとしてもよい。また、電源１００を、直流系統から出力される直流電力を所定の電力に変換するＤＣ／ＤＣコンバータによって構成することとしてもよい。 The power conversion system shown in FIG. 12 includes a power supply 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source and supplies DC power to the power conversion device 200. The power source 100 can be composed of various types, for example, can be composed of a direct current system, a solar battery, a storage battery, or can be composed of a rectifier circuit or an AC / DC converter connected to the alternating current system. Also good. The power supply 100 may be configured by a DC / DC converter that converts DC power output from the DC system into predetermined power.
　電力変換装置２００は、電源１００と負荷３００の間に接続された三相のインバータであり、電源１００から供給された直流電力を交流電力に変換し、負荷３００に交流電力を供給する。電力変換装置２００は、図１２に示すように、直流電力を交流電力に変換して出力する主変換回路２０１と、主変換回路２０１を制御する制御信号を主変換回路２０１に出力する制御回路２０３とを備えている。 The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts the DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. As shown in FIG. 12, the power conversion device 200 converts a DC power into an AC power and outputs the main conversion circuit 201, and a control circuit 203 outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. And.
　負荷３００は、電力変換装置２００から供給された交流電力によって駆動される三相の電動機である。なお、負荷３００は特定の用途に限られるものではなく、各種電気機器に搭載された電動機であり、例えば、ハイブリッド自動車や電気自動車、鉄道車両、エレベーター、もしくは、空調機器向けの電動機として用いられる。 The load 300 is a three-phase electric motor that is driven by AC power supplied from the power conversion device 200. Note that the load 300 is not limited to a specific application, and is an electric motor mounted on various electric devices. For example, the load 300 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.
　以下、電力変換装置２００の詳細を説明する。主変換回路２０１は、スイッチング素子と還流ダイオードを備えており（図示せず）、スイッチング素子がスイッチングすることによって、電源１００から供給される直流電力を交流電力に変換し、負荷３００に供給する。主変換回路２０１の具体的な回路構成は種々のものがあるが、本実施の形態にかかる主変換回路２０１は２レベルの三相フルブリッジ回路であり、６つのスイッチング素子とそれぞれのスイッチング素子に逆並列された６つの還流ダイオードから構成することができる。主変換回路２０１の各スイッチング素子と各還流ダイオードとの少なくともいずれかに、上述した実施の形態１～実施の形態４のいずれかに係る半導体装置を適用する。６つのスイッチング素子は２つのスイッチング素子ごとに直列接続され上下アームを構成し、各上下アームはフルブリッジ回路の各相（Ｕ相、Ｖ相、Ｗ相）を構成する。そして、各上下アームの出力端子、すなわち主変換回路２０１の３つの出力端子は、負荷３００に接続される。 Hereinafter, details of the power conversion apparatus 200 will be described. The main conversion circuit 201 includes a switching element and a free wheel diode (not shown). When the switching element switches, the main conversion circuit 201 converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. Although there are various specific circuit configurations of the main conversion circuit 201, the main conversion circuit 201 according to the present embodiment is a two-level three-phase full bridge circuit, and includes six switching elements and respective switching elements. It can be composed of six anti-parallel diodes. The semiconductor device according to any of Embodiments 1 to 4 described above is applied to at least one of the switching elements and the free-wheeling diodes of main conversion circuit 201. The six switching elements are connected in series for each of the two switching elements to constitute upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.
　また、主変換回路２０１は、各スイッチング素子を駆動する駆動回路（図示なし）を備えているが、駆動回路は半導体モジュール２０２に内蔵されていてもよいし、半導体モジュール２０２とは別に駆動回路を備える構成であってもよい。駆動回路は、主変換回路２０１のスイッチング素子を駆動する駆動信号を生成し、主変換回路２０１のスイッチング素子の制御電極に供給する。具体的には、後述する制御回路２０３からの制御信号に従い、スイッチング素子をオン状態にする駆動信号とスイッチング素子をオフ状態にする駆動信号とを各スイッチング素子の制御電極に出力する。スイッチング素子をオン状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以上の電圧信号（オン信号）であり、スイッチング素子をオフ状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以下の電圧信号（オフ信号）となる。 The main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element. However, the drive circuit may be built in the semiconductor module 202, or a drive circuit may be provided separately from the semiconductor module 202. The structure provided may be sufficient. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201. Specifically, in accordance with a control signal from the control circuit 203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element. When the switching element is maintained in the ON state, the drive signal is a voltage signal (ON signal) that is equal to or higher than the threshold voltage of the switching element, and when the switching element is maintained in the OFF state, the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element. Signal (off signal).
　制御回路２０３は、負荷３００に所望の電力が供給されるよう主変換回路２０１のスイッチング素子を制御する。具体的には、負荷３００に供給すべき電力に基づいて主変換回路２０１の各スイッチング素子がオン状態となるべき時間（オン時間）を算出する。例えば、出力すべき電圧に応じてスイッチング素子のオン時間を変調するＰＷＭ制御によって主変換回路２０１を制御することができる。そして、各時点においてオン状態となるべきスイッチング素子にはオン信号を、オフ状態となるべきスイッチング素子にはオフ信号が出力されるよう、主変換回路２０１が備える駆動回路に制御指令（制御信号）を出力する。駆動回路は、この制御信号に従い、各スイッチング素子の制御電極にオン信号又はオフ信号を駆動信号として出力する。 The control circuit 203 controls the switching element of the main conversion circuit 201 so that desired power is supplied to the load 300. Specifically, based on the power to be supplied to the load 300, the time (ON time) during which each switching element of the main converter circuit 201 is to be turned on is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the ON time of the switching element in accordance with the voltage to be output. Then, a control command (control signal) is supplied to the drive circuit included in the main conversion circuit 201 so that an ON signal is output to the switching element that should be turned on at each time point and an OFF signal is output to the switching element that should be turned off. Is output. In accordance with this control signal, the drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.
　本実施の形態に係る電力変換装置では、主変換回路２０１のスイッチング素子と還流ダイオードとして実施の形態１～実施の形態４に係る半導体モジュールを適用するため、絶縁性能を維持して信頼性を向上させるとともに小型化が可能な電力変換装置を実現することができる。 In the power conversion device according to the present embodiment, since the semiconductor module according to the first to fourth embodiments is applied as the switching element and the free wheel diode of the main conversion circuit 201, the insulation performance is maintained and the reliability is improved. In addition, it is possible to realize a power converter that can be reduced in size.
　本実施の形態では、２レベルの三相インバータに本発明を適用する例を説明したが、本発明は、これに限られるものではなく、種々の電力変換装置に適用することができる。本実施の形態では、２レベルの電力変換装置としたが３レベルやマルチレベルの電力変換装置であっても構わないし、単相負荷に電力を供給する場合には単相のインバータに本発明を適用しても構わない。また、直流負荷等に電力を供給する場合にはＤＣ／ＤＣコンバータやＡＣ／ＤＣコンバータに本発明を適用することも可能である。 In this embodiment, an example in which the present invention is applied to a two-level three-phase inverter has been described. However, the present invention is not limited to this, and can be applied to various power conversion devices. In the present embodiment, a two-level power converter is used. However, a three-level or multi-level power converter may be used. When power is supplied to a single-phase load, the present invention is applied to a single-phase inverter. You may apply. In addition, when power is supplied to a direct current load or the like, the present invention can be applied to a DC / DC converter or an AC / DC converter.
　また、本発明を適用した電力変換装置は、上述した負荷が電動機の場合に限定されるものではなく、例えば、放電加工機やレーザー加工機、又は誘導加熱調理器や非接触器給電システムの電源装置として用いることもでき、さらには太陽光発電システムや蓄電システム等のパワーコンディショナーとして用いることも可能である。 In addition, the power conversion device to which the present invention is applied is not limited to the case where the load described above is an electric motor. For example, the power source of an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system It can also be used as a device, and can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.
　（実施例）
　本発明の効果を確認するため、本発明の実施例の試料および比較例の試料を作成し、それぞれの試料について部分放電開始電圧を測定した。 (Example)
In order to confirm the effect of the present invention, a sample of an example of the present invention and a sample of a comparative example were prepared, and a partial discharge start voltage was measured for each sample.
　＜試料＞
　試料Ｎｏ．１～７という７種類の半導体装置の試料を準備した。なお、試料Ｎｏ．１～５が本発明の実施例に対応し、試料Ｎｏ．６、７が比較例に対応する。 <Sample>
Sample No. Seven types of semiconductor device samples 1 to 7 were prepared. Sample No. Nos. 1 to 5 correspond to the examples of the present invention. 6 and 7 correspond to comparative examples.
　各試料は、基本的には本発明の実施の形態１に係る半導体装置と同様の構成とし、半導体装置の平面形状やリードフレームの材質および厚み、パワー素子の種類や数などは共通とした。具体的には、金属箔付き絶縁シート３ｂとして、金属箔４として厚さ０．１ｍｍの銅箔と、エポキシ樹脂にシリカからなる高熱伝導性フィラーが混入され、厚さ０．２ｍｍの絶縁シート３とが積層された積層体を用いる。金属箔付き絶縁シート３ｂの平面形状は縦が６０ｍｍ、横が４５ｍｍの四角形状である。リードフレームは厚みが０．６ｍｍの銅製のものを用いた。パワー素子５としてはＭＯＳＦＥＴを用いた。樹脂筐体７の材料としてはエポキシ樹脂を用いた。樹脂筐体７の平面形状は縦が７０ｍｍ、横が５５ｍｍの四角形状である。 Each sample basically has the same configuration as that of the semiconductor device according to the first embodiment of the present invention, and the planar shape of the semiconductor device, the material and thickness of the lead frame, the type and number of power elements, and the like are common. Specifically, as the insulating sheet 3b with metal foil, a copper foil having a thickness of 0.1 mm as the metal foil 4 and a high thermal conductive filler made of silica in an epoxy resin are mixed, and the insulating sheet 3 having a thickness of 0.2 mm. Is used. The planar shape of the insulating sheet 3b with metal foil is a quadrangular shape having a length of 60 mm and a width of 45 mm. The lead frame was made of copper having a thickness of 0.6 mm. A MOSFET is used as the power element 5. Epoxy resin was used as the material of the resin casing 7. The planar shape of the resin casing 7 is a quadrangular shape having a length of 70 mm and a width of 55 mm.
　試料Ｎｏ．１の試料は、上述した実施の形態１に係る半導体装置と基本的に同様の構成であり、距離Ｌ１が１．０ｍｍ、距離Ｌ２が３．０ｍｍ、段差部８の高さＧが０．３ｍｍとされた。 Sample No. The sample 1 has basically the same configuration as the semiconductor device according to the first embodiment described above, the distance L1 is 1.0 mm, the distance L2 is 3.0 mm, and the height G of the step portion 8 is 0.3 mm. It was said.
　試料Ｎｏ．２の試料は、上述した実施の形態２に係る半導体装置と基本的に同様の構成であり、距離Ｌ１が１．０ｍｍ、距離Ｌ２が３．０ｍｍ、屈曲部９の高さＧが０．１ｍｍとされた。 Sample No. The sample No. 2 has basically the same configuration as the semiconductor device according to the second embodiment described above, the distance L1 is 1.0 mm, the distance L2 is 3.0 mm, and the height G of the bent portion 9 is 0.1 mm. It was said.
　試料Ｎｏ．３の試料は、上述した実施の形態３に係る半導体装置と基本的に同様の構成であり、距離Ｌ１が１．０ｍｍ、距離Ｌ２が３．０ｍｍ、段差部８の高さＧが０．３ｍｍ、中央に形成された貫通孔１１の直径が６ｍｍとされた。 Sample No. The sample No. 3 has basically the same configuration as the semiconductor device according to Embodiment 3 described above, the distance L1 is 1.0 mm, the distance L2 is 3.0 mm, and the height G of the stepped portion 8 is 0.3 mm. The diameter of the through hole 11 formed in the center was 6 mm.
　試料Ｎｏ．４の試料は、上述した実施の形態４に係る半導体装置と基本的に同様の構成であり、距離Ｌ１が１．０ｍｍ、距離Ｌ２が３．０ｍｍ、段差部８の高さＧが０．３ｍｍ、中央に形成された貫通孔１１の直径が６ｍｍ、図１１の距離Ｌ５が３ｍｍ、距離Ｌ６が３ｍｍ、距離Ｌ７が３ｍｍとされた。 Sample No. The sample No. 4 has basically the same configuration as the semiconductor device according to Embodiment 4 described above, the distance L1 is 1.0 mm, the distance L2 is 3.0 mm, and the height G of the stepped portion 8 is 0.3 mm. The diameter of the through hole 11 formed in the center is 6 mm, the distance L5 in FIG. 11 is 3 mm, the distance L6 is 3 mm, and the distance L7 is 3 mm.
　試料Ｎｏ．５の試料は、上述した実施の形態１に係る半導体装置と基本的に同様の構成であり、距離Ｌ１が０．２ｍｍ、距離Ｌ２が０．２ｍｍ、段差部８の高さＧが０．３ｍｍとされた。 Sample No. The sample No. 5 has basically the same configuration as the semiconductor device according to the first embodiment described above, the distance L1 is 0.2 mm, the distance L2 is 0.2 mm, and the height G of the step portion 8 is 0.3 mm. It was said.
　試料Ｎｏ．６の試料は、上述した実施の形態１に係る半導体装置と基本的に同様の構成であり、距離Ｌ１が０．１９ｍｍ、距離Ｌ２が３．０ｍｍ、段差部８の高さＧが０．３ｍｍとされた。 Sample No. The sample No. 6 has basically the same configuration as the semiconductor device according to the first embodiment described above, the distance L1 is 0.19 mm, the distance L2 is 3.0 mm, and the height G of the step portion 8 is 0.3 mm. It was said.
　試料Ｎｏ．７の試料は、上述した実施の形態１に係る半導体装置と基本的に同様の構成であり、距離Ｌ１が１．０ｍｍ、距離Ｌ２が０．１９ｍｍ、段差部８の高さＧが０．３ｍｍとされた。 Sample No. The sample No. 7 has basically the same configuration as the semiconductor device according to the first embodiment described above, the distance L1 is 1.0 mm, the distance L2 is 0.19 mm, and the height G of the step portion 8 is 0.3 mm. It was said.
　＜試験方法＞
　各試料について、絶縁試験を行なった。具体的には、定格動作電圧を想定した２ｋＶの電圧を端子間に印加し、金属箔４の端部における部分放電の発生の有無を確認した。 <Test method>
Each sample was subjected to an insulation test. Specifically, a voltage of 2 kV assuming a rated operating voltage was applied between the terminals, and whether or not partial discharge occurred at the end of the metal foil 4 was confirmed.
　＜結果＞
　上述した試料Ｎｏ．１～５については、上述した条件下では部分放電の発生は認められなかった。なお、試料Ｎｏ．５については、２ｋＶを超える電圧を印加した場合に、試料Ｎｏ．１～４のいずれよりも早く部分放電が発生した。 <Result>
Sample No. mentioned above. For 1 to 5, the occurrence of partial discharge was not observed under the conditions described above. Sample No. For sample 5, when a voltage exceeding 2 kV was applied, sample No. Partial discharge occurred earlier than any of 1-4.
　一方、比較例である試料Ｎｏ．６、７については、上記条件において部分放電の発生が認められた。 On the other hand, sample No. which is a comparative example. For 6 and 7, the occurrence of partial discharge was observed under the above conditions.
　このように、本発明の実施例に相当する試料は、比較例と比べて高い絶縁性能を有することが示された。 Thus, it was shown that the sample corresponding to the example of the present invention has higher insulation performance than the comparative example.
　以上のように本発明の実施の形態および実施例について説明を行ったが、上述の実施の形態を様々に変形することも可能である。また、本発明の範囲は上述の実施の形態および実施例に限定されるものではない。本発明の範囲は、請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更を含むことが意図される。 Although the embodiments and examples of the present invention have been described above, the above-described embodiments can be variously modified. Further, the scope of the present invention is not limited to the above-described embodiments and examples. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
　１　リードフレーム、２　リブ部、３　絶縁シート、３ｂ　金属箔付き絶縁シート、４　金属箔、５　パワー素子、６　ワイヤ、７　樹脂筐体、８　段差部、９　屈曲部、１０　半導体装置、１１　貫通孔、１２　外部端子部、１３，１４　端部、１５　底面、１６　穴、１７　開口部、２０　底面部、２３　内周側端部、２７　内周側リブ部、１００　電源、２００　電力変換装置、２０１　主変換回路、２０２　半導体モジュール、２０３　制御回路、３００　負荷。 1 lead frame, 2 rib part, 3 insulating sheet, 3b insulating sheet with metal foil, 4 metal foil, 5 power element, 6 wires, 7 resin casing, 8 stepped part, 9 bent part, 10 semiconductor device, 11 through hole , 12 External terminal part, 13, 14 end part, 15 bottom face, 16 holes, 17 opening part, 20 bottom face part, 23 inner peripheral side end part, 27 inner peripheral side rib part, 100 power supply, 200 power converter, 201 main Conversion circuit, 202 semiconductor module, 203 control circuit, 300 load.

Claims (16)

  1. 　導体層と絶縁層とを積層した積層シートと、
    　前記積層シート上に配置されたリードフレームと、
    　前記リードフレーム上に配置された半導体素子と、
    　前記半導体素子、前記リードフレームの一部、前記積層シートの一部を封止する樹脂製の封止筐体とを備え、
    　前記封止筐体には、前記積層シートにおいて前記リードフレームと対向する表面と反対側の裏面の一部を露出する開口部が形成され、
    　前記封止筐体は、前記開口部を囲み前記積層シートの前記裏面に対して垂直な方向に突出するリブ部を含み、
    　前記積層シートにおいて前記開口部から露出する前記一部の外周部に位置する前記導体層の端部は前記封止筐体中に埋設されている、半導体装置。     A laminated sheet in which a conductor layer and an insulating layer are laminated;
    A lead frame disposed on the laminated sheet;
    A semiconductor element disposed on the lead frame;
    The semiconductor element, a part of the lead frame, and a resin sealing housing that seals a part of the laminated sheet,
    The sealing casing is formed with an opening that exposes a part of the back surface opposite to the front surface facing the lead frame in the laminated sheet,
    The sealed casing includes a rib portion that surrounds the opening and protrudes in a direction perpendicular to the back surface of the laminated sheet,
    The semiconductor device, wherein an end portion of the conductor layer located at the outer peripheral portion of the part exposed from the opening in the laminated sheet is embedded in the sealing housing.
  2. 　前記リブ部は、前記開口部の内周面を構成する側壁を含み、
    　前記側壁における前記積層シート側の端部は、前記導体層の前記端部より内周側に位置し、
    　前記側壁における前記端部と、前記導体層の前記端部との間の距離は０．２ｍｍ以上である、請求項１に記載の半導体装置。     The rib portion includes a side wall constituting an inner peripheral surface of the opening,
    The end on the side of the laminated sheet in the side wall is located on the inner peripheral side from the end of the conductor layer,
    The semiconductor device according to claim 1, wherein a distance between the end portion of the side wall and the end portion of the conductor layer is 0.2 mm or more.
  3. 　前記リブ部において前記積層シートの前記裏面に対して垂直な方向における表面である底面と、前記導体層の前記端部との間の距離は０．２ｍｍ以上である、請求項１または請求項２に記載の半導体装置。 The distance between the bottom surface which is the surface in the direction perpendicular | vertical with respect to the said back surface of the said laminated sheet in the said rib part, and the said edge part of the said conductor layer is 0.2 mm or more. A semiconductor device according to 1.
  4. 　前記封止筐体は、トランスファーモールド法を用いて形成された成形体である、請求項１～請求項３のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 3, wherein the sealed casing is a molded body formed using a transfer molding method.
  5. 　前記封止筐体を平面視した場合の形状は、第１辺および前記第１辺と異なる第２辺を外周に含む多角形状であり、
    　前記リードフレームは、前記封止筐体の前記第１辺から外側に突出する第１外部端子部と、前記封止筐体の前記第２辺から外側に突出する第２外部端子部とを含む、請求項１～請求項４のいずれか１項に記載の半導体装置。     The shape when the sealing housing is viewed in plan is a polygonal shape including a first side and a second side different from the first side on the outer periphery,
    The lead frame includes a first external terminal portion that protrudes outward from the first side of the sealing housing, and a second external terminal portion that protrudes outward from the second side of the sealing housing. The semiconductor device according to any one of claims 1 to 4.
  6. 　前記リードフレームは、前記積層シート上において前記積層シートから離れる方向に段差部が形成されており、
    　前記段差部の高さは前記リードフレームの厚み未満である、請求項１～請求項５のいずれか１項に記載の半導体装置。     The lead frame has a step portion formed in a direction away from the laminated sheet on the laminated sheet,
    6. The semiconductor device according to claim 1, wherein a height of the step portion is less than a thickness of the lead frame.
  7. 　前記リードフレームは、平面視において前記開口部と重なる第１部分と、前記第１部分に連なり前記導体層の端部と重なる第２部分とを含み、
    　前記リードフレームにおいて、前記第２部分が前記導体層の前記端部と間隔を隔てて配置するように、前記第１部分には前記段差部が形成されている、請求項６に記載の半導体装置。     The lead frame includes a first portion that overlaps with the opening in a plan view, and a second portion that continues to the first portion and overlaps an end portion of the conductor layer,
    The semiconductor device according to claim 6, wherein in the lead frame, the step portion is formed in the first portion such that the second portion is disposed at a distance from the end portion of the conductor layer. .
  8. 　前記リードフレームは、前記半導体素子が実装された実装部分と、前記実装部分より外周側に位置する外周部分とを含み、
    　前記積層シートの前記表面に対して垂直な方向において、前記積層シートから前記実装部分の表面までの距離は、前記積層シートから前記外周部分の表面までの距離より小さい、請求項１～請求項７のいずれか１項に記載の半導体装置。     The lead frame includes a mounting portion on which the semiconductor element is mounted, and an outer peripheral portion located on the outer peripheral side from the mounting portion,
    The distance from the laminated sheet to the surface of the mounting portion in a direction perpendicular to the surface of the laminated sheet is smaller than the distance from the laminated sheet to the surface of the outer peripheral portion. The semiconductor device according to any one of the above.
  9. 　前記積層シートの前記表面に対して垂直な方向において、前記実装部分の前記表面と前記外周部分の前記表面との間の距離は前記リードフレームの厚み未満である、請求項８に記載の半導体装置。 The semiconductor device according to claim 8, wherein a distance between the surface of the mounting portion and the surface of the outer peripheral portion is less than a thickness of the lead frame in a direction perpendicular to the surface of the laminated sheet. .
  10. 　前記積層シートの前記表面に対して垂直な方向における前記封止筐体の上面から、前記開口部において露出する前記積層シートの前記裏面の一部にまで到達する貫通孔が形成されている、請求項１～請求項９のいずれか１項に記載の半導体装置。 The through-hole which reaches from the upper surface of the said sealing housing | casing in the direction perpendicular | vertical to the said surface of the said lamination sheet to a part of said back surface of the said lamination sheet exposed in the said opening part is formed. The semiconductor device according to any one of claims 1 to 9.
  11. 　前記貫通孔の内壁は前記封止筐体の一部により構成されており、
    　前記封止筐体は、前記貫通孔の前記内壁に面する前記積層シートにおける前記導体層の内周側端部を囲む内周側リブ部を含み、
    　前記内周側リブ部は、前記リブ部に面する外周側側壁を含み、
    　前記外周側側壁における前記積層シート側の端部は、前記導体層の前記内周側端部より外周側に位置し、
    　前記外周側側壁における前記端部と、前記導体層の前記内周側端部との間の距離は０．２ｍｍ以上である、請求項１０に記載の半導体装置。     The inner wall of the through hole is constituted by a part of the sealed casing,
    The sealed casing includes an inner peripheral rib portion that surrounds an inner peripheral end of the conductor layer in the laminated sheet facing the inner wall of the through hole,
    The inner peripheral rib portion includes an outer peripheral side wall facing the rib portion,
    The end on the laminated sheet side of the outer peripheral side wall is located on the outer peripheral side from the inner peripheral end of the conductor layer,
    The semiconductor device according to claim 10, wherein a distance between the end portion on the outer peripheral side wall and the inner peripheral end portion of the conductor layer is 0.2 mm or more.
  12. 　前記内周側リブ部において前記積層シートの前記裏面に対して垂直な方向における表面である底面と、前記導体層の前記内周側端部との間の距離は０．２ｍｍ以上である、請求項１０または請求項１１に記載の半導体装置。 The distance between the bottom surface which is the surface in the direction perpendicular to the back surface of the laminated sheet in the inner peripheral rib portion and the inner peripheral end portion of the conductor layer is 0.2 mm or more. Item 12. The semiconductor device according to Item 10 or Item 11.
  13. 　前記積層シートの厚み方向における変形量が０．３ｍｍ以下である、請求項１～請求項１２のいずれか１項に記載の半導体装置。 13. The semiconductor device according to claim 1, wherein an amount of deformation in the thickness direction of the laminated sheet is 0.3 mm or less.
  14. 　前記半導体素子は、ワイドバンドギャップ半導体材料により構成されている、請求項１～請求項１３のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 13, wherein the semiconductor element is made of a wide band gap semiconductor material.
  15. 　前記ワイドバンドギャップ半導体材料は、炭化珪素、窒化ガリウム、ダイヤモンドからなる群から選択される１種を含む、請求項１４に記載の半導体装置。 The semiconductor device according to claim 14, wherein the wide band gap semiconductor material includes one selected from the group consisting of silicon carbide, gallium nitride, and diamond.
  16. 　請求項１記載の半導体装置を有し、入力される電力を変換して出力する主変換回路と、
    　前記主変換回路を制御する制御信号を前記主変換回路に出力する制御回路と、
    　を備えた電力変換装置。     A main conversion circuit comprising the semiconductor device according to claim 1 for converting and outputting input power;
    A control circuit for outputting a control signal for controlling the main conversion circuit to the main conversion circuit;
    The power converter provided with.
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