WO2018141158A1 - 移位寄存器单元及其驱动方法、栅极驱动装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动装置 Download PDF

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Publication number
WO2018141158A1
WO2018141158A1 PCT/CN2017/102243 CN2017102243W WO2018141158A1 WO 2018141158 A1 WO2018141158 A1 WO 2018141158A1 CN 2017102243 W CN2017102243 W CN 2017102243W WO 2018141158 A1 WO2018141158 A1 WO 2018141158A1
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WIPO (PCT)
Prior art keywords
pull
signal
transistor
node
coupled
Prior art date
Application number
PCT/CN2017/102243
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English (en)
French (fr)
Inventor
王珍
孙建
乔赟
詹小舟
黄飞
张寒
秦文文
丛乐乐
王争奎
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US15/760,294 priority Critical patent/US10923206B2/en
Publication of WO2018141158A1 publication Critical patent/WO2018141158A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to the field of display control technologies, and in particular, to a shift register unit and a driving method thereof, a gate driving device, an array substrate, a display device, and an electronic device.
  • OLED Organic Light Emitting Diode
  • LCD liquid crystal display
  • a gate switch circuit of a thin film transistor is usually integrated on an array substrate of a display panel by using a Gate Driver on Array (GOA) technology. Scan drive for the display panel.
  • GOA Gate Driver on Array
  • Such a gate drive circuit integrated on an array substrate using GOA technology is also referred to as a GOA circuit or a shift register circuit.
  • the display device using the GOA circuit can reduce the cost from both the material cost and the manufacturing process by eliminating the part that binds the driving circuit.
  • Embodiments of the present disclosure provide a shift register unit and a driving method thereof, a gate driving device, an array substrate, a display device, and an electronic device, wherein the shift register unit can effectively improve a display panel having a touch function
  • the level that needs to be activated after the end of the Touch The voltage of the GOA pull-up node PU, thereby solving the problem of insufficient charging of the pixel transistor of the pixel region.
  • a shift register unit comprising: a first input circuit, a second input circuit, a pull-down control circuit, an output circuit, a pull-down circuit, and a control circuit.
  • the first input circuit is configured to provide a first control signal from the first signal control terminal to the pull up node based on the first input signal from the first signal input.
  • the second input circuit is configured to provide a second control signal from the second signal control terminal to the pull up node based on the second input signal from the second signal input.
  • the pull-down control circuit is configured to provide a voltage of the first voltage terminal to the pull-down node according to the voltage of the pull-up node, or to control the voltage of the pull-down node according to the first clock signal from the input of the first clock signal.
  • the output circuit is configured to provide a second clock signal from the second clock signal input to the signal output as an output signal based on the voltage of the pull-up node.
  • the pull-down circuit is configured to provide the voltage of the first voltage terminal to the pull-up node and the signal output terminal according to the voltage of the pull-down node.
  • the control circuit is configured to provide the first input signal to the pull up node based on the first control signal and the first clock signal.
  • the control circuit includes a second transistor and a third transistor.
  • the control electrode of the second transistor is coupled to the first signal control terminal, the first electrode of the second transistor is coupled to the second electrode of the third transistor, and the second electrode of the second transistor is coupled to the first signal input terminal.
  • the control electrode of the third transistor is coupled to the input end of the first clock signal, the first pole of the third transistor is coupled to the pull-up node, and the second pole of the third transistor is coupled to the first pole of the second transistor.
  • control circuit is further configured to provide the second input signal to the pull-up node based on the second control signal and the first clock signal.
  • the control circuit includes a fifth transistor and a sixth transistor.
  • the control electrode of the fifth transistor is coupled to the second signal control terminal, and the first electrode of the fifth transistor is coupled to the second signal input terminal.
  • the second pole of the fifth transistor is coupled to the first pole of the sixth transistor.
  • the control electrode of the sixth transistor is coupled to the first clock signal input terminal, the first electrode of the sixth transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the sixth transistor is coupled to the pull-up node.
  • the first input circuit includes a first transistor.
  • a control electrode of the first transistor is coupled to the first signal input end, and a first pole of the first transistor is coupled to the pull-up node, A second pole of a transistor is coupled to the first signal control terminal.
  • the second input circuit includes a fourth transistor.
  • the control electrode of the fourth transistor is coupled to the second signal input terminal, the first pole of the fourth transistor is coupled to the second signal control terminal, and the second pole of the fourth transistor is coupled to the pull-up node.
  • the pull-down control circuit includes a seventh transistor, a ninth transistor, a tenth transistor, and a second capacitor.
  • the control electrode and the second pole of the seventh transistor are coupled to the first clock signal input terminal, and the first pole of the seventh transistor is coupled to the pull-down node.
  • the control electrode of the ninth transistor is coupled to the pull-up node, the first pole of the ninth transistor is coupled to the first voltage terminal, and the second pole of the ninth transistor is coupled to the pull-down node.
  • the control electrode of the tenth transistor is coupled to the signal output end, the first pole of the tenth transistor is coupled to the first voltage terminal, and the second pole of the tenth transistor is coupled to the pull-down node.
  • the second capacitor is coupled between the pull-down node and the first voltage terminal.
  • the output circuit includes a twelfth transistor and a first capacitor.
  • the control electrode of the twelfth transistor is coupled to the pull-up node
  • the first pole of the twelfth transistor is coupled to the signal output terminal
  • the second pole of the twelfth transistor is coupled to the second clock signal input terminal.
  • the first capacitor is coupled between the pull up node and the signal output.
  • the pull-down circuit includes an eighth transistor and an eleventh transistor.
  • the control electrode of the eighth transistor is coupled to the pull-down node, the first pole of the eighth transistor is coupled to the first voltage terminal, and the second pole of the eighth transistor is coupled to the pull-up node.
  • the control electrode of the eleventh transistor is coupled to the pull-down node, the first pole of the eleventh transistor is coupled to the first voltage terminal, and the second pole of the eleventh transistor is coupled to the signal output terminal.
  • a method for driving a shift register unit is provided.
  • the first input circuit is turned on according to the first input signal from the first signal input terminal to provide the first control signal from the first signal control terminal to the pull-up node, according to the first control signal and a first clock signal at the input end of the first clock signal, causing the control circuit to be turned on to provide the first input signal to the pull-up node, and the output circuit is turned on according to the voltage of the pull-up node to input the signal from the second clock signal
  • the second clock signal of the terminal is output to the signal output terminal.
  • the second input circuit is turned on according to the second input signal to provide the second control signal to the pull-up node, according to the second control signal and the first clock signal
  • the control circuit is turned on to provide the first input signal to the pull-up node
  • the output circuit is turned on according to the voltage of the pull-up node to output the second clock signal to the signal output end.
  • the voltage of the pull-up node is maintained, the output circuit is kept turned on to output the second clock signal to the signal output terminal, and the voltage of the pull-down node is controlled by the pull-down control circuit according to the voltage of the pull-up node.
  • the first clock signal is provided to the pull-down node to turn on the pull-down circuit to provide the voltage of the first voltage terminal to the pull-up node and the signal output terminal.
  • a gate driving apparatus includes a plurality of cascaded shift register units, each of which is any one of the shift register units described above.
  • the signal output end of each shift register unit is coupled to the first signal input end of the shift register unit of the next stage, and the signal output of the second signal input end of each shift register unit and the shift register unit of the next stage The end is coupled.
  • an array substrate including the above-described gate driving device is provided.
  • a display device including the above array substrate is provided.
  • an electronic device including the above display device.
  • Figure 1 is a circuit diagram of a shift register unit
  • FIG. 2 is a schematic block diagram of a shift register unit in accordance with an embodiment of the present disclosure
  • FIG. 3 is an exemplary block diagram of a shift register unit in accordance with an embodiment of the present disclosure
  • FIG. 4 is an exemplary circuit diagram of a shift register unit in accordance with another embodiment of the present disclosure.
  • FIG. 5 is a timing diagram of signals of a shift register unit, in accordance with an embodiment of the present disclosure.
  • FIG. 6 is a schematic flowchart of a method for driving a shift register unit according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a gate driving circuit in accordance with an embodiment of the present invention.
  • FIG. 8 is a block schematic diagram of a touch display device according to an embodiment of the present disclosure.
  • FIG. 9 is a block schematic diagram of a touch sensitive electronic device in accordance with an embodiment of the present disclosure.
  • FIG. 1 shows a circuit diagram of a shift register unit 8T2C.
  • a shift register unit and a driving method thereof, a gate driving device, an array substrate, a display device, and an electronic device according to an embodiment of the present disclosure are described below with reference to the accompanying drawings.
  • the shift register unit 200 proposed by the embodiment of the present disclosure includes a first input circuit 210, a second input circuit 220, a pull-down control circuit 230, an output circuit 240, a pull-down circuit 250, and a control circuit 260.
  • the first input circuit 210 is coupled to the first signal input terminal STV, the first signal control terminal CN, and the pull-up node PU.
  • the first input circuit 210 can be at the first from the first signal input terminal STV
  • the first control signal from the first signal control terminal CN is supplied to the pull-up node PU under the control of the input signal.
  • the second input circuit 220 is coupled to the second signal input terminal RESET, the second signal control terminal CNB, and the pull-up node PU.
  • the second input circuit 220 can provide the second control signal from the second signal control terminal CNB to the pull-up node PU under the control of the second input signal from the second signal input terminal RESET.
  • the pull-down control circuit 230 is coupled to the first clock signal input terminal CLKB, the pull-up node PU, the pull-down node PD, the first voltage terminal VSS, and the signal output terminal OUTPUT.
  • the pull-down control circuit 230 can supply the voltage of the first voltage terminal VSS to the pull-down node PD under the control of the voltage of the pull-up node PU.
  • the pull-down control circuit 230 can also supply the voltage of the first voltage terminal VSS to the pull-down node PD under the control of the output signal of the signal output terminal OUTPUT.
  • the pull-down control circuit 230 can store the voltage of the second clock signal terminal CLKB, and provide the first clock signal to the pull-down node PD under the control of the first clock signal from the first clock signal input terminal CLKB, or The stored voltage is released to the pull-down node PD to control the voltage of the pull-down node PD.
  • the output circuit 240 is coupled to the pull-up node PU, the second clock signal input terminal CLK, and the signal output terminal OUTPUT.
  • the output circuit 240 can supply the second clock signal from the second clock signal input terminal CLK to the signal output terminal OUTPUT as an output signal under the control of the voltage of the pull-up node PU.
  • the pull-down circuit 250 is coupled to the first voltage terminal VSS, the pull-down node PD, the pull-up node PU, and the signal output terminal OUTPUT.
  • the pull-down circuit 250 can supply the voltage of the first voltage terminal VSS to the pull-up node PU and the signal output terminal OUTPUT under the control of the voltage of the pull-down node PD.
  • the control circuit 260 is coupled to the first signal control terminal CN, the first signal input terminal STV, the first clock signal input terminal CLKB, and the pull-up node PU.
  • the control circuit 260 can provide the first input signal to the pull-up node PU under the control of the first control signal and the first clock signal.
  • FIG. 3 shows a schematic block diagram of a shift register unit 300 in accordance with another embodiment of the present disclosure.
  • the control circuit 360 in the shift register unit 300 has a structure of the control circuit 260 of FIG. 2, a second signal control terminal CNB, a second signal input terminal RESET, a first clock signal input terminal CLKB, and a pull-up node PU. Coupling.
  • the control circuit 360 is further operative to provide the second input signal to the pull up node PU under the control of the second control signal and the first clock signal.
  • FIG. 4 shows an exemplary circuit diagram of the shift register unit 300 shown in FIG.
  • the transistor employed may be an N-type transistor or a P-type transistor.
  • the transistor may be an N-type or P-type field effect transistor (MOSFET), or an N-type or P-type bipolar transistor (BJT).
  • MOSFET N-type or P-type field effect transistor
  • BJT N-type or P-type bipolar transistor
  • the gate of the transistor is referred to as the gate. Since the source and the drain of the transistor are symmetrical, the source and the drain are not distinguished, that is, the source of the transistor can be the first pole (or the second pole), and the drain can be the second pole (or the One pole).
  • any controlled switching device having a strobe signal input can be used to implement the function of the transistor, and the controlled intermediate terminal of the switching device for receiving a control signal (eg, for turning the controlled switching device on and off) is referred to as
  • the control pole has the other ends being the first pole and the second pole, respectively.
  • NMOS N-type field effect transistor
  • the first input circuit 210 includes a first transistor T1.
  • the control electrode of the first transistor T1 is coupled to the first signal input terminal STV
  • the first pole of the first transistor T1 is coupled to the pull-up node PU
  • the second pole of the first transistor T1 is coupled to the first signal control terminal CN. .
  • the second input circuit 220 includes a fourth transistor T4.
  • the control electrode of the fourth transistor T4 is coupled to the second signal input terminal RESET, the first electrode of the fourth transistor T4 is coupled to the second signal control terminal CNB, and the second electrode of the fourth transistor T4 is coupled to the pull-up node PU. .
  • the pull-down control circuit 230 includes a seventh transistor T7, a ninth transistor T9, a tenth transistor T10, and a second capacitor C2.
  • the control electrode and the second electrode of the seventh transistor T7 are coupled to the first clock signal input terminal CLKB, and the first electrode of the seventh transistor T7 is coupled to the pull-down node PD.
  • the control electrode of the ninth transistor T9 is coupled to the pull-up node PU, the first pole of the ninth transistor T9 is coupled to the first voltage terminal VSS, and the second pole of the ninth transistor T9 is coupled to the pull-down node PD.
  • the control electrode of the tenth transistor T10 is coupled to the signal output terminal OUTPUT, the first electrode of the tenth transistor T10 is coupled to the first voltage terminal VSS, and the second electrode of the tenth transistor T10 is coupled to the pull-down node PD.
  • Second The capacitor C2 is coupled between the pull-down node PD and the first voltage terminal VSS.
  • the output circuit 240 includes a twelfth transistor T12 and a first capacitor C1.
  • the control electrode of the twelfth transistor T12 is coupled to the pull-up node PU, the first pole of the twelfth transistor T12 is coupled to the signal output terminal OUTPUT, and the second pole of the twelfth transistor T12 is coupled to the second clock signal input terminal CLK. Coupling.
  • the first capacitor C1 is coupled between the pull-up node PU and the signal output terminal OUTPUT.
  • the pull-down circuit 250 includes an eighth transistor T8 and an eleventh transistor T11.
  • the control electrode of the eighth transistor T8 is coupled to the pull-down node PD, the first electrode of the eighth transistor T8 is coupled to the first voltage terminal VSS, and the second electrode of the eighth transistor T8 is coupled to the pull-up node PU.
  • the control electrode of the eleventh transistor T11 is coupled to the pull-down node PD.
  • the first electrode of the eleventh transistor T11 is coupled to the first voltage terminal VSS, and the second electrode of the eleventh transistor T11 is coupled to the signal output terminal OUTPUT.
  • the control circuit 360 includes a second transistor T2 and a third transistor T3.
  • the control electrode of the second transistor T2 is coupled to the first signal control terminal CN, the first electrode of the second transistor T2 is coupled to the second electrode of the third transistor T3, and the second electrode of the second transistor T2 is coupled to the first signal.
  • the end STV is coupled.
  • the control electrode of the third transistor T3 is coupled to the first clock signal input terminal CLKB, the first electrode of the third transistor T3 is coupled to the pull-up node PU, and the second electrode of the third transistor T3 is coupled to the first transistor T2. Polar coupling.
  • control circuit 360 further includes a fifth transistor T5 and a sixth transistor T6.
  • the control electrode of the fifth transistor T5 is coupled to the second signal control terminal CNB, and the first pole of the fifth transistor T5 is coupled to the second signal input terminal RSEST.
  • the second pole of the fifth transistor T5 is coupled to the first pole of the sixth transistor T6.
  • the control electrode of the sixth transistor T6 is coupled to the first clock signal input terminal CLKB, the first electrode of the sixth transistor T6 is coupled to the second electrode of the fifth transistor T5, and the second electrode of the sixth transistor T6 is coupled to the pull-up node. PU coupling.
  • the transistors in the shift register unit are all N-type transistors as an example.
  • the voltage of the first voltage terminal VSS is a low level.
  • the first signal control terminal CN provides a first control signal of a high level
  • the second signal control terminal CNB provides a second control signal of a low level.
  • the first input signal provided by the first signal input terminal STV is at a high level
  • the first clock signal provided by the first clock signal input terminal CKB is at a high level
  • the second clock signal input terminal CK is provided at a second level.
  • the clock signal is low.
  • the first transistor T1 is turned on, and the second transistor T2 and the third transistor T3 are turned on, and the high level provided by the first signal control terminal CN is output to the pull-up node PU through the first transistor T1 to charge the first capacitor C1.
  • the second transistor T2 and the third transistor T3 are also output to the pull-up node PU to charge the first capacitor C1.
  • the voltage of the pull-up node PU becomes a high level
  • the twelfth transistor T12 is turned on. Since the second clock signal provided by the second clock signal input terminal CK is at a low level, the signal output terminal OUTPUT outputs a low level.
  • the first clock signal provided by the first clock signal input terminal CKB is at a low level and the second clock signal provided by the second clock signal input terminal CK is at a high level.
  • the voltage of the pull-up node PU is further improved by the bootstrapping function, that is, the first capacitor C1 performs voltage bootstrap on the PU point of the pull-up node to keep the PU point of the pull-up node high.
  • the twelfth transistor T12 remains turned on, and the signal output terminal OUTPUT outputs a high level.
  • the ninth transistor T9 and the tenth transistor T10 are turned on, and the voltage of the first voltage terminal VSS is supplied to the pull-down node PD, so that the pull-down node PD becomes a low level.
  • the first clock signal provided by the first clock signal input terminal CKB is at a low level and the second clock signal provided by the second clock signal input terminal CK is at a low level.
  • the pull-up node PU is lower at the level of the bootstrap action, but is still at a higher level, that is, the pull-up node PU maintains a high level.
  • the twelfth transistor T12 is turned on, and at this time, the second clock signal CK is at a low level, so that the signal output terminal OUTPUT outputs a low level.
  • the ninth transistor T9 is turned on, and the pull-down node PD is kept at a low level.
  • the second input signal provided by the second signal input terminal RESET is at a high level
  • the first clock signal provided by the first clock signal input terminal CKB is at a high level
  • the second clock signal input terminal CK is provided at a second level.
  • the clock signal is low. Since the input signal provided by the second signal input terminal RESET is at a high level, the fourth transistor T4 is turned on, the voltage of the pull-up node PU is pulled low to the low level, and the ninth transistor T9 is turned off.
  • the seventh transistor T7 is turned on, and the pull-down node PD point becomes a high level.
  • the eleventh transistor T11 is turned on, and the signal output terminal OUTPUT outputs a low level.
  • the second clock signal provided by the second clock signal input terminal CK is a low level.
  • the first clock signal provided by the first clock signal input terminal CKB is at a low level.
  • the first signal control terminal CN provides a first control signal of a low level
  • the second signal control terminal CNB provides a second control signal of a high level.
  • the working process of the reverse scan is similar to the working process of the forward scan, which is described in detail below.
  • a second input signal of a high level is supplied at the second signal input terminal RESET.
  • the fourth transistor T4 is turned on, and the fifth transistor T5 and the sixth transistor T6 are turned on, and the high level provided by the second signal control terminal CNB is output to the pull-up node PU through the fourth transistor T4 to charge the first capacitor C1.
  • the first transistor C1 is also charged by the fifth transistor T5 and the sixth transistor T6 to the pull-up node PU.
  • the voltage of the pull-up node PU becomes a high level, and the twelfth transistor T12 is turned on. Since the second clock signal is at a low level, the signal output terminal OUTPUT outputs a low level.
  • the working process at times t2 and t3 is the same as the working process at times t2 and t3 in the forward scanning, and will not be described herein.
  • a first input signal of a high level is supplied at the first signal input terminal STV.
  • the first transistor T1 is turned on, the voltage of the pull-up node PU is pulled low, and the ninth transistor T9 is turned off.
  • the seventh transistor T7 is turned on, and the pull-down node PD point becomes a high level.
  • the eleventh transistor T11 is turned on, and the signal output terminal OUTPUT outputs a low level.
  • the first capacitor C1 functions to bootstrap the voltage of the pull-up node PU
  • the second capacitor C2 functions to stabilize the voltage of the pull-down node PD and reduce the voltage of the pull-down node PD. effect.
  • the first capacitor C1 can be charged by the transistors T1 and T2, T3, so that the voltage of the pull-up node PU rises, and in the reverse scan, the transistors T4 and T5 can be passed.
  • T6 charges the first capacitor C1 to increase the voltage of the pull-up node PU.
  • the voltage of the pull-up node PU is higher than that of the shift register unit charged by only one transistor in FIG.
  • the shift register unit When the shift register unit does not have an output, it can pass through the forward scan. Transistors T2 and T3 pull the pull-up node PU low to accelerate the discharge of the pull-up node PU. When the reverse scan is performed, the pull-up node PU can be pulled low to the low level through the transistors T5 and T6 to accelerate the pull-up. The discharge of the node PU. Therefore, a quick response of the display panel having the touch function can be realized.
  • FIG. 6 is a schematic flow chart of a method for driving a shift register unit in accordance with an embodiment of the present invention.
  • step S610 the first input circuit is turned on according to the first input signal from the first signal input terminal to turn the first control signal from the first signal control terminal.
  • the control circuit Providing to the pull-up node, according to the first control signal and the first clock signal from the input end of the first clock signal, turning on the control circuit to provide the first input signal to the pull-up node, according to the voltage of the pull-up node
  • the output circuit is turned on to output a second clock signal from the second clock signal input terminal to the signal output terminal.
  • step S620 the voltage of the pull-up node is maintained, the output circuit is kept turned on to output the second clock signal to the signal output terminal, and the voltage of the pull-down node is controlled by the pull-down control circuit according to the voltage of the pull-up node.
  • step S630 the second input circuit is turned on according to the second input signal from the second signal input terminal to provide the second control signal from the second signal control terminal to the pull-up node, and the output circuit is turned off. And according to the first clock signal, the first clock signal is provided to the pull-down node, and the pull-down circuit is turned on to provide the voltage of the first voltage terminal to the pull-up node and the signal output end.
  • step S610 the second input circuit is turned on according to the second input signal to provide the second control signal to the pull-up node, according to the second control signal and the first clock signal.
  • the control circuit is turned on to provide the first input signal to the pull-up node, and the output circuit is turned on according to the voltage of the pull-up node to output the second clock signal to the signal output end.
  • step S620 the voltage of the pull-up node is maintained, the output circuit is kept turned on to output the second clock signal to the signal output terminal, and the voltage of the pull-down node is controlled by the pull-down control circuit according to the voltage of the pull-up node.
  • step S630 the second input circuit is turned on according to the second input signal from the second signal input terminal to provide the second control signal from the second signal control terminal to the pull-up node, the output circuit is turned off, and
  • the first clock signal provides the first clock signal to the pull-down node to turn on the pull-down circuit to provide the voltage of the first voltage terminal to the pull-up node and the signal output terminal.
  • FIG. 7 shows a schematic structural diagram of a gate driving circuit 700 according to an embodiment of the present invention.
  • the gate driving circuit 700 may include a plurality of cascaded shift register units SR1, SR2, ..., SRn, SR(n+1), .
  • the shift register unit of each stage can adopt the structure of the shift register unit 200 or 300 as described above.
  • the port of each stage of the shift register unit may include: a first signal input terminal STV, a first signal control terminal CN, a second signal input terminal RESET, a second signal control terminal CNB, and a first clock.
  • the signal output terminal OUTPUT of each stage shift register SRn is coupled to the first signal input terminal STV of the next stage shift register SR(n+1), and the second signal input terminal RESET of each stage shift register unit SRn It is coupled to the signal output terminal OUTPUT of the shift register unit SR(n+1) of the next stage.
  • the second signal input terminal RESET of the first stage shift register SR1 receives the output signal from the signal output terminal OUTPUT of the second stage shift register SR2 as the second input signal RESET of the first stage shift register SR1 (ie, , reset signal).
  • the first signal input terminal STV of the second stage shift register SR2 receives the output signal from the signal output terminal OUTPUT of the first stage shift register SR1 as the first signal input terminal STV of the second stage shift register SR1 (ie, Frame open signal).
  • the second clock signal supplied from the second clock signal input terminal CK when the first clock signal supplied from the first clock signal input terminal CKB is at a high level, the second clock signal supplied from the second clock signal input terminal CK is at a low level.
  • the first clock signal provided by the first clock signal input terminal CKB is at a low level.
  • an embodiment of the present disclosure also proposes a display device 800 that includes an array substrate 810.
  • the array substrate 810 includes the gate driving device 700 described in the above embodiment.
  • the display device 800 can be a display panel with a touch function or other devices with a touch display function.
  • the voltage of the pull-up node PU of the shift register unit GOA of the stage that needs to be activated after the end of the touch can be effectively increased by the above-described gate driving device.
  • the problem that the voltage of the pull-up node PU of the shift register unit GOA of the first stage that needs to be activated after the end of the touch is low due to the leakage of the pull-up node PU is avoided.
  • the voltage of the pull-up node PU is prevented from becoming lower, which causes the problem of insufficient charging of the pixel transistor of the pixel region, ensuring the touch display effect and fully satisfying the needs of the user.
  • an embodiment of the present disclosure also proposes an electronic device 900 including the above-described display device 800.
  • the electronic device 900 can be, for example, a mobile phone with a touch display, a tablet computer, a display screen, a wearable device, and the like.
  • the electronic device adopts the above display device, has good touch display effect, fast response, and improves user experience.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include at least one of the features, either explicitly or implicitly.
  • the meaning of "a plurality” is at least two, such as two, three, etc., unless specifically defined otherwise.
  • Coupled shall be understood broadly, and may be directly connected or indirectly connected through an intermediary medium unless otherwise specified. limited.
  • the specific meanings of the above terms in the present disclosure can be understood by those skilled in the art on a case-by-case basis.
  • the first feature "on” or “under” the second feature may be a direct contact of the first and second features, or the first and second features may be indirectly through an intermediate medium, unless otherwise explicitly stated and defined. contact.
  • the first feature "above”, “above” and “above” the second feature may be that the first feature is directly above or above the second feature, or merely that the first feature level is higher than the second feature.
  • the first feature “below”, “below” and “below” the second feature may be that the first feature is directly below or below the second feature, or merely that the first feature is less than the first feature.

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Abstract

本公开实施例涉及移位寄存器单元及其驱动方法、栅极驱动装置。移位寄存器单元包括第一输入电路、第二输入电路、下拉控制电路、输出电路、下拉电路和控制电路。第一输入电路根据第一输入信号，将第一控制信号提供给上拉节点。第二输入电路根据第二输入信号，将第二控制信号提供给上拉节点。下拉控制电路根据上拉节点的电压，将第一电压端的电压提供给下拉节点，或者根据第一时钟信号，控制下拉节点的电压。输出电路根据上拉节点的电压，将第二时钟信号提供给信号输出端。下拉电路根据下拉节点的电压，将第一电压端的电压提供给上拉节点和信号输出端。控制电路根据第一控制信号和第一时钟信号，将第一输入信号提供给上拉节点。

Description

移位寄存器单元及其驱动方法、栅极驱动装置
相关申请的交叉引用
本申请要求于2017年2月6日递交的中国专利申请第201710065761.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示控制技术领域，具体地，涉及移位寄存器单元及其驱动方法、栅极驱动装置、阵列基板、显示装置和电子设备。
背景技术
随着显示技术的进步，相对于传统的液晶显示(Liquid Crystal Display，LCD)装置，新一代的有机发光二极管(Organic Light Emitting Diode，OLED)显示装置具有更低的制造成本，更快的反应速度，更高的对比度，更广的视角，更大的工作温度范围，不需要背光单元，色彩鲜艳及轻薄等优点，因此OLED显示技术成为当前发展最快的显示技术。
为了提高OLED面板的工艺集成度并降低成本，通常采用阵列基板行驱动(Gate Driver on Array，简称GOA)技术而将薄膜晶体管(TFT)的栅极开关电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动。这种利用GOA技术而集成在阵列基板上的栅极驱动电路也称为GOA电路或移位寄存器电路。采用GOA电路的显示装置由于省去了绑定驱动电路的部分，可以从材料成本和制作工艺两方面降低成本。
发明内容
本公开的实施例提供了一种移位寄存器单元及其驱动方法、栅极驱动装置、阵列基板、显示装置和电子设备，其中移位寄存器单元能够有效提高具有触控(Touch)功能的显示面板在Touch结束后需要启动的那一级的 GOA的上拉节点PU的电压，从而解决像素区晶体管TFT的充电不足的问题。
根据本公开的一方面，提出一种移位寄存器单元，包括：第一输入电路、第二输入电路、下拉控制电路、输出电路、下拉电路和控制电路。第一输入电路被配置为根据来自第一信号输入端的第一输入信号，将来自第一信号控制端的第一控制信号提供给上拉节点。第二输入电路被配置为根据来自第二信号输入端的第二输入信号，将来自第二信号控制端的第二控制信号提供给上拉节点。下拉控制电路被配置为根据上拉节点的电压，将第一电压端的电压提供给下拉节点，或者根据来自第一时钟信号输入端的第一时钟信号，控制下拉节点的电压。输出电路被配置为根据上拉节点的电压，将来自第二时钟信号输入端的第二时钟信号提供给信号输出端，作为输出信号。下拉电路被配置为根据下拉节点的电压，将第一电压端的电压提供给上拉节点和信号输出端。控制电路被配置为根据第一控制信号和第一时钟信号，将第一输入信号提供给上拉节点。
在本公开的实施例中，控制电路包括第二晶体管和第三晶体管。第二晶体管的控制极与第一信号控制端耦接，第二晶体管的第一极与第三晶体管的第二极耦接，第二晶体管的第二极与第一信号输入端耦接。第三晶体管的控制极与第一时钟信号输入端耦接，第三晶体管的第一极与上拉节点耦接，第三晶体管的第二极与第二晶体管的第一极耦接。
在本公开的实施例中，控制电路进一步被配置为根据第二控制信号和第一时钟信号，将第二输入信号提供给上拉节点。
在本公开的实施例中，控制电路包括第五晶体管和第六晶体管，第五晶体管的控制极与第二信号控制端耦接，第五晶体管的第一极与第二信号输入端耦接，第五晶体管的第二极与第六晶体管的第一极耦接。第六晶体管的控制极与第一时钟信号输入端耦接，第六晶体管的第一极与第五晶体管的第二极耦接，第六晶体管的第二极与上拉节点耦接。
在本公开的实施例中，第一输入电路包括第一晶体管。第一晶体管的控制极与第一信号输入端耦接，第一晶体管的第一极与上拉节点耦接，第 一晶体管的第二极与第一信号控制端耦接。
在本公开的实施例中，第二输入电路包括第四晶体管。第四晶体管的控制极与第二信号输入端耦接，第四晶体管的第一极与第二信号控制端耦接，第四晶体管的第二极与上拉节点耦接。
在本公开的实施例中，下拉控制电路包括第七晶体管、第九晶体管、第十晶体管和第二电容。第七晶体管的控制极和第二极与第一时钟信号输入端耦接，第七晶体管的第一极与下拉节点耦接。第九晶体管的控制极与上拉节点耦接，第九晶体管的第一极与第一电压端耦接，第九晶体管的第二极与下拉节点耦接。第十晶体管的控制极与信号输出端耦接，第十晶体管的第一极与第一电压端耦接，第十晶体管的第二极与下拉节点耦接。第二电容被耦接在下拉节点和第一电压端之间。
在本公开的实施例中，输出电路包括第十二晶体管和第一电容。第十二晶体管的控制极与上拉节点耦接，第十二晶体管的第一极与信号输出端耦接，第十二晶体管的第二极与第二时钟信号输入端耦接。第一电容被耦接在上拉节点和信号输出端之间。
在本公开的实施例中，下拉电路包括第八晶体管和第十一晶体管。第八晶体管的控制极与下拉节点耦接，第八晶体管的第一极与第一电压端耦接，第八晶体管的第二极与上拉节点耦接。第十一晶体管的控制极与下拉节点耦接，第十一晶体管的第一极与第一电压端耦接，第十一晶体管的第二极与信号输出端耦接。
根据本公开的另一方面，提供一种用于驱动移位寄存器单元的方法。在该方法中，根据来自第一信号输入端的第一输入信号，使第一输入电路导通，以将来自第一信号控制端的第一控制信号提供给上拉节点，根据第一控制信号和来自第一时钟信号输入端的第一时钟信号，使控制电路导通，以将第一输入信号提供给上拉节点，根据上拉节点的电压，使输出电路导通，以将来自第二时钟信号输入端的第二时钟信号输出至信号输出端。维持上拉节点的电压，使输出电路保持导通，以将第二时钟信号输出至信号输出端，并且根据上拉节点的电压，通过下拉控制电路控制下拉节点的电 压。根据来自第二信号输入端的第二输入信号，使第二输入电路导通，以将来自第二信号控制端的第二控制信号提供给上拉节点，使输出电路截止，并且根据第一时钟信号，将第一时钟信号提供给下拉节点，使下拉电路导通，以将第一电压端的电压提供给上拉节点和信号输出端。
在本公开的实施例中，在方法中，根据第二输入信号，使第二输入电路导通，以将第二控制信号提供给上拉节点，根据第二控制信号和第一时钟信号，使控制电路导通，以将第一输入信号提供给上拉节点，根据上拉节点的电压，使输出电路导通，以将第二时钟信号输出至信号输出端。维持上拉节点的电压，使输出电路保持导通，以将第二时钟信号输出至信号输出端，并且根据上拉节点的电压，通过下拉控制电路控制下拉节点的电压。根据来自第二信号输入端的第二输入信号，使第二输入电路导通，以将来自第二信号控制端的第二控制信号提供给上拉节点，使输出电路截止，并且根据第一时钟信号，将第一时钟信号提供给下拉节点，使下拉电路导通，以将第一电压端的电压提供给上拉节点和信号输出端。
根据本公开的另一方面，提供一种栅极驱动装置，其包括多个级联的移位寄存器单元，每级移位寄存器单元是上述任一种移位寄存器单元。各级移位寄存器单元的信号输出端与下一级移位寄存器单元的第一信号输入端耦接，各级移位寄存器单元的第二信号输入端与下一级移位寄存器单元的信号输出端耦接。
根据本公开的另一方面，提供一种阵列基板，包括上述栅极驱动装置。
根据本公开的另一方面，提供一种显示装置，包括上述阵列基板。
根据本公开的另一方面，还提供一种电子设备，包括上述显示装置。
附图说明
为了更清楚地说明本发明的技术方案，下面将对实施例的附图进行简单说明。应当知道，以下描述的附图仅仅是本发明的一些实施例，而非对本发明的限制，其中：
图1是一种移位寄存器单元的电路图；
图2是根据本公开的实施例的移位寄存器单元的示意性框图；
图3是根据本公开的实施例的移位寄存器单元的示例性框图；
图4是根据本公开的另一实施例的移位寄存器单元的示例性电路图；
图5是根据本公开的实施例的移位寄存器单元的各信号的时序图；
图6是用于驱动根据本公开的实施例的移位寄存器单元的方法的示意性流程图；
图7是根据本发明的实施例的栅极驱动电路的示意图；
图8是根据本公开实施例的触控显示装置的方框示意图；以及
图9是根据本公开实施例的触控式电子设备的方框示意图。
具体实施方式
为了使本发明的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本发明的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例仅仅是本发明的一部分实施例，而并非全部的实施例。基于所描述的实施例，本领域的普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本发明的范围。
图1示出了一种移位寄存器单元8T2C的电路图。该8T2C的GOA电路应用于显示触控面板时，Touch结束后，需要启动的那一级的GOA在Touch阶段PU节点只通过一个TFT进行充电变为高电平，但是由于PU节点会漏电，从而会导致Touch结束后需要启动的那一级的GOA的PU节点电平变得较低，导致像素区TFT存在充电不足问题。
下面参照附图来描述根据本公开实施例提出的移位寄存器单元及其驱动方法、栅极驱动装置、阵列基板、显示装置和电子设备。
如图2所示，本公开实施例提出的移位寄存器单元200包括：第一输入电路210、第二输入电路220、下拉控制电路230、输出电路240、下拉电路250和控制电路260。
第一输入电路210与第一信号输入端STV、第一信号控制端CN和上拉节点PU耦接。第一输入电路210可在来自第一信号输入端STV的第一 输入信号的控制下，将来自第一信号控制端CN的第一控制信号提供给上拉节点PU。
第二输入电路220与第二信号输入端RESET、第二信号控制端CNB和上拉节点PU耦接。第二输入电路220可在来自第二信号输入端RESET的第二输入信号的控制下，将来自第二信号控制端CNB的第二控制信号提供给上拉节点PU。
下拉控制电路230与第一时钟信号输入端CLKB、上拉节点PU、下拉节点PD、第一电压端VSS和信号输出端OUTPUT耦接。下拉控制电路230可在上拉节点PU的电压的控制下，将第一电压端VSS的电压提供给下拉节点PD。下拉控制电路230还可在信号输出端OUTPUT的输出信号的控制下，将第一电压端VSS的电压提供给下拉节点PD。此外，下拉控制电路230可对第二时钟信号端CLKB的电压进行存储，并在来自第一时钟信号输入端CLKB的第一时钟信号的控制下，将第一时钟信号提供给下拉节点PD，或将存储的电压释放至下拉节点PD，以控制下拉节点PD的电压。
输出电路240与上拉节点PU、第二时钟信号输入端CLK和信号输出端OUTPUT耦接。输出电路240可在上拉节点PU的电压的控制下，将来自第二时钟信号输入端CLK的第二时钟信号提供给信号输出端OUTPUT，作为输出信号。
下拉电路250与第一电压端VSS、下拉节点PD、上拉节点PU和信号输出端OUTPUT耦接。下拉电路250可在下拉节点PD的电压的控制下，将第一电压端VSS的电压提供给上拉节点PU和信号输出端OUTPUT。
控制电路260与第一信号控制端CN、第一信号输入端STV、第一时钟信号输入端CLKB和上拉节点PU耦接。控制电路260可在第一控制信号和第一时钟信号的控制下，将第一输入信号提供给上拉节点PU。
图3示出了根据本公开的另一实施例的移位寄存器单元300的示意性框图。移位寄存器单元300中的第一输入电路210、第二输入电路220、下拉控制电路230、输出电路240和下拉电路250与如上结合图2所描述的第一输入电路210、第二输入电路220、下拉控制电路230、输出电路240 和下拉电路250相同。移位寄存器单元300中的控制电路360除了具有图2中控制电路260的结构外，还与第二信号控制端CNB、第二信号输入端RESET、第一时钟信号输入端CLKB和上拉节点PU耦接。控制电路360进一步可在第二控制信号和第一时钟信号的控制下，将第二输入信号提供给上拉节点PU。
图4示出了图3所示的移位寄存器单元300的示例性电路图。在实施例中，所采用的晶体管可以是N型晶体管或者P型晶体管。具体地，晶体管可以是N型或P型场效应晶体管(MOSFET)，或者N型或P型双极性晶体管(BJT)。在本发明的实施例中，晶体管的栅极被称为控制极。由于晶体管的源极和漏极是对称的，因此对源极和漏极不做区分，即晶体管的源极可以为第一极(或第二极)，漏极可以为第二极(或第一极)。进一步，可以采用具有选通信号输入的任何受控开关器件来实现晶体管的功能，将用于接收控制信号(例如用于开启和关断受控开关器件)的开关器件的受控中间端称为控制极，另外两端分别为第一极和第二极。以下，以N型场效应晶体管(NMOS)为例进行详细的描述。
如图4所示，第一输入电路210包括第一晶体管T1。第一晶体管T1的控制极与第一信号输入端STV耦接，第一晶体管T1的第一极与上拉节点PU耦接，第一晶体管T1的第二极与第一信号控制端CN耦接。
第二输入电路220包括第四晶体管T4。第四晶体管T4的控制极与第二信号输入端RESET耦接，第四晶体管T4的第一极与第二信号控制端CNB耦接，第四晶体管T4的第二极与上拉节点PU耦接。
下拉控制电路230包括第七晶体管T7、第九晶体管T9、第十晶体管T10和第二电容C2。第七晶体管T7的控制极和第二极与第一时钟信号输入端CLKB耦接，第七晶体管T7的第一极与下拉节点PD耦接。第九晶体管T9的控制极与上拉节点PU耦接，第九晶体管T9的第一极与第一电压端VSS耦接，第九晶体管T9的第二极与下拉节点PD耦接。第十晶体管T10的控制极与信号输出端OUTPUT耦接，第十晶体管T10的第一极与第一电压端VSS耦接，第十晶体管T10的第二极与下拉节点PD耦接。第二 电容C2被耦接在下拉节点PD和第一电压端VSS之间。
输出电路240包括第十二晶体管T12和第一电容C1。第十二晶体管T12的控制极与上拉节点PU耦接，第十二晶体管T12的第一极与信号输出端OUTPUT耦接，第十二晶体管T12的第二极与第二时钟信号输入端CLK耦接。第一电容C1被耦接在上拉节点PU和信号输出端OUTPUT之间。
下拉电路250包括第八晶体管T8和第十一晶体管T11。第八晶体管T8的控制极与下拉节点PD耦接，第八晶体管T8的第一极与第一电压端VSS耦接，第八晶体管T8的第二极与上拉节点PU耦接。第十一晶体管T11的控制极与下拉节点PD耦接，第十一晶体管T11的第一极与第一电压端VSS耦接，第十一晶体管T11的第二极与信号输出端OUTPUT耦接。
控制电路360包括第二晶体管T2和第三晶体管T3。第二晶体管T2的控制极与第一信号控制端CN耦接，第二晶体管T2的第一极与第三晶体管T3的第二极耦接，第二晶体管T2的第二极与第一信号输入端STV耦接。第三晶体管T3的控制极与第一时钟信号输入端CLKB耦接，第三晶体管T3的第一极与上拉节点PU耦接，第三晶体管T3的第二极与第二晶体管T2的第一极耦接。
进一步，控制电路360还包括第五晶体管T5和第六晶体管T6，第五晶体管T5的控制极与第二信号控制端CNB耦接，第五晶体管T5的第一极与第二信号输入端RSEST耦接，第五晶体管T5的第二极与第六晶体管T6的第一极耦接。第六晶体管T6的控制极与第一时钟信号输入端CLKB耦接，第六晶体管T6的第一极与第五晶体管T5的第二极耦接，第六晶体管T6的第二极与上拉节点PU耦接。
下面结合图5所示的时序图，对如图4所示的移位寄存器单元的工作过程进行详细描述。在以下的描述中，以移位寄存器单元中的晶体管均是N型晶体管为例。第一电压端VSS的电压为低电平。在正向扫描的过程中，第一信号控制端CN提供高电平的第一控制信号，第二信号控制端CNB提供低电平的第二控制信号。
在t1时刻，第一信号输入端STV提供的第一输入信号为高电平、第一时钟信号输入端CKB提供的第一时钟信号为高电平且第二时钟信号输入端CK提供的第二时钟信号为低电平。第一晶体管T1导通，且第二晶体管T2和第三晶体管T3导通，第一信号控制端CN提供的高电平通过第一晶体管T1输出至上拉节点PU以给第一电容C1充电，同时还通过第二晶体管T2和第三晶体管T3输出至上拉节点PU以给第一电容C1充电。上拉节点PU的电压变为高电平，第十二晶体管T12导通，由于第二时钟信号输入端CK提供的第二时钟信号为低电平，信号输出端OUTPUT输出低电平。
在t2时刻，第一时钟信号输入端CKB提供的第一时钟信号为低电平且第二时钟信号输入端CK提供的第二时钟信号为高电平。通过第一电容C1，上拉节点PU的电压由于自举作用(bootstrpping)而被进一步提高，即第一电容C1对上拉节点PU点进行电压自举以使上拉节点PU点保持高电平，第十二晶体管T12保持导通，信号输出端OUTPUT输出高电平。第九晶体管T9和第十晶体管T10导通，将第一电压端VSS的电压提供给下拉节点PD，使下拉节点PD变为低电平。
在t3时刻，第一时钟信号输入端CKB提供的第一时钟信号为低电平且第二时钟信号输入端CK提供的第二时钟信号为低电平。上拉节点PU由于自举作用电平降低，但还是处于较高电平，即上拉节点PU保持高电平。第十二晶体管T12打开，此时第二时钟信号CK为低电平，使信号输出端OUTPUT输出低电平。第九晶体管T9导通，保持下拉节点PD为低电平。
在t4时刻，第二信号输入端RESET提供的第二输入信号为高电平、第一时钟信号输入端CKB提供的第一时钟信号为高电平且第二时钟信号输入端CK提供的第二时钟信号为低电平。由于第二信号输入端RESET提供的输入信号为高电平，第四晶体管T4导通，上拉节点PU的电压被拉低到低电平，第九晶体管T9截止。第七晶体管T7导通，下拉节点PD点变为高电平。第十一晶体管T11导通，信号输出端OUTPUT输出低电平。
在本公开的实施例中，如图5所示，当第一时钟信号输入端CKB提供的第一时钟信号为高电平时，第二时钟信号输入端CK提供的第二时钟信号为低电平。当第二时钟信号输入端CK提供的第二时钟信号为高电平时，第一时钟信号输入端CKB提供的第一时钟信号为低电平。
另一方面，在反向扫描过程中，第一信号控制端CN提供低电平的第一控制信号，第二信号控制端CNB提供高电平的第二控制信号。反向扫描的工作过程与正向扫描的工作过程类似，以下对此进行详细描述。
在t1时刻，在第二信号输入端RESET提供高电平的第二输入信号。第四晶体管T4导通，且第五晶体管T5和第六晶体管T6导通，第二信号控制端CNB提供的高电平通过第四晶体管T4输出至上拉节点PU以给第一电容C1充电，同时还通过第五晶体管T5和第六晶体管T6输出至上拉节点PU以给第一电容C1充电。上拉节点PU的电压变为高电平，第十二晶体管T12导通，由于第二时钟信号为低电平，信号输出端OUTPUT输出低电平。
在反向扫描过程中，t2与t3时刻的工作过程与上述正向扫描时的t2与t3时刻的工作过程相同，在此不再赘述。
在t4时刻，在第一信号输入端STV提供高电平的第一输入信号。第一晶体管T1导通，上拉节点PU的电压被拉低到低电平，第九晶体管T9截止。第七晶体管T7导通，下拉节点PD点变为高电平。第十一晶体管T11导通，信号输出端OUTPUT输出低电平。
在本公开的实施例中，第一电容C1是起到使上拉节点PU的电压自举的作用，第二电容C2是起到稳定下拉节点PD的电压及降低下拉节点PD的电压的噪声的作用。当移位寄存器单元存在输出时，正向扫描时，可以通过晶体管T1和T2、T3给第一电容C1充电，使上拉节点PU的电压升高，反向扫描时，可以通过晶体管T4和T5、T6给第一电容C1充电，使上拉节点PU的电压升高。与图1中的仅通过一个晶体管充电的移位寄存器单元相比，上拉节点PU的电压更高，从而解决像素区晶体管存在的充电不足的问题。当移位寄存器单元不存在输出时，正向扫描时，可以通过 晶体管T2和T3将上拉节点PU拉低到低电平，加速上拉节点PU的放电，反向扫描时，可以通过晶体管T5和T6将上拉节点PU拉低到低电平，加速上拉节点PU的放电。因此，可以实现具有Touch功能的显示面板的快速响应。
图6是用于驱动根据本发明的实施例的移位寄存器单元的方法的示意性流程图。
如图6所示，对于正向扫描过程，首先在步骤S610中，根据来自第一信号输入端的第一输入信号，使第一输入电路导通，以将来自第一信号控制端的第一控制信号提供给上拉节点，根据第一控制信号和来自第一时钟信号输入端的第一时钟信号，使控制电路导通，以将第一输入信号提供给上拉节点，根据上拉节点的电压，使输出电路导通，以将来自第二时钟信号输入端的第二时钟信号输出至信号输出端。
在步骤S620中，维持上拉节点的电压，使输出电路保持导通，以将第二时钟信号输出至信号输出端，并且根据上拉节点的电压，通过下拉控制电路控制下拉节点的电压。
接下来，在步骤S630中，根据来自第二信号输入端的第二输入信号，使第二输入电路导通，以将来自第二信号控制端的第二控制信号提供给上拉节点，使输出电路截止，并且根据第一时钟信号，将第一时钟信号提供给下拉节点，使下拉电路导通，以将第一电压端的电压提供给上拉节点和信号输出端。
在反向扫描的实施例中，在步骤S610中，根据第二输入信号，使第二输入电路导通，以将第二控制信号提供给上拉节点，根据第二控制信号和第一时钟信号，使控制电路导通，以将第一输入信号提供给上拉节点，根据上拉节点的电压，使输出电路导通，以将第二时钟信号输出至信号输出端。
在步骤S620中，维持上拉节点的电压，使输出电路保持导通，以将第二时钟信号输出至信号输出端，并且根据上拉节点的电压，通过下拉控制电路控制下拉节点的电压。
在步骤S630中，根据来自第二信号输入端的第二输入信号，使第二输入电路导通，以将来自第二信号控制端的第二控制信号提供给上拉节点，使输出电路截止，并且根据第一时钟信号，将第一时钟信号提供给下拉节点，使下拉电路导通，以将第一电压端的电压提供给上拉节点和信号输出端。
图7示出根据本发明的实施例的栅极驱动电路700的示意性结构图。如图7所示，栅极驱动电路700可包括多个级联的移位寄存器单元SR1、SR2、…、SRn、SR(n+1)、...。每级移位寄存器单元可以采用如上所述的移位寄存器单元200或300的结构。
在栅极驱动电路700中，每级移位寄存器单元的端口可包括：第一信号输入端STV、第一信号控制端CN、第二信号输入端RESET、第二信号控制端CNB、第一时钟信号输入端CLKB、第二时钟信号输入端CLK、第一电压信号端VSS和信号输出端OUTPUT。
每一级移位寄存器SRn的信号输出端OUTPUT与下一级移位寄存器SR(n+1)的第一信号输入端STV耦接，每一级移位寄存器单元SRn的第二信号输入端RESET与下一级移位寄存器单元SR(n+1)的信号输出端OUTPUT耦接。例如，第一级移位寄存器SR1的第二信号输入端RESET接收来自第二级移位寄存器SR2的信号输出端OUTPUT的输出信号，作为第一级移位寄存器SR1的第二输入信号RESET(即，复位信号)。第二级移位寄存器SR2的第一信号输入端STV接收来自第一级移位寄存器SR1的信号输出端OUTPUT的输出信号，作为第二级移位寄存器SR1的第一信号输入端STV(即，帧开启信号)。
根据本公开的实施例，当第一时钟信号输入端CKB提供的第一时钟信号为高电平时，第二时钟信号输入端CK提供的第二时钟信号为低电平。当第二时钟信号输入端CK提供的第二时钟信号为高电平时，第一时钟信号输入端CKB提供的第一时钟信号为低电平。
如图8所示，本公开的实施例还提出了一种显示装置800，其包括阵列基板810。阵列基板810包括上述实施例描述的栅极驱动装置700。
其中，显示装置800可以是带有Touch功能的显示面板，或者其他具有触控显示功能的装置。
根据本公开实施例的显示装置，通过上述的栅极驱动装置，能够有效地提高Touch结束后需要启动的那一级的移位寄存器单元GOA的上拉节点PU的电压。避免因上拉节点PU漏电而导致Touch结束后需要启动的那一级的移位寄存器单元GOA的上拉节点PU的电压较低的问题。防止上拉节点PU的电压变得较低而导致像素区晶体管TFT存在充电不足的问题，保证了触控显示效果，充分满足用户的需要。
此外，如图9所示，本公开的实施例还提出了一种电子设备900，其包括上述的显示装置800。电子设备900例如可以是带有触控显示屏的移动电话、平板计算机、显示屏、可穿戴设备等。
本公开实施例的电子设备，采用上述的显示装置，触控显示效果佳，响应快速，提高了用户体验。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本公开的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
在本公开中，除非另有明确的规定和限定，术语“耦接”、“连接”等术语应做广义理解，例如，可以是直接相连，也可以通过中间媒介间接相连，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
在本公开中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。而且，第一特征在第二特征“之上”、“上方”和“上面”可是第一特征在第二特征正上方或斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”可以是第一特征在第二特征正下方或斜下方，或仅仅表示第一特征水平高度小于第 二特征。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (15)

  1. 一种移位寄存器单元，包括：
    第一输入电路，其被配置为根据来自第一信号输入端的第一输入信号，将来自第一信号控制端的第一控制信号提供给上拉节点；
    第二输入电路，其被配置为根据来自第二信号输入端的第二输入信号，将来自第二信号控制端的第二控制信号提供给所述上拉节点；
    下拉控制电路，其被配置为根据所述上拉节点的电压，将第一电压端的电压提供给下拉节点，或者根据来自第一时钟信号输入端的第一时钟信号，控制所述下拉节点的电压；
    输出电路，其被配置为根据所述上拉节点的电压，将来自第二时钟信号输入端的第二时钟信号提供给信号输出端，作为输出信号；
    下拉电路，其被配置为根据所述下拉节点的电压，将所述第一电压端的电压提供给所述上拉节点和所述信号输出端；以及
    控制电路，其被配置为根据所述第一控制信号和所述第一时钟信号，将所述第一输入信号提供给所述上拉节点。
  2. 如权利要求1所述的移位寄存器单元，其中，所述控制电路包括第二晶体管和第三晶体管，
    所述第二晶体管的控制极与所述第一信号控制端耦接，所述第二晶体管的第一极与所述第三晶体管的第二极耦接，所述第二晶体管的第二极与所述第一信号输入端耦接；
    所述第三晶体管的控制极与所述第一时钟信号输入端耦接，所述第三晶体管的第一极与所述上拉节点耦接，所述第三晶体管的第二极与所述第二晶体管的第一极耦接。
  3. 如权利要求1所述的移位寄存器单元，其中，所述控制电路进一步被配置为根据所述第二控制信号和所述第一时钟信号，将所述第二输入信号提供给所述上拉节点。
  4. 如权利要求3所述的移位寄存器单元，其中，所述控制电路包括第五晶体管和第六晶体管，
    所述第五晶体管的控制极与所述第二信号控制端耦接，所述第五晶体管的第一极与所述第二信号输入端耦接，所述第五晶体管的第二极与所述第六晶体管的第一极耦接；
    所述第六晶体管的控制极与所述第一时钟信号输入端耦接，所述第六晶体管的第一极与所述第五晶体管的第二极耦接，所述第六晶体管的第二极与所述上拉节点耦接。
  5. 如权利要求1所述的移位寄存器单元，其中，所述第一输入电路包括第一晶体管，
    所述第一晶体管的控制极与所述第一信号输入端耦接，所述第一晶体管的第一极与所述上拉节点耦接，所述第一晶体管的第二极与所述第一信号控制端耦接。
  6. 如权利要求1所述的移位寄存器单元，其中，所述第二输入电路包括第四晶体管，
    所述第四晶体管的控制极与所述第二信号输入端耦接，所述第四晶体管的第一极与所述第二信号控制端耦接，所述第四晶体管的第二极与所述上拉节点耦接。
  7. 如权利要求1所述的移位寄存器单元，其中，所述下拉控制电路包括第七晶体管、第九晶体管、第十晶体管和第二电容，
    所述第七晶体管的控制极和第二极与所述第一时钟信号输入端耦接，所述第七晶体管的第一极与所述下拉节点耦接；
    所述第九晶体管的控制极与所述上拉节点耦接，所述第九晶体管的第一极与所述第一电压端耦接，所述第九晶体管的第二极与所述下拉节点耦接；
    所述第十晶体管的控制极与所述信号输出端耦接，所述第十晶体管的第一极与所述第一电压端耦接，所述第十晶体管的第二极与所述下拉节点耦接；
    所述第二电容被耦接在所述下拉节点和所述第一电压端之间。
  8. 如权利要求1所述的移位寄存器单元，其中，所述输出电路包括第 十二晶体管和第一电容，
    所述第十二晶体管的控制极与所述上拉节点耦接，所述第十二晶体管的第一极与所述信号输出端耦接，所述第十二晶体管的第二极与所述第二时钟信号输入端耦接；
    所述第一电容被耦接在所述上拉节点和所述信号输出端之间。
  9. 如权利要求1所述的移位寄存器单元，其中，所述下拉电路包括第八晶体管和第十一晶体管，
    所述第八晶体管的控制极与所述下拉节点耦接，所述第八晶体管的第一极与所述第一电压端耦接，所述第八晶体管的第二极与所述上拉节点耦接；
    所述第十一晶体管的控制极与所述下拉节点耦接，所述第十一晶体管的第一极与所述第一电压端耦接，所述第十一晶体管的第二极与所述信号输出端耦接。
  10. 一种用于驱动如权利要求1至9中的任一项所述的移位寄存器单元的方法，包括：
    根据来自第一信号输入端的第一输入信号，使第一输入电路导通，以将来自第一信号控制端的第一控制信号提供给上拉节点，根据所述第一控制信号和来自第一时钟信号输入端的第一时钟信号，使控制电路导通，以将所述第一输入信号提供给所述上拉节点，根据所述上拉节点的电压，使输出电路导通，以将来自第二时钟信号输入端的第二时钟信号输出至信号输出端；
    维持所述上拉节点的电压，使所述输出电路保持导通，以将所述第二时钟信号输出至所述信号输出端，并且根据所述上拉节点的电压，通过下拉控制电路控制下拉节点的电压；
    根据来自第二信号输入端的第二输入信号，使第二输入电路导通，以将来自第二信号控制端的第二控制信号提供给所述上拉节点，使所述输出电路截止，并且根据所述第一时钟信号，将所述第一时钟信号提供给所述下拉节点，使下拉电路导通，以将第一电压端的电压提供给所述上拉节点 和所述信号输出端。
  11. 如权利要求10所述的方法，包括：
    根据所述第二输入信号，使第二输入电路导通，以将所述第二控制信号提供给所述上拉节点，根据所述第二控制信号和所述第一时钟信号，使所述控制电路导通，以将所述第一输入信号提供给所述上拉节点，根据所述上拉节点的电压，使所述输出电路导通，以将所述第二时钟信号输出至所述信号输出端；
    维持所述上拉节点的电压，使所述输出电路保持导通，以将所述第二时钟信号输出至所述信号输出端，并且根据所述上拉节点的电压，通过下拉控制电路控制下拉节点的电压；
    根据所述第一输入信号，使第一输入电路导通，以将所述第一控制信号提供给所述上拉节点，使所述输出电路截止，并且根据所述第一时钟信号，将所述第一时钟信号提供给所述下拉节点，使所述下拉电路导通，以将第一电压端的电压提供给所述上拉节点和所述信号输出端。
  12. 一种栅极驱动装置，包括：多个级联的移位寄存器单元，其中，每级移位寄存器单元是如权利要求1至9中的任一项所述的移位寄存器单元，
    其中，各级移位寄存器单元的信号输出端与下一级移位寄存器单元的第一信号输入端耦接，各级移位寄存器单元的第二信号输入端与下一级移位寄存器单元的信号输出端耦接。
  13. 一种阵列基板，包括如权利要求12所述的栅极驱动装置。
  14. 一种显示装置，包括如权利要求13所述的阵列基板。
  15. 一种电子设备，包括如权利要求14所述的显示装置。
PCT/CN2017/102243 2017-02-06 2017-09-19 移位寄存器单元及其驱动方法、栅极驱动装置 WO2018141158A1 (zh)

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