WO2018137529A1 - 一种数据传输的方法、装置、设备和系统 - Google Patents

一种数据传输的方法、装置、设备和系统 Download PDF

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Publication number
WO2018137529A1
WO2018137529A1 PCT/CN2018/073074 CN2018073074W WO2018137529A1 WO 2018137529 A1 WO2018137529 A1 WO 2018137529A1 CN 2018073074 W CN2018073074 W CN 2018073074W WO 2018137529 A1 WO2018137529 A1 WO 2018137529A1
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address
soc
processor
data
storage medium
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PCT/CN2018/073074
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English (en)
French (fr)
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陈昊
李思聪
陈亚军
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华为技术有限公司
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Priority to EP18744606.7A priority Critical patent/EP3561684A4/en
Priority to EP22174492.3A priority patent/EP4116832A1/en
Publication of WO2018137529A1 publication Critical patent/WO2018137529A1/zh
Priority to US16/523,771 priority patent/US10810135B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
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    • G06F2213/28—DMA

Definitions

  • Embodiments of the present invention relate to the field of storage, and in particular, to a method, an apparatus, a device, and a system for data transmission.
  • converged infrastructure refers to data centers such as servers, storage devices, network devices, and virtualization software.
  • the basic elements provide users with computing resources (such as CPU and memory), storage resources (such as disks), and network resources (such as network cards) in a pre-integrated manner to meet the business needs of users.
  • the data interaction mode of the converged infrastructure adopts a direct memory access (DMA) transmission mode, as shown in FIG. 1 , in the data transmission scheme shown in FIG. 1 : the processor needs to be written.
  • Data is written to the storage medium as an example: first, the processor sends a control instruction for instructing the SoC to move data to be written to the SoC to a system on chip (SoC); then, the DMA controller of the SoC according to the control instruction
  • the data to be written is moved from the double-rate synchronous dynamic random access memory (DDR) of the processor to the DDR of the SoC; secondly, the SoC sends a write data command to the storage medium, wherein, as shown in FIG.
  • DDR double-rate synchronous dynamic random access memory
  • the storage medium may be a non-Volatile Memory Express (NVMe) SSD, and then the SSD DMA controller moves the data to be written from the SoC DDR to a storage medium (such as SSD). in.
  • NVMe non-Volatile Memory Express
  • the process of the processor reading the data to be read in the storage medium is similar to the process of the processor writing the data to be written to the storage medium, and the DMA processing process is also required for one read operation process.
  • the present application provides a data transmission method, apparatus, device, and system for solving a data transmission in an existing converged infrastructure data interaction scenario, requiring high latency and transmission caused by two DMA movements of the SoC and the storage medium. Inefficient problem.
  • the present application provides a method for data transmission, the method being applied to a storage system including a processor, a system on chip SoC, and a storage medium, wherein the processor, the SoC, and the storage medium extend through the periphery
  • the component interconnects a high-speed PCIe bus communication, and the storage medium includes a direct memory access DMA controller.
  • the method includes: the SoC acquires a first request message including a first address and an operation type of the storage medium where the data to be operated is located, where the operation The type includes a read operation or a write operation, where the first address is the address that the processor allocates for the storage medium in the managed memory address; the SoC is according to the preset address mapping relationship according to the first The address determines a second address allocated by the storage medium in a memory address managed by the SoC; the SoC sends a first control instruction to the DMA controller of the storage medium, where the first control instruction is used to instruct the DMA controller to acquire the carrier a second request message of the second address and the operation type; when the operation type is a read operation, the SoC receives the first message sent by the DAM controller According to the first data, the DMA controller acquires according to the second address; then, the SoC sends the first data to the processor; when the operation type is a write operation, the SoC receives the second data sent by the processor, and the first The second data is sent to the
  • the present application provides a method for data transmission, because the SoC obtains a first request message from a processor by using a first control instruction, and converts a first address carried in the first request message into a second address, and then stores the target message.
  • the medium sending is used to obtain a second control instruction, where the second control instruction carries a second request message of the second address and the operation type. Therefore, during the transmission of the target data from the processor to the target storage medium, the SoC is responsible for converting the first address to the second address, and the first data to be read or the second data to be written in the processor and the storage. Forwarding between media, the data transfer process only requires the DMA controller of the storage medium to participate, and does not require the SoC's DMA controller to participate.
  • the embodiment of the present invention moves the first data or the second data between the processor and the storage medium only by the DMA controller of the storage medium, thereby avoiding the delay caused by the DMA controller that needs to pass through the SoC during data transmission. High and low transmission efficiency.
  • the method provided by the application further includes: the second control instruction sent by the SoC receiving processor, where the second control instruction carries a unique identifier An identifier of the first request message; acquiring the first request message according to the identifier of the first request message.
  • the determining, by the SoC, the second address according to the first address includes: acquiring, according to the first address, a second address corresponding to the first address from the preset address mapping table, where
  • the preset address mapping table includes a mapping relationship between an address allocated by the storage medium in a memory address managed by the processor and an address allocated by the storage medium in a memory address managed by the SoC; and the first address exists The address of the correspondence is determined as the second address of the storage medium. .
  • the SoC when the operation type is a read operation, receives the first data sent by the DAM controller; and sends the first data to the processor, including: the SoC receiving the DMA controller sends First data; mapping the second address of the storage medium to a first address according to a preset address mapping table; and forwarding the first data to the processor according to the first address.
  • the SoC receives a first interrupt sent by the DMA controller, where the first interrupt is used to indicate that the DMA controller has successfully transmitted the first data to the SoC; when the SoC determines that the SoC is in accordance with the first When the address successfully transmits the first data to the processor, the second interrupt is sent to the processor, and the second interrupt is used to instruct the SoC to successfully forward the first data to the processor.
  • the SoC when the operation type is a write operation request, receives the second data sent by the processor, and sends the second data to the DMA controller, triggering the DMA controller according to the Writing, by the second address, the second data to the storage medium comprises: the SoC receiving the second data sent by the processor; mapping the first address of the storage medium to the second address; and transmitting the second data to the DMA control according to the second address Device.
  • the SoC before the SoC receives the second data sent by the processor, the SoC receives the read request message sent by the DMA controller, where the read request message carries the second address; The second address in the read request message is mapped to the first address, and a third request message is generated, where the third request message is used to instruct the processor to send the data to be written to the SoC; and send a third request to the processor. Message.
  • the embodiment of the present application provides a storage system including a processor, a system-on-chip SoC, and a storage medium, and a high-speed PCIe bus communication, a storage medium, is interconnected between the processor, the SoC, and the storage medium by extending peripheral components.
  • a direct memory access DMA controller configured to send, to the SoC, a first control instruction for acquiring a first request message, the first control instruction carrying an identifier for uniquely identifying the first request message; the first request The message includes a first address and an operation type of the storage medium; the first address is an address allocated by the storage medium in a memory address managed by the processor; and the SoC is configured to receive the first control instruction sent by the processor Obtaining a first request message according to the first control instruction; determining a second address according to the first address, and generating a second request message, where the second address is an address allocated by the storage medium in a memory address managed by the SoC, The second request message carries the second address and the operation type; and sends the first control instruction to the DMA controller of the storage medium according to the second address
  • the first control instruction is used to instruct the DMA controller to acquire the second request message; when the operation type is the read operation, the first data sent by the DAM controller is received, and the first data is obtained by the DMA controller
  • the DMA controller of the storage medium is configured to receive a second control instruction, where the second control instruction carries an identifier for uniquely identifying the first request message; and acquiring the second request according to the second control instruction a message; when the operation type is a read operation, acquiring the first data according to the second address; transmitting the first data to the SoC; and when the operation type is the write operation, receiving the second data sent by the SoC, and according to the second address The second data is written to the storage medium.
  • the present application provides a system-on-a-chip (SoC) including various modules for performing a fault processing method in the first aspect or any of the possible implementations of the first aspect.
  • SoC system-on-a-chip
  • the present application provides a system-on-a-chip (SoC) including a processor, a memory, a communication interface, and a bus.
  • SoC system-on-a-chip
  • the processor, the memory, and the communication interface are connected by a bus and complete communication with each other, and the memory is used for storage.
  • the computer executes instructions that, when the SoC is running, execute a method in which the computer in the memory executes instructions to utilize the hardware resources in the SoC to perform the data transfer described in any one of the first aspect and the first aspect.
  • the present application provides a readable storage medium having stored therein instructions that, when run on a computer, are computers that perform the methods described in the above aspects.
  • the present application may further combine to provide more implementations.
  • FIG. 2a is a structural diagram of a storage system according to an embodiment of the present invention.
  • FIG. 2b is a structural diagram of another storage system according to an embodiment of the present invention.
  • FIG. 3 is a schematic flowchart of a data transmission method according to an embodiment of the present disclosure
  • FIG. 4 is a schematic flowchart of another data transmission method according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic flowchart of another data transmission method according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of another data transmission method when a read operation request is provided according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of another data transmission method when a write operation request is provided according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a storage system according to an embodiment of the present disclosure.
  • FIG. 8b is a schematic structural diagram of another storage system according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a system on chip according to an embodiment of the present disclosure.
  • 9b is a schematic structural diagram of another system on a chip according to an embodiment of the present invention.
  • 9c is a schematic structural diagram of another system on a chip according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a hardware structure of a system on chip according to an embodiment of the present invention.
  • FIG. 2a is a structural diagram of a storage system to which a method for data transmission according to an embodiment of the present invention is applied.
  • the storage system includes a processor 201, a system on chip (SoC) 202, and a storage medium 203, wherein the processor and the SoC are configured with double rate synchronous dynamic random access memory (Double Data Rate, DDR), not shown in FIG. 2a, the processor 201, the system on chip 202, the DDR 204, and the storage medium 203 are connected by a Peripheral Component Interconnect Express (PCIe) bus, and the processor 201 includes a root complex.
  • PCIe Peripheral Component Interconnect Express
  • Root complex RC is a management module for managing access devices in the PCIe bus.
  • the root complex is connected to the SoC through a root port (RP), and the SoC is used as an endpoint device of the processor 201 (end) Point, EP)
  • the SoC runs a redundant arrays of independent disks (RAID) controller for managing the storage medium 203.
  • the storage medium 203 is used to store data to be read or data to be written.
  • processors 201 in FIG. 2a may be one or more, and the number of storage media 203 may be one or more.
  • each PCIe bus requires a unique bus number identifier, and each PCIe structure is limited by a limited resource.
  • the PCIe bus structure supports up to 256 bus numbers.
  • an endpoint root complex can be established in an endpoint device (for example, a SoC).
  • the endpoint root complex is a management module for managing access devices that access the extended PCIe structure in the extended PCIe structure, and the SoC passes the endpoint root.
  • the RP of the complex is connected to the storage medium 203, and each storage medium 203 is connected to the PCIe bus as an endpoint device in the extended PCIe structure, thereby expanding the number of endpoint devices in the PCIe structure.
  • the storage medium 203 may be a non-volatile memory express (NVMe) solid state disk (SSD), or may be other types of storage media.
  • NVMe non-volatile memory express
  • SSD solid state disk
  • Each storage medium 203 runs a direct memory access (DMA) controller, and the DMA controller directly moves the data to be read from the storage medium to the DDR corresponding to the processor without processing.
  • DMA direct memory access
  • the root complex of processor 201 also maps various connected devices (including storage locations of the devices, such as registers and storage locations) onto the PCIe storage space, i.e., into system memory. These types of mapping and storage spaces are referred to as memory mapped input/output (MMIO) spaces.
  • MMIO memory mapped input/output
  • the endpoint root complex in the SoC also maps the devices it connects (such as registers, storage media) to the PCIe storage space.
  • the memory space managed by the root complex of the processor 201 and the memory space managed by the endpoint root complex of the SoC are independent of each other, and there is a preset address mapping relationship between the two, and the preset address mapping relationship is stored in the In the SoC, when the processor receives the read operation request message or the write operation request message, the root complex of the processor may determine the storage location of the storage medium according to the address information carried in the request message, and then be composited by the endpoint root of the SoC.
  • the preset address mapping relationship determining the address information of the storage medium in the memory managed by the storage medium, that is, the storage location of the storage medium in the PCIe structure of the endpoint root complex of the SoC; finally, the DMA control of the storage medium The device performs data processing.
  • the memory space managed by the processor 201 is 8 TB, the address of the memory space is 00000000000-7fffffffff (equivalent to 0TB-8TB), and the processor 201 is allocated by the SoC 202 in the memory space managed by the processor 201.
  • the memory size is 4TB, and the address of the 4TB memory allocated by the processor 201 for the SoC202 is 3fffffffff-7ffffffffffffffff (equivalent to from 4TB-8TB).
  • the memory space managed by the SoC202 is 6TB, and the address of the memory space managed by the SoC is 00000000000-5ffffffffffff (equivalent to 0TB-6TB).
  • the memory allocated by the storage medium 203 in the memory space of the SoC202 is also 4TB, and the address is 1fffffffff. -5fffffffff (equivalent to from 2TB-6TB). Therefore, if the storage medium 203 is mapped to 4TB in the SoC 202 to the 4TB of the processor 201, an address mapping conversion is required, and the 1fffffffff address of the SoC 202 is mapped to the 3fffffffff address of the processor 201.
  • a request queue (SQ) and a completion queue (CQ) are stored in the processor 201, the SoC 202, and the storage medium 203.
  • the request queue is configured to store a read operation request message or a write operation request message to be processed, and the CQ is configured to store the completed read operation request message or the write operation request message.
  • the SQ of the processor 201 stores a read operation request message or a write operation request message to be processed by the processor 201
  • the CQ stores a read operation request message or a write operation request message that has been completed by the processor 201.
  • the read operation request message or the write operation request message stored in the SQ and the CQ of the processor 201 carries a first address, where the first address is a storage medium storing data to be read or to be written.
  • the write operation request message carries a second address in the read operation request message or the write operation request message stored in the SQ and the CQ of the SoC, where the second address is a storage for storing data to be read or to be written.
  • FIG. 2b is a structural diagram of a storage system to which a data transmission method according to another embodiment of the present invention is applied.
  • the processor 201, the SoC 202, and the storage medium 203 are shown in FIG. 2b and FIG. 2a.
  • the functions are the same, and the application will not be repeated here.
  • 2b differs from FIG. 2a in that, in FIG. 2a, each storage medium 203 is used as an EP, and is directly connected to the PCIe bus through one RP in the SoC.
  • the SoC 202 is connected to the storage medium 203 through a PCIe switch.
  • the PCIe switch chip 204 includes at least one uplink port and at least one downlink port.
  • the uplink port of the PCIe switch chip 204 is used for connecting with the RP in the SoC 202, and the downlink port is used for connecting to the storage medium 203.
  • the uplink port is a port that points to the root complex, and the downlink port is a port that is far from the root complex. It is only shown in Figure 2b that the root complex includes a root port, it being understood that the root complex includes multiple root ports (e.g., between four to six root ports) during actual use.
  • processors 201 in FIG. 2a may be one or more, and the number of storage media 203 may be one or more.
  • the storage architecture applied in the embodiment of the present invention is connected to the storage medium through the PCIe switch chip 204 as shown in FIG. 2b, and the storage medium may be externally connected through the interface card.
  • the storage architecture shown in FIG. 2b may be an application.
  • NVMe of fabric, NoF network-based non-volatile memory
  • the storage system architecture shown in FIG. 2a and FIG. 2b in the embodiment of the present invention may be a storage array, wherein the storage array includes a controller and a disk enclosure, the controller runs in the processor 201, and the storage medium 203 may be stored and stored.
  • the controller of the array is a hard disk device in the same physical device. It can also be connected to the storage array of the physical device where the controller resides.
  • the storage array also includes a RAID controller.
  • the RAID controller runs in the SoC202. It is used to manage the RAID relationship of storage media in the storage array.
  • the storage system architecture shown in FIG. 2a and FIG. 2b in the embodiment of the present invention may also be a server, where the server includes a processor 201, a SoC 202, and a storage medium 203.
  • any one of the storage media 203 in the embodiment of the present invention may receive a read operation request message or a write operation request message sent by one or more processors 201 through the SoC 202, and one or more The data requested to be written in the write operation request message transmitted by the processor 201 is stored in the storage medium 203.
  • any storage medium 203 may also return the data to be read by the processor 201 from the storage medium 203 to the processor 201 according to the read operation request message sent by the processor 201, and store it in the DDR20 of the processor 201. .
  • FIG. 3 is applied to the storage system shown in FIG. 2a or FIG. 2b, as shown in FIG. Methods.
  • the processor sends a second control instruction to the SoC.
  • the second control instruction is used to instruct the SoC to obtain a first request message from a request queue of the processor, where the first request message includes a first address and an operation type of the storage medium, where the storage medium is used to store the to-be-read The data fetched or written, the first address being an address allocated by the storage medium in a memory address managed by the processor, the operation type including a read operation or a write operation.
  • the second control instruction includes a first identifier, where the first identifier is used to uniquely identify a first request message.
  • the request queue stored in the processor includes at least one request message, and each request message indicates a read operation request message or a write operation request message to be processed by one processor, and each request message corresponds to one identifier.
  • the unique identifier of the first request message 1 is 1001
  • the unique identifier of the first request message 2 is 1002
  • the unique identifier of the first request message 3 is 1003.
  • the SoC obtains a request corresponding to 1001 from the request queue of the processor according to the identifier. Message 1.
  • the SoC receives a second control instruction sent by the processor.
  • the SoC acquires the first request message from the request queue of the processor according to the second control instruction.
  • the second control instruction carries the first identifier of the first request message
  • the SoC obtains the first request that is corresponding to the first identifier from the request queue of the processor according to the first identifier of the first request message. Message.
  • the SoC obtains a corresponding relationship with the first identifier from the SQ queue according to the first identifier. After the first request message, the storage space at the storage location where the first request message is located will be vacated. When the processor generates a new first request message, the processor may store the newly generated first request message on the emptied storage location.
  • the SoC determines a second address of the storage medium according to the first address, and generates a second request message.
  • the second address is an address allocated by the storage medium in a memory address managed by the SoC.
  • the second request message carries a second address and an operation type
  • the second request message is corresponding to a second identifier, where the second request message is used to indicate that the DMA controller of the storage medium is to be the second type according to the operation type.
  • the storage medium corresponding to the address performs a read operation or a write operation.
  • the type of operation carried in the second request message is consistent with the type of operation carried in the first request message. For example, if the type of operation carried in the first request message is a write operation, the type of operation carried in the second request message is also a write operation. If the type of operation carried in the first request message is a read operation, the type of operation carried in the second request message is also a read operation.
  • step S304 in the embodiment of the present invention may be implemented in the following manner:
  • the SoC obtains, according to the first address, a second address that has a correspondence with the first address from the preset address mapping table.
  • the preset address mapping table includes a mapping relationship between the first address and the second address.
  • the SoC stores a preset address mapping table, where a specific mapping rule of the first address and the second address is established, and the SoC can determine the mapping with the first address by using the mapping rule.
  • a second address of the relationship wherein the first address is an address allocated by the storage medium in a memory address managed by the processor, and the second address is an address allocated by the storage medium to be operated in a memory address managed by the SoC.
  • the address obtained by the SoC from the first request message obtained by the request queue of the processor is recorded as the first address, and if the first address carried in the first request message is 10001, the SoC can pass the pre-
  • the address mapping table determines that the second address that has a mapping relationship with the first address 10001 is 2000002.
  • the SoC stores the second request message in a request queue of the SoC.
  • the SoC sends a first control instruction to the DMA controller of the storage medium, where the first control instruction is used to instruct the DMA controller of the storage medium to obtain a second request message from a request queue of the SoC.
  • the first control instruction carries a second identifier, where the second identifier is used to uniquely identify the second request message stored in the request queue of the SoC.
  • the second identifier in the embodiment of the present invention may be an identifier that can uniquely identify a second request message, such as a letter or a number, which is not limited by the embodiment of the present invention.
  • the SoC request queue includes one or more storage locations, and each of the one or more storage locations is used to store a second request message, that is, one or more stored in the SoC request queue. a second request message, each of the one or more second request messages carrying a second address and an operation type, each second request message corresponding to a second identifier uniquely identifying the second request message .
  • Table 3 the unique identifier of the second request message 1 is 101, the unique identifier of the second request message 2 is 102, and the unique identifier of the second request message 3 is 103.
  • Second logo Second request message 101 Second request message 1 102 Second request message 2 103 Second request message 3
  • the second control instruction is used to indicate that the DMA controller of the storage medium acquires the corresponding identifier of the second identifier 101 from the request queue of the SoC.
  • the second request message 1 of the relationship is exemplary, when the second identifier carried in the first control instruction is 101, the second control instruction is used to indicate that the DMA controller of the storage medium acquires the corresponding identifier of the second identifier 101 from the request queue of the SoC.
  • the second request message 1 of the relationship is
  • the DMA controller of the storage medium acquires the second request message from the request queue of the SoC according to the first control instruction, the storage space at the storage location where the second request message is located will be empty.
  • the SoC can store the new second request message in the vacated storage location.
  • the DMA controller of the storage medium acquires a second request message according to the first control instruction, and processes the data according to an operation type carried in the second request message.
  • the DMA controller of the storage medium acquires a second request message that the second identifier has a corresponding relationship from the request queue of the SoC according to the second identifier carried in the first control instruction.
  • the operation type of the second request message may be a read operation, or may be a write operation, but different operation types are different in the specific implementation process, the following will respectively combine the operation type as a read operation request and the operation type is
  • the two implementations of the write operation request detail the specific implementation process of step S307:
  • step S307 can be implemented by:
  • the DMA controller of the storage medium acquires a second address corresponding to the first data stored in the storage medium, where the first data is data to be read stored in the storage medium.
  • the DMA controller of the storage medium sends the first data to the SoC in a DMA memory access manner, and then executes S3081.
  • step S307 can be implemented in the following manner:
  • the DMA controller of the storage medium sends a read request message to the SoC, where the read request message carries a second address, where the read request message is used to indicate that the second request is obtained.
  • Data wherein the second data is data to be written to the storage medium.
  • the DMA controller of the storage medium acquires the second data from the processor in a DMA memory access manner, and then executes S3082.
  • the method further includes:
  • the embodiment of the present invention provides a data transmission method, in which the SoC obtains a first request message from a processor by using a first control instruction, and converts the first address carried in the first request message, and then sends the target address to the target storage medium. Sending a second control instruction to cause the target storage medium to acquire the second request message according to the second control instruction. Therefore, during the transmission of the first data or the second data from the processor to the storage medium, the SoC is responsible for converting the first address to the second address, and forwarding the first data or the second data between the processor and the storage medium. And moving the first data or the second data from the processor to the storage medium requires only the DMA controller of the storage medium to participate, and does not require the DMA controller of the SoC to participate.
  • the embodiment of the present invention moves the first data or the second data between the processor and the storage medium only by the DMA controller of the storage medium, thereby avoiding the need for the DMA controller of the SoC to perform forwarding when the data is transmitted. High latency and low transmission efficiency.
  • the operation type of the first request message acquired by the SoC from the SQ of the processor may be a read operation, or may be a write operation
  • a request message of a different operation type may be different in a specific implementation process. Therefore, the interaction between the SoC and the processor and the target storage medium, respectively, when the operation type is a read operation request or a write operation request will be described in detail below.
  • the present application only passes the operation when the operation type is a read operation.
  • a DMA controller of the storage medium moves the first data to be read from the storage medium to the processor; when the operation type is a write operation, the DMA controller only through the storage medium will be the second to be written Data is transferred from the processor to the storage medium.
  • the second data is transferred from the storage medium to the processor, the second data is transmitted only through the internal bus of the SoC, and the DMA controller of the SoC is not required to participate in the movement. Therefore, the delay can be avoided.
  • FIG. 4 is a data transmission process when the operation type is a read operation, and the difference between FIG. 4 and FIG. 3 is that S301 is executed.
  • the steps in the embodiment of the present invention further include: S307a.
  • the data transmission process of step S308 is described in detail in FIG. 4, and the process of steps S301-S307 can be referred to FIG. 3, and details are not described herein again.
  • the method provided by the embodiment of the present invention includes:
  • the DMA controller of the storage medium sends the first data to the SoC in a DMA memory access manner.
  • step S3081 may further include:
  • the SoC receives the first data sent by the DMA controller of the storage medium in a DMA memory access manner.
  • the SoC maps the second address of the storage medium to a first address.
  • the SoC may map the address of the target data from the second address to the first address by using a preset address mapping table as shown in Table 2.
  • the SoC forwards the first data to the processor.
  • the method provided by the embodiment of the present invention further includes:
  • S3083a1 The SoC receives a first interrupt sent by the DMA controller of the storage medium, where the first interrupt is used to indicate that the DMA controller has successfully transmitted the first data to the SoC.
  • the method for the DMA controller of the storage medium to determine that the first data is successfully forwarded to the processor can be understood as: the amount of data sent by the SoC to the processor is equal to the size of the first data. That is, if the size of the first data is A, if the SoC determines that the size of the first data that has been forwarded to the processor is also A, it is determined that the target data is successfully forwarded.
  • the DMA controller of the storage medium may also record the size and the check value of the first data, record and transmit the location information of the first data by using a pointer, and calculate a check value of the first data that has been sent, when calculating When the obtained check value of the transmitted first data is equal to the recorded check value, it is determined that the first data transmission is successful.
  • S3083a2 When the SoC determines that the SoC successfully transmits the first data to the processor, sends a second interrupt to the processor, where the second interrupt is used to instruct the SoC to successfully forward the first data to the processor. .
  • the DMA controller of the storage medium sends the first data to the memory of the SoC in a DMA memory access manner, and the SoC sends the first data to the processor through the PCIe bus.
  • FIG. 5 is a data transmission process when the operation type is a write operation request, and the difference between FIG. 5 and FIG. 3 is that 5, the specific implementation process of the step S308 is specifically described in the case where the operation request is a write operation request, and the process of the steps S301-S307 can be referred to FIG. 3, and details are not described herein again.
  • the method provided by the embodiment of the present invention includes:
  • the DMA controller of the storage medium sends a read request message to the SoC, where the read request message carries a second address.
  • the read request message is used to instruct the processor to send the second data to be written to the SoC.
  • the SoC receives a read request message sent by the DMA controller of the storage medium.
  • S3082b The SoC maps the second address in the read request message to the first address, and generates a third request message, where the third request message is used to instruct the processor to send the second data.
  • the SoC sends a third request message to the processor.
  • the processor sends the second data to the SoC according to the third request message.
  • the SoC receives the second data sent by the processor.
  • the SoC converts the address of the target data from the first address to the second address.
  • the SoC may convert the address of the target data from the first address to the second address by using the preset address mapping table shown in Table 2 above.
  • the SoC sends the second data to the DMA controller of the storage medium according to the second address, the DMA controller that triggers the storage medium acquires the second data in a DMA memory access manner, and stores the second data to the In the storage medium.
  • the SoC After receiving the read request message, and mapping the second address in the read request message to the first address, the SoC generates a third request message, and sends a third request message to the processor, where the processor receives the After the third request message, the second data is obtained from the memory of the processor, and the second data is sent to the SoC, and then the SoC maps the address of the storage medium to be stored by the second data from the first address to After the second address, finally, the DMA controller of the storage medium moves the second data from the SoC to the storage medium in a DMA memory access manner.
  • FIG. 6 is a schematic structural diagram of a data transmission in a scenario of a read operation request scenario, where the processor includes a processor for the storage system. Processing operations are performed by a read operation or a write operation of the processor.
  • the SoC further includes a memory address management unit, a redirection unit, a memory address management unit, and a redirection unit, which are computer programs running on the processor, and the memory address management unit is used for The address of the data to be read or to be written is mapped, and the redirection unit is configured to implement a sequence function on the processing of the read operation request, thereby achieving consistency of the storage system.
  • the data transmission method includes:
  • the processor sends a second control instruction to the SoC, where the second control instruction is used to instruct the SoC to acquire the first address read operation instruction (that is, the first request message described in the foregoing embodiment) from the request queue of the processor. .
  • the SoC acquires, according to the second control instruction, a read operation instruction that carries the first address from the request queue of the processor, and maps the first address in the read operation instruction to the second address to generate the first The second address and the second request message of the read operation instruction, and the second request message is stored in the request queue of the SoC.
  • the SoC sends a first control instruction to the storage medium, where the first control instruction is used to indicate that the DMA controller of the storage medium to be read or written data acquires the second request message from the request queue of the SoC.
  • the DMA controller of the storage medium reads the first data from the storage medium according to the second address, where the first data is data to be read stored in the storage medium.
  • the DMA controller of the storage medium sends the first data to the SoC through a transmission link in a DMA memory access manner.
  • the DMA controller of the storage medium writes a read operation instruction that has completed the second address to the CQ of the SoC, and sends a first interrupt to the CPU of the SoC.
  • the SoC After receiving the first interrupt, the SoC obtains the completed first data read operation instruction from the completion queue of the SoC.
  • the SoC determines that the first data is completely forwarded to the processor
  • the first interrupt received by the SoC is processed, and then the second interrupt is sent to the processor, so that the processing can be guaranteed.
  • the first data in the storage medium is read, the first data must arrive at the processor before the second interrupt.
  • the step can be implemented by using a redirection unit running in the SoC. If the redirection unit is not running in the SoC, the SoC will immediately send a second interrupt to the processor after receiving the first interrupt.
  • step 707a of 6 there is a case where the second interrupt is returned to the processor earlier than the target data, thereby causing processor side consistency to be unguaranteed and data loss is avoided.
  • the SoC maps the address of the storage medium from the second address to the first address, and then forwards the first data to the processor through the PCIe bus.
  • the SoC maps the second address to the first address, and acquires a new write-back instruction, where the new write-back instruction is used to indicate that the read operation instruction of the first data has been completed.
  • the SoC determines that the first data has been completely forwarded to the processor, and writes the read operation instruction of the completed first address into the completion queue of the processor, and sends a second interrupt to the processor.
  • the processor After receiving the second interrupt, the processor reads the read operation instruction that has completed the first address from the completion queue of the processor, thereby determining that the first data has been successfully read from the storage medium.
  • FIG. 7 shows a data transmission architecture diagram of an operation type in a write operation request scenario according to an embodiment of the present invention.
  • the data transmission method includes:
  • the processor sends a second control instruction to the SoC, where the second control instruction is used to instruct the SoC to acquire a carry operation instruction from the request queue of the processor, where the write operation instruction is used to indicate the first in the processor memory.
  • Two data is written into the storage medium.
  • the SoC acquires a write operation instruction from a request queue of the processor, and maps a first address of the storage medium to be written in the write operation instruction to a second address, and is in a request queue of the SoC. A second request message carrying the second address and the type of operation is generated.
  • the SoC sends a first control instruction to the DMA controller of the storage medium, where the first control instruction is used to instruct the DMA controller of the storage medium to acquire the second address and the operation type from the request queue of the SoC. Two request messages.
  • the DMA controller of the storage medium acquires a second request message carrying a second address and an operation type from a request queue of the SoC according to the first control instruction.
  • the storage medium processes the second request message that is acquired in the request queue of the SoC and carries the second address and the operation type, and generates a read request message, where the request message includes the second address and the operation type. And storing the read request message into a request queue of the storage medium.
  • the DMA controller of the storage medium sends a read request message carrying a second address and an operation type to the SoC.
  • the SoC maps the second address in the read request message carrying the second address and the operation type to the first address.
  • the SoC sends the read request message after the first address to the processor by using the PCIe bus.
  • the processor After receiving the read request message carrying the first address, the processor sends the second data and the first address to the SoC.
  • the SoC maps the first address to the second address, and then sends the second data to the DMA controller of the storage medium according to the second address.
  • the DMA controller of the storage medium moves the second data from the SoC to the storage medium.
  • the DMA controller of the storage medium writes an instruction that the second data is written to the storage medium to the CQ of the SoC, and sends a first interrupt to the SoC.
  • the SoC After receiving the first interrupt, the SoC acquires an instruction that the second data is written into the storage medium from the CQ of the SoC.
  • the SoC will map the second address to the first address to obtain a new CQ writeback instruction.
  • the SoC writes a new CQ writeback instruction into the CQ of the processor, and sends a second interrupt to the processor.
  • steps S811-S814 may be omitted.
  • the processor reads data in the storage medium through the SoC or writes data to the storage medium through the SoC, and uninstalls functions such as RAID.
  • the data exchange between the processor and the storage medium is straight through (that is, the processor is directly connected to the storage device), and the data no longer needs to be copied to the DDR of the SoC and directly moved to the storage medium.
  • the following process is performed when the storage medium is an SSD. For further explanation, take an example:
  • the processor In the RAID0 mode, the processor only needs one DMA operation to read/write the target data.
  • the data is directly connected between the processor and the SSD, and no calculation is performed, and a pure data copy is performed.
  • the processor In the RAID1 mode, the processor only needs one DMA operation to read/write the target data, and the data is directly connected between the processor and the SSD.
  • the processor only needs one DMA operation to read/write the target data, and the data is directly connected between the HOST and the SSD.
  • the data transmission method provided by the embodiment of the present invention may be in a RAID mode (not limited to the foregoing cases) in which the SoC does not participate in the calculation, and the SoC only needs to map the first address in the read or write operation request sent by the processor to The second address, or the second address is mapped to the first address, so that the DMA controller of the storage medium can recognize. Therefore, in the transmission between the storage medium and the processor, the SoC only completes the processing of the requested processing, forwarding, and address, and the data is moved from the processor to the storage medium or from the storage medium to the processor, only by the storage medium.
  • the DMA controller does not require the SoC's DMA controller to participate in the move, which increases bandwidth utilization and the SoC does not participate in DMA move, thus avoiding SoC performance bottlenecks. Furthermore, the IOPS (input/output per second) capability can be stacked by SSD line type, which significantly improves the performance of the storage system.
  • FIG. 8a is a schematic structural diagram of a storage system according to an embodiment of the present invention.
  • the storage system shown in FIG. 8a is a storage array.
  • the storage system 20 can include a processor 201, a system on chip 202, a storage medium 203, a communication interface 206, and a memory 207, wherein the processor 201, the system on chip 202, the storage medium 203, the communication interface 206, and the memory 207 is connected by a communication bus 204.
  • the processor 201 includes a controller, and the system on chip 202 includes a RAID controller.
  • the storage medium 203 includes a DMA controller.
  • the storage medium 203 may be the same physical device as the processor 201.
  • One or more storage media may also be one or more storage media connected to the physical device where the controller is located through the disk enclosure 205.
  • the processor configured to send, to the SoC, a first control instruction for acquiring a first request message, where the first control instruction carries an identifier for uniquely identifying the first request message; the first request The message includes a first address and an operation type of the storage medium; the first address is an address assigned by the processor to the storage medium in the managed memory address.
  • the SoC is configured to receive the first control instruction sent by the processor, and acquire the first request message according to the first control instruction; determine a second address according to the first address, and generate a first a second request message, the second address is an address that the SoC is allocated to the storage medium in the managed memory address, and the second request message carries the second address and the operation type; Transmitting, by the second address, a first control instruction to the DMA controller of the storage medium, where the first control instruction is used to instruct the DMA controller to acquire a second request message; when the operation type is a read operation, Receiving first data sent by the DAM controller, the first data is obtained by the DMA controller according to the second address; the first data is sent to the processor; when the operation type is write Receiving, in operation, receiving second data sent by the processor, and transmitting the second data to the DMA controller, triggering the DMA controller to write the second data according to the second address The storage medium .
  • a DMA controller of the storage medium configured to receive a second control instruction, where the second control instruction carries an identifier for uniquely identifying the first request message; and acquiring a second request message according to the second control instruction And when the operation type is a read operation, acquiring the first data according to the second address; transmitting the first data to the SoC; and when the operation type is a write operation, receiving the The second data sent by the SoC, and the second data is written to the storage medium according to the second address.
  • the communication interface 206 is used for communication between the storage system and other devices.
  • the memory 207 is for storing a program
  • the memory 206 may include a high speed RAM memory, and may also include a non-volatile memory (English name: non-volatile memory), for example, at least one disk memory. It can be understood that the memory can be a non-transitory machine readable medium that can store program code, such as random-access memory (RAM), hard disk, optical disk, SSD, or non-volatile memory. .
  • RAM random-access memory
  • SSD or non-volatile memory.
  • the processor 201 can be a CPU, and the processor 201 can also be other general purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs), or other programmable logic devices, discrete. Gate or transistor logic, discrete hardware components, etc.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like. The processor is configured to perform the operation steps performed by the processor in FIG. 3 to FIG. 7 in the foregoing embodiment as an execution subject.
  • the DMA controller of the storage medium is used to execute the operation steps of the DMA controller of the storage medium in FIGS. 3 to 7 in the above embodiment as the execution subject.
  • processors in FIG. 8a may be one or more, and the number of storage media may be one or more.
  • FIG. 8b is a schematic structural diagram of another storage system 20 according to an embodiment of the present invention.
  • the storage system shown in FIG. 8b is a storage device, such as a server.
  • the difference between FIG. 8b and FIG. 8a is that, in FIG. 8b, there is no controller in the processor 201, and there is no RAID controller in the SoC.
  • the functions of the respective hardware structures shown in FIG. 8b are the same as those in FIG. 8a.
  • the hardware structure shown in the figure is the same, and details are not described herein again.
  • the storage system shown in FIG. 8a is a schematic structural diagram when the storage system shown in FIG. 2a is a storage array
  • the storage system shown in FIG. 2b is a schematic structural diagram when the storage system shown in FIG. 2a is a storage device.
  • the solution provided by the embodiment of the present invention is mainly introduced from the perspective of the SoC. It can be understood that, in order to implement the above functions, the SoC and the like include hardware structures and/or software modules corresponding to the execution of the respective functions.
  • the present invention can be implemented in a combination of hardware or hardware and computer software in combination with the elements and algorithm steps of the various examples described in the embodiments disclosed herein. Whether a function is implemented in hardware or computer software to drive hardware depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods for implementing the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present invention.
  • the embodiments of the present invention may divide the function modules of the SoC or the like according to the foregoing method examples.
  • each function module may be divided according to each function, or two or more functions may be integrated into one processing module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of the module in the embodiment of the present invention is schematic, and is only a logical function division, and the actual implementation may have another division manner.
  • FIG. 9a shows a possible structural diagram of the SoC involved in the foregoing embodiment, and the SoC1 includes an obtaining unit 10, an address management unit 11, and a transmitting unit 12, in the case where the respective functional modules are divided by the respective functions.
  • the obtaining unit 10 is configured to acquire a first request message, where the first request message includes a first address and an operation type of the storage medium, and the operation type includes a read operation or a write operation, where the first The address is an address allocated by the processor to the storage medium in the managed memory address; when the operation type is a read operation, the SoC receives the first data sent by the DAM controller, The first data is acquired by the DMA controller according to the second address; when the operation type is a write operation, the second data sent by the processor is received.
  • the address management unit 11 is configured to determine, by the first address, a second address of the storage medium, and generate a second request message, where the second address is that the SoC is the storage medium in the managed memory address At the assigned address, the second request message carries the second address and the type of operation.
  • the sending unit 12 is configured to send, according to the second address, a first control instruction to the DMA controller of the storage medium, where the first control instruction is used to instruct the DMA controller to acquire a second request message; Transmitting the first data by the processor; transmitting the second data to the DMA controller, triggering the DMA controller to write the second data to the storage medium according to the second address.
  • the SoC in the embodiment of the present invention further includes a receiving unit 13 configured to receive a second control command sent by the processor, where the second control command carries a unique identifier for carrying Determining an identifier of the first request message; acquiring the first request message according to the identifier of the first request message.
  • the address management unit 11 in the SoC in the embodiment of the present invention determines the second address according to the first address, and includes:
  • the preset address mapping table includes at least the storage medium in the processor a mapping relationship between an address allocated in the managed memory address and an address allocated by the storage medium in a memory address managed by the SoC; determining an address corresponding to the first address as the first of the storage medium Two addresses.
  • the receiving unit 13 in the SoC in the embodiment of the present invention is further configured to: when the operation type is a read operation request, receive the first data sent by the DMA controller;
  • the address management unit 11 is further configured to map the second address of the storage medium to the first address according to a preset address mapping table.
  • the sending unit 12 is further configured to forward the first data to the processor according to the first address.
  • the SoC in the embodiment of the present invention further includes a redirecting unit 14 as shown in FIG. 9c;
  • the receiving unit 13 is further configured to receive a first interrupt sent by the DMA controller, where the first interrupt is used to indicate that the DMA controller has successfully transmitted the first data to the SoC.
  • the redirecting unit 14 is configured to: when the SoC determines that the SoC successfully transmits the first data to the processor according to the first address, send a second interrupt to the processor, the second The interrupt is for instructing the SoC to successfully forward the first data to the processor.
  • the receiving unit 13 in the embodiment of the present invention is further configured to: when the operation type is a write operation request, the second data sent by the processor.
  • the address management unit 11 is further configured to map the first address of the storage medium to the second address.
  • the sending unit 12 is further configured to send the second data to the DMA controller according to the second address.
  • the receiving unit 13 is further configured to: before receiving the second data sent by the processor, receive a read request message sent by the DMA controller, where the read request message carries the second address.
  • the address management unit 11 is further configured to map the second address in the read request message to the first address, and generate a third request message, where the third request message is used to indicate that the processor is The SoC sends the second data.
  • the sending unit 12 is further configured to send the third request message to the processor.
  • the SoC1 in FIG. 9a may correspond to performing the method described in the embodiments of the present invention, and the above and other operations and/or functions of the respective units in the SoC1 are respectively implemented to implement the respective methods in FIGS. 3 to 7.
  • the corresponding process of the SoC as the execution subject is not repeated here for the sake of brevity.
  • FIG. 9d is a schematic diagram of a hardware structure of a SoC according to an embodiment of the present invention.
  • the SoC includes a processor 901, a memory 902, a communication interface 903, a bus 904, a processor 901, a memory 902, and a communication interface 903. They are connected by bus 904 and communicate with each other.
  • the memory 902 is used to store computer execution instructions.
  • the processor 901 executes the computer execution instructions in the memory 902 to perform the following steps by using hardware resources in the SoC:
  • the first request message includes a first address and an operation type of the storage medium, the operation type includes a read operation or a write operation, and the first address is that the processor is in the The address assigned to the storage medium in the managed memory address;
  • the second request message carries the second address and the type of operation
  • the processor 901 can be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), and a field.
  • the processor may also be a combination of computing functions, for example, including one or more microprocessor combinations, a combination of a DSP and a microprocessor, and the like.
  • the bus 904 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus.
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • the bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 9d, but it does not mean that there is only one bus or one type of bus.
  • the SoC according to the embodiment of the present invention corresponds to the functional device of the SoC in FIG. 9b provided by the embodiment of the present invention, and the SoC is used to implement the corresponding process of the method shown in FIG. 3 to FIG. Let me repeat.
  • the above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination.
  • software When implemented in software, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded or executed on a computer, the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be wired from a website site, computer, server or data center (for example, infrared, wireless, microwave, etc.) to another website site, computer, server or data center.
  • the computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that contains one or more sets of available media.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state hard disk SSD) or the like.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the modules or units is only a logical function division.
  • there may be another division manner for example, multiple units or components may be used. Combinations can be integrated into another system, or some features can be ignored or not executed.
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Abstract

一种数据传输的方法、装置、设备和系统，该方法包括：SoC(202)获取第一请求消息，第一请求消息包括存储介质(203)的第一地址和操作类型，第一地址为处理器(201)在所管理的内存地址中为存储介质(203)分配的地址；根据第一地址确定第二地址，并生成第二请求消息，第二地址为SoC(202)在所管理的内存地址中为存储介质(203)分配的地址；根据第二地址向存储介质(203)的DMA控制器发送第一控制指令，第一控制指令用于指示DMA控制器获取第二请求消息；当为读取操作时，接收所述DAM控制器发送的第一数据；向处理器(201)发送所述第一数据；当为写入操作时，接收处理器(201)发送的第二数据，并将第二数据发送给所述DMA控制器。

Description

一种数据传输的方法、装置、设备和系统 技术领域
本发明实施例涉及存储领域，尤其涉及一种数据传输的方法、装置、设备和系统。
背景技术
随着云计算、大数据、分布式系统、机器学习、认知计算、增强现实(Augmented Reality，AR)、虚拟现实(Virtual Reality，VR)等各种新型应用不断产生，对计算系统的需求越来越高。各种新型的融合基础设施不断涌现，对融合基础设施的性能和数据交互提出了更高的要求，其中，融合基础设施是指将服务器、存储设备、网络设备、以及虚拟化软件等数据中心的基本要素以预集成的方式，向用户提供计算资源(如CPU、内存)、存储资源(如磁盘)、网络资源(如网卡)，以满足用户的业务需求。
目前，融合基础设施的数据交互方式采用直接存储器存取(Direct Memory Access，DMA)传输方式，如图1所示，在图1所示的数据传输方案中：以处理器需要将待写入的数据写入存储介质为例：首先，处理器向片上系统(System on Chip，SoC)发送用于指示SoC将待写入的数据搬移至SoC的控制指令；然后，SoC的DMA控制器根据控制指令将待写入的数据从处理器的双倍速率同步动态随机存储器(Double Data Rate，DDR)搬移至SoC的DDR中；其次，SoC再向存储介质发送写数据指令，其中，图1中所示的存储介质可以为非易失性高速传输总线(Non-Volatile Memory express，NVMe)SSD，然后，SSD的DMA控制器再将待写入的数据从SoC的DDR中搬移至存储介质(如SSD)中。处理器读取存储介质中待读取的数据的过程与处理器将待写入的数据写入存储介质的过程类似，一次读取操作处理过程也需要两次DMA处理过程。
如图1描述的方案中，在处理器和存储介质的数据传输过程中，需要经过两次DMA搬移，这样当存在多个存储介质时，SoC需要同时处理多个存储介质的DMA搬迁请求，导致耗费更多SoC的CPU计算资源和存储(Memory)资源来参与DMA搬移，使得数据传输效率低，时延高。
发明内容
本申请提供一种数据传输的方法、装置、设备和系统，用以解决现有融合基础设施数据交互场景中的一次数据传输，需要SoC和存储介质的两次DMA搬移造成的时延高、传输效率低的问题。
为达到上述目的，本申请采用如下技术方案：
第一方面，本申请提供一种数据传输的方法，该方法应用于存储系统中，该存储系 统包括处理器、片上系统SoC和存储介质，其中，处理器、SoC和存储介质之间通过扩展外围组件互连高速PCIe总线通信，存储介质中包含直接内存存取DMA控制器，该方法包括：SoC获取包括待操作数据所在的存储介质的第一地址和操作类型的第一请求消息，其中，操作类型包括读取操作或写入操作，第一地址为所述第一地址为所述处理器在所管理的内存地址中为所述存储介质分配的地址；SoC按照预设地址映射关系根据第一地址确定所述存储介质在SoC所管理的内存地址中分配的第二地址；SoC再向所述存储介质的DMA控制器发送第一控制指令，该第一控制指令用于指示DMA控制器获取携带第二地址和操作类型的第二请求消息；当操作类型为读取操作时，SoC接收DAM控制器发送的第一数据，第一数据为DMA控制器根据第二地址获取；然后，SoC向处理器发送所述第一数据；当操作类型为写入操作时，SoC接收处理器发送的第二数据，并将第二数据发送给DMA控制器，触发DMA控制器根据第二地址将第二数据写入存储介质。
本申请提供一种数据传输的方法，由于SoC通过第一控制指令从处理器中获取第一请求消息，并将该第一请求消息中携带的第一地址转换为第二地址，然后向目标存储介质发送用于获取第二控制指令，其中，第二控制指令中携带第二地址和操作类型的第二请求消息。因此，在目标数据从处理器到目标存储介质的传输过程中，SoC负责将第一地址转换为第二地址，将待读取的第一数据或待写入的第二数据在处理器和存储介质之间转发，数据传输过程只需要存储介质的DMA控制器参与，并不需要SoC的DMA控制器参与。因此，本发明实施例仅通过存储介质的DMA控制器将第一数据或第二数据在处理器和存储介质之间搬移，能够避免数据传输时需要经过SoC的DMA控制器进行转发导致的延时高、传输效率低的问题。
在第一方面的一种可能的实现方式中，SoC获取第一请求消息之前，本申请提供的方法还包括：SoC接收处理器发送的第二控制指令，第二控制指令中携带有用于唯一识别第一请求消息的标识；根据第一请求消息的标识获取第一请求消息。
在第一方面的一种可能的实现方式中，SoC根据第一地址确定第二地址，包括：根据第一地址从预设地址映射表中获取与第一地址存在对应关系的第二地址，其中，预设地址映射表中包括所述存储介质在处理器所管理的内存地址中分配的地址与所述存储介质在SoC所管理的内存地址中分配的地址的映射关系；将与第一地址存在对应关系的地址确定为所述存储介质的第二地址。。
在第一方面的一种可能的实现方式中，当操作类型为读取操作时，SoC接收DAM控制器发送的第一数据；以及向处理器发送第一数据，包括：SoC接收DMA控制器发送的第一数据；按照预设地址映射表将所述存储介质的第二地址映射为第一地址；按照第一地址将第一数据转发给处理器。
在第一方面的一种可能的实现方式中，SoC接收DMA控制器发送的第一中断，第一中断用于指示DMA控制器已成功将第一数据传输给SoC；当SoC确定SoC按照第一地址将第一数据成功传输给处理器时，向处理器发送第二中断，第二中断用于指示SoC将所述第一数据成功转发给处理器。
在第一方面的一种可能的实现方式中，当操作类型为写入操作请求时，SoC接收处理器发送的第二数据，并将第二数据发送给DMA控制器，触发DMA控制器根据第二地址将第二数据写入所述存储介质，包括：SoC接收处理器发送的第二数据；将存储介质的 第一地址映射为第二地址；按照第二地址将第二数据发送给DMA控制器。
在第一方面的一种可能的实现方式中，SoC接收所述处理器发送的第二数据之前，SoC接收DMA控制器发送的读取请求消息，读取请求消息中携带有第二地址；将读取请求消息中的第二地址映射为所述第一地址，生成第三请求消息，第三请求消息用于指示处理器向SoC发送所述待写入的数据；向处理器发送第三请求消息。
第二方面，本申请实施例提供一种存储系统，该存储系统包括处理器、片上系统SoC和存储介质，处理器、SoC和存储介质之间通过扩展外围组件互连高速PCIe总线通信，存储介质中包含直接存储器存取DMA控制器；处理器，用于向SoC发送用于获取第一请求消息的第一控制指令，第一控制指令携带用于唯一识别第一请求消息的标识；第一请求消息包括所述存储介质的第一地址和操作类型；第一地址为所述存储介质在处理器所管理的内存地址中分配的地址；所述SoC，用于接收处理器发送的第一控制指令，以及根据第一控制指令获取第一请求消息；根据第一地址确定第二地址，并生成第二请求消息，第二地址为所述存储介质在SoC所管理的内存地址中分配的地址，第二请求消息携带第二地址和操作类型；根据第二地址向所述存储介质的DMA控制器发送第一控制指令，所述第一控制指令用于指示DMA控制器获取第二请求消息；当操作类型为读取操作时，接收DAM控制器发送的第一数据，第一数据为DMA控制器根据第二地址获取；向处理器发送第一数据；当操作类型为写入操作时，接收处理器发送的第二数据，并将第二数据发送给DMA控制器，触发DMA控制器根据第二地址将第二数据写入所述存储介质；所述存储介质的DMA控制器，用于接收第二控制指令，第二控制指令中携带有用于唯一识别第一请求消息的标识；根据第二控制指令获取第二请求消息；当操作类型为读取操作时，根据第二地址获取第一数据；向SoC发送第一数据；当操作类型为写入操作时，接收SoC发送的第二数据，并根据第二地址将第二数据写入所述存储介质。
第三方面，本申请提供一种片上系统SoC，所述SoC包括用于执行第一方面或第一方面任一种可能实现方式中的故障处理方法的各个模块。
第四方面，本申请提供一种片上系统SoC，该SoC包括处理器、存储器、通信接口、总线，处理器、存储器和通信接口之间通过总线连接并完成相互间的通信，存储器中用于存储计算机执行指令，该SoC运行时，处理器执行存储器中的计算机执行指令以利用该SoC中的硬件资源执行第一方面及第一方面中任意一种可能的实现方式所描述的数据传输的方法。
第五方面，本申请提供一种可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，是的计算机执行上述各方面所述的方法。
本申请在上述各方面提供的实现方式的基础上，还可以进行进一步组合以提供更多实现方式。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍。
图1为现有技术提供的一种数据传输示意图；
图2a为本发明实施例提供的一种存储系统的架构图；
图2b为本发明实施例提供的另一种存储系统的架构图；
图3为本发明实施例提供的一种数据传输方法的流程示意；
图4为本发明实施例提供的另一种数据传输方法的流程示意；
图5为本发明实施例提供的另一种数据传输方法的流程示意；
图6为本发明实施例提供的另一种读取操作请求时的数据传输方法的结构示意图；
图7为本发明实施例提供的另一种写入操作请求时的数据传输方法的结构示意图；
图8a为本发明实施例提供的一种存储系统的结构示意图；
图8b为本发明实施例提供的另一种存储系统的结构示意图；
图9a为本发明实施例提供的一种片上系统的结构示意图；
图9b为本发明实施例提供的另一种片上系统的结构示意图；
图9c为本发明实施例提供的另一种片上系统的结构示意图；
图9d为本发明实施例提供的一种片上系统的硬件结构示意图。
具体实施方式
下面结合附图，对本发明的实施例进行详细的描述。为了便于清楚描述本发明实施例的技术方案，在本发明的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分，本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定。
如图2a所示，图2a示出了本发明实施例提供的一种数据传输的方法所应用的存储系统的架构图。如图2a所示，该存储系统包括处理器201、片上系统(system on chip，SoC)202和存储介质203，其中，处理器和SoC均配置有双倍速率同步动态随机存储器(Double Data Rate，DDR)，图2a中未示出，处理器201、片上系统202、DDR204和存储介质203之间通过扩展外围组件互连高速(Peripheral Component Interconnect express，PCIe)总线相连，处理器201中包括根复合体(root complex，RC)，RC为用于在PCIe总线中管理接入设备的管理模块，根复合体通过根端口(root port，RP)连接SoC，SoC作为处理器201的一个端点设备(end point，EP)接入PCIe总线结构中，SoC中运行有独立磁盘冗余阵列(redundant arrays of independent disks，RAID)控制器，用于管理存储介质203。存储介质203用于存储待读取的数据或待写入的数据。
值得说明的是，图2a中处理器201的个数可以为1个或多个，存储介质203的个数也可以为1个或多个。
本领域技术人员应理解的是，在PCIe总线标准中，每个PCIe总线中的设备均需要唯一总线号标识，每个PCIe结构受到有限的资源限制，例如，PCIe总线结构最大支持256个总线号。在PCIe结构中可以在端点设备(例如，SoC)中建立端点根复合体，端点根复合体在扩展PCIe结构中是用于管理接入扩展PCIe结构的接入设备的管理模块，SoC通过端点根复合体的RP连接存储介质203，每个存储介质203作为扩展PCIe结构中一个端点设备接入PCIe总线中，以此扩展PCIe结构中端点设 备的数量。另外，存储介质203可以为非易失性高速传输总线(non-volatile memory express，NVMe)固态硬盘(solid state disk，SSD)，也可以为其他类型的存储介质。每个存储介质203中均运行有直接内存存取(direct memory access，DMA)控制器，DMA控制器用于直接将待读取的数据从存储介质搬迁到处理器对应的DDR中，而不需要处理器201的参与。
处理器201的根复合体还将各种所连接的装置(包含装置的存储位置，例如寄存器和存储位置)映射到PCIe存储空间上，即映射到系统内存中。这些类型的映射和存储空间被称为存储器映射输入/输出(memory mapped input/output，MMIO)空间。同样的，SoC中的端点根复合体也将其所连接的装置(如寄存器、存储介质)映射到PCIe存储空间上。其中，处理器201的根复合体所管理的内存空间和SoC的端点根复合体所管理的内存空间是相互独立的，二者之间存在预设地址映射关系，该预设地址映射关系存储在SoC中，当处理器接收读取操作请求消息或写入操作请求消息时，处理器的根复合体可以根据请求消息中携带的地址信息确定存储介质的存储位置，然后再由SoC的端点根复合体根据预设地址映射关系，确定该存储介质在其所管理的内存中的地址信息，即该存储介质在SoC的端点根复合体的PCIe结构中的存储位置；最后由该存储介质的DMA控制器执行数据处理。
示例性的，处理器201所管理的内存空间为8TB，该内存空间的地址为00000000000-7ffffffffff(相当于0TB-8TB)，处理器201为SoC202在处理器201所管理的内存空间中所分配的内存大小为4TB，处理器201为SoC202所分配的4TB内存的地址为3ffffffffff-7ffffffffff(相当于从4TB-8TB)。SoC202所管理的内存空间是6TB，SoC所管理的内存空间的地址为00000000000-5ffffffffff(相当于0TB-6TB)，存储介质203在SoC202的内存空间所分配到的内存大小也为4TB，地址为1ffffffffff-5ffffffffff(相当于从2TB-6TB)。因此，若要将存储介质203在SoC202中的4TB映射到处理器201的4TB中，需要一个地址映射转换，如SoC202的1ffffffffff地址就映射到处理器201的3ffffffffff地址。
另外，在处理器201、SoC202和存储介质203中均存储有请求队列(submission queue，SQ)和完成队列(completion queue，CQ)。其中，请求队列用于存储待处理的读取操作请求消息或写入操作请求消息，CQ用于存储已完成的读取操作请求消息或写入操作请求消息。
具体的，处理器201的SQ中存储有处理器201待处理的读取操作请求消息或写入操作请求消息，CQ中存储有处理器201已完成的读取操作请求消息或写入操作请求消息，而且，处理器201的SQ和CQ中存储的读取操作请求消息或写入操作请求消息中均携带有第一地址，该第一地址为存储待读取或待写入的数据的存储介质在处理器所管理的内存地址中分配的地址；SoC202中的SQ中存储有SoC202待处理的读取操作请求消息或写入操作请求消息，CQ中存储有SoC202已完成的读取操作请求消息或写入操作请求消息，SoC的SQ和CQ中存储的读取操作请求消息或写入操作请求消息中均携带有第二地址，该第二地址为存储待读取或待写入的数据的存储介质在SoC所管理的内存地址中分配的地址；存储介质203中的SQ中存储有存储介质203待处理的读取操作请求消息或写入操作请求消息，CQ中存储有存储介质203 已完成的读取操作请求消息或写入操作请求。
图2b示出了另一种本发明实施例提供的一种数据传输方法所应用的存储系统的架构图，如图2b所示，在图2b和图2a中处理器201、SoC202和存储介质203的功能均相同，本申请在此不再赘述。图2b与图2a的区别在于，图2a中是将每个存储介质203作为一个EP，通过SoC中的一个RP直接接入PCIe总线中。而图2b中是通过PCIe交换芯片(switch)204将SoC202与存储介质203连接。具体的，该PCIe交换芯片204包括至少一个上行端口和至少一个下行端口，该PCIe交换芯片204的上行端口用于与SoC202中的RP连接，下行端口用于连接存储介质203。其中，上行端口为指向根复合体的端口，下行端口为远离根复合体的端口。在图2b中仅示出了根复合体包括一个根端口，可以理解的是，在实际使用过程中根复合体包括多个根端口(例如，四个到六个根端口之间)。
值得说明的是，图2a中处理器201的个数可以为1个或多个，存储介质203的个数也可以为1个或多个。
可选的，本发明实施例应用的存储架构图2b所示的通过PCIe交换芯片204连接存储介质外，还可以通过接口卡外接其他存储介质，此时，图2b所示的存储架构可以为应用于基于网络的非易失性存储器(NVMe of fabric，NoF)的存储系统中。
本发明实施例中的图2a和图2b所示的存储系统架构可以为一个存储阵列，其中，存储阵列包括控制器和硬盘框，控制器运行在处理器201中，存储介质203可以是与存储阵列的控制器在同一物理设备中的硬盘设备，也可以是以硬盘框形式连接到控制器所在物理设备的存储阵列；存储阵列中还包括RAID控制器，RAID控制器运行在SoC202中，RAID控制器用于对存储阵列中存储介质的RAID关系进行管理。
可选的，本发明实施例中图2a和图2b所示的存储系统架构也可以为一个服务器，该服务器包括处理器201、SoC202和存储介质203。
结合图2a和图2b，本发明实施例中的任意一个存储介质203均可以通过SoC202接收一个或多个处理器201发送的读取操作请求消息或者写入操作请求消息，并将一个或多个处理器201发送的写入操作请求消息中请求待写入的数据存储在存储介质203中。同时，任意一个存储介质203也可以根据处理器201发送的读取操作请求消息，将处理器201需要从存储介质203中待读取的数据返回给处理器201，存储在处理器201的DDR20中。
接下来，结合图3进一步介绍本发明实施例提供的一种数据传输的方法，该方法应用于如图2a或图2b所示的存储系统中，如图3所示，本发明实施例提供的方法包括：
S301、处理器向SoC发送第二控制指令。
具体的，该第二控制指令用于指示SoC从处理器的请求队列中获取第一请求消息，该第一请求消息包括存储介质的第一地址和操作类型，所述存储介质用于存储待读取或写入的数据，该第一地址为所述存储介质在处理器所管理的内存地址中分配的地址，该操作类型包括读取操作或写入操作。
可选的，第二控制指令中包括第一标识，第一标识用于唯一标识一个第一请求消息。
可以理解的是，在处理器中存储的请求队列中包括至少一个请求消息，每个请求消息指示一个处理器待处理的读取操作请求消息或写入操作请求消息，每个请求消息对应一个标识。如表1所示，第一请求消息1的唯一标识为1001，第一请求消息2的唯一标识为1002，第一请求消息3的唯一标识为1003。
表1 处理器中第一请求消息与第一标识的对应关系示例
第一标识 第一请求消息
1001 第一请求消息1
1002 第一请求消息2
1003 第一请求消息3
示例性的，例如，若第一请求消息为第一请求消息1，该第一请求消息1的唯一标识为1001，则SoC根据该标识从处理器的请求队列中获取与1001存在对应关系的请求消息1。
S302、SoC接收处理器发送的第二控制指令。
S303、SoC根据第二控制指令，从处理器的请求队列中获取第一请求消息。
具体的，该第二控制指令中携带有第一请求消息的第一标识，SoC根据第一请求消息的第一标识从处理器的请求队列中获取与该第一标识存在对应关系的第一请求消息。
可以理解的是，处理器的SQ队列中存在有多个存储位置，一个存储位置用于存储一个第一请求消息，当SoC根据第一标识从SQ队列中获取与该第一标识存在对应关系的第一请求消息后，该第一请求消息所在的存储位置上的存储空间将被空出。当处理器产生新的第一请求消息时，处理器可以将新产生的第一请求消息存储在上述被清空的存储位置上。
S304、SoC根据第一地址确定存储介质的第二地址，并生成第二请求消息。
具体的，该第二地址为所述存储介质在SoC所管理的内存地址中分配的地址。
另外，第二请求消息中携带有第二地址和操作类型，该第二请求消息对应一个第二标识，该第二请求消息用于指示所述存储介质的DMA控制器将按照操作类型对第二地址对应的所述存储介质执行读取操作或写入操作。该第二请求消息中携带的操作类型与第一请求消息中携带的操作类型一致。例如，若第一请求消息中携带的操作类型为写入操作，则该第二请求消息中携带的操作类型也为写入操作。若第一请求消息中携带的操作类型为读取操作，则该第二请求消息中携带的操作类型也为读取操作。
可选的，本发明实施例中的步骤S304可以通过以下方式实现：
S3041、SoC根据第一地址，从预设地址映射表中获取与第一地址存在对应关系的第二地址。
其中，预设地址映射表中包括第一地址和第二地址之间的映射关系。
示例性的，该SoC中存储有一个预设地址映射表，该预设地址映射表中建立了第一地址和第二地址的具体映射规则，SoC可以通过该映射规则确定与第一地址存在映射关系的第二地址，其中，第一地址为所述存储介质在处理器所管理的内存地 址中分配的地址，第二地址为待操作的存储介质在SoC所管理的内存地址中分配的地址。
表2 预设地址映射表
第一地址 第二地址
100001 2000002
100011 200011
100012 200013
在表2中，将SoC从处理器的请求队列中获取的第一请求消息中得到的地址记为第一地址，若第一请求消息中携带的第一地址为100001，则SoC可以通过该预设地址映射表确定与第一地址100001存在映射关系的第二地址为2000002。
S305、SoC将第二请求消息存储到SoC的请求队列中。
S306、SoC向所述存储介质的DMA控制器发送第一控制指令，该第一控制指令用于指示所述存储介质的DMA控制器从SoC的请求队列中获取第二请求消息。
可选的，该第一控制指令中携带有第二标识，该第二标识用于唯一识别SoC的请求队列中存储的第二请求消息。
本发明实施例中的第二标识可以为字母、数字等任意一种可以唯一标识一个第二请求消息的标识，本发明实施例对此不进行限定。
可以理解的是，SoC的请求队列中包括一个或多个存储位置，一个或多个存储位置中每个存储位置用于存储一个第二请求消息，也即SoC的请求队列中存储有一个或多个第二请求消息，该一个或多个第二请求消息中每个第二请求消息携带一个第二地址以及操作类型，每个第二请求消息对应一个唯一识别该第二请求消息的第二标识。如表3所示，第二请求消息1的唯一标识为101，第二请求消息2的唯一标识为102，第二请求消息3的唯一标识为103。
表3 SoC的请求队列中第二请求消息与标识之间的对应关系示例
第二标识 第二请求消息
101 第二请求消息1
102 第二请求消息2
103 第二请求消息3
示例性的，当第一控制指令中携带的第二标识为101时，则该第二控制指令用于指示所述存储介质的DMA控制器从SoC的请求队列中获取与第二标识101存在对应关系的第二请求消息1。
可以理解的是，当所述存储介质的DMA控制器根据上述第一控制指令，从SoC的请求队列中获取第二请求消息后，该第二请求消息所在的存储位置上的存储空间将被空出，SoC可以将新的第二请求消息存储在该空出的存储位置。
S307、所述存储介质的DMA控制器根据第一控制指令获取第二请求消息，以及按照该第二请求消息中携带的操作类型处理数据。
具体的，所述存储介质的DMA控制器根据第一控制指令中携带的第二标识从SoC的请求队列中获取该第二标识存在对应关系的第二请求消息。
由于第二请求消息的操作类型可以为读取操作，也可以为写入操作，但是不同的操作类型在具体实施过程中存在差异，因此以下将分别结合操作类型为读取操作请求和操作类型为写入操作请求这两种情况详细介绍步骤S307的具体实现过程：
一方面，当第二请求消息的操作类型为读取操作时，结合图3，可选的，步骤S307可以通过以下方式实现：
S3071A、所述存储介质的DMA控制器获取第二地址对应所述存储介质中存储的第一数据，其中，第一数据为所述存储介质中存储的待读取的数据。
S3072A、所述存储介质的DMA控制器以DMA内存存取方式向SoC发送第一数据，然后执行S3081。
另一方面，当第二请求消息的操作类型为写入操作时，处理器将待写入的数据写入所述存储介质，但是对所述存储介质而言，则是根据从处理器中请求读取待写入的数据，因此，结合图3，步骤S307可以通过以下方式实现：
S3071B、所述存储介质的DMA控制器在获取到第二请求消息后，向SoC发送读取请求消息，该读取请求消息中携带有第二地址，该读取请求消息用于指示获取第二数据，其中，第二数据为待写入所述存储介质的数据。
S3072B、所述存储介质的DMA控制器以DMA内存存取方式从处理器中获取第二数据，然后执行S3082。
在步骤S307后，所述方法还包括：
S3081、当操作类型为读取操作时，SoC向所述处理器发送所述第一数据。
S3082、当操作类型为写入操作时，SoC将处理器发送的第一数据转发给所述存储介质的DMA控制器。
本发明实施例提供一种数据传输的方法，由于SoC通过第一控制指令从处理器中获取第一请求消息，并对该第一请求消息中携带的第一地址进行转换，然后向目标存储介质发送第二控制指令，以使得目标存储介质根据第二控制指令获取第二请求消息。因此，在第一数据或第二数据从处理器到存储介质的传输过程中，SoC负责将第一地址转换为第二地址，将第一数据或第二数据在处理器和存储介质之间转发，并且第一数据或第二数据从处理器到存储介质中的搬移只需要所述存储介质的DMA控制器参与，并不需要SoC的DMA控制器参与。因此，本发明实施例仅通过所述存储介质的DMA控制器将第一数据或第二数据在处理器和存储介质之间搬移，能够避免数据传输时需要经过SoC的DMA控制器进行转发导致的延时高、传输效率低的问题。
由于SoC从处理器的SQ中获取的第一请求消息的操作类型可能为读取操作，也可能为写入操作，不同操作类型的请求消息，在具体实施过程中存在差异。因此，下述将分别详细介绍操作类型为读取操作请求或者写入操作请求时，SoC分别与处理器和目标存储介质之间的交互。
为了避免目标数据在处理器和存储介质之间传输过程中由于SoC的DMA控制器 参与搬移所导致的时延，传输效率低的问题，本申请在操作类型为读取操作时，仅通过所述存储介质的DMA控制器将待读取的第一数据从所述存储介质搬移至处理器；在操作类型为写入操作时，仅通过所述存储介质的DMA控制器将待写入的第二数据从处理器搬移至所述存储介质，在第二数据从所述存储介质到处理器之间传输时，第二数据仅通过SoC的内部总线传输，不需要SoC的DMA控制器参与搬移。因此，能够避免时延。
作为一个可能的实施例，结合图3，如图4所示，图4为本发明提供的一种操作类型为读取操作时数据传输过程，图4与图3的区别在于，在执行完S301-S307之后，本发明实施例中的步骤还包括：S307a。图4中详细介绍了步骤S308的数据传输过程，其中，步骤S301-S307的处理过程可以参见图3，本发明实施例在此不再赘述。如图4所示，本发明实施例提供的方法包括：
S307a、所述存储介质的DMA控制器将第一数据以DMA内存存取的方式发送给SoC。
可选的，如图4所示，步骤S3081还可以包括：
S3081a、SoC接收所述存储介质的DMA控制器以DMA内存存取方式发送的第一数据。
S3082a、SoC将所述存储介质的第二地址映射为第一地址。
具体的，SoC可以通过如表2所示的预设地址映射表将目标数据的地址从第二地址映射为第一地址。
S3083a、SoC将第一数据转发给处理器。
可选的，在执行步骤S3081过程中，本发明实施例提供的方法还包括：：
S3083a1、SoC接收所述存储介质的DMA控制器发送的第一中断，该第一中断用于指示DMA控制器已成功将第一数据传输给所述SoC。
具体的，存储介质的DMA控制器确定第一数据成功转发给处理器的方法可以理解为：SoC向处理器发送的数据量的等于第一数据的大小。也即，若第一数据的大小为A，则若SoC确定已向处理器转发的第一数据的大小也为A，则确定目标数据成功转发。
可选的，存储介质的DMA控制器也可以记录第一数据的大小和校验值，通过指针方式记录和传输第一数据的位置信息，并计算已发送第一数据的校验值，当计算获得的已发送的第一数据的校验值和所记录的校验值相等时，确定第一数据传输成功。
S3083a2、当SoC确定SoC将第一数据成功传输给处理器时，向处理器发送第二中断，第二中断用于指示SoC将第一数据成功转发给所述处理器。。
其中，SoC判断第一数据是否成功的方法可以参见S3083a1的描述，在此不再赘述。
所述存储介质的DMA控制器以DMA内存存取方式将第一数据发送至SoC的内存，SoC通过PCIe总线将第一数据发送至处理器。
作为另一个可能的实施例，结合图3，如图5所示，图5为本发明提供的一种操作类型为写入操作请求时的数据传输过程，图5与图3的区别在于，图5中具体 介绍了操作请求为写入操作请求时，步骤S308的具体实现过程，其中，步骤S301-S307的处理过程可以参见图3，本发明实施例在此不再赘述。如图5所示，本发明实施例提供的方法包括：
S307b、所述存储介质的DMA控制器向SoC发送读取请求消息，该读取请求消息中携带有第二地址。
具体的，该读取请求消息用于指示处理器将待写入的第二数据发送给SoC。
S3081b、SoC接收所述存储介质的DMA控制器发送的读取请求消息。
S3082b、SoC将读取请求消息中的第二地址映射为第一地址，生成第三请求消息，第三请求消息用于指示处理器发送第二数据。
S3083b、SoC将第三请求消息发送给处理器。
S3084b、处理器根据第三请求消息将第二数据发送给SoC。
S3085b、SoC接收处理器发送的第二数据。
S3086b、SoC将目标数据的地址从第一地址转换为第二地址。
具体的，SoC可以通过上述表2所示的预设地址映射表将目标数据的地址从第一地址转换为第二地址。
S3087b、SoC按照第二地址向所述存储介质的DMA控制器发送第二数据，触发所述存储介质的DMA控制器以DMA内存存取方式获取第二数据，并将第二数据存储至所述存储介质中。
具体的，SoC接收读取请求消息，并将该读取请求消息中的第二地址映射为第一地址之后，生成第三请求消息，并向处理器发送第三请求消息，处理器接收到该第三请求消息之后，从处理器的内存中获取第二数据，并将该第二数据发送给SoC，然后，SoC将该第二数据要存储的所述存储介质的地址从第一地址映射为第二地址之后，最终，所述存储介质的DMA控制器以DMA内存存取方式将第二数据从SoC中搬移至所述存储介质。
下面结合图6和图7对本发明实施例提供的数据传输方法做进一步说明。
如图6所示，图6示出了本发明实施例提供的一种操作类型为读取操作请求场景下的数据传输的流程架构图，SoC中包括处理器,该处理器用于对存储系统的处理器的读取操作或写入操作进行处理,SoC中还包括内存地址管理单元、重定向单元，内存地址管理单元和重定向单元是运行在处理器上的计算机程序，内存地址管理单元用于对待读取或待写入的数据的地址进行映射，重定向单元用于对读取操作请求的处理过程实现整序功能，实现存储系统的一致性。如图6所示，该数据传输方法包括：
S701、处理器发送第二控制指令给SoC，该第二控制指令用于指示SoC从处理器的请求队列中获取携带第一地址读取操作指令(即上述实施例中描述的第一请求消息)。
S702、SoC根据该第二控制指令，从处理器的请求队列中获取携带第一地址的读取操作指令，以及将该读取操作指令中的第一地址映射为第二地址，以生成携带第二地址和读取操作指令的第二请求消息，并且将第二请求消息存储到SoC的请求队列中。
S703、SoC向所述存储介质发送第一控制指令，该第一控制指令用于指示待读取或写入数据的存储介质的DMA控制器从SoC的请求队列中获取第二请求消息。
S704、所述存储介质的DMA控制器根据第二地址从所述存储介质中读取第一数据，其中，第一数据为所述存储介质中存储的待读取的数据。
S705、所述存储介质的DMA控制器将第一数据以DMA内存存取方式通过传输链路发送给SoC。
S706、所述存储介质的DMA控制器向SoC的CQ中写入已完成第二地址的读取操作指令，并向该SoC的CPU发送第一中断。
S707、SoC在接收到第一中断后，从SoC的完成队列中获取已完成第一数据读取操作指令。
需要说明的是，本发明实施例中只有在SoC确定第一数据完全转发至处理器之后，才将SoC接收到的第一中断做处理后，向处理器发送第二中断，这样能够保证在处理器读取所述存储介质中的第一数据时，该第一数据一定早于第二中断到达处理器。具体的，该步骤可以通过运行在SoC中的重定向单元来实现，若SoC内没有运行重定向单元，则会存在SoC接收到第一中断后，便立刻向处理器发送第二中断，即图6中的步骤707a，这样会存在第二中断早于目标数据返回处理器的情况发生，从而造成处理器侧一致性无法保证，避免数据丢失。
S708、SoC将所述存储介质的地址从第二地址映射为第一地址后，将第一数据通过PCIe总线转发给处理器。
S709、SoC将第二地址映射为第一地址，并获取新的回写指令，该新的回写指令用于指示已完成第一数据的读取操作指令。
S710、SoC在确定第一数据已完全转发至处理器，则将该已完成第一地址的读取操作指令写入处理器的完成队列中，并向处理器发送第二中断。
S711、处理器在接收到第二中断后，从处理器的完成队列中读取已完成第一地址的读取操作指令，从而确定已成功从所述存储介质中读取第一数据。
如图7所示，图7示出了本发明实施例提供的一种操作类型为写入操作请求场景下的数据传输架构图，如图7所示，该数据传输方法包括：
S801、处理器向SoC发送第二控制指令，该第二控制指令用于指示SoC从处理器的请求队列中获取携带写入操作指令，该写入操作指令用于指示将处理器内存中的第二数据写入所述存储介质中。
S802、SoC从处理器的请求队列中获取携带写入操作指令，并将该写入操作指令中的待写入数据的存储介质的第一地址映射为第二地址，以及在SoC的请求队列中生成携带第二地址和操作类型的第二请求消息。
S803、SoC向所述存储介质的DMA控制器发送第一控制指令，该第一控制指令用于指示所述存储介质的DMA控制器从SoC的请求队列中获取携带第二地址和操作类型的第二请求消息。
S804、所述存储介质的DMA控制器根据第一控制指令，从SoC的请求队列中获取携带第二地址和操作类型的第二请求消息。
具体的，该所述存储介质将SoC的请求队列中获取的携带第二地址和操作类型 的第二请求消息进行处理，并生成读取请求消息，该请求消息中包括第二地址和操作类型，并将该读取请求消息存储至所述存储介质的请求队列中。
S805、所述存储介质的DMA控制器将携带第二地址和操作类型的读取请求消息发送给SoC。
S806、SoC将携带第二地址和操作类型的读取请求消息中的第二地址映射为第一地址。
S807、SoC通过PCIe总线将携带第一地址之后的读取请求消息通过发送给处理器。
S808、处理器接收到携带第一地址的读取请求消息之后，将第二数据和第一地址发送给SoC。
S809、SoC将第一地址映射为第二地址，然后按照第二地址向存储介质的DMA控制器发送第二数据。
S810、所述存储介质的DMA控制器将第二数据从SoC中搬移至所述存储介质。
S811、所述存储介质的DMA控制器向SoC的CQ中写入已将第二数据写入所述存储介质的指令，并向SoC发送第一中断。
S812、SoC接收到第一中断之后，从SoC的CQ中获取已将第二数据写入所述存储介质的指令。
S813、SoC将已将第二地址映射为第一地址，以获取新的CQ回写指令。
S814、SoC将新的CQ回写指令写入处理器的CQ中，并向处理器发送第二中断。
可以理解的是，本发明实施例中当操作类型为写入时，步骤S811-S814可以省略。
当本发明实施例提供的数据传输方法应用于图2a或者图2b所示的架构中时，处理器通过SoC读取存储介质中的数据或通过SoC向存储介质中写入数据，卸载RAID等功能，处理器与存储介质间的数据交互直通(即处理器直接与存储设备连接)，数据不再需要拷贝到SoC挂载的DDR里，直接搬移到存储介质，以下以存储介质为SSD时处理过程为例进行进一步解释：
1)、在RAID0模式下处理器读取/写入目标数据都只需要一次DMA操作，数据在处理器和SSD之间直通，不做计算，纯粹的数据拷贝。
2)、在RAID1模式下处理器读取/写入目标数据都只需要一次DMA操作，数据在处理器和SSD之间直通。
3)、RAID10模式下处理器读取/写入目标数据都只需要一次DMA操作，数据在HOST和SSD之间直通。
4)、RAID5模式下当处理器从SSD中读取目标数据时，只需要一次DMA操作，数据直接从SSD中通过SSD的DMA控制器搬移至处理器；当处理器向SSD中写入目标数据时，由于写操作需要对数据做运算，然后写入硬盘，写入的同时还需要硬盘上写入检验信息，因此数据必须进入SoC。
5)、RAID6模式下当处理器从SSD中读取目标数据时只需要一次DMA操作，数据直接从SSD拷贝到处理器，当处理器向SSD中写入目标数据时需要对数据做运算，数据必须进入SoC。
本发明实施例提供的数据传输方法可以在无需SoC参与计算的RAID模式(不限于前述几种情况)下，SoC只需要将处理器发送的读取或写入操作请求中的第一地址映射为第二地址，或者将第二地址映射为第一地址，以使得存储介质的DMA控制器可以识别。因此，在存储介质和处理器之间的传输中，SoC仅完成请求的处理、转发和地址的映射，数据从处理器搬移至存储介质或者从存储介质搬移至处理器过程中，仅由存储介质的DMA控制器执行，并不需要SoC的DMA控制器参与搬移，这样便提高了带宽利用率，并且SoC不参与DMA搬移，如此，便避免了造成SoC性能瓶颈。再者，IOPS(每秒的输入输出量，input/output per second)能力可以由SSD线型堆叠，使得存储系统性能明显提升。
图8a示出了本发明实施例提供的一种存储系统的结构示意图，图8a所示的存储系统为一种存储阵列。如图8a所示，该存储系统20可以包括处理器201、片上系统202、存储介质203、通信接口206以及存储器207，其中，处理器201、片上系统202、存储介质203、通信接口206以及存储器207通过通信总线204连接。其中，处理器201包含控制器，片上系统202包含RAID控制器，在存储介质203中包含DMA控制器，在图8a所示的存储系统中，存储介质203可以是与处理器201在同一物理设备中的一个或多个存储介质，也可以是通过硬盘框205连接到控制器所在的物理设备上的一个或多个存储介质。
所述处理器，用于向所述SoC发送用于获取第一请求消息的第一控制指令，所述第一控制指令携带用于唯一识别所述第一请求消息的标识；所述第一请求消息包括所述存储介质的第一地址和操作类型；所述第一地址为所述处理器在所管理的内存地址中为所述存储介质分配的地址。
所述SoC，用于接收所述处理器发送的所述第一控制指令，以及根据所述第一控制指令获取所述第一请求消息；根据所述第一地址确定第二地址，并生成第二请求消息，所述第二地址为所述SoC在所管理的内存地址中为所述存储介质在分配的地址，所述第二请求消息携带所述第二地址和所述操作类型；根据所述第二地址向所述存储介质的DMA控制器发送第一控制指令，所述第一控制指令用于指示所述DMA控制器获取第二请求消息；当所述操作类型为读取操作时，接收所述DAM控制器发送的第一数据，所述第一数据为所述DMA控制器根据所述第二地址获取；向所述处理器发送所述第一数据；当所述操作类型为写入操作时，接收所述处理器发送的第二数据，并将所述第二数据发送给所述DMA控制器，触发所述DMA控制器根据所述第二地址将所述第二数据写入所述存储介质。
所述存储介质的DMA控制器，用于接收第二控制指令，所述第二控制指令中携带有用于唯一识别所述第一请求消息的标识；根据所述第二控制指令获取第二请求消息；当所述操作类型为读取操作时，根据所述第二地址获取所述第一数据；向所述SoC发送所述第一数据；当所述操作类型为写入操作时，接收所述SoC发送的第二数据，并根据所述第二地址将所述第二数据写入所述存储介质。
其中，通信接口206，用于存储系统与其他设备之间的通信。
存储器207，用于存放程序，存储器206可能包括高速RAM存储器，也可以包 括非易失性存储器(英文名称：non-volatile memory)，例如，至少一个磁盘存储器。可以理解的是，存储器可以为随机存储器(random-access memory，RAM)、硬盘、光盘、SSD或者非易失性存储器等各种可以存储程序代码的非短暂性(non-transitory)机器可读介质。
处理器201可以是CPU，该处理器201还可以是其他通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。该处理器用于执行上述实施例中图3至图7中处理器为执行主体执行的操作步骤。
存储介质的DMA控制器用于执行上述实施例中图3至图7中存储介质的DMA控制器为执行主体的操作步骤。
值得说明的是，图8a中处理器的个数可以为1个或多个，存储介质的个数也可以为1个或多个。
图8b示出了本发明实施例提供的另一种存储系统20的结构示意图，图8b所示的存储系统为一种存储设备，如服务器。图8b与图8a的区别在于，在图8b中，处理器201中不存在控制器，且在SoC中不存在RAID控制器，具体的，图8b所示的各个硬件结构的功能均和图8a所示的硬件结构功能相同，本发明实施例在此不再赘述。
图8a所示的存储系统为图2a所示的存储系统的架构为存储阵列时的结构示意图，图8b所示的存储系统为图2a所示的存储系统的结构为存储设备时的结构示意图。
上述主要从SoC的角度对本发明实施例提供的方案进行了介绍。可以理解的是，SoC等为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，本发明能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
本发明实施例可以根据上述方法示例对SoC等进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本发明实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在采用对应各个功能划分各个功能模块的情况下，图9a示出了上述实施例中所涉及的SoC的一种可能的结构示意图，SoC1包括：获取单元10，地址管理单元11,发送单元12。
其中，获取单元10，用于获取第一请求消息，所述第一请求消息包括所述存储介质的第一地址和操作类型，所述操作类型包括读取操作或写入操作，所述第一地址为所述处理器在所管理的内存地址中为所述存储介质分配的地址；当所述操作类 型为读取操作时，所述SoC接收所述DAM控制器发送的第一数据，所述第一数据为所述DMA控制器根据所述第二地址获取；当所述操作类型为写入操作时，接收所述处理器发送的第二数据。
地址管理单元11，用于所述第一地址确定所述存储介质的第二地址，并生成第二请求消息，所述第二地址为所述SoC在所管理的内存地址中为所述存储介质在分配的地址，所述第二请求消息携带所述第二地址和所述操作类型。
发送单元12，用于根据所述第二地址向所述存储介质的DMA控制器发送第一控制指令，所述第一控制指令用于指示所述DMA控制器获取第二请求消息；向所述处理器发送所述第一数据；将所述第二数据发送给所述DMA控制器，触发所述DMA控制器根据所述第二地址将所述第二数据写入所述存储介质。
可选的，如图9b所示，本发明实施例中的SoC还包括接收单元13，用于接收所述处理器发送的第二控制指令，所述第二控制指令中携带有用于唯一识别所述第一请求消息的标识；根据所述第一请求消息的标识获取所述第一请求消息。
可选的，本发明实施例中的SoC中地址管理单元11根据所述第一地址确定所述第二地址，包括：
根据所述第一地址从预设地址映射表中获取与所述第一地址存在对应关系的第二地址，其中，所述预设地址映射表中至少包括所述存储介质在所述处理器所管理的内存地址中分配的地址与所述存储介质在所述SoC所管理的内存地址中分配的地址的映射关系；将与所述第一地址存在对应关系的地址确定为所述存储介质的第二地址。
可选的，本发明实施例中的SoC中接收单元13，还用于当所述操作类型为读取操作请求时，接收所述DMA控制器发送的所述第一数据；。
地址管理单元11，还用于按照预设地址映射表将所述存储介质的第二地址映射为所述第一地址。
发送单元12，还用于按照所述第一地址将所述第一数据转发给所述处理器。
可选的，如图9c所示本发明实施例中的SoC还包括重定向单元14；
所述接收单元13，还用于接收所述DMA控制器发送的第一中断，所述第一中断用于指示所述DMA控制器已成功将所述第一数据传输给所述SoC。
重定向单元14，用于当所述SoC确定所述SoC按照所述第一地址将所述第一数据成功传输给所述处理器时，向所述处理器发送第二中断，所述第二中断用于指示所述SoC将所述第一数据成功转发给所述处理器。
可选的，本发明实施例中的接收单元13，还用于当所述操作类型为写入操作请求时，所述处理器发送的所述第二数据。
地址管理单元11，还用于将所述存储介质的所述第一地址映射为所述第二地址。
发送单元12，还具体用于按照所述第二地址将所述第二数据发送给所述DMA控制器。
可选的，接收单元13，还用于在接收所述处理器发送的第二数据之前，接收所述DMA控制器发送的读取请求消息，所述读取请求消息中携带有所述第二地址。
地址管理单元11，还用于将所述读取请求消息中的所述第二地址映射为所述第 一地址，生成第三请求消息，所述第三请求消息用于指示所述处理器向所述SoC发送所述第二数据。
发送单元12，还用于向所述处理器发送所述第三请求消息。
根据本发明实施例的图9a中SoC1可对应于执行本发明实施例中描述的方法，并且SoC1中的各个单元的上述和其它操作和/或功能分别为了实现图3至图7中的各个方法中SoC作为执行主体的相应流程，为了简洁，在此不再赘述。
9d为本发明实施例提供了一种SoC的硬件结构示意图，如图9c所示，该SoC包括处理器901、存储器902、通信接口903、总线904，处理器901、存储器902、通信接口903之间通过总线904连接并完成相互间的通信，存储器902中用于存储计算机执行指令，SoC运行时，处理器901执行所述存储器902中的计算机执行指令以利用SoC中的硬件资源执行以下步骤：
获取第一请求消息，所述第一请求消息包括所述存储介质的第一地址和操作类型，所述操作类型包括读取操作或写入操作，所述第一地址为所述处理器在所管理的内存地址中为所述存储介质分配的地址；
根据所述第一地址确定所述存储介质的第二地址，并生成第二请求消息，所述第二地址为所述SoC在所管理的内存地址中为所述存储介质在分配的地址，所述第二请求消息携带所述第二地址和所述操作类型；
根据所述第二地址向所述存储介质的DMA控制器发送第一控制指令，所述第一控制指令用于指示所述DMA控制器获取第二请求消息；
当所述操作类型为读取操作时，接收所述DAM控制器发送的第一数据，所述第一数据为所述DMA控制器根据所述第二地址获取；向所述处理器发送所述第一数据；
当所述操作类型为写入操作时，接收所述处理器发送的第二数据，并将所述第二数据发送给所述DMA控制器，触发所述DMA控制器根据所述第二地址将所述第二数据写入所述存储介质。。
其中，处理器901，例如可以是中央处理器(central processing unit，CPU)，通用处理器，数字信号处理器(digital signal processor，DSP)，专用集成电路(application-specific integrated circuit，ASIC)，现场可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。其可以实现或执行结合本发明公开内容所描述的各种示例性的逻辑方框，模块和电路。所述处理器也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，DSP和微处理器的组合等等。
总线904可以是外设部件互连标准(Peripheral Component Interconnect，PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，图9d中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
应理解，根据本发明实施例的SoC对应于本发明实施例提供的图9b中SoC的功能装置，该SoC用于实现图3至图7中所示方法的相应流程，为了简洁，在此不再赘述。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，仅以上述各功 能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
上述实施例，可以全部或部分地通过软件、硬件、固件或其他任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载或执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存在计算机可读介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集合的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如,固态硬盘SSD)等。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种数据传输的方法，其特征在于，所述方法应用于存储系统中，所述存储系统包括处理器、片上系统SoC和存储介质，所述处理器、所述SoC和所述存储介质之间通过扩展外围组件互连高速PCIe总线通信，所述存储介质包含直接内存存取DMA控制器，所述方法包括：
    所述SoC获取第一请求消息，所述第一请求消息包括所述存储介质的第一地址和操作类型，所述操作类型包括读取操作或写入操作，所述第一地址为所述处理器在所管理的内存地址中为所述存储介质分配的地址；
    所述SoC根据所述第一地址确定所述存储介质的第二地址，并生成第二请求消息，所述第二地址为所述SoC在所管理的内存地址中为所述存储介质在分配的地址，所述第二请求消息携带所述第二地址和所述操作类型；
    所述SoC根据所述第二地址向所述存储介质的DMA控制器发送第一控制指令，所述第一控制指令用于指示所述DMA控制器获取第二请求消息；
    当所述操作类型为读取操作时，所述SoC接收所述DAM控制器发送的第一数据，所述第一数据为所述DMA控制器根据所述第二地址获取；所述SoC向所述处理器发送所述第一数据；
    当所述操作类型为写入操作时，所述SoC接收所述处理器发送的第二数据，并将所述第二数据发送给所述DMA控制器，触发所述DMA控制器根据所述第二地址将所述第二数据写入所述存储介质。
  2. 根据权利要求1所述的方法，其特征在于，所述SoC获取第一请求消息之前，所述方法还包括：
    所述SoC接收所述处理器发送的第二控制指令，所述第二控制指令中携带有用于唯一识别所述第一请求消息的标识；
    则所述SoC获取第一请求消息具体为：
    所述SoC根据所述第一请求消息的标识获取所述第一请求消息。
  3. 根据权利要求1或2所述的方法，其特征在于，所述SoC根据所述第一地址，确定所述存储介质的第二地址，包括：
    所述SoC根据所述第一地址从预设地址映射表中获取与所述第一地址存在对应关系的第二地址，其中，所述预设地址映射表中包括所述存储介质在所述处理器所管理的内存地址中分配的地址与所述存储介质在所述SoC所管理的内存地址中分配的地址的映射关系；
    所述SoC将与所述第一地址存在对应关系的地址确定为所述存储介质的第二地址。
  4. 根据权利要求1-3任意一项所述的方法，其特征在于，所述当所述操作类型为读取操作时，所述SoC接收所述DAM控制器发送的第一数据；以及所述SoC向所述处理器发送所述第一数据，包括：
    所述SoC接收所述DMA控制器发送的所述第一数据；
    所述SoC按照预设地址映射表将所述存储介质的第二地址映射为所述第一地址；
    所述SoC按照所述第一地址将所述第一数据转发给所述处理器。
  5. 根据权利要求4所述的方法，其特征在于，所述方法还包括：
    所述SoC接收所述DMA控制器发送的第一中断，所述第一中断用于指示所述DMA控制器已成功将所述第一数据传输给所述SoC；
    当所述SoC确定所述SoC按照所述第一地址将所述第一数据成功传输给所述处理器时，向所述处理器发送第二中断，所述第二中断用于指示所述SoC将所述第一数据成功转发给所述处理器。
  6. 根据权利要求1-3任意一项所述的方法，其特征在于，当所述操作类型为写入操作时，所述SoC接收所述处理器发送的第二数据，并将所述第二数据发送给所述DMA控制器，触发所述DMA控制器根据所述第二地址将所述第二数据写入所述存储介质，包括：
    所述SoC接收所述处理器发送的所述第二数据；
    所述SoC将所述存储介质的所述第一地址映射为所述第二地址；
    所述SoC按照所述第二地址将所述第二数据发送给所述DMA控制器。
  7. 根据权利要求6所述的方法，其特征在于，所述SoC接收所述处理器发送的第二数据之前，所述方法还包括：
    所述SoC接收所述DMA控制器发送的读取请求消息，所述读取请求消息中携带有所述第二地址；
    所述SoC将所述读取请求消息中的所述第二地址映射为所述第一地址，生成第三请求消息，所述第三请求消息用于指示所述处理器向所述SoC发送所述第二数据；
    所述SoC向所述处理器发送所述第三请求消息。
  8. 一种存储系统，其特征在于，所述存储系统包括处理器、片上系统SoC和存储介质，所述处理器、SoC和存储介质之间通过扩展外围组件互连高速PCIe总线通信，所述存储介质中包含直接存储器存取DMA控制器；
    所述处理器，用于向所述SoC发送用于获取第一请求消息的第一控制指令，所述第一控制指令携带用于唯一识别所述第一请求消息的标识；所述第一请求消息包括所述存储介质的第一地址和操作类型；所述第一地址为所述处理器在所管理的内存地址中为所述存储介质分配的地址；
    所述SoC，用于接收所述处理器发送的所述第一控制指令，以及根据所述第一控制指令获取所述第一请求消息；根据所述第一地址确定第二地址，并生成第二请求消息，所述第二地址为所述SoC在所管理的内存地址中为所述存储介质在分配的地址，所述第二请求消息携带所述第二地址和所述操作类型；根据所述第二地址向所述存储介质的DMA控制器发送第一控制指令，所述第一控制指令用于指示所述DMA控制器获取第二请求消息；当所述操作类型为读取操作时，接收所述DAM控制器发送的第一数据，所述第一数据为所述DMA控制器根据所述第二地址获取；向所述处理器发送所述第一数据；当所述操作类型为写入操作时，接收所述处理器发送的第二数据，并将所述第二数据发送给所述DMA控制器，触发所述DMA控制器根据所述第二地址将所述第二数据写入所述存储介质；
    所述存储介质的DMA控制器，用于接收第二控制指令，所述第二控制指令中携带有用于唯一识别所述第一请求消息的标识；根据所述第二控制指令获取第二请求消息；当所述操作类型为读取操作时，根据所述第二地址获取所述第一数据；向所述SoC发送所 述第一数据；当所述操作类型为写入操作时，接收所述SoC发送的第二数据，并根据所述第二地址将所述第二数据写入所述存储介质。
  9. 一种片上系统SoC，其特征在于，所述SoC应用于存储系统中，所述存储系统包括处理器、片上系统SoC和存储介质，所述处理器、所述SoC和所述存储介质之间通过扩展外围组件互连高速PCIe总线通信，所述存储介质中包含直接存储器存取DMA控制器，所述SoC包括：
    获取单元，用于获取第一请求消息，所述第一请求消息包括所述存储介质的第一地址和操作类型，所述操作类型包括读取操作或写入操作，所述第一地址为所述处理器在所管理的内存地址中为所述存储介质分配的地址；当所述操作类型为读取操作时，所述SoC接收所述DAM控制器发送的第一数据，所述第一数据为所述DMA控制器根据所述第二地址获取，所述第二地址为所述SoC在所管理的内存地址中为所述存储介质在分配的地址；当所述操作类型为写入操作时，接收所述处理器发送的第二数据；
    地址管理单元，用于所述第一地址确定所述存储介质的第二地址，并生成第二请求消息，所述第二请求消息携带所述第二地址和所述操作类型；
    发送单元，用于根据所述第二地址向所述存储介质的DMA控制器发送第一控制指令，所述第一控制指令用于指示所述DMA控制器获取第二请求消息；向所述处理器发送所述第一数据；将所述第二数据发送给所述DMA控制器，触发所述DMA控制器根据所述第二地址将所述第二数据写入所述存储介质。
  10. 根据权利要求9所述的SoC，其特征在于，所述SoC还包括：
    接收单元，用于接收所述处理器发送的第二控制指令，所述第二控制指令中携带有用于唯一识别所述第一请求消息的标识；根据所述第一请求消息的标识获取所述第一请求消息。
  11. 根据权利要求9或10所述的SoC，其特征在于，所述地址管理单元根据所述第一地址，确定所述目标数据的第二地址，包括：
    根据所述第一地址从预设地址映射表中获取与所述第一地址存在对应关系的第二地址，其中，所述预设地址映射表中至少包括所述存储介质在所述处理器所管理的内存地址中分配的地址与所述存储介质在所述SoC所管理的内存地址中分配的地址的映射关系；将与所述第一地址存在对应关系的地址确定为所述存储介质的第二地址。
  12. 根据权利要求9-11任意一项所述的SoC，其特征在于，
    所述接收单元，还用于当所述操作类型为读取操作请求时，接收所述DMA控制器发送的所述第一数据；
    所述地址管理单元，还用于按照预设地址映射表将所述存储介质的第二地址映射为所述第一地址；
    所述发送单元，还用于按照所述第一地址将所述第一数据转发给所述处理器。
  13. 根据权利要求12所述的SoC，其特征在于，所述SoC还包括重定向单元；
    所述接收单元，还用于接收所述DMA控制器发送的第一中断，所述第一中断用于指示所述DMA控制器已成功将所述第一数据传输给所述SoC；
    所述重定向单元，用于当所述SoC确定所述SoC按照所述第一地址将所述第一数据成功传输给所述处理器时，向所述处理器发送第二中断，所述第二中断用于指示所述SoC 将所述第一数据成功转发给所述处理器。
  14. 根据权利要求9-11任意一项所述的SoC，其特征在于，
    所述接收单元，还用于当所述操作类型为写入操作请求时，所述处理器发送的所述第二数据；
    所述地址管理单元，还用于将所述存储介质的所述第一地址映射为所述第二地址；
    所述发送单元，还用于按照所述第二地址将所述第二数据发送给所述DMA控制器。
  15. 根据权利要求14所述的SoC，其特征在于，
    所述接收单元，还用于在接收所述处理器发送的第二数据之前，接收所述DMA控制器发送的读取请求消息，所述读取请求消息中携带有所述第二地址；
    所述地址管理单元，还用于将所述读取请求消息中的所述第二地址映射为所述第一地址，生成第三请求消息，所述第三请求消息用于指示所述处理器向所述SoC发送所述第二数据；
    所述发送单元，还用于向所述处理器发送所述第三请求消息。
  16. 一种片上系统SoC，其特征在于，所述SoC包括处理器、存储器、通信接口、总线，所述处理器、存储器和通信接口之间通过总线连接并完成相互间的通信，所述存储器中用于存储计算机执行指令，所述SoC运行时，所述处理器执行所述存储器中的计算机执行指令以利用所述SoC中的硬件资源执行权利要求1至7中任一所述方法的数据传输的方法。
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