WO2018135706A1 - Procédé de production d'un boîtier de semi-conducteur - Google Patents

Procédé de production d'un boîtier de semi-conducteur Download PDF

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Publication number
WO2018135706A1
WO2018135706A1 PCT/KR2017/004825 KR2017004825W WO2018135706A1 WO 2018135706 A1 WO2018135706 A1 WO 2018135706A1 KR 2017004825 W KR2017004825 W KR 2017004825W WO 2018135706 A1 WO2018135706 A1 WO 2018135706A1
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WIPO (PCT)
Prior art keywords
metal layer
tray
wafers
wafer
seed metal
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Application number
PCT/KR2017/004825
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English (en)
Korean (ko)
Inventor
김남철
여용운
권용태
이영석
Original Assignee
주식회사 네패스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority claimed from KR1020170053560A external-priority patent/KR101901988B1/ko
Application filed by 주식회사 네패스 filed Critical 주식회사 네패스
Publication of WO2018135706A1 publication Critical patent/WO2018135706A1/fr
Priority to US16/505,970 priority Critical patent/US10804146B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Definitions

  • the technical idea of the present invention relates to a method of manufacturing a semiconductor package, and more particularly, to a method of manufacturing a semiconductor package using a wafer level package technology.
  • a semiconductor package is manufactured by performing a semiconductor package process on semiconductor chips manufactured by performing various semiconductor processes on a wafer.
  • a wafer level package technology for performing a semiconductor package process at the wafer level and individualizing the wafer level semiconductor package subjected to the semiconductor package process into semiconductor chips has been proposed.
  • the wafer level package According to the wafer level package, a printed circuit board is unnecessary, so that the overall thickness of the semiconductor package can be made thin, and the semiconductor package can be manufactured with a low heat dissipation effect.
  • a method that can further reduce the cost of the semiconductor package process and improve the productivity of the semiconductor package process in using the wafer level package technology.
  • An object of the present invention is to provide a method for manufacturing a semiconductor package that can improve the productivity of the semiconductor package process.
  • the technical idea of the present invention is to arrange a plurality of wafers in a tray, and to form a first insulating layer having an opening exposing pads of the plurality of wafers on the plurality of wafers. Forming a seed metal layer on the first insulating layer, the seed metal layer connected to the pad exposed through the first insulating layer, and contacting a plating jig with at least one point on the seed metal layer.
  • 1 provides a method of manufacturing a semiconductor package comprising the step of forming a metal layer.
  • the semiconductor package can be manufactured by using a wafer level package technology, so that a semiconductor package can be manufactured compact and excellent in heat dissipation efficiency.
  • the semiconductor package process can be performed at the panel level by placing a plurality of wafers in the tray, it is possible to reduce the cost of the semiconductor package process and The productivity of the process can be improved.
  • FIG. 1 is a flowchart illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concept.
  • FIG. 2A is a perspective view of a tray in accordance with some embodiments of the present invention.
  • FIG. 2B is a cross-sectional view of the tray taken along the line IIB-IIB ′ of FIG. 2A, illustrating a plurality of wafers arranged on the tray.
  • FIG 3 is a perspective view of a tray according to some embodiments of the inventive concept.
  • FIG. 4 is a cross-sectional view illustrating a plurality of wafers disposed in a tray according to some embodiments of the inventive concept.
  • FIG. 5 is a cross-sectional view illustrating a plurality of wafers disposed in a tray according to some embodiments of the inventive concept.
  • 6A through 6L are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concept.
  • FIGS. 7A to 7G are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concept.
  • FIGS. 8A to 8C are diagrams conceptually illustrating a plating process in a method of manufacturing a semiconductor package according to some embodiments of the inventive concepts.
  • a method of manufacturing a semiconductor package according to the present invention includes disposing a plurality of wafers in a tray, forming a first insulating layer having an opening exposing pads of the plurality of wafers on the plurality of wafers; Forming a seed metal layer connected to the pad exposed through the first insulating layer on the insulating layer, and contacting a plating jig with at least one point on the seed metal layer to form a first metal layer on the seed metal layer. Forming a step.
  • first and second may be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another.
  • first component may be referred to as the second component, and vice versa, the second component may be referred to as the first component.
  • FIG. 1 is a flowchart illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concept.
  • a method of manufacturing a semiconductor package may include preparing a plurality of wafers (S100), placing a plurality of wafers in a tray (S200), and placing a plurality of wafers on a plurality of wafers. Forming an interconnection structure (S300), separating the plurality of wafers from the tray (S400), and cutting each of the plurality of wafers in package units (S500) may be sequentially performed.
  • the semiconductor substrate may include, for example, silicon (Si).
  • the semiconductor substrate may include a semiconductor element such as germanium (Ge, germanium) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP).
  • the semiconductor substrate may have a silicon on insulator (SOI) structure.
  • the semiconductor substrate may include a buried oxide layer (BOX).
  • the semiconductor substrate may include a conductive region, for example, a well doped with impurities.
  • the semiconductor substrate may have various device isolation structures such as a shallow trench isolation (STI) structure.
  • STI shallow trench isolation
  • the semiconductor device may include various types of individual devices.
  • a plurality of individual devices may be used for various microelectronic devices, for example, metal-oxide-semiconductor field effect transistors (MOSFETs) such as complementary metal-insulator-semiconductor transistors, CMOS systems, and large scale integration. ), Image sensors such as CMOS imaging sensors (CIS), micro-electro-mechanical systems (MEMS), active devices, passive devices, and the like.
  • the plurality of individual devices may be electrically connected to the conductive region of the semiconductor substrate.
  • the semiconductor device may further include at least two of the plurality of individual devices or conductive wires or conductive plugs electrically connecting the plurality of individual devices with the conductive region of the semiconductor substrate.
  • the plurality of individual devices may be electrically separated from other neighboring individual devices by an insulating film.
  • a tray having a structure suitable for placing the plurality of wafers (for example, see 100 of FIG. 2A) is prepared, and the plurality of wafers are disposed at a predetermined position of the tray. Wafers are placed.
  • the tray may have a plurality of cavities that can accommodate the plurality of wafers to facilitate placement of the plurality of wafers.
  • the top surface of the padded wafer may face upwards and the bottom surface opposite the top surface of the wafer may contact the surface of the tray.
  • step S300 of forming an interconnection structure on the plurality of wafers the interconnection structure is simultaneously formed for the plurality of wafers arranged in the tray.
  • the interconnection structure (see 200 of FIG. 6K) may refer to a structure formed on the wafer to electrically connect the pad of the semiconductor element formed on the wafer and the external device. Forming an interconnection structure on the wafers will be described in more detail in the following description of FIGS. 6B-6J.
  • the plurality of wafers are separated from the tray.
  • Each of the plurality of wafers separated from the tray may be a semiconductor package in the form of a wafer level package including an interconnection structure formed thereon. Separating the plurality of wafers from the tray will be described in more detail in the following description of FIG. 6K.
  • each of the plurality of wafers is cut in a package unit, and a sawing process is performed on a wafer-level semiconductor package separated from a tray, thereby cutting the wafer-level semiconductor package into a plurality of package units. Can be singulated into semiconductor packages.
  • the semiconductor package can be manufactured by using a wafer level package technology, so that a semiconductor package can be manufactured compact and excellent in heat dissipation efficiency.
  • At least a portion of the unit processes of the semiconductor package process may be performed at a panel level by placing a plurality of wafers in a tray. Therefore, since the semiconductor package process can be performed on a plurality of wafers at the same time, the semiconductor package process can be simplified and productivity can be improved.
  • FIG. 2A is a perspective view of a tray 100 in accordance with some embodiments of the present invention.
  • FIG. 2B is a cross-sectional view of the tray 100 taken along line IIB-IIB ′ of FIG. 2A, and illustrates a state in which a plurality of wafers 10 are disposed on the tray 100.
  • the tray 100 has a plate shape and may include a body 110 and a plurality of cavities 120.
  • the tray 100 may have a sufficient horizontal area so that the plurality of wafers 10 may be disposed at the same time.
  • the tray 100 may support the plurality of wafers 10 during the semiconductor package process of the plurality of wafers 10.
  • the outer edge of the tray 100 may have a rectangular shape as shown in FIG. 2A, but the shape of the outer edge of the tray 100 is not limited thereto.
  • the body 110 constitutes an overall appearance of the tray 100, and like the tray 100, may have a planar surface sufficient to simultaneously arrange a plurality of wafers 10.
  • the plurality of cavities 120 may provide a space in which the plurality of wafers 10 may be accommodated, respectively. That is, the cavity 120 may refer to a recessed area provided in the body 110, and may include a bottom surface facing the bottom surface of the wafer 10 and a sidewall facing the side of the wafer 10. Can be.
  • the plurality of cavities 120 may have a shape corresponding to the wafer 10.
  • the cavities 120 may have a circular shape.
  • 2A and 2B although the plurality of cavities 120 are shown to have substantially the same dimensions, the dimensions of the plurality of cavities 120, such as the horizontal area of each of the plurality of cavities 120 and / or Alternatively, the depths 120h may be different from each other.
  • the number of cavities 120 formed in one tray 100 may be two, three, or five or more.
  • the tray 100 may include a notch 130.
  • the notch 130 may be disposed in each of the plurality of cavities 120, and for example, may be disposed on the sidewall of the cavity 120.
  • the notch 130 may be provided to position the wafer 10 at a predetermined position of the tray 100. Through the notch 130, the wafer 10 may be aligned in a predetermined direction in the cavity 120. In some embodiments, notch 130 may contact the notch of wafer 10 to secure wafer 10 within cavity 120.
  • the tray 100 may include an align mark 140.
  • the alignment mark 140 may be disposed around each of the plurality of cavities 120 on the upper surface 111 of the body 110.
  • the alignment mark 140 may be provided to position the wafer 10 at a predetermined position of the tray 100.
  • semiconductor manufacturing equipment for performing a plurality of unit processes during the semiconductor package process may use the alignment mark 140 to recognize the position of the wafer 120 and / or the wafer 10 disposed in the cavity 120. Can be.
  • the wafer 10 has a cavity 120 such that the top surface 11 on which the pad 13 is formed faces upward and the bottom surface opposite to the top surface 11 faces the bottom surface of the cavity 120.
  • a cavity 120 such that the top surface 11 on which the pad 13 is formed faces upward and the bottom surface opposite to the top surface 11 faces the bottom surface of the cavity 120.
  • the horizontal width of the cavity 120 for example, the horizontal width across the diameter of the cavity 120, may be greater than the horizontal width of the wafer 10, such that the sidewalls of the cavity 120 and the edges of the wafer 10 are predetermined.
  • Distance 190 may be spaced apart.
  • the distance 190 between the sidewall of the cavity 120 and the edge of the wafer 10 may be an insulating layer (eg, a lamination method) on the surface of the plurality of wafers 10 and the tray 100.
  • insulating layer eg, a lamination method
  • 211 of FIG. 6B may be appropriately adjusted so that the space 120S between the sidewall of the cavity 120 and the edge of the wafer 10 is not filled by the insulating layer.
  • the depth 120h of the cavity 120 may be substantially the same as the thickness 10h of the wafer 10.
  • the upper surface 111 of the body 110 may have the same level as the upper surface 11 of the wafer 10.
  • the layer can be formed with almost no stepped portion.
  • At least a part of the manufacturing process of the semiconductor package is made with the plurality of wafers 10 arranged on the tray 100, so that the tray 100 is formed of a material having chemical resistance and heat resistance. Can be done.
  • tray 100 may be comprised of a metallic material, such as iron, nickel, cobalt, titanium, or an alloy containing them.
  • tray 100 may be composed of a ceramic material, such as alumina or silicon carbide.
  • tray 100 may be comprised of carbon fiber.
  • the tray 100 may be composed of a prepreg, which is an insulator, for example, the tray 100 penetrates a thermosetting resin into a reinforcing fiber before being molded to B-stage (the semi-cured state of the resin). It may be composed of a cured material.
  • FIG. 3 is a perspective view of a tray 100a according to some embodiments of the inventive concept.
  • the tray 100a illustrated in FIG. 3 may have a configuration substantially the same as that of the tray 100 illustrated in FIGS. 2A and 2B except that the plurality of cavities 120a and 120b have different horizontal widths. have.
  • the same reference numerals as in Figs. 2A and 2B denote the same members, and detailed description thereof will be omitted or simplified here.
  • the tray 100a may include a first cavity 120a and a second cavity 120b having different horizontal widths.
  • the diameter of the first cavity 120a may be larger than the diameter of the second cavity 120b. Since the tray 100a includes a first cavity 120a and a second cavity 120b having different horizontal widths, wafers having different diameters may be simultaneously mounted on the tray 100a. Therefore, using the tray 100a, the semiconductor package process may be simultaneously performed on wafers having different diameters.
  • the tray 100a is illustrated as including cavities having two horizontal widths, but may also include cavities having three or more horizontal widths.
  • FIG. 4 is a cross-sectional view illustrating a plurality of wafers 10 disposed on a tray 100b according to some embodiments of the inventive concept.
  • the tray 100b shown in FIG. 4 may have substantially the same configuration as the tray 100 shown in FIGS. 2A and 2B except for the depth 120ha of the cavity 120a.
  • the same reference numerals as in Figs. 2A and 2B denote the same members, and detailed description thereof is omitted or simplified here.
  • the depth 120ha of the cavity 120a provided in the tray 100b may be smaller than the thickness 10h of the wafer 10.
  • the wafer 10 when the wafer 10 is disposed in the cavity 120a, at least a portion of the wafer 10 may protrude from the top surface 111a of the body 110a. That is, when the wafer 10 is disposed in the cavity 120a, the upper surface 111a of the body 110a may be located at a level lower than the upper surface 11 of the wafer 10.
  • the tray 100b may include a notch portion (see 130 of FIG. 2A) disposed on the sidewall of the cavity 120a and / or an alignment mark disposed on the upper surface 111a of the body 110a (FIG. 2A). 140).
  • the insulating layer (for example, see 211 of FIG. 6B) to be formed may be formed to have a step at a portion adjacent to the edge of the wafer 10. In addition, the insulating layer may be formed to cover a portion of the side surface of the wafer 10.
  • FIG. 5 is a cross-sectional view illustrating a plurality of wafers 10 disposed on a tray 100c according to some embodiments of the inventive concept.
  • the tray 100c illustrated in FIG. 5 may have a configuration substantially the same as that of the tray 100 illustrated in FIGS. 2A and 2B except that the cavity is not formed.
  • the same reference numerals as in Figs. 2A and 2B denote the same members, and detailed description thereof will be omitted or simplified here.
  • the tray 100c may provide a flat upper surface 111b on which a plurality of wafers 10 may be disposed.
  • the plurality of wafers 10 may be located at predetermined positions on the upper surface 111b of the body 110b, respectively.
  • the tray 100c may include an alignment mark (see 140 of FIG. 2A) disposed on the top surface 111b of the body 110b.
  • an insulating layer formed along the surface of the tray 100c and the surface of the wafer 10 may be formed of the tray 100c.
  • the upper surface 111b may be covered and at least a portion of the upper surface 11 and the side surfaces of the wafer 10 may be covered.
  • the wafer 10 disposed in the tray 100c may be fixed during the semiconductor package process.
  • 6A through 6L are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concept. 6A to 6L, a method of manufacturing a semiconductor package using the tray 100 shown in FIGS. 2A and 2B will be described.
  • a plurality of wafers 10 are disposed in the tray 100.
  • Each of the plurality of wafers 10 may be arranged to be accommodated in different cavities 120 provided in the tray 100.
  • the wafer 10 may be disposed in the cavity 120 so that the top surface 11 of the wafer 10 on which the pad 13 is formed is exposed upward.
  • the wafer 10 may be disposed in the cavity 120 so that the bottom surface opposite to the top surface 11 faces the bottom surface of the cavity 120.
  • the active surface of the wafer 10 may be exposed and the inactive surface of the wafer 10 may be in contact with the surface of the tray 100.
  • the wafer 10 may be disposed in the cavity 120 to be spaced apart from the sidewall of the cavity 120. As the side surface of the wafer 10 and the side wall of the cavity 120 are spaced apart from each other, a space 120S may be formed between the side surface of the wafer 10 and the side wall of the cavity 120.
  • the depth of the cavity 120 may be substantially the same as the thickness of the wafer 10, thus the top surface 11 and the body 110 of the wafer 10 disposed in the cavity 120.
  • the top surface 111 of) may have the same height level.
  • the present invention is not limited thereto, and when the wafer 10 is disposed in the cavity 120, the upper surface of the body 110 may have a height level different from that of the upper surface 11 of the wafer 10.
  • the upper surface of the body 110 may have a lower level than the upper surface 11 of the wafer 10.
  • a first insulating layer 211 is formed on the tray 100 and the plurality of wafers 10.
  • the first insulating layer 211 may be formed to have an opening 211H through which at least a portion of the pad 13 may be exposed.
  • the first insulating layer 211 may cover the upper surface 111 of the body 110 and the upper surface 11 of the plurality of wafers 10.
  • the first insulating layer 211 may function to fix the wafer 10 disposed in the cavity 120 during the subsequent process.
  • the first insulating layer 211 may cover the space 120S between the wafer 10 and the sidewall of the cavity 120.
  • the space 120S between the wafer 10 and the sidewall of the cavity 120 may be sealed by the first insulating layer 211.
  • the first insulating layer 211 may cover the space 120S between the sidewalls of the wafer 10 and the cavity 120 while the interconnection structure is formed, thereby preventing foreign matter from entering the space 120S. .
  • the first insulating layer 211 is formed to cover the top of the space 120S between the side of the wafer 10 and the sidewall of the cavity 120, wherein the side and the cavity of the wafer 10 are covered.
  • the material constituting the first insulating layer 211 may not be filled in the space 120S between the sidewalls of the 120. Since the material constituting the first insulating layer 211 is not filled in the space 120S between the side surface of the wafer 10 and the side wall of the cavity 120, the wafer 10 may be easily separated from the tray 100 in the future. Can be.
  • the first insulating layer 211 may be formed by a laminating method.
  • the first insulating layer 211 may include a photosensitive material. More specifically, in order to form the first insulating layer 211, the photosensitive film is attached to the upper surface 111 of the body 110 and the upper surface 11 of the plurality of wafers 10, and then exposed and developed. A portion of the photosensitive film may be removed to expose the pad of the wafer 10 through the process.
  • the first insulating layer 211 may include a non-photosensitive material.
  • the non-photosensitive film is attached to the upper surface 111 of the body 110 and the upper surface 11 of the plurality of wafers 10, and then the wafer is processed with a laser cutting device. A portion of the non-photosensitive film can be removed so that the pad of (10) is exposed.
  • the first insulating layer 211 may be made of a polymer material such as, for example, polyimide.
  • the first insulating layer 211 may be formed by a spin-coating method.
  • the seed metal layer 221a covering the surface of the pad 13 exposed through the opening 211H of the first insulating layer 211 and the opening of the first insulating layer 211 is formed.
  • the seed metal layer 221a may be deposited by, for example, a sputtering method, but a method of forming the seed metal layer 221a is not limited thereto.
  • the seed metal layer 221a may include, for example, any one of Ti, Cu, Ni, Al, Pt, Au, Ag, W, Ta, Co, or a combination thereof.
  • a first mask pattern 290 having a first mask opening 290H is formed on the seed metal layer 221a. A portion of the seed metal layer 221a may be exposed by the first mask opening 290H.
  • the first mask pattern 290 may be formed by, for example, forming a photosensitive material layer on the seed metal layer 221a and then patterning the photosensitive material layer using photolithography.
  • a photolithography process an exposure mask having a predetermined pattern may be used, and a laser light source such as KrF or ArF may be used.
  • the first mask pattern 290 may be formed by a laminating method. For example, after attaching the photosensitive film on the seed metal layer 221a to cover the seed metal layer 221a, a first mask opening 290H exposing a portion of the seed metal layer 221a through an exposure and development process may be formed. Can be.
  • a first metal layer 223 filling at least a portion of the first mask opening 290H is formed.
  • the first metal layer 223 may be formed to cover the surface of the seed metal layer 221a exposed through the first mask opening 290H.
  • the first metal layer 223 may be formed by, for example, a plating method.
  • the first metal layer 223 may be made of copper.
  • the first metal layer 223 may be formed by a plating method using the seed metal layer 221a as a seed.
  • the first metal layer 223 may be formed by immersion plating, electroless plating, electroplating, or a combination thereof.
  • the tray 100 on which the plurality of wafers 10 are disposed is immersed in the plating bath 500, and the plating jig 520 is at least formed on the seed metal layer 221a.
  • One point 280 may be contacted.
  • the power supply 510 applies a voltage to the plating jig 520, the first metal layer is formed on the surface of the seed metal layer 221a exposed through the first mask opening 290H. 223 may be formed.
  • the seed metal layer 221a may be plated.
  • the portion of the seed metal layer 221a of the region vertically overlapped with the plurality of wafers 10 is electrically connected to the point 280 where the plating jig 520 is in contact, and thus is perpendicular to the plurality of wafers 10.
  • the first metal layer 223 may be plated on the seed metal layer 221a of the overlapped region.
  • a point 280 on the seed metal layer 221a that the plating jig 520 contacts may be spaced in a peripheral direction from a portion of the seed metal layer 221a on the plurality of wafers 10.
  • a point 280 on the seed metal layer 221a to which the plating jig 520 contacts may be spaced in a peripheral direction from a predetermined region of the seed metal layer 221a vertically overlapped with the plurality of wafers 10.
  • the point 280 on the seed metal layer 221a that the plating jig 520 contacts may be spaced apart from the cavity 120 in the circumferential direction.
  • the plating process may be simplified more than the plating process by contacting the plating jig 520 to a portion of the seed metal layer 221a on the plurality of wafers 10.
  • Each may have a generally uniform thickness.
  • the depth of the cavity 120 is substantially the same as the thickness of the wafer 10 accommodated in the cavity 120, in the vicinity of the space between the sidewall of the cavity 120 and the wafer 10 accommodated in the cavity 120.
  • the seed metal layer 211a may be parallel to the top surface 111 of the tray 100.
  • the thickness of the portion of the seed metal layer 221a on the space between the sidewall of the cavity 120 and the wafer 10 accommodated in the cavity 120 may be equal to the thickness of the portion of the seed metal layer 221a on the plurality of wafers 10. May be substantially the same.
  • the power applied from the plating jig 520 to at least one point 280 on the seed metal layer 221a is more uniform throughout the seed metal layer 221a. Can be delivered.
  • a point 280a on the seed metal layer 221a to which the plating jig 520 contacts is located in a portion of the seed metal layer 221a on the plurality of wafers 10. can do.
  • a point 280a on the seed metal layer 221a to which the plating jig 520 contacts may be located in a predetermined region of the seed metal layer 221a vertically overlapping the plurality of wafers 10.
  • the plating jig 520 When the plating jig 520 is brought into contact with a point 280a in the portion of the seed metal layer 221a on the plurality of wafers 10 and power is applied to the plating jig 520, the seeds on each of the plurality of wafers 10 are provided. Since the regions of the metal layer 221a are electrically connected to each other, the first metal layer 223 may be formed on portions of the seed metal layer 221a on the plurality of wafers 10.
  • portions of the seed metal layer 221a of FIG. 6G under the first mask pattern 290 and the first mask pattern 290 are removed from the resultant of FIG. 6E. do.
  • An ashing or strip process may be used to remove the first mask pattern 290.
  • a chemical etching method may be used to remove a portion of the seed metal layer 221a of FIG. 6G under the first mask pattern 290.
  • the first metal layer 223 and the seed metal layer 221 may be integrally coupled to each other, and may constitute a distribution layer 220.
  • a second insulating layer 213 covering the first metal layer 223 is formed, and then a second metal layer 225 penetrating through the second insulating layer 213 and connected to the first metal layer 223.
  • the first insulating layer 211, the wiring layer 220, the second insulating layer 213, and the second metal layer 225 may constitute the interconnection structure 200a.
  • the second insulating layer 213 may be formed by a laminating method similar to the first insulating layer 211 described with reference to FIG. 6B.
  • the second insulating layer 213 may include a photosensitive material or may include a non-photosensitive material.
  • the second metal layer 225 may be an under bump metal (UBM). In other embodiments, the second metal layer 225 may be omitted.
  • UBM under bump metal
  • an external connection terminal 400 is formed on the second metal layer 225.
  • the external connection terminal 400 may be, for example, solder balls or solder bumps.
  • the external connection terminal 400 may be configured to electrically connect the semiconductor package and the external device.
  • the external connection terminal 400 may be electrically connected to the pad 13 of the wafer 10 through the seed metal layer 221, the first metal layer 223, and the second metal layer 225. Meanwhile, when the second metal layer 225 is omitted, the external connection terminal 400 may be attached to the first metal layer 223 exposed by the second insulating layer 213.
  • a portion of the structure stacked on the tray 100 and / or the plurality of wafers 10 may be removed.
  • the material remaining between the sidewall and the wafer 10 accommodated in the cavity 120 may be removed.
  • a separation lane 250 may be formed in the interconnection structure 200.
  • the separation lane 250 may vertically penetrate the first insulating layer 211 and the second insulating layer 213, and may be formed along an edge portion of each of the plurality of wafers 10.
  • the separation lane 250 may have a ring shape when viewed from the top.
  • the separation lane 250 the space 120S between the sidewall of the cavity 120 and the edge of the wafer 10 may be exposed upward.
  • a portion of the edge region of the wafer 10 and / or a portion of the surface of the tray 100 may be exposed.
  • the separation lane 250 the wafer-level semiconductor packages including the wafer 10 and the interconnection structure 200 on the wafer 10 may be separated from each other.
  • the separation lane 250 may be formed through, for example, a laser drilling method.
  • the wafer-level semiconductor package 1 is separated from the tray, and the wafer-level semiconductor package 1 is singulated into semiconductor packages in a plurality of package units through a sawing process.
  • the sawing blade BL may be cut along the scribe lane SL to separate the wafer-level semiconductor package 1.
  • the semiconductor package 1 at the wafer level can be individualized into semiconductor packages of multiple package units.
  • 7A to 7G are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concept.
  • 7A to 7G a method of manufacturing a semiconductor package using the tray 100c shown in FIG. 5 will be described, and descriptions overlapping with those described with reference to FIGS. 6A to 6L will be omitted or simplified.
  • a plurality of wafers 10 are disposed on the tray 100c.
  • Each of the wafers 10 may have an upper surface 11 on which a pad 13 is formed, and a lower surface opposite to the upper surface 11 may face the surface of the tray 100c.
  • an alignment mark (see 140 of FIG. 2A) provided on the tray 100c may be used.
  • a first insulating layer 311 is formed to cover the surface of the tray 100c and the surface of the wafer 10 and have an opening 311H exposing the pad 13 of the wafer 10. . Since the upper surface 11 of the wafer 10 has a higher level than the surface of the tray 100c, the first insulating layer 311 may be formed to have a stepped shape. The first insulating layer 311 may fix the plurality of wafers 10 at a predetermined position on the tray 100c during a subsequent process.
  • the seed metal layer 3 may be disposed on the pad 13 of the wafer 10 exposed between the first insulating layer 311 and the opening 311H of the first insulating layer 311.
  • 321a is formed, and a second mask pattern 390 having a second mask opening 3900H is formed on the seed metal layer 321a.
  • the tray 100c on which the plurality of wafers 10 are disposed is immersed in the plating bath 500, and the plating jig 520 is disposed on the seed metal layer 321a. At least one point 380 may be contacted. Subsequently, when the power supply unit 510 applies a voltage to the plating jig 520, the first metal layer 323 may be formed on the surface of the seed metal layer 321a exposed through the first mask opening 390H. .
  • At least one point 380 on the seed metal layer 321a to which the plating jig 520 contacts is formed from a portion of the seed metal layer 321a on the plurality of wafers 10. It may be spaced apart in the peripheral direction. That is, the plating jig 520 may be positioned on an area other than an area in which the plurality of wafers 10 are disposed among the upper surfaces 111b of the tray 100c.
  • At least one point 380a on the seed metal layer 321a to which the plating jig 520 is in contact may be a seed metal layer 321a on the plurality of wafers 10. ) May be located within the part.
  • the first mask pattern 390 and portions of the seed metal layer 321a below the first mask pattern 390 are removed.
  • the second insulating layer 313, the second metal layer 323, and the external connection terminal 400 may be sequentially formed through the same process as described with reference to FIGS. 6I and 6J.
  • a portion of the interconnection structure 300a of FIG. 7E is removed along the edges of the plurality of wafers 10 to form a separation lane 350.
  • a portion and a portion of the first insulating layer 311 may be removed.
  • the semiconductor package of the wafer level including the wafer 10 and the interconnection structure 300 on the wafer 10 may be separated from each other by the separation lane 350.
  • the wafer-level semiconductor packages may be separated from the tray 100c.
  • Each of the separated wafer-level semiconductor packages may be individualized into semiconductor packages in a plurality of package units through a sawing process.
  • a plurality of unit processes of the semiconductor package process may be performed using a tray capable of supporting a plurality of wafers. That is, the semiconductor package process is performed by placing a plurality of wafers in a tray, so that a plurality of wafer-level semiconductor packages can be manufactured at the panel level. Therefore, according to the technical concept of the present invention, since the semiconductor package process for a plurality of wafers can be performed at the same time, productivity can be improved.
  • 8A to 8C are diagrams conceptually illustrating a plating process in a method of manufacturing a semiconductor package according to some embodiments of the inventive concepts.
  • 8A to 8C illustrations of the wafer disposed on the tray, the tray and the structure formed on the wafer will be omitted for convenience of description.
  • a part of the manufacturing method of the semiconductor package using the tray 100 shown in FIGS. 2A and 2B will be described.
  • the number of points 280b where the plating jig 520 contacts the seed metal layer may be smaller than the number of wafers disposed in the tray 100.
  • the plating jig 520 has two points 280b on the top surface 111 of the tray 100. ) May be applied to the seed metal layer for the plating process.
  • the two points 280b where the plating jig 520 contacts the seed metal layer may be spaced apart from the upper surface 111 of the tray 100 in the circumferential direction of the region where the wafer is disposed. That is, the two points 280b may be spaced apart from the upper surface 111 of the tray 100 in the circumferential direction of the cavity 120. In addition, the two points 280b may be adjacent to two different corner portions of the upper surface 111 of the tray 100.
  • the two points 280c where the plating jig 520 contacts the seed metal layer are located at the top surface 111 of the tray 100 where the wafer is placed. It may be spaced apart in the peripheral direction, and may be adjacent to the center of the edge of the upper surface 111 of the tray 100.
  • the number of points 280d where the plating jig 520 contacts the seed metal layer may be the same as the number of wafers disposed in the tray 100.
  • the plating jig 520 contacts four points 280d on the top surface 111 of the tray 100 to supply power for the plating process. It may be applied to the seed metal layer.
  • each of the four points 280d is a wafer accommodated in the four cavities 120.
  • a power source for the plating process may be applied to the seed metal layer formed on each of them.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

L'invention concerne un procédé de production d'un boîtier de semi-conducteur, le procédé selon le concept technique de la présente invention comprenant les étapes consistant à : agencer une pluralité de plaquettes sur un plateau ; former, sur la pluralité de plaquettes, une première couche d'isolation ayant des ouvertures qui mettent à nu les pastilles de la pluralité de plaquettes ; former, sur la première couche d'isolation, une couche de métal d'injection qui se connecte aux pastilles mises à nu par la première couche d'isolation ; et former une première couche métallique sur la couche de métal d'injection par mise en contact d'un gabarit de placage avec au moins un point sur celui-ci.
PCT/KR2017/004825 2017-01-17 2017-05-10 Procédé de production d'un boîtier de semi-conducteur WO2018135706A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/505,970 US10804146B2 (en) 2017-01-17 2019-07-09 Method for producing semiconductor package

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2017-0008190 2017-01-17
KR20170008190 2017-01-17
KR1020170053560A KR101901988B1 (ko) 2017-01-17 2017-04-26 반도체 패키지의 제조 방법
KR10-2017-0053560 2017-04-26

Related Parent Applications (1)

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PCT/KR2017/004829 Continuation WO2018135707A1 (fr) 2017-01-17 2017-05-10 Support plan pour produire un boîtier de semi-conducteur

Related Child Applications (2)

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PCT/KR2017/004824 Continuation WO2018135705A1 (fr) 2017-01-17 2017-05-10 Procédé de production de boîtier de semi-conducteur
PCT/KR2017/004830 Continuation WO2018135708A1 (fr) 2017-01-17 2017-05-10 Procédé de production d'un boîtier de semi-conducteur

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WO2018135706A1 true WO2018135706A1 (fr) 2018-07-26

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020022600A (ko) * 2000-09-20 2002-03-27 마에다 시게루 기판도금장치 및 도금방법
KR20120138517A (ko) * 2011-06-15 2012-12-26 삼성전자주식회사 칩 고정 장치 및 이를 이용한 칩의 테스트 방법
JP2015504608A (ja) * 2011-11-22 2015-02-12 日本テキサス・インスツルメンツ株式会社 マイクロ表面実装デバイスパッケージング
KR20150065544A (ko) * 2013-12-05 2015-06-15 심기준 반도체 칩의 전기적 연결 구조 및 방법
KR20170003352A (ko) * 2015-06-30 2017-01-09 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 3ｄ 패키지 구조 및 그 형성 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020022600A (ko) * 2000-09-20 2002-03-27 마에다 시게루 기판도금장치 및 도금방법
KR20120138517A (ko) * 2011-06-15 2012-12-26 삼성전자주식회사 칩 고정 장치 및 이를 이용한 칩의 테스트 방법
JP2015504608A (ja) * 2011-11-22 2015-02-12 日本テキサス・インスツルメンツ株式会社 マイクロ表面実装デバイスパッケージング
KR20150065544A (ko) * 2013-12-05 2015-06-15 심기준 반도체 칩의 전기적 연결 구조 및 방법
KR20170003352A (ko) * 2015-06-30 2017-01-09 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 3ｄ 패키지 구조 및 그 형성 방법

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