WO2018133415A1 - 一种物理编码子层的数据编解码方法和装置、存储介质 - Google Patents

一种物理编码子层的数据编解码方法和装置、存储介质 Download PDF

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Publication number
WO2018133415A1
WO2018133415A1 PCT/CN2017/099355 CN2017099355W WO2018133415A1 WO 2018133415 A1 WO2018133415 A1 WO 2018133415A1 CN 2017099355 W CN2017099355 W CN 2017099355W WO 2018133415 A1 WO2018133415 A1 WO 2018133415A1
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data
field
block
decoding
encoding
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PCT/CN2017/099355
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English (en)
French (fr)
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任伟丽
张艳阳
史光明
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深圳市中兴微电子技术有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0023—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the signalling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0033—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0046—Code rate detection or code type detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0075—Transmission of coding parameters to receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0079—Formats for control data

Definitions

  • the present invention relates to a high performance chip design technique, and in particular, to a data encoding and decoding method and apparatus for a physical coding sublayer, and a computer storage medium.
  • Ethernet is a baseband LAN technology developed by Xeros. It is divided into 7 layers according to its functions.
  • the physical layer is the lowest layer, which defines the coding and line status required for data transmission and reception.
  • the Physical Coding Sublayer (PCS) mainly implements an encoding function and a decoding function.
  • the PCS layer has the following characteristics:
  • the block type field is 8 bits, and 15 cases are encoded.
  • PCS layer data transmission is forward error correction (FEC, Forward Error Correction) function to ensure data transmission reliability, but the FEC structure is complex, if the link state is relatively stable, you can not use the FEC function, but this transmission The data will not undergo any verification, and even if the receiving end receives the data information of the transmission error, there will be no alarm.
  • FEC Forward Error Correction
  • the Ethernet flow control mechanism sends a flow control packet through the sub-layer of the Medium Access Control (MAC), parses the packet at the receiving end, and proceeds according to the analysis result. Line control.
  • MAC Medium Access Control
  • the information exchange between the two ends of the Ethernet link is carried out by means of grouping, which lacks the flexibility and real-time of information interaction.
  • the block type field is 8 bits, 15 cases of block type are encoded, and the 8 bit field is not fully utilized; when the FEC function is not used, data is not protected during data transmission.
  • the flow control packet of Ethernet occupies the system bandwidth, and the transmitted information needs to go through grouping and unpacking operations, and there is a certain delay; the information interaction at both ends of the link lacks flexibility and real-time.
  • the embodiments of the present invention provide a data encoding and decoding method and apparatus for a physical coding sublayer, which solves the problem that the 8-bit coding of the block type field existing in the prior art is not fully utilized, and the FEC function is not used.
  • the next data has no problems such as defects in verification protection.
  • An embodiment of the present invention provides a data encoding and decoding method of a physical coding sublayer, where the method includes:
  • the first data After receiving the first data by the data encoding side of the physical coding sublayer, the first data is divided into a data block and a control block, and the data block is encoded according to a protocol; for the control block, the block type field is corresponding to The bit is divided into a first field and a second field, the first field is encoded according to a block type identifier, and the second field is encoded according to configuration information of a sending end of the first data;
  • the data decoding side of the physical coding sublayer determines that the second data is a data block or a control block, and if the second data is a data block, performs decoding according to the protocol;
  • the second data is a control block, and is decoded according to configuration information of the transmitting end of the second data.
  • the method further includes:
  • a first sync header is filled in front of the block of the data block, and a second sync header is filled in front of the block of the control block.
  • the second field is encoded according to the configuration information of the sending end of the first data, including:
  • Determining configuration information of the transmitting end of the first data encoding the second field into a cyclic redundancy check code of a payload field according to the determined configuration information, and encoding the second field into a real-time buffer register Status information, encoding the second field as a command to reset the peer, encoding the second field as an event command, or encoding the second field as a pre-set other extended function.
  • the determining that the second data is a data block or a control block includes:
  • the synchronization header of the data is a second synchronization header, and the second data is determined to be a control block.
  • the decoding according to the configuration information of the sending end of the second data, includes:
  • Determining configuration information of the transmitting end of the second data decoding the second field into a cyclic redundancy check code of the payload field according to the determined configuration information, and decoding the second field into a peer receiving end buffer register Real-time status information, decoding the second field to a command that the peer requires the local end to reset, decoding the second field as an event command, or decoding the second field into a preset other extended function.
  • An embodiment of the present invention provides a data encoding and decoding apparatus for an Ethernet physical coding sublayer, where the apparatus includes: an encoding module and a decoding module;
  • the encoding module is configured to divide the first data into data after receiving the first data a block and a control block for encoding the data block according to a protocol; for the control block, dividing a bit corresponding to the block type field into a first field and a second field, the first field according to the block type identifier Encoding, the second field is encoded according to configuration information of the sending end of the first data;
  • the decoding module is configured to: after receiving the second data, determine that the second data is a data block or a control block, and if the second data is a data block, perform decoding according to the protocol; if the second The data is a control block, and is decoded according to the configuration information of the transmitting end of the second data.
  • the encoding module is further configured to: fill a first synchronization header in front of the block of the data block, and fill a second synchronization header in front of the block of the control block.
  • the coding module is specifically configured to: determine configuration information of the sending end of the second data, and encode the second field into a cyclic redundancy check code of the payload field according to the determined configuration information,
  • the second field is encoded as real-time status information of the receiving end buffer register, encoding the second field as a command to reset the peer, encoding the second field as an event command, or encoding the second field as a pre-set Other extended features.
  • the decoding module is configured to: determine, according to the synchronization header of the second data, that the second data is a data block or a control block, and if the synchronization header of the second data is the first synchronization header, Determining that the second data is a data block; if the synchronization header of the data is a second synchronization header, determining that the second data is a control block.
  • the decoding module is specifically configured to: determine configuration information of the sending end of the second data, and decode the second field into a cyclic redundancy check code of the payload field according to the determined configuration information, Decoding the second field into real-time status information of the buffer of the peer receiving end buffer, decoding the second field into a command for the local end to request local reset, decoding the second field into an event command, or The two fields are decoded into other extended functions preset.
  • the encoding module and the decoding module may use a central processing unit (CPU, when performing processing). Central Processing Unit), Digital Signal Processor (DSP), or Field-Programmable Gate Array (FPGA).
  • CPU central processing unit
  • DSP Digital Signal Processor
  • FPGA Field-Programmable Gate Array
  • a computer storage medium according to an embodiment of the present invention, wherein a computer program for executing a data encoding and decoding method of the physical coding sublayer is stored.
  • the data encoding and decoding method of the physical coding sublayer includes: after receiving the first data by the data encoding side of the physical coding sublayer, dividing the first data into a data block and a control block, a data block, encoded according to a protocol; for the control block, the bit corresponding to the block type field is divided into a first field and a second field, the first field is encoded according to a block type identifier, the second field Encoding according to the configuration information of the sending end of the first data; after receiving the second data by the data decoding side of the physical coding sublayer, determining that the second data is a data block or a control block, if the second data is The data block is decoded according to the protocol; if the second data is a control block, decoding is performed according to configuration information of the transmitting end of the second data.
  • the utilization of the block type field coding is improved, the check bit of the transmission data can be increased by the corresponding configuration information, and the reliability of the data transmission is improved; the real-time status information of the buffer register of the receiving end can be embedded in the control.
  • the symbol solves the problem that the Ethernet link layer flow control occupies the transmission bandwidth and delay; the PCS function can be extended to increase the remote reset; the predefined event command can be added to increase the flexibility of interaction between the two ends.
  • FIG. 1 is a schematic flowchart of a data encoding and decoding method of a physical coding sublayer according to an embodiment of the present invention
  • FIG. 2 is a schematic flowchart of a data encoding method of a physical coding sublayer according to an embodiment of the present invention
  • FIG. 3 is a schematic flowchart of a data decoding method of a physical coding sublayer according to an embodiment of the present disclosure
  • 4 is a schematic diagram of mapping of 64B/66B coding in the original protocol
  • FIG. 5 is a schematic diagram of mapping of 64B/66B encoding according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a data encoding and decoding apparatus of a physical coding sublayer according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a data encoding and decoding system of a physical coding sublayer according to an embodiment of the present invention.
  • the first data is divided into a data block and a control block, and the data block is encoded according to a protocol;
  • the control block divides a bit corresponding to the block type field into a first field and a second field, where the first field is encoded according to a block type identifier, and the second field is according to a sending end of the first data.
  • the configuration information is encoded; after the data decoding side of the physical coding sublayer receives the second data, it is determined that the second data is a data block or a control block, and if the second data is a data block, the protocol is performed according to the protocol. Decoding; if the second data is a control block, decoding is performed according to configuration information of the transmitting end of the second data.
  • FIG. 1 is a schematic flowchart of a data encoding and decoding method of a physical coding sublayer according to an embodiment of the present invention; as shown in FIG. 1, the method includes:
  • Step 101 After receiving the first data by the data encoding side of the physical coding sublayer (PCS), the first data is divided into a data block and a control block; for the data block, mapping is performed according to a protocol; for the control block And dividing a bit corresponding to a block type into a first field and a second field, where the first field is encoded according to a block type identifier, and the second field is configured according to a sending end of the first data.
  • Information is encoded;
  • the first data is data received by the physical coding sublayer from a medium access control layer (MAC);
  • MAC medium access control layer
  • the bit corresponding to the block type is 8 bits.
  • the first field after the division is 4 bits, and the second field is 4 bits.
  • the method further includes:
  • the first synchronization header is used to identify the data block;
  • a second synchronization header is filled in front of the block of the control block, and the second synchronization header is used for Identify the control block.
  • the 64B/66B encoding is applied to an Ethernet system, and the transmitted data can be encoded by a 64B/66B encoder to form data in units of 66 bits.
  • the 66-bit data contains a 2-bit sync character (Sync Header) and a 64-bit Payload field.
  • the 64-bit information is the data information of the MAC frame, the data is called a data block, and the synchronization character can be set to "01"; if the 64-bit information contains control characters such as IPG, the data is called a control block. Its sync character can be set to "10" and the type of 64-bit information is represented by setting a block type.
  • the data block and the control block can be distinguished by determining whether the information contained in the 64-bit information in the first data is the data information of the MAC frame or the control character.
  • the first synchronization header may be represented by a character “01”; the second synchronization header may be represented by a character “10”.
  • the coding is directly performed according to a protocol; here, the protocol is: IEEE Standard for Ethernet protocol.
  • control block 15 cases of the block type are encoded with the first field, that is, 4 bits; the remaining 4 bits are used as the second field for function expansion, and encoding is performed according to the configuration information.
  • the second field is encoded according to the configuration information of the sending end of the first data, and includes:
  • the encoding according to the determined configuration information includes: encoding the second field into a Payload field cyclic redundancy check code, encoding the second field as real-time status information of the receiving end buffer register, The second field is encoded as a command to reset the peer, encode the second field as an event command, or encode the second field as a pre-set other extended function.
  • the configuration information may include any one of the following information: configuration one, configuration two, configuration three, configuration four; for example:
  • the configuration one: encoding 4 bits into a Cyclic Redundancy Check (CRC) code of a Payload field, specifically a CRC-4 check code;
  • CRC Cyclic Redundancy Check
  • the configuration 1 can improve data reliability when the FEC function is not used
  • the configuration 2 encoding 4 bits as real-time status information of a buffer buffer of the receiving end;
  • the real-time status information of the receiving end buffer can be notified by the configuration 2, so that the peer end performs real-time flow control according to the received real-time status information;
  • the configuration 3 encoding 4 bits as a command for resetting the opposite end;
  • the command includes two cases: one, reset interface (reset-port) command, then reset various error statistics and error indication registers of the opposite PCS; second, reset device (reset-device) command, then reset the opposite PCS All registers;
  • the configuration 4 encoding 4 bits as an event command; specifically, may include 16 kinds of event commands, each of which is pre-defined at both ends, and after receiving the event command at the opposite end, performs corresponding operations.
  • the second field is encoded according to the configuration information of the sending end of the first data, and may include:
  • Reading the configuration information determining whether the configuration information is configured one, that is, encoding 4 bits into a CRC-4 check code
  • the configuration information is the configuration one, the 4 bit is encoded into the CRC-4 check code of the Payload field according to the configuration information; otherwise, it is determined whether the configuration information is the configuration 2, that is, the 4 bit encoding is the real time of the receiving end buffer. status information;
  • the configuration information is the configuration 2
  • the 4 bit is encoded as the real-time status information of the receiving end buffer according to the configuration information; otherwise, the configuration information is determined to be the configuration 3, that is, the 4 bit encoding is the command to reset the opposite end;
  • the configuration information is the configuration 3
  • the 4 bit is encoded as the command to reset the peer according to the configuration information; otherwise, it is determined whether the configuration information is the configuration 4, that is, the event command preset by the 4 bit encoding;
  • the 4 bit is encoded into an event command preset at both ends according to the configuration information; otherwise, the 4 bit is encoded as another extended function preset by the user.
  • the configuration information of the transmitting end of the first data is configuration information obtained by software of the transmitting end or software configured by the user for the transmitting end.
  • the data encoding side of the physical coding sublayer may read the configuration information of the transmitting end of the first data when performing 64B/66B encoding, and perform encoding according to the configuration information.
  • Step 102 After receiving the second data, the data decoding side of the physical coding sublayer determines that the second data is a data block or a control block, and if the data is a data block, demap according to a protocol; The second data is a control block, and is decoded according to the configuration information of the transmitting end of the second data.
  • the second data is data received by the physical coding sublayer.
  • the determining the second data is a data block or a control block, including:
  • the data decoding side of the physical coding sublayer reads the synchronization header of the second data, and if the synchronization header is the first synchronization header, it is determined as a data block; if the synchronization header is the second synchronization header, then Determined as a control block.
  • the first synchronization header may be represented by a character “01”; the second synchronization header may be represented by a character “10”.
  • the decoding according to the configuration information of the sending end of the second data includes:
  • the decoding is performed according to the determined configuration information, including:
  • Decoding the second field into a cyclic redundancy check code of the Payload field decoding the second field into real-time status information of the peer receiving end buffer register, and decoding the second field to the peer end requesting local end A reset command, decoding the second field into an event command, or decoding the second field into other extended functions that are preset.
  • the decoding according to the configuration information of the sending end of the second data, specifically includes:
  • the configuration information is configuration five
  • the 4 bit is decoded into the CRC-4 check code of the Payload field, and the correctness of the check is further determined. If the check is correct, the decoding is performed according to the reverse process of the encoding, and the decoding is performed. The information is transmitted to the MAC layer, and if the check is incorrect, it is processed according to the error code; otherwise, it is determined whether the configuration information is the configuration 6, that is, the 4 bit is decoded into the real-time status information of the peer receiving side buffer;
  • the 4 bit is decoded into the real-time status information of the peer receiving side buffer, and the real-time status information of the buffer status field is transmitted to the MAC layer flow control module for flow control; otherwise, the determining unit Whether the configuration information is configuration seven, that is, decoding 4 bits into a command for resetting the opposite end;
  • the 4 bit is decoded into a command that the local end requires the local end to reset; the command includes two cases: one, if the reset-port command is received, the PCS error statistics and error status are obtained. The indicated register is reset; second, if the reset-device command is received, all PCS registers are reset;
  • configuration information is not configuration seven, it is determined whether the configuration information is configuration eight, that is, 4 bits are decoded, and 16 types of pre-defined event commands are defined at both ends;
  • the 4 bit is decoded into a predefined event command at both ends, and the corresponding operation is performed according to the decoded event command; otherwise, the 4 bit is decoded into other extended functions preset by the user.
  • the configuration information of the transmitting end of the second data is configuration information obtained by software of the transmitting end or software configured by the user for the transmitting end.
  • the data decoding side of the physical coding sublayer may read the configuration message of the sending end of the second data, and perform decoding according to the configuration message.
  • the configuration 5, the configuration 6, the configuration 7, and the configuration 8 respectively correspond to the configuration 1, the configuration 2, the configuration 3, and the configuration 4.
  • FIG. 2 is a schematic flowchart of a data encoding method of a physical coding sublayer according to an embodiment of the present invention; as shown in FIG. 2, the coding method includes:
  • Step 201 Receive first data from a MAC layer, and divide the received first data into a data block and a control block.
  • the first sync header is filled in front of the block, here the character "01", and the data block is encoded according to the protocol;
  • the second synchronization header is filled in front of the block, here the character "10", the block type field is encoded as 4 bits, and the remaining 4 bits are encoded according to the configuration information of the data transmitting end, Implement various flexible functions; the remaining Payload fields are mapped according to the protocol;
  • Step 202 Determine whether the configuration information of the sending end of the first data is the configuration one, that is, the 4-bit encoding is the CRC-4 check code of the Payload field.
  • step 203 If the configuration information is configuration one, proceed to step 203; otherwise, proceed to step 204;
  • Step 203 Encode 4 bits into a CRC-4 check code of the Payload field.
  • Step 204 Determine whether the configuration information is configuration 2, that is, 4 bit encoding is real-time status information of the receiving end buffer;
  • step 205 If the configuration information is configuration 2, proceed to step 205, otherwise, proceed to step 206;
  • Step 205 encoding 4 bits into real-time status information of the receiving end buffer
  • Step 206 Determine whether the configuration information is configuration three, that is, the 4-bit encoding is a command to reset the opposite end;
  • step 207 If the configuration information is configuration three, proceed to step 207, otherwise, proceed to step 208;
  • Step 207 encoding 4 bits as a command to reset the opposite end
  • Step 208 Determine whether the configuration information is configuration four, that is, 4 bit encoding 16 kinds of event commands defined in advance by two ends;
  • step 209 If the configuration information is configuration four, proceed to step 209, otherwise, proceed to step 210;
  • Step 209 Encode 4 bits into pre-defined event commands at both ends;
  • Step 210 Encode 4 bits into other extended functions preset by the user.
  • FIG. 3 is a schematic flowchart of a data decoding method of a physical coding sublayer according to an embodiment of the present invention. As shown in FIG. 3, the decoding method includes:
  • Step 301 Receive second data, and identify, according to the synchronization header, the second data as a data block or a control block.
  • the data is sent directly to the MAC layer after the synchronization header is removed;
  • the block type field and the Payload field are decoded according to the encoding information, and the remaining 4 bits are decoded according to the configuration information;
  • Step 302 Determine whether the configuration information is configuration five, that is, decode 4 bits into a CRC-4 check code of the Payload field.
  • step 303 If the configuration information is configuration five, proceed to step 303, otherwise proceed to step 304;
  • Step 303 Decode 4bit into a CRC-4 check code of the Payload field, and determine the correctness of the check. If the check is correct, the decoded information is transmitted to the MAC layer. If the check is incorrect, the error code is processed. , for example: giving an error alarm;
  • Step 304 Determine whether the configuration information is configuration six, that is, decoding 4 bits into real-time status information of the peer receiving side buffer;
  • step 305 If the configuration information is configuration 6, go to step 305, otherwise go to step 306;
  • Step 305 Decode 4 bits into real-time status information of the receiving end buffer, and transmit real-time status information to the flow control module.
  • Step 306 Determine whether the configuration information is configuration seven, that is, decoding 4 bits as a command for resetting the opposite end;
  • step 307 If the configuration information is configuration 7, go to step 307, otherwise go to step 308;
  • Step 307 Decode 4bit into a command for the local end to request local reset. If the reset-port command is received, reset the PCS error statistics and the error status indication register. If the reset-device command is received, reset all PCS register;
  • Step 308 Determine whether the configuration information is configuration eight, that is, decode any one of 16 types of event commands defined in advance by 4 bits;
  • step 309 If the configuration information is configuration eight, proceed to step 309, otherwise proceed to step 310;
  • Step 309 decoding 4 bits into pre-defined event commands at both ends, and performing corresponding operations according to the decoded event commands;
  • Step 310 Decode 4 bits into other extended functions preset by the user.
  • FIG. 4 is a schematic diagram of mapping of 64B/66B coding in the original protocol.
  • data received from the MAC layer is divided into a data block and a control block, and the coding mode of the data block 64B/66B is A 2-bit sync header "01" is added before the block, and the control block is encoded by adding a sync header "10" before the block, and the 8 bits following the sync header are mapped according to the block type and the block payload.
  • FIG. 5 is a schematic diagram of mapping of 64B/66B encoding according to an embodiment of the present invention. As shown in FIG. 5, the difference from the original protocol is that the 8 bit of the block type is divided into two parts, and the first half of the 4 bits are user-defined, and then The half of the 4 bits is the block type encoding information.
  • FIG. 6 is a schematic structural diagram of a data encoding and decoding device of a physical coding sublayer according to an embodiment of the present invention; as shown in FIG. 6, the device includes: an encoding module and a decoding module;
  • the encoding module is configured to, after receiving the first data, divide the first data into a data block and a control block, where the data block is encoded according to a protocol; for the control block, the block type field is corresponding to The bit is divided into a first field and a second field, the first field is encoded according to a block type identifier, and the second field is encoded according to configuration information of a sending end of the first data;
  • the decoding module is configured to: after receiving the second data, determine that the second data is a data block or a control block, and if the second data is a data block, perform decoding according to the protocol; if the second The data is a control block, and is decoded according to the configuration information of the transmitting end of the second data.
  • the encoding module is further configured to: fill a first synchronization header in front of the block of the data block, and fill a second synchronization header in front of the block of the control block.
  • the first sync header may be represented by a character "01”
  • the second sync header may be represented by a character "10”.
  • the coding module is specifically configured to: determine configuration information of the sending end of the second data, and encode the second field into a cyclic redundancy check code of a Payload field according to the determined configuration information, where The second field is encoded as real-time status information of the receiving end buffer register, encoding the second field as a command to reset the peer, encoding the second field as an event command, or encoding the second field to a predetermined Other extensions.
  • the decoding module is configured to: determine, according to the synchronization header of the second data, that the second data is a data block or a control block, and if the synchronization header of the second data is a first synchronization header, determine The second data is a data block; if the synchronization header of the data is a second synchronization header, determining that the second data is a control block.
  • the decoding module is specifically configured to: determine configuration information of the sending end of the second data, and decode the second field into a cyclic redundancy check code of the Payload field according to the determined configuration information, where Decoding the second field into real-time status information of the peer receiving end buffer register, decoding the second field to a command that the peer end requests the local end reset, decoding the second field into an event command, or decoding the second field Decoded to other extended features preset.
  • FIG. 7 is a schematic structural diagram of a data encoding and decoding system of a physical coding sublayer according to an embodiment of the present invention; as shown in FIG. 7, the system includes: a 64B/66B encoding device and a 66B/64B decoding device;
  • the 64B/66B encoding apparatus is configured to map a 64-bit data block and a control block to 66 bits;
  • the 64B/66B encoding device is specifically configured to: determine whether the data received from the MAC layer is a data block or a control block, if it is a data block, encode according to a protocol, and if it is a control block, the block type field
  • the code is 4 bits, and the remaining 4 bits are encoded according to the configuration information of the sender.
  • the 66B/64B decoding apparatus is configured to perform decoding of 66-bit to 64-bit information in accordance with a reverse process of 64B/66B encoding.
  • the embodiment of the invention provides a computer storage medium, wherein a computer program for executing the data encoding and decoding method of the physical coding sublayer described in any of the above embodiments is stored.
  • the method when the computer program located on the computer storage medium is executed by the processor, the method includes:
  • the first data is divided into a data block and a control block, for which the data block is encoded according to a protocol; for the control block, the bit corresponding to the block type field is divided into a first field and a second field, and the first field is identified according to the block type Encoding, the second field is encoded according to configuration information of the sending end of the first data;
  • the data decoding side of the physical coding sublayer determines that the second data is a data block or a control block, and if the second data is a data block, performs decoding according to the protocol;
  • the second data is a control block, and is decoded according to configuration information of the transmitting end of the second data.
  • the method further includes:
  • a first sync header is filled in front of the block of the data block, and a second sync header is filled in front of the block of the control block.
  • the method further includes:
  • Determining configuration information of the transmitting end of the first data encoding the second field into a cyclic redundancy check code of a payload field according to the determined configuration information, and encoding the second field into a real-time buffer register Status information, encoding the second field as a command to reset the peer, encoding the second field as an event command, or encoding the second field as a pre-set other extended function.
  • the method further includes:
  • the synchronization header of the data is a second synchronization header, and the second data is determined to be a control block.
  • the method further includes:
  • Determining configuration information of the transmitting end of the second data decoding the second field into a cyclic redundancy check code of the payload field according to the determined configuration information, and decoding the second field into a peer receiving end buffer register Real-time status information, decoding the second field to a command that the peer requires the local end to reset, decoding the second field as an event command, or decoding the second field into a preset other extended function.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded into a computer or other programmable data processing device Having a series of operational steps performed on a computer or other programmable device to produce computer-implemented processing such that instructions executed on a computer or other programmable device are provided for implementing one or more processes in a flowchart and/or Or block diagram the steps of a function specified in a box or multiple boxes.
  • the utilization of the block type field coding is improved, the check bit of the transmission data can be increased by the corresponding configuration information, and the reliability of the data transmission is improved; the real-time status information of the buffer register of the receiving end can be embedded in the control.
  • the symbol solves the problem that the Ethernet link layer flow control occupies the transmission bandwidth and delay; the PCS function can be extended to increase the remote reset; the predefined event command can be added to increase the flexibility of interaction between the two ends.

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Abstract

本发明公开了一种物理编码子层的数据编解码方法，包括：物理编码子层的数据编码侧接收第一数据后，将所述第一数据分为数据块和控制块，对于所述数据块，按协议进行编码；对于所述控制块，将块类型字段对应的比特位分为第一字段和第二字段，所述第一字段根据块类型标识符进行编码，所述第二字段根据所述第一数据的发送端的配置信息进行编码；所述物理编码子层的数据解码侧接收第二数据后，判断所述第二数据为数据块或控制块，如果所述第二数据为数据块，则按所述协议进行解码；如果所述第二数据为控制块，则根据所述第二数据的发送端的配置信息进行解码。本发明还公开了一种物理编码子层的数据编解码装置、计算机存储介质。

Description

一种物理编码子层的数据编解码方法和装置、存储介质
相关申请的交叉引用
本申请基于申请号为201710054537.X、申请日为2017年01月22日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及高性能芯片设计技术，尤其涉及一种物理编码子层的数据编解码方法和装置、计算机存储介质。
背景技术
以太网(Ethernet)是由Xeros公司开发的一种基带局域网技术，按其功能划分为7个层，其中物理层为最低层，定义了数据传输和接收需要的编码、线路状态等，物理层中的物理编码子层(PCS，Physical Coding Sublayer)主要实现编码功能和解码功能。
在现有的技术方案中PCS层有以下特征：
1、PCS 64B/66B编码时，块类型(block type)字段为8bit，编码15种情况。
2、PCS层数据传输是由前向纠错(FEC，Forward Error Correction)功能来保证数据传输可靠性的，但是FEC结构复杂，如果链路状态比较稳定，可以不使用FEC功能，但是这样传输的数据不会经过任何的校验，即使接收端接收到了传输错误的数据信息，也不会有任何的告警。
3、以太网流控机制是通过在介质访问控制(MAC，Media Access Control)子层发送流量控制包，在接收端对包进行解析，根据解析结果进 行控制。
4、以太网链路两端的信息交互都是通过组包的方式进行，缺乏信息交互的灵活性和实时性。
现有的技术方案中存在以下不足：
在PCS 64B/66B编码时，块类型(block type)字段为8bit，编码block type的15种情况，8bit的字段没有得到充分利用；在FEC功能不使用时，数据传输过程中没有对数据进行保护；以太网的流控包占据系统带宽，并且传输的信息需要经过组包和解包操作，存在一定的延迟；链路两端的信息交互缺乏灵活性和实时性。
发明内容
为解决现有存在的技术问题，本发明实施例提供一种物理编码子层的数据编解码方法和装置，解决现有技术中存在的block type字段的8bit编码没有充分利用、FEC功能不使用情况下数据无任何校验保护的缺陷等问题。
为达到上述目的，本发明的技术方案是这样实现的：
本发明实施例提供了一种物理编码子层的数据编解码方法，所述方法包括：
物理编码子层的数据编码侧接收第一数据后，将所述第一数据分为数据块和控制块，对于所述数据块，按协议进行编码；对于所述控制块，将块类型字段对应的比特位分为第一字段和第二字段，所述第一字段根据块类型标识符进行编码，所述第二字段根据所述第一数据的发送端的配置信息进行编码；
所述物理编码子层的数据解码侧接收第二数据后，判断所述第二数据为数据块或控制块，如果所述第二数据为数据块，则按所述协议进行解码；如果所述第二数据为控制块，则根据所述第二数据的发送端的配置信息进行解码。
上述方案中，所述将第一数据分为数据块和控制块之后，所述方法还包括：
在所述数据块的块前填充第一同步头，在所述控制块的块前填充第二同步头。
上述方案中，所述第二字段根据所述第一数据的发送端的配置信息进行编码，包括：
确定所述第一数据的发送端的配置信息，根据确定的配置信息将所述第二字段编码为有效负载字段的循环冗余校验码、将所述第二字段编码为接收端缓冲寄存器的实时状态信息、将所述第二字段编码为复位对端的命令、将所述第二字段编码为事件命令或将所述第二字段编码为预先设定的其他扩展功能。
上述方案中，所述判断第二数据为数据块或控制块，包括：
根据所述第二数据的同步头判断所述第二数据为数据块或控制块，如果所述第二数据的同步头为第一同步头，则确定所述第二数据为数据块；如果所述数据的同步头为第二同步头，则确定所述第二数据为控制块。
上述方案中，所述根据所述第二数据的发送端的配置信息进行解码，包括：
确定所述第二数据的发送端的配置信息，根据确定的配置信息将所述第二字段解码为有效负载字段的循环冗余校验码、将所述第二字段解码为对端接收端缓存寄存器的实时状态信息、将所述第二字段解码为对端要求本端复位的命令、将所述第二字段解码为事件命令或将所述第二字段解码为预先设定的其他扩展功能。
本发明实施例提供了一种以太网物理编码子层的数据编解码装置，所述装置包括：编码模块和解码模块；其中，
所述编码模块，配置为在接收第一数据后，将所述第一数据分为数据 块和控制块，对于所述数据块，按协议进行编码；对于所述控制块，将块类型字段对应的比特位分为第一字段和第二字段，所述第一字段根据块类型标识符进行编码，所述第二字段根据所述第一数据的发送端的配置信息进行编码；
所述解码模块，配置为在接收第二数据后，判断所述第二数据为数据块或控制块，如果所述第二数据为数据块，则按所述协议进行解码；如果所述第二数据为控制块，则根据所述第二数据的发送端的配置信息进行解码。
上述方案中，所述编码模块，还配置为：在所述数据块的块前填充第一同步头，在所述控制块的块前填充第二同步头。
上述方案中，所述编码模块，具体配置为：确定所述第二数据的发送端的配置信息，根据确定的配置信息将所述第二字段编码为有效负载字段的循环冗余校验码、将所述第二字段编码为接收端缓冲寄存器的实时状态信息、将所述第二字段编码为复位对端的命令、将所述第二字段编码为事件命令或将所述第二字段编码为预先设定的其他扩展功能。
上述方案中，所述解码模块，配置为：根据所述第二数据的同步头判断所述第二数据为数据块或控制块，如果所述第二数据的同步头为第一同步头，则确定所述第二数据为数据块；如果所述数据的同步头为第二同步头，则确定所述第二数据为控制块。
上述方案中，所述解码模块，具体配置为：确定所述第二数据的发送端的配置信息，根据确定的配置信息将所述第二字段解码为有效负载字段的循环冗余校验码、将所述第二字段解码为对端接收端缓存寄存器的实时状态信息、将所述第二字段解码为对端要求本端复位的命令、将所述第二字段解码为事件命令或将所述第二字段解码为预先设定的其他扩展功能。
所述编码模块和解码模块，在执行处理时，可以采用中央处理器(CPU， Central Processing Unit)、数字信号处理器(DSP，Digital Singnal Processor)或可编程逻辑阵列(FPGA，Field－Programmable Gate Array)实现。
本发明实施例提供的计算机存储介质，其中存储有计算机程序，该计算机程序用于执行上述物理编码子层的数据编解码方法。
本发明实施例所提供的物理编码子层的数据编解码方法，包括：物理编码子层的数据编码侧接收第一数据后，将所述第一数据分为数据块和控制块，对于所述数据块，按协议进行编码；对于所述控制块，将块类型字段对应的比特位分为第一字段和第二字段，所述第一字段根据块类型标识符进行编码，所述第二字段根据所述第一数据的发送端的配置信息进行编码；所述物理编码子层的数据解码侧接收第二数据后，判断所述第二数据为数据块或控制块，如果所述第二数据为数据块，则按所述协议进行解码；如果所述第二数据为控制块，则根据所述第二数据的发送端的配置信息进行解码。
采用本发明实施例，提高块类型字段编码的利用率，通过相应的配置信息可以增加传输数据的校验位，提高数据传输的可靠性；可以将接收端缓冲寄存器的实时状态信息内嵌于控制符号，解决以太网链路层流控占据传输带宽和延迟问题；可以扩展PCS的功能，增加远端复位；可以增加预先定义的事件命令，增加两端交互的灵活性。
附图说明
图1为本发明实施例提供的一种物理编码子层的数据编解码方法的流程示意图；
图2为本发明实施例提供的一种物理编码子层的数据编码方法的流程示意图；
图3为本发明实施例提供的一种物理编码子层的数据解码方法的流程示意图；
图4为原协议中64B/66B编码的映射示意图；
图5为本发明实施例提供的64B/66B编码的映射示意图；
图6为本发明实施例提供的一种物理编码子层的数据编解码装置的结构示意图；
图7为本发明实施例提供的一种物理编码子层的数据编解码系统的结构示意图。
具体实施方式
在本发明的各种实施例中，物理编码子层的数据编码侧接收第一数据后，将所述第一数据分为数据块和控制块，对于所述数据块，按协议进行编码；对于所述控制块，将块类型字段对应的比特位分为第一字段和第二字段，所述第一字段根据块类型标识符进行编码，所述第二字段根据所述第一数据的发送端的配置信息进行编码；所述物理编码子层的数据解码侧接收第二数据后，判断所述第二数据为数据块或控制块，如果所述第二数据为数据块，则按所述协议进行解码；如果所述第二数据为控制块，则根据所述第二数据的发送端的配置信息进行解码。
下面结合实施例对本发明再作进一步详细的说明。
图1为本发明实施例提供的一种物理编码子层的数据编解码方法的流程示意图；如图1所示，所述方法，包括：
步骤101：物理编码子层(PCS)的数据编码侧接收第一数据后，将所述第一数据分为数据块和控制块；对于所述数据块，按协议进行映射；对于所述控制块，将块类型(block type)对应的比特位分为第一字段和第二字段，所述第一字段根据块类型标识符进行编码，所述第二字段根据所述第一数据的发送端的配置信息进行编码；
具体地，所述第一数据为所述物理编码子层从介质访问控制层(MAC)接收的数据；
所述块类型对应的比特位为8bit，这里，分割后的所述第一字段为4bit，所述第二字段为4bit。
具体地，所述将第一数据分为数据块和控制块之后，所述方法还包括：
在所述数据块的块前填充第一同步头，所述第一同步头用于标识所述数据块；在所述控制块的块前填充第二同步头，所述第二同步头用于标识所述控制块。
这里，对于所述数据块和所述控制块作以下说明：
64B/66B编码应用于以太网系统中，可以由64B/66B编码器将传送来的数据进行编码，形成以66比特(bit)为单位的数据。66比特数据包含2比特的同步字符(Sync Header)和64比特的有效负载(Payload)字段。
如果64比特信息为MAC帧的数据信息，则该数据称为数据块，其同步字符可设置为“01”；如果64比特信息中包含如IPG等控制字符时，则该数据称为控制块，其同步字符可以设置为“10”，并通过对块类型(block type)设置来表示64比特信息的类型。
这里，可以通过确定所述第一数据中64比特信息包含的信息为MAC帧的数据信息还是控制字符来区分数据块和控制块。
本发明实施例中，所述第一同步头可以用字符“01”表示；所述第二同步头可以用字符“10”表示。
具体地，对于所述数据块，按照协议直接进行编码；这里，所述协议为：IEEE Standard for Ethernet协议。
对于控制块，将块类型(block type)的15种情况用第一字段、即4bit进行编码；剩余4bit作为第二字段，用于进行功能扩展，根据配置信息进行编码。
具体地，所述第二字段根据所述第一数据的发送端的配置信息进行编码，包括：
确定所述第一数据的发送端的配置信息，根据确定的配置信息进行编码；
所述根据确定的配置信息进行编码，包括：将所述第二字段编码为有效负载(Payload)字段循环冗余校验码、将所述第二字段编码为接收端缓冲寄存器的实时状态信息、将所述第二字段编码为复位对端的命令、将所述第二字段编码为事件命令或将所述第二字段编码为预先设定的其他扩展功能。
这里，所述配置信息，可以包括以下信息任一种：配置一、配置二、配置三、配置四；举例来说：
所述配置一：将4bit编码为有效负载(Payload)字段的循环冗余校验(CRC，Cyclic Redundancy Check)码，具体为CRC-4校验码；
这里，通过所述配置一可以提高FEC功能不使用时的数据可靠性；
所述配置二：将4bit编码为接收端缓冲寄存器(buffer)的实时状态信息；
这里，通过所述配置二可以告知对端接收端buffer的实时状态信息，以利于对端根据接收到的实时状态信息进行实时流控；
所述配置三：将4bit编码为复位对端的命令；
所述命令包括两种情况：一，复位接口(reset-port)命令，则复位对端PCS的各种错误统计和错误指示寄存器；二，复位装置(reset-device)命令，则复位对端PCS的所有寄存器；
所述配置四：将4bit编码为事件(event)命令；具体可以包括16种event命令，每种event命令两端经过预定义，在对端接收到event命令后，执行相应的操作。
以上所述的四种配置只是提供一种实施例，其他配置均可以作为配置信息进行扩展。
结合上述例子具体来说，所述第二字段根据所述第一数据的发送端的配置信息进行编码，可以包括：
读取所述配置信息，判断所述配置信息是否为配置一，即将4bit编码为CRC-4校验码；
如果所述配置信息为配置一，则根据所述配置信息将4bit编码为Payload字段的CRC-4校验码；否则，判断所述配置信息是否为配置二，即将4bit编码为接收端buffer的实时状态信息；
如果所述配置信息为配置二，则根据所述配置信息将4bit编码为接收端buffer的实时状态信息；否则，判断所述配置信息是否为配置三，即将4bit编码为复位对端的命令；
如果所述配置信息为配置三，则根据所述配置信息将4bit编码为复位对端的命令；否则，判断所述配置信息是否为配置四，即将4bit编码预先设定的事件命令；
如果所述配置信息为配置四，则根据所述配置信息将4bit编码为两端预先设定的事件命令；否则，将4bit编码为用户预先设定的其他扩展功能。
这里，所述第一数据的发送端的配置信息为由发送端的软件或用户针对发送端的软件进行配置，从而获得的配置信息。
所述物理编码子层的数据编码侧在进行64B/66B编码时，可以读取所述第一数据的发送端的配置信息，并根据所述配置信息进行编码。
步骤102、所述物理编码子层的数据解码侧接收第二数据后，判断所述第二数据为数据块或控制块，如果所述数据为数据块，则按照协议解映射；如果所述第二数据为控制块，则根据所述第二数据的发送端的配置信息进行解码。
具体地，所述第二数据为所述物理编码子层接收到的数据。
所述判断第二数据为数据块或控制块，包括：
所述物理编码子层的数据解码侧读取所述第二数据的同步头，如果所述同步头为第一同步头，则确定为数据块；如果所述同步头为第二同步头，则确定为控制块。
本发明实施例中，所述第一同步头可以用字符“01”表示；所述第二同步头可以用字符“10”表示。
具体地，所述根据所述第二数据的发送端的配置信息进行解码，包括：
确定所述第二数据的发送端的配置信息，根据确定的配置信息进行解码；
所述根据确定的配置信息进行解码，包括：
将所述第二字段解码为Payload字段的循环冗余校验码、将所述第二字段解码为对端接收端缓存寄存器的实时状态信息、将所述第二字段解码为对端要求本端复位的命令、将所述第二字段解码为事件命令或将所述第二字段解码为预先设定的其他扩展功能。
具体来说，所述根据所述第二数据的发送端的配置信息进行解码，具体包括：
判断所述配置信息是否为配置五，即将4bit解码为CRC-4校验码；
如果所述配置信息是配置五，则将4bit解码为Payload字段的CRC-4校验码，并进一步判断校验的正确性，如果校验正确，则按照编码的反过程进行解码，将解码后信息传递到MAC层，如果校验错误，则按错误码处理；否则，判断所述配置信息是否为配置六，即将4bit解码为对端接收侧buffer的实时状态信息；
如果所述配置信息为配置六，则将4bit解码为对端接收侧buffer的实时状态信息，并将所述buffer状态字段的实时状态信息传递到MAC层流控模块进行流控；否则，判断所述配置信息是否为配置七，即将4bit解码为复位对端的命令；
如果所述配置信息为配置七，则将4bit解码为对端要求本端复位的命令；所述命令包括两种情况：一，如果接收到reset-port命令，则将PCS的错误统计和错误状态指示的寄存器进行复位；二，如果接收到reset-device命令，则复位所有的PCS寄存器；
如果所述配置信息不是配置七，则判断所述配置信息是否为配置八，即将4bit解码16种两端预先定义的事件(event)命令的任一种；
如果所述配置信息为配置八，则将4bit解码为两端预先定义的事件命令，根据解码出的事件命令，执行相应的操作；否则，将4bit解码为用户预先设定的其他扩展功能。
这里，所述第二数据的发送端的配置信息为由发送端的软件或用户针对发送端的软件进行配置，从而获得的配置信息。
所述物理编码子层的数据解码侧可以读取所述第二数据的发送端的配置消息，并根据所述配置消息进行解码。
以上实施例中的所述配置五、配置六、配置七、配置八分别与配置一、配置二、配置三、配置四对应。
需要说明的是，以上只是给了四种配置信息的实施例，其他配置信息也可以通过预先定义做为扩展功能。
图2为本发明实施例提供的一种物理编码子层的数据编码方法的流程示意图；如图2所示，所述编码方法，包括：
步骤201、从MAC层接收到第一数据，将接收的第一数据区分为数据块和控制块；
针对数据块，在块前填充第一同步头，这里为字符“01”，所述数据块按照协议进行编码；
针对控制块，在块前填充第二同步头，这里为字符“10”，将块类型(block type)字段编码为4bit，剩余4bit根据数据发送端的配置信息进行编码，以 实现各种灵活的功能；其余Payload字段按照协议进行映射；
步骤202、判断所述第一数据的发送端的配置信息是否为配置一，即将4bit编码为Payload字段的CRC-4校验码；
所述配置信息为配置一，则进入步骤203；否则，进入步骤204；
步骤203、将4bit编码为Payload字段的CRC-4校验码；
步骤204、判断所述配置信息是否为配置二，即将4bit编码为接收端buffer的实时状态信息；
所述配置信息为配置二，则进入步骤205，否则，进入步骤206；
步骤205、将4bit编码为接收端buffer的实时状态信息；
步骤206、判断所述配置信息是否为配置三，即将4bit编码为复位对端的命令；
所述配置信息为配置三，则进入步骤207，否则，进入步骤208；
步骤207、将4bit编码为复位对端的命令；
步骤208、判断所述配置信息是否为配置四，即将4bit编码16种两端预先定义的事件命令中的任一种；
所述配置信息为配置四，则进入步骤209，否则，进入步骤210；
步骤209、将4bit编码为两端预先定义的事件命令；
步骤210、将4bit编码为用户预先设定的其他扩展功能。
图3为本发明实施例提供的一种物理编码子层的数据解码方法的流程示意图；如图3所示，所述解码方法，包括：
步骤301、接收第二数据，根据同步头识别所述第二数据为数据块或控制块；
对于数据块，去除同步头后直接将数据发送给MAC层；
对于控制块，block type字段和Payload字段根据编码信息进行解码，剩余4bit根据配置信息进行解码；
步骤302、判断所述配置信息是否为配置五，即将4bit解码为Payload字段的CRC-4校验码；
所述配置信息为配置五，则进入步骤303，否则进入步骤304；
步骤303、将4bit解码为Payload字段的CRC-4校验码，并判断校验的正确性，如果校验正确，则将解码后信息传递到MAC层，如果校验错误，则按错误码处理，例如：给出错误报警；
步骤304、判断所述配置信息是否为配置六，即将4bit解码为对端接收侧buffer的实时状态信息；
所述配置信息为配置六，则进入步骤305，否则进入步骤306；
步骤305、将4bit解码为对端接收侧buffer的实时状态信息，并将实时状态信息传递到流控模块；
步骤306、判断所述配置信息是否为配置七，即将4bit解码为复位对端的命令；
所述配置信息为配置七，则进入步骤307，否则进入步骤308；
步骤307、将4bit解码为对端要求本端复位的命令，如果接收到reset-port命令，则将PCS的错误统计和错误状态指示的寄存器进行复位，如果接收到reset-device命令，则复位所有的PCS寄存器；
步骤308、判断所述配置信息是否为配置八，即将4bit解码16种两端预先定义的事件命令中的任一种；
所述配置信息为配置八，则进入步骤309，否则进入步骤310；
步骤309、将4bit解码为两端预先定义的事件命令，根据解码出的事件命令执行相应的操作；
步骤310、将4bit解码为用户预先设定的其他扩展功能。
图4为原协议中64B/66B编码的映射示意图，如图4所示，从MAC层接收的数据分为数据块和控制块，数据块64B/66B编码的编码方式为在 块前添加2bit同步头“01”，所述控制块的编码方式为在块前添加同步头“10”，同步头后面的8bit根据block type、block payload进行相应的映射。
图5为本发明实施例提供的64B/66B编码的映射示意图，如图5所示，与原协议的不同之处在于block type的8bit分为两部分，前半部分的4bit为用户自定义，后半部分的4bit为block type的编码信息。
图6为本发明实施例提供的一种物理编码子层的数据编解码装置的结构示意图；如图6所示，所述装置，包括：编码模块和解码模块；其中，
所述编码模块，配置为在接收第一数据后，将所述第一数据分为数据块和控制块，对于所述数据块，按协议进行编码；对于所述控制块，将块类型字段对应的比特位分为第一字段和第二字段，所述第一字段根据块类型标识符进行编码，所述第二字段根据所述第一数据的发送端的配置信息进行编码；
所述解码模块，配置为在接收第二数据后，判断所述第二数据为数据块或控制块，如果所述第二数据为数据块，则按所述协议进行解码；如果所述第二数据为控制块，则根据所述第二数据的发送端的配置信息进行解码。
具体地，所述编码模块，还配置为：在所述数据块的块前填充第一同步头，在所述控制块的块前填充第二同步头。
这里，所述第一同步头可以用字符“01”表示，所述第二同步头可以用字符“10”表示。
具体地，所述编码模块，具体配置为：确定所述第二数据的发送端的配置信息，根据确定的配置信息将所述第二字段编码为Payload字段的循环冗余校验码、将所述第二字段编码为接收端缓冲寄存器的实时状态信息、将所述第二字段编码为复位对端的命令、将所述第二字段编码为事件命令或将所述第二字段编码为预先设定的其他扩展功能。
具体地，所述解码模块，配置为：根据所述第二数据的同步头判断所述第二数据为数据块或控制块，如果所述第二数据的同步头为第一同步头，则确定所述第二数据为数据块；如果所述数据的同步头为第二同步头，则确定所述第二数据为控制块。
具体地，所述解码模块，具体配置为：确定所述第二数据的发送端的配置信息，根据确定的配置信息将所述第二字段解码为Payload字段的循环冗余校验码、将所述第二字段解码为对端接收端缓存寄存器的实时状态信息、将所述第二字段解码为对端要求本端复位的命令、将所述第二字段解码为事件命令或将所述第二字段解码为预先设定的其他扩展功能。
图7为本发明实施例提供的一种物理编码子层的数据编解码系统的结构示意图；如图7所示，所述系统，包括：64B/66B编码装置和66B/64B解码装置；其中，
所述64B/66B编码装置，配置为将64bit的数据块和控制块映射为66bit；
具体地，所述64B/66B编码装置，具体配置为：判断从MAC层接收到数据为数据块还是控制块，如果是数据块，则按照协议进行编码，如果是控制块，则将block type字段编码为4bit，剩余4bit根据发送端的配置信息进行编码。
所述66B/64B解码装置，配置为按照64B/66B编码的反过程完成66bit到64bit信息的解码。
本发明实施例提供了一种计算机存储介质，其中存储有计算机程序，该计算机程序用于执行上述任一实施例所述的物理编码子层的数据编解码方法。
一种实施方式中，具体的，位于计算机存储介质的该计算机程序被处理器执行时，包括：
物理编码子层的数据编码侧接收第一数据后，将所述第一数据分为 数据块和控制块，对于所述数据块，按协议进行编码；对于所述控制块，将块类型字段对应的比特位分为第一字段和第二字段，所述第一字段根据块类型标识符进行编码，所述第二字段根据所述第一数据的发送端的配置信息进行编码；
所述物理编码子层的数据解码侧接收第二数据后，判断所述第二数据为数据块或控制块，如果所述第二数据为数据块，则按所述协议进行解码；如果所述第二数据为控制块，则根据所述第二数据的发送端的配置信息进行解码。
具体的，位于计算机存储介质的该计算机程序被处理器执行时，还包括：
在所述数据块的块前填充第一同步头，在所述控制块的块前填充第二同步头。
具体的，位于计算机存储介质的该计算机程序被处理器执行时，还包括：
确定所述第一数据的发送端的配置信息，根据确定的配置信息将所述第二字段编码为有效负载字段的循环冗余校验码、将所述第二字段编码为接收端缓冲寄存器的实时状态信息、将所述第二字段编码为复位对端的命令、将所述第二字段编码为事件命令或将所述第二字段编码为预先设定的其他扩展功能。
具体的，位于计算机存储介质的该计算机程序被处理器执行时，还包括：
根据所述第二数据的同步头判断所述第二数据为数据块或控制块，如果所述第二数据的同步头为第一同步头，则确定所述第二数据为数据块；如果所述数据的同步头为第二同步头，则确定所述第二数据为控制块。
具体的，位于计算机存储介质的该计算机程序被处理器执行时，还包括：
确定所述第二数据的发送端的配置信息，根据确定的配置信息将所述第二字段解码为有效负载字段的循环冗余校验码、将所述第二字段解码为对端接收端缓存寄存器的实时状态信息、将所述第二字段解码为对端要求本端复位的命令、将所述第二字段解码为事件命令或将所述第二字段解码为预先设定的其他扩展功能。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备 上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。
工业实用性
采用本发明实施例，提高块类型字段编码的利用率，通过相应的配置信息可以增加传输数据的校验位，提高数据传输的可靠性；可以将接收端缓冲寄存器的实时状态信息内嵌于控制符号，解决以太网链路层流控占据传输带宽和延迟问题；可以扩展PCS的功能，增加远端复位；可以增加预先定义的事件命令，增加两端交互的灵活性。

Claims (11)

  1. 一种物理编码子层的数据编解码方法，所述方法包括：
    物理编码子层的数据编码侧接收第一数据后，将所述第一数据分为数据块和控制块，对于所述数据块，按协议进行编码；对于所述控制块，将块类型字段对应的比特位分为第一字段和第二字段，所述第一字段根据块类型标识符进行编码，所述第二字段根据所述第一数据的发送端的配置信息进行编码；
    所述物理编码子层的数据解码侧接收第二数据后，判断所述第二数据为数据块或控制块，如果所述第二数据为数据块，则按所述协议进行解码；如果所述第二数据为控制块，则根据所述第二数据的发送端的配置信息进行解码。
  2. 根据权利要求1所述的方法，其中，所述将第一数据分为数据块和控制块之后，所述方法还包括：
    在所述数据块的块前填充第一同步头，在所述控制块的块前填充第二同步头。
  3. 根据权利要求1所述的方法，其中，所述第二字段根据所述第一数据的发送端的配置信息进行编码，包括：
    确定所述第一数据的发送端的配置信息，根据确定的配置信息将所述第二字段编码为有效负载字段的循环冗余校验码、将所述第二字段编码为接收端缓冲寄存器的实时状态信息、将所述第二字段编码为复位对端的命令、将所述第二字段编码为事件命令或将所述第二字段编码为预先设定的其他扩展功能。
  4. 根据权利要求1所述的方法，其中，所述判断第二数据为数据块或控制块，包括：
    根据所述第二数据的同步头判断所述第二数据为数据块或控制块， 如果所述第二数据的同步头为第一同步头，则确定所述第二数据为数据块；如果所述数据的同步头为第二同步头，则确定所述第二数据为控制块。
  5. 根据权利要求1所述的方法，其中，所述根据所述第二数据的发送端的配置信息进行解码，包括：
    确定所述第二数据的发送端的配置信息，根据确定的配置信息将所述第二字段解码为有效负载字段的循环冗余校验码、将所述第二字段解码为对端接收端缓存寄存器的实时状态信息、将所述第二字段解码为对端要求本端复位的命令、将所述第二字段解码为事件命令或将所述第二字段解码为预先设定的其他扩展功能。
  6. 一种以太网物理编码子层的数据编解码装置，所述装置包括：编码模块和解码模块；其中，
    所述编码模块，配置为在接收第一数据后，将所述第一数据分为数据块和控制块，对于所述数据块，按协议进行编码；对于所述控制块，将块类型字段对应的比特位分为第一字段和第二字段，所述第一字段根据块类型标识符进行编码，所述第二字段根据所述第一数据的发送端的配置信息进行编码；
    所述解码模块，配置为在接收第二数据后，判断所述第二数据为数据块或控制块，如果所述第二数据为数据块，则按所述协议进行解码；如果所述第二数据为控制块，则根据所述第二数据的发送端的配置信息进行解码。
  7. 根据权利要求6所述的装置，其中，所述编码模块，还配置为：在所述数据块的块前填充第一同步头，在所述控制块的块前填充第二同步头。
  8. 根据权利要求6所述的装置，其中，所述编码模块，具体配置为： 确定所述第二数据的发送端的配置信息，根据确定的配置信息将所述第二字段编码为有效负载字段的循环冗余校验码、将所述第二字段编码为接收端缓冲寄存器的实时状态信息、将所述第二字段编码为复位对端的命令、将所述第二字段编码为事件命令或将所述第二字段编码为预先设定的其他扩展功能。
  9. 根据权利要求6所述的装置，其中，所述解码模块，配置为：根据所述第二数据的同步头判断所述第二数据为数据块或控制块，如果所述第二数据的同步头为第一同步头，则确定所述第二数据为数据块；如果所述数据的同步头为第二同步头，则确定所述第二数据为控制块。
  10. 根据权利要求6所述的装置，其中，所述解码模块，具体配置为：确定所述第二数据的发送端的配置信息，根据确定的配置信息将所述第二字段解码为有效负载字段的循环冗余校验码、将所述第二字段解码为对端接收端缓存寄存器的实时状态信息、将所述第二字段解码为对端要求本端复位的命令、将所述第二字段解码为事件命令或将所述第二字段解码为预先设定的其他扩展功能。
  11. 一种计算机存储介质，其中存储有计算机程序，该计算机程序用于执行上述权利要求1-5任一项所述的物理编码子层的数据编解码方法。
PCT/CN2017/099355 2017-01-22 2017-08-28 一种物理编码子层的数据编解码方法和装置、存储介质 WO2018133415A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110830152A (zh) * 2018-08-07 2020-02-21 华为技术有限公司 接收码块流的方法、发送码块流的方法和通信装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112995751A (zh) * 2019-12-18 2021-06-18 西安诺瓦星云科技股份有限公司 数据传输方法和系统

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1905541A (zh) * 2005-05-24 2007-01-31 阿瓦戈科技通用Ip(新加坡)股份有限公司 编码和解码分组化数据
US20080228941A1 (en) * 2003-11-06 2008-09-18 Petre Popescu Ethernet Link Monitoring Channel
CN101309258A (zh) * 2007-05-18 2008-11-19 华为技术有限公司 高速以太网介质无关接口码块的分发和接收方法及装置
CN101610134A (zh) * 2009-07-10 2009-12-23 中兴通讯股份有限公司 64b/66b编解码装置及实现64b/66b编解码的方法
CN104426629A (zh) * 2013-08-30 2015-03-18 华为技术有限公司 一种物理层编解码方法及其装置
CN105900386A (zh) * 2014-02-05 2016-08-24 英特尔公司 具有线速和分组数据速率匹配的以太网分组数据的可靠传输

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101312349B (zh) * 2007-05-26 2010-08-25 华为技术有限公司 信息块编码及同步检测的方法和装置
KR101438864B1 (ko) * 2007-06-06 2014-09-15 인터디지탈 테크날러지 코포레이션 피기백된 ａｃｋ／ｎａｃｋ 필드가 어드레싱된 임시 블록 흐름(ｔｂｆ)을 표시하기 위한 방법 및 장치
CN101330350B (zh) * 2007-06-21 2011-09-14 华为技术有限公司 适配载荷带宽传输数据的发送方法、接收处理方法及装置
CN101436917B (zh) * 2007-11-12 2012-06-27 华为技术有限公司 用于以太网无源光网络的数据编译码方法及装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080228941A1 (en) * 2003-11-06 2008-09-18 Petre Popescu Ethernet Link Monitoring Channel
CN1905541A (zh) * 2005-05-24 2007-01-31 阿瓦戈科技通用Ip(新加坡)股份有限公司 编码和解码分组化数据
CN101309258A (zh) * 2007-05-18 2008-11-19 华为技术有限公司 高速以太网介质无关接口码块的分发和接收方法及装置
CN101610134A (zh) * 2009-07-10 2009-12-23 中兴通讯股份有限公司 64b/66b编解码装置及实现64b/66b编解码的方法
CN104426629A (zh) * 2013-08-30 2015-03-18 华为技术有限公司 一种物理层编解码方法及其装置
CN105900386A (zh) * 2014-02-05 2016-08-24 英特尔公司 具有线速和分组数据速率匹配的以太网分组数据的可靠传输

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110830152A (zh) * 2018-08-07 2020-02-21 华为技术有限公司 接收码块流的方法、发送码块流的方法和通信装置
CN110830152B (zh) * 2018-08-07 2021-04-09 华为技术有限公司 接收码块流的方法、发送码块流的方法和通信装置
US11251905B2 (en) 2018-08-07 2022-02-15 Huawei Technologies Co., Ltd. Method for receiving code block stream, method for transmitting code block stream, and communications apparatus

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