WO2018121469A1

WO2018121469A1 - System and method for high-precision clock delay calibration

Info

Publication number: WO2018121469A1
Application number: PCT/CN2017/118233
Authority: WO
Inventors: 叶立平; 唐可信
Original assignee: 深圳市志奋领科技有限公司
Priority date: 2016-12-30
Filing date: 2017-12-25
Publication date: 2018-07-05
Also published as: CN106612111B; CN106612111A

Abstract

Disclosed in the present invention are a system and a method for high-precision clock delay calibration. The calibration system comprises a NAND gate, an AND gate, a time delay chip, a multiplexer and a processing module; the multiplexer comprising a calibration end and an output end, the processing module comprising a time delay control end, a selection control end and a control switch end; the output end of the AND gate being electrically connected to the input end of the multiplexer by means of the time delay chip, the time delay control end of the processing module being electrically connected to the time delay chip, the selection control end of the processing module being electrically connected to the multiplexer, the control switch end of the processing module being electrically connected to the input end of the NAND gate, and the output end of the NAND gate being electrically connected to the input end of the AND gate. The present invention uses a pulse oscillation counting method to measure pulse width, then calculates the time delay, before finally adjusting the time delay chip so as to achieve the purpose of time delay calibration; the system can perform the calibration in real time, preventing the time delay chip from being affected by the temperature and other external factors, thereby, a high-precision measurement effect is achieved.

Description

System and method for high precision delayed clock calibration

Technical field

The invention belongs to the technical field of computers, and in particular relates to a system and method for high precision delayed clock calibration.

Background technique

In some technical fields such as radar and laser, precise delay is the key to the whole system, but the actual value of the delay is affected by the external environment such as temperature. For example, the MC100EP196 of ON Semiconductor has a large temperature drift effect. Time calibration is an important measure to improve the accuracy of the entire system.

Summary of the invention

In order to overcome the deficiencies of the prior art, it is an object of the present invention to provide a high precision delayed clock calibration system that solves the technical problem of delayed clock calibration.

A second object of the present invention is to provide a delayed clock calibration method that solves the technical problem of delayed clock calibration.

One of the objects of the present invention is achieved by the following technical solutions:

A system for delaying clock calibration, comprising a NAND gate, an AND gate, a delay chip, a multiplexer and a processing module, the multiplexer comprising a calibration output and a clock output, the processing module including a delay Control terminal, selection control terminal and control switch terminal;

The two input ends of the AND gate are respectively connected to the output end of the NAND gate and the clock input end; the output end of the AND gate is connected to the input end of the multiplexer via the delay chip, and the delay of the processing module The control end and the selection control end are respectively connected to the control end of the delay chip and the control end of the multiplexer, and the two input ends of the NAND gate are respectively connected to the control switch end of the processing module and the calibration of the multiplexer Output

The selection control end of the processing module and the control switch end have the same output logic. When the selection control end of the processing module outputs a high level, the multiplexer outputs a calibration signal through the calibration output end, and at the selection control end of the processing module When the output is low, the multiplexer outputs a clock signal through the clock output.

Preferably, a frequency divider is further included, and the calibration output of the multiplexer is electrically connected to the processing module through a frequency divider.

Preferably, the multiplexer is a two-way selector.

Preferably, the model of the time delay chip is MC100EP196.

In another aspect, the present invention also provides a system for delay clock calibration, comprising a NOT gate, an AND gate, a delay chip, a multiplexer and a processing module, the multiplexer including a calibration output and a clock output. The processing module includes a delay control terminal and a selection control terminal;

The two input ends of the AND gate are respectively connected to the output terminal of the NOT gate and the clock input terminal; the output end of the AND gate is connected to the input end of the multiplexer via a delay chip, and the delay control of the processing module The terminal and the selection control terminal are respectively connected to the control end of the delay chip and the control end of the multiplexer, and the input terminals of the NOT gate are respectively connected to the control switch end of the processing module and the calibration output end of the multiplexer;

When the selection control terminal of the processing module outputs a high level, the multiplexer outputs a calibration signal through the calibration output terminal, and when the selection control terminal of the processing module outputs a low level, the multiplexer outputs a clock signal through the clock output terminal.

In still another aspect, the present invention also provides a delay clock calibration method, including the following steps:

S1: the output delay of the control delay chip is zero, and the number of pulses M is calculated;

S2: the output delay of the control delay chip is 1 unit set value, and the number of pulses is calculated N;

S3: Calculating the difference K between M and N, which is the number of oscillations generated by delaying a unit set value;

S4: The output delay of the control delay chip is set to 100 units, and the number of pulses N1 is calculated;

S5: Calculating the difference K100 between M and N1, the difference K100 is the number of oscillations generated by delaying 100 unit set values;

S6: It is judged whether the difference between the K100 and the 100*K is within a preset range, and if yes, the process ends. If not, the process returns to the step S4 and adjusts the output delay.

Preferably, the preset range is K.

Compared with the prior art, the beneficial effects of the present invention are:

The invention adopts the pulse oscillation counting method to realize the pulse width measurement, and then performs the delay calculation, and finally adjusts the delay chip to achieve the purpose of the delay calibration. The method is economical to use, can be calibrated in real time, and excludes temperature and other external delays. The effect of the chip, thus achieving the effect of high-precision measurement.

DRAWINGS

1 is a block diagram showing the structure of a system for high-precision delayed clock of the first embodiment;

Figure 2 is a circuit diagram of Figure 1;

3 is a structural block diagram of a system for high-precision delayed clock of the second embodiment;

4 is a flow chart of a method of accurately delaying a clock of the present invention.

detailed description

The present invention will be further described below in conjunction with the drawings and specific embodiments.

Embodiment 1:

As shown in FIG. 1 , the embodiment provides a delay clock calibration system, including a NAND gate, an AND gate, a delay chip, a multiplexer, a frequency divider, and a processing module, where the multiplexer includes calibration. And the processing module includes a delay control terminal, a selection control terminal, and a control switch terminal, wherein the multiplexer is a two-way selector in this embodiment;

The output end of the AND gate is electrically connected to the input end of the multiplexer through a delay chip, and the calibration end of the multiplexer is electrically connected to the processing module through a frequency divider, and the delay of the processing module The control end is electrically connected to the delay chip, and the selection control end of the processing module is electrically connected to the multiplexer, the control switch end of the processing module is connected to the NAND gate, and the selection control end of the processing module is The output logic of the control switch end is consistent. When the output logic of the selection control terminal of the processing module is “1”, the input end of the multiplexer is connected to the calibration end thereof, and at this time, a calibration signal is output, and the selection control terminal of the processing module outputs When the logic is “0”, the input end of the multiplexer is connected to the output end thereof, and the clock signal is output at this time;

The multiplexer calibration end is electrically connected to the processing module, and the control switch end of the processing module is electrically connected to the input end of the NAND gate, and the output end of the NAND gate and the input end of the AND gate are electrically connected. Connected, the input of the AND gate receives the clock input signal.

The premise of the whole system work is that the duty cycle of the clock input is fixed. This is true for most clock circuits. The whole system works in two modes, one is the calibration mode, and the other is Output mode, both modes are controlled by the logic of the processing module output.

As shown in FIG. 2, in the calibration mode, the processing module controls the multiplexer to select the calibration terminal, and the clock forms a closed loop;

1) If the clock input is low at this time, since the first stage is an AND gate, the logic of b is always "0" regardless of the logic of e, so that a, b, c, d, and output can be obtained. Is "0", that is, the clock output of a0b0c0d0 is 0;

2) If the clock input is high at this time, since the first stage is the AND gate, the logic of b will not be changed by 1, but will be changed by e.

Assuming that the logic of e is "1", then b logic is "1", c logic is "1", d logic is "1", and e logic is "0";

Assuming that the logic of e is "0", then b logic is "0", c logic is "0", d logic is "0", and e logic is "1";

According to the above analysis, when the clock input is low, the output is low; when the clock input is high, the output will have an oscillating square wave, and the oscillation period is delayed by the delay chip. The multiplexer delay and the NAND gate delay are determined. The frequency divider divides the oscillating waveform when the system is operating in the high speed mode (such as 100M), and the pulse width is within the capability of the processor to count. .

In the case of normal mode output, the processing module controls the multiplexer to select the output. At this time, the clock output logic is equal to the clock input logic, and the entire system outputs normally.

Embodiment 2:

As shown in FIG. 3, the difference between this embodiment and the first embodiment is that the NAND gate in the first embodiment is replaced by a NAND gate, and there are some differences in the circuit structure setting, and the calibration end of the multiplexer is different. The input of the gate is electrically connected; the same effect exists in the actual logic output. As shown in FIG. 4, the present invention provides a high-precision delayed clock calibration method, which includes the following steps: since the oscillation period is fixed, the processing module can obtain the pulse width width by counting the number of pulses, and the calibration process can be as follows: Method is carried out:

S1: Set the delay of the delay chip to zero, calculate the number of pulses M; the number of M is determined by the delay chip delay set to 0, multiplexer delay and inverter delay , we can call it the inherent delay;

S2: Set the delay of the delay chip to a unit setting value, and calculate the number of pulses N; the number of N at this time is a unit setting value of the delay chip delay, the multiplexer delay and The delay of the inverter is determined;

S3: Calculate the difference between M and N to obtain S. This value is the number of oscillations generated by the unit set value. Since only a certain set of data will produce a certain error, different levels of calibration can be performed. First, we Perform a rough calibration;

S4: setting the delay of the delay chip to a set value of 100 units, and obtaining the number of pulses N1, which is obtained by subtracting M from M1 to obtain the number K100 of oscillations generated by 100 unit setting values. In theory, K100 should be 100 times K, but the temperature drift and the nonlinearity of the chip will be different, so the measurement is not accurate; then adjust the delay control data to 99 units set time or 101 The unit sets the time, repeats step S4, and then calculates K99 and K101, and compares it with 100K, so that the obtained value is within the K range. In this embodiment, only the delay of 100 unit setting values is listed. In fact, in fact, you can also list 1000 or a few units of the set value, this can be based on the user's needs, you can perform different settings.

Since the coarse calibration can only calibrate the error greater than one unit set value, the error of less than one unit set value can be adjusted by the analog control of the delay chip MC100EP196 to make fine adjustment, so that K100 is closer to 100 times K, through the above In the step we can get an accurate delay value of 100 units.

Various other changes and modifications may be made by those skilled in the art in light of the above-described technical solutions and concepts, and all such changes and modifications are intended to fall within the scope of the appended claims.

Claims

A high-precision delayed clock calibration system, comprising: a NAND gate, an AND gate, a delay chip, a multiplexer and a processing module, the multiplexer comprising a calibration output and a clock output, The processing module includes a delay control terminal, a selection control terminal, and a control switch terminal;

One input of the AND gate is connected to the output of the NAND gate, and the other input of the AND gate is for receiving a clock input; the output of the AND gate is connected to the input of the multiplexer via a delay chip, The delay control end and the selection control end of the processing module are respectively connected to the control end of the delay chip and the control end of the multiplexer, and the two input ends of the NAND gate are respectively connected to the control switch end of the processing module And a calibration output of the multiplexer;

The selection control end of the processing module and the control switch end have the same output logic. When the selection control end of the processing module outputs a high level, the multiplexer outputs a calibration signal through the calibration output end, and at the selection control end of the processing module When the output is low, the multiplexer outputs a clock signal through the clock output.
The high precision delayed clock calibration system of claim 1 further comprising a frequency divider, the calibration output of said multiplexer being electrically coupled to the processing module by a frequency divider.
The high precision delayed clock calibration system of claim 1 wherein said multiplexer is a two way selector.
The high precision delayed clock calibration system of claim 1 wherein said time delay chip is of the type MC100EP196.
A high-precision delayed clock calibration system, comprising: a NOT gate, an AND gate, a delay chip, a multiplexer and a processing module, the multiplexer comprising a calibration output and a clock output, the processing The module includes a delay control terminal and a selection control terminal;

The two input ends of the AND gate are respectively connected to the output terminal of the NOT gate and the clock input terminal; the output end of the AND gate is connected to the input end of the multiplexer via a delay chip, and the delay control of the processing module The terminal and the selection control terminal are respectively connected to the control end of the delay chip and the control end of the multiplexer, and the input terminals of the NOT gate are respectively connected to the control switch end of the processing module and the calibration output end of the multiplexer;

When the selection control terminal of the processing module outputs a high level, the multiplexer outputs a calibration signal through the calibration output terminal, and when the selection control terminal of the processing module outputs a low level, the multiplexer outputs a clock signal through the clock output terminal.
The high-precision delayed clock calibration system of claim 5, further comprising a frequency divider, the calibration output of the multiplexer being electrically coupled to the processing module by a frequency divider.
A delayed clock calibration method, comprising the steps of:

S1: the output delay of the control delay chip is zero, and the number of pulses M is calculated;

S2: the output delay of the control delay chip is 1 unit set value, and the number of pulses is calculated N;

S3: Calculating the difference K between M and N, which is the number of oscillations generated by delaying a unit set value;

S4: The output delay of the control delay chip is set to 100 units, and the number of pulses N1 is calculated;

S5: Calculating the difference K100 between M and N1, the difference K100 is the number of oscillations generated by delaying 100 unit set values;

S6: Determine whether the difference between K100 and 100*K is within a preset range, and if yes, end, if no, return to step S4 and adjust the output delay.
The delayed clock calibration method of claim 7, wherein the predetermined range is K.