CN116633325A - Programmable long delay circuit - Google Patents

Programmable long delay circuit Download PDF

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Publication number
CN116633325A
CN116633325A CN202310529240.XA CN202310529240A CN116633325A CN 116633325 A CN116633325 A CN 116633325A CN 202310529240 A CN202310529240 A CN 202310529240A CN 116633325 A CN116633325 A CN 116633325A
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CN
China
Prior art keywords
delay
module
output
input end
inverter
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Pending
Application number
CN202310529240.XA
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Chinese (zh)
Inventor
毛洪卫
勇智强
贺泽斌
许宏劲
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Beijing Jialyu Electronic Co ltd
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Beijing Jialyu Electronic Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Jialyu Electronic Co ltd filed Critical Beijing Jialyu Electronic Co ltd
Priority to CN202310529240.XA priority Critical patent/CN116633325A/en
Publication of CN116633325A publication Critical patent/CN116633325A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection

Abstract

The application provides a programmable long delay circuit, comprising: the device comprises an oscillator module, a delay signal selection module and a control module; the oscillator module is used for determining whether to output an output signal for representing starting or stopping oscillation according to the output result of the control module; the delay module is connected with the delay signal selection module and is used for delaying according to the output signal of the oscillator module and sending a delay result to the delay signal selection module; the delay signal selection module is connected with the delay module and is used for selecting a delay signal according to an external delay selection signal; and the control module is used for determining the on or off condition of the oscillator module based on the signal to be delayed and the delay signal generated by the delay signal selection module. The application can effectively alleviate the problems of large size area or high power consumption of the delay circuit in the prior art, and simultaneously, the programmable delay signal selection module is added, so that different delay results can be selected according to design requirements.

Description

Programmable long delay circuit
Technical Field
The present application relates to the field of integrated circuits, and more particularly, to a programmable long delay circuit.
Background
Where there are many delay circuits required in designing an integrated circuit, such delays may be on the order of up to milliseconds, depending on the design requirements; in the prior art, some design methods use stacking of inverter chains, or use capacitive resistors to form a delay circuit; there are also flip-flops that delay signals by a long time according to the clock frequency.
Such designs, the design of inverter chains and resistive-capacitive networks can greatly increase chip area; the area size of the flip-flop chain is greatly improved compared to the inverter chain or the resistor-capacitor network, but the flip-flop chain requires a clock to be provided inside or outside the chip, and this approach creates unnecessary pin and power consumption waste for the one-time delay requirement.
Disclosure of Invention
The application aims to solve the technical problems of how to alleviate the large size area or high power consumption of the delay circuit and select different delay results according to design requirements; in view of this, the present application provides a programmable long delay circuit.
The technical scheme adopted by the application is that the programmable long delay circuit comprises: the device comprises an oscillator module, a delay signal selection module and a control module; wherein, the liquid crystal display device comprises a liquid crystal display device,
the oscillator module is connected with the control module and the delay module and is used for determining whether to output an output signal for representing starting or stopping oscillation according to the output result of the control module;
the delay module is connected with the delay signal selection module and is used for delaying according to the output signal of the oscillator module and sending a delay result to the delay signal selection module;
the delay signal selection module is connected with the delay module and is used for selecting a delay signal matched with the current working condition according to the external delay selection signal;
and the control module is used for determining the starting or closing condition of the oscillator module based on the signal to be delayed and the delay signal generated by the delay signal selection module.
In one embodiment, the delay module comprises at least two delay cells connected in sequence, wherein each delay cell
The first input end of the first delay unit is connected with the output end of the first delay unit, the second input end receives the output signal of the oscillator module, the output ends are respectively connected with the first input end and the second input end of the second delay unit, and meanwhile, the first output of the first delay unit is connected to the delay signal selection module;
the output end of the nth delay unit is connected with the first input end of the nth delay unit, meanwhile, the nth output serving as a delay module is connected with the delay signal selection module, and the second input end is connected with the output end of the (n-1) th delay unit.
In one embodiment, the delay unit comprises two input ports and one output port, comprising internally 5 inverters, one tri-state gate and two controlled switches, wherein,
the control end of the tri-state gate is connected with the second input end of the delay unit, the input end of the tri-state gate is connected with the first input end of the delay unit, and the output end of the tri-state gate is connected with the input end of the first switch;
the input end of the first inverter is connected with the second input end of the delay unit, and the output end of the first inverter is connected with the input end of the second inverter and the control end of the first controlled switch;
the input end of the first controlled switch is connected with the output end of the tri-state gate, the output end of the first controlled switch is respectively connected with the input end of the third inverter and the output end of the second switch, and the control end of the first controlled switch is connected with the output end of the first inverter;
the input end of the second inverter is connected with the output end of the first inverter, and the output end of the second inverter is connected with the control end of the second controlled switch;
the input end of the third inverter is connected with the output end of the first controlled switch, and the output end of the third inverter is respectively connected with the input ends of the fourth inverter and the fifth inverter;
the input end of the fourth inverter is connected with the output end of the third inverter, and the output end of the fourth inverter is connected with the input end of the second controlled switch;
the input end of the second controlled switch is connected with the output end of the fourth inverter, and the output end of the second controlled switch is connected with the input end of the third inverter;
the input end of the fifth inverter is connected with the output end of the third inverter, and the output end is an output signal of the delay unit;
in one embodiment, when the second input end of the delay unit is at a low level, the tri-state gate is turned on, the first controlled switch is closed, the second controlled switch is opened, and the signal of the output end of the delay unit and the signal of the first input end are in opposite phases; when the second input end of the delay unit is at a high level, the three-state gate is turned off, the first controlled switch is turned off, and the second controlled switch is turned on, so that the signal of the output end of the delay unit keeps the current state and is not controlled by the first input end.
In one embodiment, the delay signal selection module is a plurality of selectors, an input terminal is an output terminal of each of the delay units in the delay module, an output terminal is a delay result output, and the result is sent to the control module.
By adopting the technical scheme, the embodiment provided by the application can effectively solve the problems of large size area or high power consumption of the delay circuit in the prior art, and meanwhile, the programmable delay signal selection module is added, so that different delay results can be selected according to design requirements.
Drawings
FIG. 1 is a schematic diagram of a programmable long delay circuit according to an embodiment of the application;
fig. 2 is a schematic diagram of a delay module structure according to an embodiment of the present application;
fig. 3 is a schematic diagram of a delay unit according to an embodiment of the application.
Reference numerals
A 1-control module, a 2-oscillator module, a 3-delay module, and a 4-delay signal selection module;
three-state gate 301, first controlled switch1, second controlled switch2, first inverter inv1, second inverter inv2, third inverter inv3, fourth inverter inv4, fifth inverter inv5.
Detailed Description
In order to further describe the technical means and effects adopted by the present application for achieving the intended purpose, the following detailed description of the present application is given with reference to the accompanying drawings and preferred embodiments.
In the drawings, the thickness, size and shape of the object have been slightly exaggerated for convenience of explanation. The figures are merely examples and are not drawn to scale.
It will be further understood that the terms "comprises," "comprising," "includes," "including," "having," "containing," and/or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of the following" appears after a list of features that are listed, the entire listed feature is modified instead of modifying a separate element in the list. Furthermore, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
As used herein, the terms "substantially," "about," and the like are used as terms of a table approximation, not as terms of a table level, and are intended to illustrate inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
In one embodiment of the present application, a programmable long delay circuit, as shown in fig. 1, includes:
an oscillator module 2, a delay module 3, a delay signal selection module 4, a control module 1; wherein, the liquid crystal display device comprises a liquid crystal display device,
the oscillator module 2 is connected with the control module 1 and the delay module 3 and is used for determining whether to output an output signal for representing starting or stopping oscillation according to the output result of the control module 1;
a delay module 3 connected to the delay signal selection module 4 for delaying according to the output signal of the oscillator module 2 and transmitting the delay result to the delay signal selection module 4;
the delay signal selection module 4 is connected with the delay module 3 and is used for selecting a delay signal matched with the current working condition according to an external delay selection signal;
a control module 1 for determining the on or off condition of the oscillator module 2 based on the signal to be delayed and the delay signal generated by the delay signal selection module 4.
In this embodiment, referring again to fig. 1, when the signal to be delayed is valid, the control module 1 controls the oscillator to start oscillating; when the delay process is finished, the control module 1 controls the oscillator to finish oscillation.
The delay module 3 delays the output signal of the oscillator module 2 and sends the delay result to the delay signal selection module 4.
In some embodiments, as shown in fig. 2, the delay module 3 includes n delay units connected in turn, where the output of each delay unit is taken as one output of the delay module 3, and a first input terminal of the first delay unit is connected to the output terminal of the first delay unit, a second input terminal receives the output signal of the oscillator module 2, and output terminals are respectively connected to the first input terminal and the second input terminal of the second delay unit, and meanwhile, taken as the first output of the delay module 3, connected to the delay signal selecting module 4; and so on, until the output end of the nth delay unit is connected with the first input end of the nth delay unit, the nth output serving as the delay module 3 is connected to the delay signal selection module 4, and the second input end is connected with the output end of the n-1 th delay unit.
That is, each time the signal generated by the oscillator module 2 passes through a delay unit, it is divided by 2, i.e., the delay increases by an index of 2; if the required delay time is not 2 times, the oscillation frequency of the oscillator module 2 can be modified to generate different delay times;
specifically, the delay unit is used for logically processing an input signal and comprises two input ports and an output port, wherein the delay unit internally comprises 5 inverters, a tri-state gate and two controlled switches,
the control end of the tri-state gate 301 is connected with the second input end in2 of the delay unit, the input end is connected with the first input end in1 of the delay unit, and the output end is connected with the input end of the first controlled switch 1;
the input end of the first inverter inv1 is connected with the second input end in2 of the delay unit, and the output end of the first inverter inv1 is connected with the input end of the second inverter inv2 and the control end of the first controlled switch 1;
the input end of the first controlled switch1 is connected with the output end of the three-state gate 301, the output end is respectively connected with the input end of the third inverter inv3 and the output end of the second controlled switch2, and the control end is connected with the output end of the first inverter inv 1;
the input end of the second inverter inv2 is connected with the output end of the first inverter inv1, and the output end is connected with the control end of the second controlled switch 2;
the input end of the third inverter inv3 is connected with the output end of the first controlled switch1, and the output ends of the third inverter inv3 are respectively connected with the input ends of the fourth inverter inv4 and the fifth inverter inv 5;
the input end of the fourth inverter inv4 is connected with the output end of the third inverter inv3, and the output end of the fourth inverter inv4 is connected with the input end of the second controlled switch 2;
the input end of the second controlled switch2 is connected with the output end of the fourth inverter inv4, and the output end is connected with the input end of the third inverter inv 3;
the input end of the fifth inverter inv5 is connected with the output end of the third inverter inv3, and the output end is the output signal out of the delay unit.
In this embodiment, as shown in fig. 3, when the second input terminal in2 of the delay unit is at a low level, the tri-state gate 301 is turned on, the first controlled switch1 is closed, the second controlled switch2 is opened, and at this time, the output terminal signal out of the delay unit is inverted from the signal in1 of the first input terminal; when the second input terminal in2 of the delay unit is at a high level, the tri-state gate 301 is turned off, the first controlled switch1 is turned off, and the second controlled switch2 is turned on, and at this time, the output terminal signal out of the delay unit maintains the current state and is not controlled by the first input terminal in 1.
In this embodiment, the delay signal selecting module 4 is a multiple selector, the input terminal is the output terminal out of each delay unit in the delay module 3, the output terminal out is the delay result output, and the result is sent to the control module 1.
Compared with the prior art, the embodiment has at least the following advantages:
1) The embodiment can effectively solve the problems of large size area or high power consumption of the delay circuit in the prior art;
2) In this embodiment, by adding a programmable delay signal selection module, different delay results can be selected according to design requirements.
While the application has been described in connection with specific embodiments thereof, it is to be understood that these drawings are included in the spirit and scope of the application, it is not to be limited thereto.

Claims (5)

1. A programmable long delay circuit comprising: the device comprises an oscillator module, a delay signal selection module and a control module; wherein, the liquid crystal display device comprises a liquid crystal display device,
the oscillator module is connected with the control module and the delay module and is used for determining whether to output an output signal for representing starting or stopping oscillation according to the output result of the control module;
the delay module is connected with the delay signal selection module and is used for delaying according to the output signal of the oscillator module and sending a delay result to the delay signal selection module;
the delay signal selection module is connected with the delay module and is used for selecting a delay signal matched with the current working condition according to the external delay selection signal;
and the control module is used for determining the starting or closing condition of the oscillator module based on the signal to be delayed and the delay signal generated by the delay signal selection module.
2. A programmable long delay circuit according to claim 1, characterized in that the delay module comprises at least two delay cells connected in sequence, wherein,
the first input end of the first delay unit is connected with the output end of the first delay unit, the second input end receives the output signal of the oscillator module, the output ends are respectively connected with the first input end and the second input end of the second delay unit, and meanwhile, the first output of the first delay unit is connected to the delay signal selection module; and so on until
The output end of the nth delay unit is connected with the first input end of the nth delay unit, meanwhile, the nth output serving as a delay module is connected with the delay signal selection module, and the second input end is connected with the output end of the (n-1) th delay unit.
3. A programmable long delay circuit according to claim 1 characterized in that said delay cell comprises two input ports and one output port, comprising internally 5 inverters, one tri-state gate and two controlled switches, wherein,
the control end of the tri-state gate is connected with the second input end of the delay unit, the input end of the tri-state gate is connected with the first input end of the delay unit, and the output end of the tri-state gate is connected with the input end of the first controlled switch;
the input end of the first inverter is connected with the second input end of the delay unit, and the output end of the first inverter is connected with the input end of the second inverter and the control end of the first controlled switch;
the input end of the first controlled switch is connected with the output end of the tri-state gate, the output end of the first controlled switch is respectively connected with the input end of the third inverter and the output end of the second switch, and the control end of the first controlled switch is connected with the output end of the first inverter;
the input end of the second inverter is connected with the output end of the first inverter, and the output end of the second inverter is connected with the control end of the second controlled switch;
the input end of the third inverter is connected with the output end of the first controlled switch, and the output end of the third inverter is respectively connected with the input ends of the fourth inverter and the fifth inverter;
the input end of the fourth inverter is connected with the output end of the third inverter, and the output end of the fourth inverter is connected with the input end of the second controlled switch;
the input end of the second controlled switch is connected with the output end of the fourth inverter, and the output end of the second controlled switch is connected with the input end of the third inverter;
the input end of the fifth inverter is connected with the output end of the third inverter, and the output end is an output signal of the delay unit.
4. A programmable long delay circuit according to claim 3,
when the second input end of the delay unit is at a low level, the tri-state gate is conducted, the first controlled switch is closed, the second controlled switch is opened, and at the moment, the signal of the output end of the delay unit is in phase opposition with the signal of the first input end;
when the second input end of the delay unit is at a high level, the three-state gate is turned off, the first controlled switch is turned off, and the second controlled switch is turned on, so that the signal of the output end of the delay unit keeps the current state and is not controlled by the first input end.
5. A programmable long delay circuit according to claim 1,
the delay signal selection module is a plurality of selectors, the input end is the output end of each delay unit in the delay module, the output end is the delay result output, and the result is sent to the control module.
CN202310529240.XA 2023-05-11 2023-05-11 Programmable long delay circuit Pending CN116633325A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310529240.XA CN116633325A (en) 2023-05-11 2023-05-11 Programmable long delay circuit

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Application Number Priority Date Filing Date Title
CN202310529240.XA CN116633325A (en) 2023-05-11 2023-05-11 Programmable long delay circuit

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CN102446551A (en) * 2010-09-30 2012-05-09 北京兆易创新科技有限公司 Method and device for optimizing datum access of asynchronous storage chip
CN102466779A (en) * 2010-11-16 2012-05-23 北京中电华大电子设计有限责任公司 Built-in testing method for delay of trigger and circuit
CN102684646A (en) * 2012-04-28 2012-09-19 北京大学 Single-edge master-slave D trigger
JP2013127396A (en) * 2011-12-19 2013-06-27 Renesas Electronics Corp Scan flip-flop and semiconductor integrated circuit device
WO2018121469A1 (en) * 2016-12-30 2018-07-05 深圳市志奋领科技有限公司 System and method for high-precision clock delay calibration
CN111884626A (en) * 2020-07-03 2020-11-03 上海华虹宏力半导体制造有限公司 Double-edge D flip-flop
CN112929023A (en) * 2021-01-25 2021-06-08 深圳市南方硅谷半导体有限公司 Wide-range ring oscillator

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080218233A1 (en) * 2007-03-05 2008-09-11 Nec Electronics Corporation Master-slave type flip-flop circuit and latch circuit
CN101291149A (en) * 2008-06-18 2008-10-22 北京中星微电子有限公司 Clock frequency dividing method based on trigger ring and clock frequency dividing circuit thereof
CN102446551A (en) * 2010-09-30 2012-05-09 北京兆易创新科技有限公司 Method and device for optimizing datum access of asynchronous storage chip
CN102466779A (en) * 2010-11-16 2012-05-23 北京中电华大电子设计有限责任公司 Built-in testing method for delay of trigger and circuit
JP2013127396A (en) * 2011-12-19 2013-06-27 Renesas Electronics Corp Scan flip-flop and semiconductor integrated circuit device
CN102684646A (en) * 2012-04-28 2012-09-19 北京大学 Single-edge master-slave D trigger
WO2018121469A1 (en) * 2016-12-30 2018-07-05 深圳市志奋领科技有限公司 System and method for high-precision clock delay calibration
CN111884626A (en) * 2020-07-03 2020-11-03 上海华虹宏力半导体制造有限公司 Double-edge D flip-flop
CN112929023A (en) * 2021-01-25 2021-06-08 深圳市南方硅谷半导体有限公司 Wide-range ring oscillator

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