WO2018120304A1 - 薄膜晶体管阵列基板及显示面板 - Google Patents

薄膜晶体管阵列基板及显示面板 Download PDF

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Publication number
WO2018120304A1
WO2018120304A1 PCT/CN2017/071157 CN2017071157W WO2018120304A1 WO 2018120304 A1 WO2018120304 A1 WO 2018120304A1 CN 2017071157 W CN2017071157 W CN 2017071157W WO 2018120304 A1 WO2018120304 A1 WO 2018120304A1
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Prior art keywords
pixel
pixel unit
electrode
thin film
film transistor
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PCT/CN2017/071157
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English (en)
French (fr)
Inventor
赵丽
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/327,387 priority Critical patent/US10401692B2/en
Publication of WO2018120304A1 publication Critical patent/WO2018120304A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133753—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers with different alignment orientations or pretilt angles on a same surface, e.g. for grey scale or improved viewing angle
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/122—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode having a particular pattern
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2203/00—Function characteristic
    • G02F2203/01—Function characteristic transmissive

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor array substrate and a display panel.
  • a pixel electrode is disposed in a pixel unit in a conventional thin film transistor array substrate.
  • the pixel electrode includes a strip electrode and a stem electrode.
  • the strip electrodes are disposed in a pixel partition divided by the trunk electrodes.
  • the strip electrodes are used to form a uniform electric field force in the pixel partition, otherwise the electric field force will be concentrated in a local area in the pixel partition, and the pixel electrode cannot make the electric field force Uniformly distributed throughout the pixel unit.
  • the gap weakens the electric field force of the pixel unit, so that the transmittance of the pixel unit is low.
  • a thin film transistor array substrate comprising: at least two pixel unit rows, at least two of the pixel unit rows are arranged in an array in a first direction, the pixel unit row comprising at least two pixel units, At least two of the pixel units in the row of pixel cells are arranged in an array in a second direction; at least two pixel unit columns, at least two of which are arranged in an array in the second direction, the pixels
  • the unit column includes at least two of the pixel units, and at least two of the pixel unit columns are arranged in an array along the first direction; wherein the pixel unit comprises: a trunk electrode, the trunk The electrode divides the pixel unit into at least four pixel partitions; at least four strip electrode arrays, the strip electrode array is disposed in the pixel partition, the strip electrode array comprises at least two electrodes; at least four connecting electrodes
  • the connection electrode is disposed in the pixel partition, and the connection electrode and at least two of the strips located in the pixel partition Connecting electrodes for increasing the transmittance
  • the longitudinal direction of the connection electrode is parallel to the first direction.
  • the longitudinal direction of the connection electrode is parallel to the second direction.
  • connection electrodes of any two of the pixel units in the same pixel unit row have the same length direction, and are located in any two of the pixel unit columns.
  • the length direction of the connection electrodes is the same; or the connection electrodes of any two of the pixel units in the same pixel unit row have the same length direction, and the two adjacent pixel units in the same pixel unit column.
  • the length direction of the connecting electrode is perpendicular; or the connecting electrodes of two adjacent pixel units in the same pixel unit row are perpendicular to the longitudinal direction, and are located in the same two of the same pixel unit column.
  • the length direction of the connection electrode of the pixel unit is perpendicular.
  • a thin film transistor array substrate comprising: at least two pixel unit rows, at least two of the pixel unit rows are arranged in an array in a first direction, the pixel unit row comprising at least two pixel units, At least two of the pixel units in the row of pixel cells are arranged in an array in a second direction; at least two pixel unit columns, at least two of which are arranged in an array in the second direction, the pixels
  • the unit column includes at least two of the pixel units, and at least two of the pixel unit columns are arranged in an array along the first direction; wherein the pixel unit comprises: a trunk electrode, the trunk The electrode divides the pixel unit into at least four pixel partitions; at least four strip electrode arrays, the strip electrode array is disposed in the pixel partition, the strip electrode array comprises at least two electrodes; at least four connecting electrodes
  • the connection electrode is disposed in the pixel partition, and the connection electrode and at least two of the strips located in the pixel partition Electrodes are connected to the connection electrode for improving
  • an angle between a longitudinal direction of the connection electrode and a longitudinal direction of the strip electrode is in a range of 1 to 89 degrees.
  • the included angle is 45 degrees.
  • the longitudinal direction of the connection electrode is parallel to the first direction.
  • the longitudinal direction of the connection electrode is parallel to the second direction.
  • connection electrodes of any two of the pixel units in the same pixel unit row have the same length direction, and are located in any two of the pixel unit columns.
  • the length direction of the connection electrodes is the same; or the connection electrodes of any two of the pixel units in the same pixel unit row have the same length direction, and the two adjacent pixel units in the same pixel unit column.
  • the length direction of the connecting electrode is perpendicular; or the connecting electrodes of two adjacent pixel units in the same pixel unit row are perpendicular to the longitudinal direction, and are located in the same two of the same pixel unit column.
  • the length direction of the connection electrode of the pixel unit is perpendicular.
  • connection electrode is for increasing a total area occupied by the pixel electrode in the pixel unit to increase an electric field effect of the pixel electrode applied to liquid crystal molecules in the liquid crystal layer force.
  • connection electrode is further configured to reduce electric field interference between any two of the strip electrodes in the pixel partition.
  • a display panel comprising: a color filter substrate; a liquid crystal layer; a thin film transistor array substrate, the thin film transistor array substrate comprising: at least two pixel unit rows, at least two of the pixel unit rows being arrayed in a first direction Arranging, the pixel unit row includes at least two pixel units, at least two of the pixel unit rows are arranged in an array in a second direction; at least two pixel unit columns, at least two of the pixel units The columns are arranged in an array along the second direction, the column of pixel units includes at least two of the pixel units, and at least two of the pixel units of the pixel unit are arranged in an array along the first direction
  • the pixel unit comprises: a stem electrode, the stem electrode dividing the pixel unit into at least four pixel partitions; at least four strip electrode arrays, wherein the strip electrode array is disposed in the pixel partition
  • the strip electrode array includes at least two electrodes; at least four connection electrodes, the connection electrodes are disposed in the pixel partition, S
  • an angle between a longitudinal direction of the connection electrode and a longitudinal direction of the strip electrode is in a range of 1 to 89 degrees.
  • the included angle is 45 degrees.
  • the length direction of the connection electrode is parallel to the first direction.
  • the length direction of the connection electrode is parallel to the second direction.
  • connection electrodes of any two of the pixel units in the same pixel unit row have the same length direction, and the connections of any two of the pixel units in the same pixel unit column are
  • the length direction of the electrodes is the same; or the connecting electrodes of any two of the pixel units in the same pixel unit row have the same length direction, and are located in the same two pixel units in the same pixel unit column.
  • the length direction of the connecting electrode is perpendicular; or the connecting electrodes of two adjacent pixel units in the same pixel unit row are perpendicular to the longitudinal direction, and the two adjacent pixels in the same pixel unit column are located
  • the length direction of the connection electrode of the unit is perpendicular.
  • connection electrode is for increasing a total area occupied by the pixel electrode in the pixel unit to increase an electric field force applied by the pixel electrode to liquid crystal molecules in the liquid crystal layer.
  • connection electrode of the present invention increases the total area occupied by the pixel electrode in the pixel unit, the electric field force applied to the liquid crystal molecules in the liquid crystal layer by the pixel electrode can be increased. Therefore, the transmittance of the pixel unit can be improved without changing the aperture ratio of the pixel unit.
  • FIG. 2 is a schematic view showing a second embodiment of a pixel unit in a thin film transistor array substrate of the present invention
  • FIG. 5 are schematic diagrams showing three arrangements of pixel units in a thin film transistor array substrate according to the present invention.
  • FIG. 6 is a schematic diagram showing a simulation effect and a transmittance ratio of a first embodiment, a second embodiment, and a conventional pixel unit of a pixel unit of a thin film transistor array substrate of the present invention in a first viewing angle;
  • FIG. 7 is a schematic diagram showing a relationship between a transmittance and a voltage of a first embodiment, a second embodiment, and a conventional pixel unit of a pixel unit of a thin film transistor array substrate of the present invention in a first viewing angle;
  • FIG. 9 is a schematic diagram showing a relationship between a transmittance and a voltage of a first embodiment, a second embodiment, and a conventional pixel unit of a pixel unit of a thin film transistor array substrate of the present invention in a second viewing angle;
  • FIG. 10 is a schematic diagram showing a simulation effect and a transmittance ratio of a first embodiment, a second embodiment, and a conventional pixel unit of a pixel unit of a thin film transistor array substrate of the present invention in a third viewing angle;
  • the display panel of the present invention may be a TFT-LCD (Thin Film Transistor Liquid) Crystal Display, thin film transistor liquid crystal display panel, etc.
  • TFT-LCD Thin Film Transistor Liquid
  • LCD Thin Film Transistor Liquid
  • a first embodiment of the display panel of the present invention includes a color filter substrate, a liquid crystal layer, and a thin film transistor array substrate, the liquid crystal layer being disposed between the color film substrate and the thin film transistor array substrate.
  • FIG. 1 is a schematic diagram of a first embodiment of a pixel unit 101 in a thin film transistor array substrate according to the present invention
  • FIGS. 3 to 5 are pixel units 101 in a thin film transistor array substrate of the present invention.
  • At least two of the rows of pixel cells are arranged in an array in a first direction 103, the row of pixel cells comprising at least two pixel cells 101, at least two of the pixel cells 101 in the row of pixels Arranged in the form of an array.
  • the first direction 103 is a direction parallel to the data line 302
  • the second direction 102 is a direction parallel to the scan line 301.
  • At least two of the pixel unit columns are arranged in an array along the second direction 102, the pixel unit column includes at least two of the pixel units 101, and at least two of the pixel unit columns are along the pixel unit 101
  • the first directions 103 are arranged in an array.
  • the scan line 301 and the data line 302 are both connected to the pixel unit 101.
  • the pixel unit 101 includes a trunk electrode 1011, an array of at least four strip electrodes 1012, and at least four connection electrodes 1013.
  • the stem electrode 1011 divides the pixel unit 101 into at least four pixel partitions.
  • the array of strip electrodes 1012 is disposed within the pixel partition, and the array of strip electrodes 1012 includes at least two electrodes 1012.
  • the connection electrode 1013 is disposed in the pixel partition, and the connection electrode 1013 is connected to at least two strip electrodes 1012 located in the pixel partition, and the connection electrode 1013 is used to increase the pixel unit 101. Penetration rate.
  • the connection electrode 1013 is configured to increase a total area occupied by the pixel electrode in the pixel unit 101 to increase an electric field force applied by the pixel electrode to liquid crystal molecules in the liquid crystal layer, thereby The transmittance of the pixel unit 101 is increased.
  • connection electrode 1013 is also used to reduce electric field interference between any two of the strip electrodes 1012 in the pixel partition.
  • an angle between a longitudinal direction of the connection electrode 1013 and a longitudinal direction of the strip electrode 1012 is in a range of 1 to 89 degrees.
  • the included angles are 1 degree, 5 degrees, 9 degrees, 13 degrees, 17 degrees, 21 degrees, 25 degrees, 29 degrees, 33 degrees, 37 degrees, 41 degrees, 45 degrees, 49 degrees, 53 degrees, 57 degrees.
  • the included angle is 45 degrees.
  • connection electrodes 1013 in the four pixel sections of the pixel unit 101 are the same.
  • the length direction of the connection electrode 1013 is parallel to the second direction 102.
  • connection electrodes 1013 of any two of the pixel units 101 in the same pixel unit row have the same length direction, and the connections of the two adjacent pixel units 101 in the same pixel unit column are The longitudinal direction of the electrode 1013 is perpendicular.
  • connection electrodes 1013 of two adjacent pixel units 101 located in the same pixel unit row are perpendicular to the longitudinal direction, and the two adjacent pixel units 101 in the same pixel unit column are The length direction of the connection electrode 1013 is vertical.
  • FIG. 2 is a schematic view of a second embodiment of a pixel unit 101 in a thin film transistor array substrate of the present invention.
  • the second embodiment of the display panel of the present invention is similar to the first embodiment described above, except that:
  • connection electrode 1013 The length direction of the connection electrode 1013 is parallel to the first direction 103.
  • FIG. 6 is a simulation effect of a first embodiment, a second embodiment, and a conventional pixel unit of a pixel unit 101 of a thin film transistor array substrate of the present invention at a first viewing angle (Theta0°, Phi0°) and A schematic of the contrast of penetration.
  • Theta0° is an angle between the line of sight corresponding to the first viewing angle and the normal of the thin film transistor array substrate is 0°
  • Phi0° refers to the line of sight corresponding to the first viewing angle and the thin film transistor.
  • the angle between the long side direction and the short side direction of the array substrate is 0°.
  • the pixel unit 101 in the first embodiment of the present invention has a transmittance of 0.2540, and the transmittance of the conventional pixel unit is 0.2485. 2.2%. Also in the first viewing angle, the pixel unit 101 in the second embodiment of the present invention has a transmittance of 0.2540, and the transmittance of the conventional pixel unit is 0.2485, and the lifting ratio is 2.2%.
  • FIG. 7 is a perspective view of a first embodiment, a second embodiment, and a conventional pixel unit of a pixel unit 101 of a thin film transistor array substrate of the present invention at a first viewing angle (Theta0°, Phi0°). Schematic diagram of the relationship with voltage. As can be seen from FIG. 7, in the first viewing angle, and in the case where the voltage applied to the pixel electrode is in the range of 5 volts (V) to 14 volts, in the first embodiment of the present invention The transmittance 702 of the pixel unit 101 and the transmittance 703 of the pixel unit 101 in the second embodiment of the present invention are both higher than the transmittance 701 of the conventional pixel unit.
  • FIG. 8 is a simulation effect of a first embodiment, a second embodiment, and a conventional pixel unit of a pixel unit 101 of a thin film transistor array substrate of the present invention in a second viewing angle (Theta 60°, Phi0°) and A schematic of the contrast of penetration.
  • Theta 60° means that the angle of view corresponding to the second viewing angle is 60° from the normal line of the thin film transistor array substrate, and Phi0° refers to the line of sight corresponding to the second viewing angle and the thin film transistor.
  • the angle between the long side direction and the short side direction of the array substrate is 0°.
  • the pixel unit 101 in the first embodiment of the present invention has a transmittance of 0.1900, and the transmittance of the conventional pixel unit is 0.1856. 2.37%. Also in the second viewing angle, the pixel unit 101 in the second embodiment of the present invention has a transmittance of 0.1972, and the transmittance of the conventional pixel unit is 0.1856, and the lifting ratio is 6.25%.
  • FIG. 9 is a view showing a first embodiment, a second embodiment, and a conventional pixel unit of the pixel unit 101 of the thin film transistor array substrate of the present invention at a second viewing angle (Theta 60°, Phi0°). Schematic diagram of the relationship between permeability and voltage. As can be seen from FIG.
  • the pixel in the second embodiment of the present invention is higher than the transmittance 702 of the pixel unit 101 in the first embodiment of the present invention, and the transmittance 702 of the pixel unit 101 in the first embodiment of the present invention is higher than the conventional one.
  • the pixel unit has a high transmittance of 701.
  • FIG. 10 is a simulation effect of a first embodiment, a second embodiment, and a conventional pixel unit of a pixel unit 101 of a thin film transistor array substrate of the present invention at a third viewing angle (Theta 60°, Phi 90°) and A schematic of the contrast of penetration.
  • Theta 60° means that the angle of view corresponding to the third viewing angle is 60° from the normal of the thin film transistor array substrate, and the Phi 90° refers to the line of sight corresponding to the third viewing angle and the thin film transistor.
  • the angle between the long side direction and the short side direction of the array substrate is 90°.
  • the pixel unit 101 in the first embodiment of the present invention has a transmittance of 0.1972, and the transmittance of the conventional pixel unit is 0.1856. 6.25%. Also in the third viewing angle, the pixel unit 101 in the second embodiment of the present invention has a transmittance of 0.1900, and the transmittance of the conventional pixel unit is 0.1856, and the promotion ratio is 2.37%.
  • FIG. 11 is a perspective view of a first embodiment, a second embodiment, and a conventional pixel unit of a pixel unit 101 of a thin film transistor array substrate of the present invention at a third viewing angle (Theta 60°, Phi 90°). Schematic diagram of the relationship with voltage. As can be seen from FIG. 11,
  • the pixel in the first embodiment of the present invention The transmittance 702 of the unit 101 is higher than the transmittance 703 of the pixel unit 101 in the second embodiment of the present invention, and the transmittance 703 of the pixel unit 101 in the second embodiment of the present invention is larger than that of the conventional pixel.
  • the unit's penetration rate is 701.
  • the third embodiment of the display panel of the present invention is similar to the first embodiment or the second embodiment described above, except that:
  • connection electrode 1013 in the two pixel regions adjacent to each other in the first direction 103 and the second direction 102 in the pixel unit 101 is perpendicular.
  • connection electrode 1013 increases the total area occupied by the pixel electrode in the pixel unit 101, the electric field force applied to the liquid crystal molecules in the liquid crystal layer by the pixel electrode can be increased. Thereby, the transmittance of the pixel unit 101 can be improved without changing the aperture ratio of the pixel unit 101.
  • the present invention is also advantageous for improving the color shift problem of the display panel at a large viewing angle.

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Abstract

一种薄膜晶体管阵列基板及显示面板。薄膜晶体管阵列基板包括像素单元行以及像素单元列，像素单元行包括至少两像素单元（101）；像素单元列包括至少两像素单元（101）；像素单元（101）包括主干电极（1011）、连接电极（1013）和条状电极（1012），连接电极（1013）与至少两条状电极（1012）相连，连接电极（1013）用于提高像素单元（101）的穿透率。

Description

薄膜晶体管阵列基板及显示面板 技术领域
本发明涉及显示技术领域，特别涉及一种薄膜晶体管阵列基板及显示面板。
 背景技术
传统的薄膜晶体管阵列基板中的像素单元内设置有像素电极。该像素电极包括条状电极和主干电极。
所述条状电极设置于所述主干电极所划分的像素分区中。所述条状电极用于在所述像素分区中形成均匀的电场作用力，否则所述电场作用力会聚集于所述像素分区中的局部区域，此时像素电极便无法使得所述电场作用力均匀遍布于所述像素单元中。
在实践中，发明人发现现有技术至少存在以下问题：
因此，由于所述像素分区中两所述条状电极之间具有间隙，该间隙会削弱所述像素单元的电场作用力，从而使得所述像素单元的穿透率较低。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种薄膜晶体管阵列基板及显示面板，其能提高像素单元的穿透率。
 技术解决方案
为解决上述问题，本发明的技术方案如下：
一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：至少两像素单元行，至少两所述像素单元行沿第一方向以阵列的形式排列，所述像素单元行包括至少两像素单元，所述像素单元行中的至少两所述像素单元沿第二方向以阵列的形式排列；至少两像素单元列，至少两所述像素单元列沿所述第二方向以阵列的形式排列，所述像素单元列包括至少两所述像素单元，所述像素单元列中的至少两所述像素单元沿所述第一方向以阵列的形式排列；其中，所述像素单元包括：一主干电极，所述主干电极将所述像素单元划分为至少四像素分区；至少四条状电极阵列，所述条状电极阵列设置在所述像素分区内，所述条状电极阵列包括至少两条状电极；至少四连接电极，所述连接电极设置在所述像素分区内，所述连接电极与位于所述像素分区内的至少两所述条状电极相连，所述连接电极用于提高所述像素单元的穿透率；至少两扫描线；至少两数据线；其中，所述扫描线和所述数据线均与所述像素单元连接，所述第一方向为与所述数据线平行的方向，所述第二方向为与所述扫描线平行的方向，在所述像素分区内，所述连接电极的长度方向与所述条状电极的长度方向的夹角处于1度至89度的范围内。
在上述薄膜晶体管阵列基板中，所述连接电极的长度方向与所述第一方向平行。
在上述薄膜晶体管阵列基板中，所述连接电极的长度方向与所述第二方向平行。
在上述薄膜晶体管阵列基板中，位于同一所述像素单元行中的任意两所述像素单元的所述连接电极的长度方向相同，位于同一所述像素单元列中的任意两所述像素单元的所述连接电极的长度方向相同；或者位于同一所述像素单元行中的任意两所述像素单元的所述连接电极的长度方向相同，位于同一所述像素单元列中的相邻两所述像素单元的所述连接电极的长度方向垂直；或者位于同一所述像素单元行中的相邻两所述像素单元的所述连接电极的长度方向垂直，位于同一所述像素单元列中的相邻两所述像素单元的所述连接电极的长度方向垂直。
一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：至少两像素单元行，至少两所述像素单元行沿第一方向以阵列的形式排列，所述像素单元行包括至少两像素单元，所述像素单元行中的至少两所述像素单元沿第二方向以阵列的形式排列；至少两像素单元列，至少两所述像素单元列沿所述第二方向以阵列的形式排列，所述像素单元列包括至少两所述像素单元，所述像素单元列中的至少两所述像素单元沿所述第一方向以阵列的形式排列；其中，所述像素单元包括：一主干电极，所述主干电极将所述像素单元划分为至少四像素分区；至少四条状电极阵列，所述条状电极阵列设置在所述像素分区内，所述条状电极阵列包括至少两条状电极；至少四连接电极，所述连接电极设置在所述像素分区内，所述连接电极与位于所述像素分区内的至少两所述条状电极相连，所述连接电极用于提高所述像素单元的穿透率。
在上述薄膜晶体管阵列基板中，在所述像素分区内，所述连接电极的长度方向与所述条状电极的长度方向的夹角处于1度至89度的范围内。
在上述薄膜晶体管阵列基板中，所述夹角为45度。
在上述薄膜晶体管阵列基板中，所述连接电极的长度方向与所述第一方向平行。
在上述薄膜晶体管阵列基板中，所述连接电极的长度方向与所述第二方向平行。
在上述薄膜晶体管阵列基板中，位于同一所述像素单元行中的任意两所述像素单元的所述连接电极的长度方向相同，位于同一所述像素单元列中的任意两所述像素单元的所述连接电极的长度方向相同；或者位于同一所述像素单元行中的任意两所述像素单元的所述连接电极的长度方向相同，位于同一所述像素单元列中的相邻两所述像素单元的所述连接电极的长度方向垂直；或者位于同一所述像素单元行中的相邻两所述像素单元的所述连接电极的长度方向垂直，位于同一所述像素单元列中的相邻两所述像素单元的所述连接电极的长度方向垂直。
在上述薄膜晶体管阵列基板中，所述连接电极用于增加所述像素电极在所述像素单元中所占据的总面积，以增加所述像素电极施加给所述液晶层中的液晶分子的电场作用力。
在上述薄膜晶体管阵列基板中，所述连接电极还用于降低所述像素分区内任意两所述条状电极之间的电场干扰。
一种显示面板，所述显示面板包括：彩膜基板；液晶层；薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：至少两像素单元行，至少两所述像素单元行沿第一方向以阵列的形式排列，所述像素单元行包括至少两像素单元，所述像素单元行中的至少两所述像素单元沿第二方向以阵列的形式排列；至少两像素单元列，至少两所述像素单元列沿所述第二方向以阵列的形式排列，所述像素单元列包括至少两所述像素单元，所述像素单元列中的至少两所述像素单元沿所述第一方向以阵列的形式排列；其中，所述像素单元包括：一主干电极，所述主干电极将所述像素单元划分为至少四像素分区；至少四条状电极阵列，所述条状电极阵列设置在所述像素分区内，所述条状电极阵列包括至少两条状电极；至少四连接电极，所述连接电极设置在所述像素分区内，所述连接电极与位于所述像素分区内的至少两所述条状电极相连，所述连接电极用于提高所述像素单元的穿透率。
在上述显示面板中，在所述像素分区内，所述连接电极的长度方向与所述条状电极的长度方向的夹角处于1度至89度的范围内。
在上述显示面板中，所述夹角为45度。
在上述显示面板中，所述连接电极的长度方向与所述第一方向平行。
在上述显示面板中，所述连接电极的长度方向与所述第二方向平行。
在上述显示面板中，位于同一所述像素单元行中的任意两所述像素单元的所述连接电极的长度方向相同，位于同一所述像素单元列中的任意两所述像素单元的所述连接电极的长度方向相同；或者位于同一所述像素单元行中的任意两所述像素单元的所述连接电极的长度方向相同，位于同一所述像素单元列中的相邻两所述像素单元的所述连接电极的长度方向垂直；或者位于同一所述像素单元行中的相邻两所述像素单元的所述连接电极的长度方向垂直，位于同一所述像素单元列中的相邻两所述像素单元的所述连接电极的长度方向垂直。
在上述显示面板中，所述连接电极用于增加所述像素电极在所述像素单元中所占据的总面积，以增加所述像素电极施加给所述液晶层中的液晶分子的电场作用力。
在上述显示面板中，所述连接电极还用于降低所述像素分区内任意两所述条状电极之间的电场干扰。
 有益效果
相对现有技术，由于本发明的连接电极增加了所述像素电极在所述像素单元中所占据的总面积，因此可以增加所述像素电极施加给所述液晶层中的液晶分子的电场作用力，从而可以使得所述像素单元的开口率不变的情况下，提高所述像素单元的穿透率。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下。
图1为本发明的薄膜晶体管阵列基板中的像素单元的第一实施例的示意图；
图2为本发明的薄膜晶体管阵列基板中的像素单元的第二实施例的示意图；
图3至图5为本发明的薄膜晶体管阵列基板中像素单元的三种排列方式的示意图；
图6为在第一视角下关于本发明的薄膜晶体管阵列基板的像素单元的第一实施例、第二实施例与传统的像素单元的模拟效果及穿透率对比的示意图；
图7为在第一视角下关于本发明的薄膜晶体管阵列基板的像素单元的第一实施例、第二实施例与传统的像素单元的穿透率与电压关系的示意图；
图8为在第二视角下关于本发明的薄膜晶体管阵列基板的像素单元的第一实施例、第二实施例与传统的像素单元的模拟效果及穿透率对比的示意图；
图9为在第二视角下关于本发明的薄膜晶体管阵列基板的像素单元的第一实施例、第二实施例与传统的像素单元的穿透率与电压关系的示意图；
图10为在第三视角下关于本发明的薄膜晶体管阵列基板的像素单元的第一实施例、第二实施例与传统的像素单元的模拟效果及穿透率对比的示意图；
图11为在第三视角下关于本发明的薄膜晶体管阵列基板的像素单元的第一实施例、第二实施例与传统的像素单元的穿透率与电压关系的示意图。
 本发明的最佳实施方式
本说明书所使用的词语“实施例”意指实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为“一个或多个”，除非另外指定或从上下文可以清楚确定单数形式。
本发明的显示面板可以是TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示面板）等。
本发明的显示面板的第一实施例包括彩膜基板、液晶层和薄膜晶体管阵列基板，所述液晶层设置于所述彩膜基板和所述薄膜晶体管阵列基板之间。
参考图1、图3至图5，图1为本发明的薄膜晶体管阵列基板中的像素单元101的第一实施例的示意图，图3至图5为本发明的薄膜晶体管阵列基板中像素单元101的三种排列方式的示意图。
所述薄膜晶体管阵列基板包括至少两扫描线301、至少两数据线302、至少两像素单元行、至少两像素单元列。
至少两所述像素单元行沿第一方向103以阵列的形式排列，所述像素单元行包括至少两像素单元101，所述像素单元行中的至少两所述像素单元101沿第二方向102以阵列的形式排列。所述第一方向103为与所述数据线302平行的方向，所述第二方向102为与所述扫描线301平行的方向。
至少两所述像素单元列沿所述第二方向102以阵列的形式排列，所述像素单元列包括至少两所述像素单元101，所述像素单元列中的至少两所述像素单元101沿所述第一方向103以阵列的形式排列。
所述扫描线301和所述数据线302均与所述像素单元101连接。其中，所述像素单元101包括一主干电极1011、至少四条状电极1012阵列和至少四连接电极1013。
所述主干电极1011将所述像素单元101划分为至少四像素分区。所述条状电极1012阵列设置在所述像素分区内，所述条状电极1012阵列包括至少两条状电极1012。所述连接电极1013设置在所述像素分区内，所述连接电极1013与位于所述像素分区内的至少两所述条状电极1012相连，所述连接电极1013用于提高所述像素单元101的穿透率。具体地，所述连接电极1013用于增加所述像素电极在所述像素单元101中所占据的总面积，以增加所述像素电极施加给所述液晶层中的液晶分子的电场作用力，从而提高所述像素单元101的穿透率。
所述连接电极1013还用于降低所述像素分区内任意两所述条状电极1012之间的电场干扰。
在本实施例的薄膜晶体管阵列基板中，在所述像素分区内，所述连接电极1013的长度方向与所述条状电极1012的长度方向的夹角处于1度至89度的范围内。例如，所述夹角为1度、5度、9度、13度、17度、21度、25度、29度、33度、37度、41度、45度、49度、53度、57度、61度、65度、69度、73度、77度、81度、85度、89度。优选地，所述夹角为45度。
所述像素单元101的四所述像素分区中的所述连接电极1013的长度方向均相同。
在本实施例的薄膜晶体管阵列基板中，所述连接电极1013的长度方向与所述第二方向102平行。
在本实施例的薄膜晶体管阵列基板中，位于同一所述像素单元行中的任意两所述像素单元101的所述连接电极1013的长度方向相同，位于同一所述像素单元列中的任意两所述像素单元101的所述连接电极1013的长度方向相同。
或者，位于同一所述像素单元行中的任意两所述像素单元101的所述连接电极1013的长度方向相同，位于同一所述像素单元列中的相邻两所述像素单元101的所述连接电极1013的长度方向垂直。
或者，位于同一所述像素单元行中的相邻两所述像素单元101的所述连接电极1013的长度方向垂直，位于同一所述像素单元列中的相邻两所述像素单元101的所述连接电极1013的长度方向垂直。
图2为本发明的薄膜晶体管阵列基板中的像素单元101的第二实施例的示意图。本发明的显示面板的第二实施例与上述第一实施例相似，不同之处在于：
所述连接电极1013的长度方向与所述第一方向103平行。
参考图6，图6为在第一视角（Theta0°，Phi0°）下关于本发明的薄膜晶体管阵列基板的像素单元101的第一实施例、第二实施例与传统的像素单元的模拟效果及穿透率对比的示意图。其中，Theta0°是指所述第一视角所对应的视线与所述薄膜晶体管阵列基板的法线的夹角为0°，Phi0°是指所述第一视角所对应的视线与所述薄膜晶体管阵列基板的长边方向或短边方向的夹角为0°。
从图6可以看出，在所述第一视角下，本发明的第一实施例中的所述像素单元101的穿透率为0.2540，相对传统的像素单元的穿透率0.2485，提升比例为2.2%。同样在所述第一视角下，本发明的第二实施例中的所述像素单元101的穿透率为0.2540，相对传统的像素单元的穿透率0.2485，提升比例为2.2%。
参考图7，图7为在第一视角（Theta0°，Phi0°）下关于本发明的薄膜晶体管阵列基板的像素单元101的第一实施例、第二实施例与传统的像素单元的穿透率与电压关系的示意图。从图7可以看出，在所述第一视角下，并且在施加至所述像素电极的电压为5伏（V）至14伏的范围内的情况下，本发明的第一实施例中的所述像素单元101的穿透率702和本发明的第二实施例中的所述像素单元101的穿透率703均比传统的像素单元的穿透率701高。
参考图8，图8为在第二视角（Theta60°，Phi0°）下关于本发明的薄膜晶体管阵列基板的像素单元101的第一实施例、第二实施例与传统的像素单元的模拟效果及穿透率对比的示意图。其中，Theta60°是指所述第二视角所对应的视线与所述薄膜晶体管阵列基板的法线的夹角为60°，Phi0°是指所述第二视角所对应的视线与所述薄膜晶体管阵列基板的长边方向或短边方向的夹角为0°。
从图8可以看出，在所述第二视角下，本发明的第一实施例中的所述像素单元101的穿透率为0.1900，相对传统的像素单元的穿透率0.1856，提升比例为2.37%。同样在所述第二视角下，本发明的第二实施例中的所述像素单元101的穿透率为0.1972，相对传统的像素单元的穿透率0.1856，提升比例为6.25%。
参考图9，图9为在第二视角（Theta60°，Phi0°）下关于本发明的薄膜晶体管阵列基板的所述像素单元101的第一实施例、第二实施例与传统的像素单元的穿透率与电压关系的示意图。从图9可以看出，在所述第二视角下，并且在施加至所述像素电极的电压为5伏至14伏的范围内的情况下，本发明的第二实施例中的所述像素单元101的穿透率703比本发明的第一实施例中的所述像素单元101的穿透率702高，本发明的第一实施例中的所述像素单元101的穿透率702比传统的像素单元的穿透率701高。
参考图10，图10为在第三视角（Theta60°，Phi90°）下关于本发明的薄膜晶体管阵列基板的像素单元101的第一实施例、第二实施例与传统的像素单元的模拟效果及穿透率对比的示意图。其中，Theta60°是指所述第三视角所对应的视线与所述薄膜晶体管阵列基板的法线的夹角为60°，Phi90°是指所述第三视角所对应的视线与所述薄膜晶体管阵列基板的长边方向或短边方向的夹角为90°。
从图10可以看出，在所述第三视角下，本发明的第一实施例中的所述像素单元101的穿透率为0.1972，相对传统的像素单元的穿透率0.1856，提升比例为6.25%。同样在所述第三视角下，本发明的第二实施例中的所述像素单元101的穿透率为0.1900，相对传统的像素单元的穿透率0.1856，提升比例为2.37%。
参考图11，图11为在第三视角（Theta60°，Phi90°）下关于本发明的薄膜晶体管阵列基板的像素单元101的第一实施例、第二实施例与传统的像素单元的穿透率与电压关系的示意图。从图11可以看出，在所述第三视角下，并且在施加至所述像素电极的电压为5伏至14伏的范围内的情况下，本发明的第一实施例中的所述像素单元101的穿透率702比本发明的第二实施例中的所述像素单元101的穿透率703高，本发明的第二实施例中的像素单元101的穿透率703比传统的像素单元的穿透率701高。
本发明的显示面板的第三实施例与上述第一实施例或第二实施例相似，不同之处在于：
所述像素单元101中在所述第一方向103和所述第二方向102上相邻的两所述像素分区中的所述连接电极1013的长度方向垂直。
通过上述技术方案，由于连接电极1013增加了所述像素电极在所述像素单元101中所占据的总面积，因此可以增加所述像素电极施加给所述液晶层中的液晶分子的电场作用力，从而可以使得所述像素单元101的开口率不变的情况下，提高所述像素单元101的穿透率。此外，本发明还有利于改善所述显示面板在大视角下出现的色偏问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种薄膜晶体管阵列基板，其特征在于，所述薄膜晶体管阵列基板包括：
    至少两像素单元行，至少两所述像素单元行沿第一方向以阵列的形式排列，所述像素单元行包括至少两像素单元，所述像素单元行中的至少两所述像素单元沿第二方向以阵列的形式排列；
    至少两像素单元列，至少两所述像素单元列沿所述第二方向以阵列的形式排列，所述像素单元列包括至少两所述像素单元，所述像素单元列中的至少两所述像素单元沿所述第一方向以阵列的形式排列；
    其中，所述像素单元包括：
    一主干电极，所述主干电极将所述像素单元划分为至少四像素分区；
    至少四条状电极阵列，所述条状电极阵列设置在所述像素分区内，所述条状电极阵列包括至少两条状电极；
    至少四连接电极，所述连接电极设置在所述像素分区内，所述连接电极与位于所述像素分区内的至少两所述条状电极相连，所述连接电极用于提高所述像素单元的穿透率；
    至少两扫描线；
    至少两数据线；
    其中，所述扫描线和所述数据线均与所述像素单元连接，所述第一方向为与所述数据线平行的方向，所述第二方向为与所述扫描线平行的方向，在所述像素分区内，所述连接电极的长度方向与所述条状电极的长度方向的夹角处于1度至89度的范围内。
  2. 根据权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述连接电极的长度方向与所述第一方向平行。
  3. 根据权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述连接电极的长度方向与所述第二方向平行。
  4. 根据权利要求1至3中任意一项所述的薄膜晶体管阵列基板，其特征在于，位于同一所述像素单元行中的任意两所述像素单元的所述连接电极的长度方向相同，位于同一所述像素单元列中的任意两所述像素单元的所述连接电极的长度方向相同；或者
    位于同一所述像素单元行中的任意两所述像素单元的所述连接电极的长度方向相同，位于同一所述像素单元列中的相邻两所述像素单元的所述连接电极的长度方向垂直；或者
    位于同一所述像素单元行中的相邻两所述像素单元的所述连接电极的长度方向垂直，位于同一所述像素单元列中的相邻两所述像素单元的所述连接电极的长度方向垂直。
  5. 一种薄膜晶体管阵列基板，其特征在于，所述薄膜晶体管阵列基板包括：
    至少两像素单元行，至少两所述像素单元行沿第一方向以阵列的形式排列，所述像素单元行包括至少两像素单元，所述像素单元行中的至少两所述像素单元沿第二方向以阵列的形式排列；
    至少两像素单元列，至少两所述像素单元列沿所述第二方向以阵列的形式排列，所述像素单元列包括至少两所述像素单元，所述像素单元列中的至少两所述像素单元沿所述第一方向以阵列的形式排列；
    其中，所述像素单元包括：
    一主干电极，所述主干电极将所述像素单元划分为至少四像素分区；
    至少四条状电极阵列，所述条状电极阵列设置在所述像素分区内，所述条状电极阵列包括至少两条状电极；
    至少四连接电极，所述连接电极设置在所述像素分区内，所述连接电极与位于所述像素分区内的至少两所述条状电极相连，所述连接电极用于提高所述像素单元的穿透率。
  6. 根据权利要求5所述的薄膜晶体管阵列基板，其特征在于，在所述像素分区内，所述连接电极的长度方向与所述条状电极的长度方向的夹角处于1度至89度的范围内。
  7. 根据权利要求6所述的薄膜晶体管阵列基板，其特征在于，所述夹角为45度。
  8. 根据权利要求6所述的薄膜晶体管阵列基板，其特征在于，所述连接电极的长度方向与所述第一方向平行。
  9. 根据权利要求6所述的薄膜晶体管阵列基板，其特征在于，所述连接电极的长度方向与所述第二方向平行。
  10. 根据权利要求6至9中任意一项所述的薄膜晶体管阵列基板，其特征在于，位于同一所述像素单元行中的任意两所述像素单元的所述连接电极的长度方向相同，位于同一所述像素单元列中的任意两所述像素单元的所述连接电极的长度方向相同；或者
    位于同一所述像素单元行中的任意两所述像素单元的所述连接电极的长度方向相同，位于同一所述像素单元列中的相邻两所述像素单元的所述连接电极的长度方向垂直；或者
    位于同一所述像素单元行中的相邻两所述像素单元的所述连接电极的长度方向垂直，位于同一所述像素单元列中的相邻两所述像素单元的所述连接电极的长度方向垂直。
  11. 根据权利要求5所述的薄膜晶体管阵列基板，其特征在于，所述连接电极用于增加所述像素电极在所述像素单元中所占据的总面积，以增加所述像素电极施加给所述液晶层中的液晶分子的电场作用力。
  12. 根据权利要求11所述的薄膜晶体管阵列基板，其特征在于，所述连接电极还用于降低所述像素分区内任意两所述条状电极之间的电场干扰。
  13. 一种显示面板，其特征在于，所述显示面板包括：
    彩膜基板；
    液晶层；
    薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
    至少两像素单元行，至少两所述像素单元行沿第一方向以阵列的形式排列，所述像素单元行包括至少两像素单元，所述像素单元行中的至少两所述像素单元沿第二方向以阵列的形式排列；
    至少两像素单元列，至少两所述像素单元列沿所述第二方向以阵列的形式排列，所述像素单元列包括至少两所述像素单元，所述像素单元列中的至少两所述像素单元沿所述第一方向以阵列的形式排列；
    其中，所述像素单元包括：
    一主干电极，所述主干电极将所述像素单元划分为至少四像素分区；
    至少四条状电极阵列，所述条状电极阵列设置在所述像素分区内，所述条状电极阵列包括至少两条状电极；
    至少四连接电极，所述连接电极设置在所述像素分区内，所述连接电极与位于所述像素分区内的至少两所述条状电极相连，所述连接电极用于提高所述像素单元的穿透率。
  14. 根据权利要求13所述的显示面板，其特征在于，在所述像素分区内，所述连接电极的长度方向与所述条状电极的长度方向的夹角处于1度至89度的范围内。
  15. 根据权利要求14所述的显示面板，其特征在于，所述夹角为45度。
  16. 根据权利要求14所述的显示面板，其特征在于，所述连接电极的长度方向与所述第一方向平行。
  17. 根据权利要求14所述的显示面板，其特征在于，所述连接电极的长度方向与所述第二方向平行。
  18. 根据权利要求14至17中任意一项所述的显示面板，其特征在于，位于同一所述像素单元行中的任意两所述像素单元的所述连接电极的长度方向相同，位于同一所述像素单元列中的任意两所述像素单元的所述连接电极的长度方向相同；或者
    位于同一所述像素单元行中的任意两所述像素单元的所述连接电极的长度方向相同，位于同一所述像素单元列中的相邻两所述像素单元的所述连接电极的长度方向垂直；或者
    位于同一所述像素单元行中的相邻两所述像素单元的所述连接电极的长度方向垂直，位于同一所述像素单元列中的相邻两所述像素单元的所述连接电极的长度方向垂直。
  19. 根据权利要求13所述的显示面板，其特征在于，所述连接电极用于增加所述像素电极在所述像素单元中所占据的总面积，以增加所述像素电极施加给所述液晶层中的液晶分子的电场作用力。
  20. 根据权利要求19所述的显示面板，其特征在于，所述连接电极还用于降低所述像素分区内任意两所述条状电极之间的电场干扰。
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