WO2018120243A1 - 一种基于现场可编程门阵列的数字控制系统及其数据传输方法 - Google Patents

一种基于现场可编程门阵列的数字控制系统及其数据传输方法 Download PDF

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Publication number
WO2018120243A1
WO2018120243A1 PCT/CN2016/114019 CN2016114019W WO2018120243A1 WO 2018120243 A1 WO2018120243 A1 WO 2018120243A1 CN 2016114019 W CN2016114019 W CN 2016114019W WO 2018120243 A1 WO2018120243 A1 WO 2018120243A1
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Prior art keywords
processor
data
transmitted
gate array
programmable gate
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PCT/CN2016/114019
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English (en)
French (fr)
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郭睿
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深圳配天智能技术研究院有限公司
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Priority to PCT/CN2016/114019 priority Critical patent/WO2018120243A1/zh
Priority to CN201680086635.5A priority patent/CN109511275A/zh
Publication of WO2018120243A1 publication Critical patent/WO2018120243A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Definitions

  • Embodiments of the present invention relate to the field of digital control, and in particular, to a digital control system based on a field programmable gate array and a data transmission method thereof.
  • CNC system is the abbreviation of digital control system, the English name is (Numerical Control System) is a special computer system that performs some or all of the digital control functions according to the control program stored in the computer memory, and is equipped with an interface circuit and a servo drive device.
  • the operation control of one or more mechanical devices is realized mainly by using digital instructions composed of numbers, characters and symbols.
  • the variables controlled by it are usually mechanical quantities and switching quantities such as position, angle and speed.
  • Bus type CNC means that the communication between the control system and the driver and IO is realized by bus communication.
  • the bus type numerical control has the advantages of simple connection, convenient interface and high reliability.
  • the processor such as ARM or DSP
  • the general embedded single-processor solution is difficult to implement such complicated process scheduling, management, 3D display, interpolation calculation, Bus communication and error handling, so the system needs at least two processors to cooperate with each other to achieve all the functions of the bus type CNC.
  • the two must communicate in order to cooperate with each other.
  • the communication scheme between the processors in the numerical control system mostly uses the master-slave serial communication mode, resulting in the resource consumption of the processor. More, data transmission speed is slow.
  • Embodiments of the present invention provide a digital control system based on a field programmable gate array and a data transmission method thereof, so that high-speed parallel communication between two processors becomes possible.
  • a technical solution adopted by the embodiment of the present invention is to provide a digital control system based on a field programmable gate array, including a first processor, a second processor, and a first processor and a A field programmable gate array between two processors, wherein a buffer unit is disposed inside the field programmable gate array, and the first processor and the second processor respectively use themselves as master devices and field programmable gate arrays as slave devices And respectively performing a read operation and a write operation on the buffer unit, thereby transmitting data to be transmitted between the first processor and the second processor.
  • the buffer unit includes a first in first out memory, wherein one of the first processor and the second processor writes data to be transferred into the FIFO memory, and the other of the first processor and the second processor are advanced The memory reads the data to be transmitted.
  • one of the first processor and the second processor first reads the state interrupt of the FIFO memory before writing the data to be transferred to the FIFO memory, and determines whether the FIFO memory is in a full state, if When the FIFO memory is not full, the data to be transmitted is written to the FIFO memory.
  • the first processor and the second processor start a timer after writing the data to be transmitted to the FIFO memory, and further determine whether a timer timeout interrupt or a field programmable gate array feedback is received. Receive completion interrupt or abnormal interrupt; if receiving the reception completion interrupt, close the timer and check whether the written data to be transmitted is correct. If the data to be transmitted is correct, the correct identifier is generated. If the transmission data is incorrect, the error number is accumulated, and it is determined whether the number of errors reaches the error threshold. If the error threshold is reached, an error flag is generated.
  • the error threshold is not reached, the data to be transmitted is rewritten; if an abnormality is received; If the interrupt is interrupted, the timer is turned off, the number of errors is accumulated, and it is determined whether the number of errors reaches the error threshold. If the error threshold is reached, an error flag is generated. If the error threshold is not reached, the data to be transmitted is rewritten; if received When the timer expires, the timeout is accumulated and it is determined whether the timeout has arrived. When the threshold number, if the number reaches the timeout threshold value, the identification error is generated, if not the number reaches the timeout threshold value, the transmission data to be rewritten.
  • the other of the first processor and the second processor receives a read interrupt of the field programmable gate array and reads the data to be transmitted from the first in first out memory in response to the read interrupt.
  • the other one of the first processor and the second processor further verifies whether the read data to be transmitted is correct. If the data to be transmitted is correct, the correct identifier is returned, and if the read data to be transmitted is incorrect. Then, the error number is accumulated, and the number of errors is determined to reach the error threshold. If the error threshold is reached, an error flag is generated. If the error threshold is not reached, the data to be transmitted is re-read.
  • the buffer unit includes a first FIFO memory and a second FIFO memory, wherein the first FIFO memory allows the first processor to perform a write operation and allows the second processor to perform a read operation, the second FIFO The memory allows the second processor to perform a write operation and allows the first processor to perform a read operation.
  • the data to be transmitted is aperiodic data.
  • the buffer unit includes a register, and the first processor and the second processor periodically perform a write operation and a read operation on the register.
  • the buffer unit comprises a first register and a second register, wherein the first register allows the first processor to perform a write operation and allows the second processor to perform a read operation, the second register allows the second processor to perform a write operation, and allows The first processor performs a read operation.
  • the buffer unit further includes a third register, and the third register allows both the first processor and the second processor to perform a write operation and/or a read operation.
  • the data to be transmitted is periodic data.
  • a technical solution adopted by the embodiment of the present invention is to provide a data transmission method based on a field programmable gate array digital control system, where the digital control system includes a first processor, a second processor, and Connected to a field programmable gate array between the first processor and the second processor, wherein the field programmable gate array is internally provided with a buffer unit, the method comprising: using the first processor as the master device, and The field programmable gate array acts as a slave device to write data to be transmitted to the buffer unit; the second processor treats itself as a master device, and the field programmable gate array acts as a slave device, and the data to be transmitted is read from the buffer unit.
  • the buffer unit comprises a FIFO memory
  • the step of the first processor as the master device and the field programmable gate array as the slave device, the data to be transmitted to the buffer unit comprises: reading the FIFO memory The state is interrupted, and it is judged whether the FIFO memory is in the full state. If the FIFO memory is not in the full state, the data to be transmitted is written to the FIFO memory.
  • the step of writing the data to be transmitted to the buffer unit by the first processor as the master device and the field programmable gate array as the slave device further includes: after writing the data to be transmitted to the first in first out memory, Start the timer; determine whether the timeout interrupt of the timer is received or the reception completion interrupt or abnormal interrupt of the field programmable gate array feedback; if the reception completion interrupt is received, the timer is turned off, and the written data to be transmitted is checked. Correctly, if the data to be transmitted is correct, a correct identifier is generated. If the data to be transmitted is incorrect, the number of errors is accumulated, and it is determined whether the number of errors reaches the threshold of the number of errors. If the threshold of the number of errors is reached, an error is generated.
  • the error threshold is not reached, the data to be transmitted is rewritten; if an abnormal interrupt is received, the timer is turned off, the number of errors is accumulated, and the number of errors is determined to reach the error threshold. If the error threshold is reached, the identifier is generated. The error identifier, if the error threshold is not reached, the data to be transmitted is rewritten; Receiving the timeout of the timer interrupt, the cumulative number of timeouts, and determines a timeout frequency reaches the timeout threshold number, if reaches the timeout threshold number of times, generating an error identification, not reached the timeout threshold number of times, the rewrite data transmission to be.
  • the step of reading the data to be transmitted from the buffer unit by the second processor as the master device and using the field programmable gate array as the slave device includes: receiving the read interrupt of the field programmable gate array; The interrupt reads the data to be transmitted from the FIFO memory.
  • the step of reading the data to be transmitted from the buffer unit by the second processor as the master device and using the field programmable gate array as the slave device includes: verifying whether the read data to be transmitted is correct, if the data is read. If the data to be transmitted is correct, the correct identifier is returned. If the data to be transmitted is incorrect, the number of errors is accumulated, and the number of errors reaches the threshold of the number of errors. If the threshold of the error is reached, an error flag is generated. If the error is not reached. The number of times threshold, then re-read the data to be transmitted.
  • the data to be transmitted is aperiodic data.
  • the buffer unit includes a register; the first processor uses itself as a master device, and the field programmable gate array acts as a slave device, and the step of writing data to be transmitted to the buffer unit includes: periodically writing to the buffer unit to be transmitted Data; the second processor uses itself as the master device, and the field programmable gate array as the slave device, the step of reading the data to be transmitted from the buffer unit includes periodically reading the data to be transmitted from the buffer unit.
  • the data to be transmitted is periodic data.
  • a technical solution adopted by the embodiment of the present invention is: a numerical control machine tool including a machine tool body and a numerical control system mounted on the machine tool body, wherein the numerical control system is the above technical solution
  • a digital control system based on a field programmable gate array is described.
  • the beneficial effects of the embodiments of the present invention are: in the field control gate array-based digital control system and the data transmission method thereof provided by the embodiments of the present invention, the field programmable gate array is used as the slave device and serves as two processors.
  • the bridge between communications enables both processors to act as masters in communications, enabling high-speed parallel communication between the two processors.
  • FIG. 1 is a schematic block diagram of a digital control system in accordance with a first embodiment of the present invention
  • FIG. 2 is a flow chart showing a write operation of a FIFO memory according to a second embodiment of the present invention
  • FIG. 3 is a flow chart showing a read operation of a FIFO memory according to a third embodiment of the present invention.
  • FIG. 4 is a flow chart showing a data transmission method of a digital control system according to a fourth embodiment of the present invention.
  • FIG. 1 is a schematic block diagram of a digital control system in accordance with a first embodiment of the present invention.
  • the digital control system of this embodiment includes a first processor 11, a second processor 13, and a field programmable gate array (Field) connected between the first processor 11 and the second processor 13.
  • Programmable Gate Array, FPGA) 12 wherein the field programmable gate array 12 is internally provided with a buffer unit 120, and the first processor 11 and the second processor 13 respectively regard themselves as a master device and the field programmable gate array 12 as a slave device.
  • the buffer unit 120 is separately read and written, and the data to be transmitted is transmitted between the first processor 11 and the second processor 13.
  • the first processor 11 and the second processor 13 are two embedded processors, and in a specific example, the first processor 11 uses a DSP+ARM dual-core processor (for example, the model number is DM8148), the second processor 13 uses an ARM processor (for example, model AM3354), and the FPGA can use Xilinx's Spartan-6 series.
  • the first processor 11 and the second processor 13 preferably pass through a built-in universal storage controller (General Purpose Memmory The Controller, GPMC) interface is coupled to the field programmable gate array 12.
  • GPMC General Purpose Memmory The Controller
  • the GPMC interface is a high-speed parallel interface that supports 8/16-bit multiplexed data/address bus, supports up to 512MB of address space, supports up to 8 chip selects, and supports non-multiplexed data/address modes.
  • the stable communication speed can reach several tens of megabytes. Therefore, high speed data transmission between the first processor 11 and the second processor 13 can be achieved.
  • the first processor 11 is mainly used as a main controller of the system, wherein the ARM core mainly implements functions of control, display, error processing, etc. of the peripheral module, and the DSP core is used to implement a large number and complex Algorithm.
  • the second processor 13 implements bus master communication, PLC control, and communication with the main keypad and external input and output.
  • the field programmable gate array 12 is used as a coprocessor of the control system to realize high-speed data transmission between the first processor 11 and the second processor 13, as well as pulse and feedback control of the spindle and key scan of the external keyboard. .
  • the field programmable gate array 13 is used as a slave device and serves as a bridge between the first processor 11 and the second memory 13, so that both the first processor 11 and the second memory 13 can serve as the main communication.
  • the device enables high-speed parallel communication between the first processor 11 and the second memory 13.
  • the data to be transmitted by the first processor 11 and the second processor 13 are classified into the following two categories:
  • Such data is aperiodic bidirectional, and may be sent by the first processor 11 to the second processor 13, or may be sent by the second processor 13 to the first processor 11.
  • the real-time requirement of such data is high. For example, when the system is in an abnormal state, the first processor 11 immediately sends a disconnect servo command to the second processor 13, and the second processor 13 sends the real actuator to the real actuator through the field bus. . If such a command data transmission speed is slow or the second processor 13 responds slowly, an unpredictable error may occur. Therefore, such aperiodic data requirements can guarantee real-time performance, and transmission errors or loss cannot occur.
  • Periodic data for example, interpolation data or position feedback data
  • Such data is periodic, wherein the interpolation data is sent to the second processor 13 after the DSP core of the first processor 11 is calculated, and then the second processor 13 sends the data to the real execution through the field bus. mechanism.
  • the position feedback data is feedback data acquired by the second processor 13 from the actuator, and the second processor 13 transmits the data to the first processor 11.
  • a feature of this type of data is that the refresh period is fixed, so that the first processor 11 and the second processor 13 can be transmitted or received on time.
  • the buffer unit 120 further includes a first FIFO (First In First) Out, FIFO) memory 121 and second FIFO memory 122, wherein the first FIFO memory 121 allows the first processor 11 to perform a write operation and allows the second processor 13 to perform a read operation, ie, a first FIFO
  • the data flow defined by the memory 121 is from the first processor 11 to the second processor 13.
  • the second FIFO memory 122 allows the second processor 13 to perform a write operation and allows the first processor 11 to perform a read operation, that is, the data flow defined by the second FIFO memory 122 is from the second processor 13 to the first A processor 11.
  • the number of the first FIFO memory 121 and the second FIFO memory 122 can be arbitrarily set according to actual conditions, and only the first processor 11 and the second processor 13 are required to be guaranteed.
  • One of the first to read data is written to the FIFO memory, and the other of the first processor 11 and the second processor 13 reads the data to be transmitted from the first in first out memory, for example, when the data transmission is one-way, Only one FIFO memory can be set.
  • the data transfer from the first processor 11 to the second processor 13 will be exemplified below, and the write operation and the read operation of the first processor 11 and the second processor 13 will be described in detail with reference to FIGS. 2 and 3.
  • the data transmission of the second processor 13 to the first processor 11 is substantially similar to the following, and details are not described herein again.
  • FIG. 2 is a schematic flowchart of a write operation of a FIFO memory according to a second embodiment of the present invention, which specifically includes the following steps:
  • Step 201 reading a state interrupt of the first FIFO memory 121
  • the first processor 11 when the first processor 11 obtains the data to be transmitted by calculation or other means, and needs to transmit to the second processor 13, the first processor 11 sends a write request interrupt to the field programmable gate array 12, and the field can be
  • the programming gate array 12 is interrupted according to the state of the first FIFO memory 121, which is used to indicate whether the first FIFO memory 121 is in a full state.
  • Step 202 Determine whether the first FIFO memory 121 is in a full state according to the state interrupt. If it is determined that the first FIFO memory 121 is in a full state, return to step 201, and if it is determined that the first FIFO memory 121 is not in a full state. , step 203 is performed;
  • Step 203 the data to be transmitted is written into the first FIFO memory 121;
  • the first processor 11 continuously writes the number of bytes of the packet length to the predetermined address.
  • Step 204 After writing data to be transmitted to the first FIFO memory 121, start a timer;
  • the first processor 11 starts a hardware or software timer, and the timer sets a feedback time limit. If the timer time exceeds the feedback time limit, the feedback timeout interrupt occurs.
  • Step 205 Determine whether a timer timeout interrupt or a reception completion interrupt or abnormal interrupt fed back by the field programmable gate array 12 is received;
  • step 206 if a reception completion interrupt is received, step 206 is performed. If an abnormal interrupt is received, step 212 is performed. If a timeout interrupt is received, step 213 is performed.
  • Step 206 If receiving a reception completion interrupt, turning off the timer to stop the timer timing and resetting;
  • Step 207 it is verified whether the data to be transmitted is correct, if the data to be transmitted is correct, step 208 is performed, if the data to be transmitted is incorrect, step 209 is performed;
  • Cyclic Redundancy can be passed. Check, CRC) to verify the written data to be transmitted.
  • CRC CRC
  • the first processor 11 compares the CRC value received from the field programmable gate array 12 with the locally calculated CRC value, and determines whether the written data to be transmitted is correct based on the comparison result.
  • the above verification action can also be completed by the field programmable gate array 12 and fed back to the first processor 11 in the form of an interrupt.
  • Step 208 generating a correct identifier and completing a write operation
  • the correct identification is used to notify the corresponding component to perform other actions, such as the field programmable gate array 12 notifying the second processor 13 to perform a read operation of the corresponding data.
  • Step 209 accumulating the number of errors
  • Step 210 Determine whether the number of errors reaches the error threshold. If the error threshold is reached, go to step 211. If the error threshold is not reached, return to step 203 to rewrite the data to be transmitted.
  • Step 211 generating an error identifier
  • the error flag can be fed back to any component to inform the component to perform other actions, such as being controlled by the first processor 11 to display an error.
  • Step 212 If an abnormal interrupt is received, the timer is turned off, and step 209 and subsequent steps are further directly performed;
  • Step 213 If a timeout interrupt of the timer is received, the timer is turned off.
  • Step 214 accumulating the number of timeouts
  • step 215 it is determined whether the timeout number reaches the timeout threshold. If the timeout threshold is reached, step 211 is executed to generate an error identifier. If the timeout threshold is not reached, the process returns to step 203 to rewrite the data to be transmitted.
  • FIG. 3 is a schematic flowchart of a read operation of a FIFO memory according to a third embodiment of the present invention, which specifically includes the following steps:
  • Step 301 receiving a read interrupt of the field programmable gate array 12;
  • the read interrupt is sent to the second processor 13 to notify the second processor 13 to perform the read operation. Since the interrupt communication mode is adopted, only one clock period of the field programmable gate array 12 is required between the completion of the write operation by the first process 11 and the reception of the read interrupt by the second processor 13, so that the mode is more obvious than the polling mode. Improve the communication efficiency of the system.
  • Step 302 Read data to be transmitted from the first FIFO memory 121 in response to the read interrupt.
  • Step 303 it is verified whether the data to be transmitted is correct, if the data to be transmitted is correct, step 304 is performed, if the data to be transmitted is incorrect, step 305 is performed;
  • the specific verification process may adopt a CRC check mode similar to the above, and details are not described herein again.
  • Step 304 generating a correct identifier
  • the correct identification is used to notify the corresponding component to perform other actions, for example, the second processor 13 sends the relevant destined to the real actuator according to the correct identification to perform the corresponding action.
  • Step 305 accumulating the number of errors
  • step 306 it is determined that the number of errors reaches the error threshold. If the error threshold is reached, step 307 is executed to generate an error identifier. If the error threshold is not reached, the process returns to step 302 to re-read the data to be transmitted.
  • step 307 an error identifier is generated.
  • the first-in first-out memory is used to cache consecutive commands to ensure that data is not lost, thereby ensuring the reliability of the system, and further informing the corresponding processor to perform corresponding actions in an interrupted manner to ensure response to the data. Real time. Further, the processor does not need to perform serial-to-parallel conversion, which reduces the burden on the processor.
  • the field programmable gate array 13 can be used as a dual port RAM, and the data to be transmitted is buffered in the internal register of the field programmable gate array 13 and is used by the first processor 11. And the second processor 13 performs periodic write operations and read operations.
  • the buffer unit 120 further sets a first register 123, a second register 124, and a third register 125, wherein the first register 123 allows the first processor 11 to perform a write operation and allows the second processor 13 to perform a read operation. Operation, the second register 124 allows the second processor 13 to perform a write operation and allows the first processor 11 to perform a read operation, and the third register 125 allows both the first processor and the second processor to perform a write operation and / or read operations.
  • the first register 123 is for storing data transmitted from the first processor 11 to the second processor 13, and the second register 124 is for storing data transmitted from the second processor 13 to the first processor 11, and the third The register 125 is used to store the field programmable gate array 13, and both the first processor 11 and the second processor 13 can be written and/or read to determine or set the state of the FPGA related task.
  • the number of the first register 123, the second register 124, and the third register 125 can be arbitrarily set according to actual conditions.
  • the first processor 11 and the second processor 13 need only perform write operations and/or read operations in accordance with the periodic timers, respectively, due to the periodic read and write operations.
  • the first processor 11 and the second processor 13 can be completed by only one instruction when reading and writing, and the first processor 11 and the second processor 13 do not need to store such data, and the first processor 11 and The second processor 13 hardly adds any communication burden.
  • FIG. 4 is a schematic flow chart of a data transmission method of a digital control system according to a fourth embodiment of the present invention.
  • a data transmission method is provided for the digital control system shown in FIG. 1, which specifically includes the following steps:
  • Step 401 The first processor 11 uses itself as a master device, and writes the field programmable gate array 12 as a slave device to the buffer unit 120 of the field programmable gate array 12 to write data to be transmitted;
  • Step 402 The second processor 13 uses itself as the master device, and the field programmable gate array 12 functions as a slave device, and the data to be transmitted is read from the buffer unit 120 of the field programmable gate array 12.
  • step 401 and step 402 The specific implementation process of step 401 and step 402 and the specific architecture of the buffer unit 120 have been described in detail above, and are not described herein again.
  • the embodiment of the invention further provides a numerical control machine tool, which comprises a machine tool body and a numerical control system mounted on the machine tool body, and the numerical control system is a field programmable gate array based on the above technical solution. Digital control system.
  • the field programmable gate array is used as the slave device and serves as two
  • the bridge between the processors enables both processors to act as masters in communication, enabling high-speed parallel communication between the two processors.
  • the embodiment of the present invention optimizes the transmission process of the periodic data and the aperiodic data for different types of data to be transmitted.

Abstract

一种基于现场可编程门阵列的数字控制系统及其数据传输方法，该数字控制系统包括第一处理器（11）、第二处理器（13）以及连接于第一处理器（11）和第二处理器（13）之间的现场可编程门阵列（12），其中现场可编程门阵列（12）的内部设置有缓冲单元（120），第一处理器（11）和第二处理器（13）分别将自身作为主设备，将现场可编程门阵列（12）作为从设备，并分别对缓冲单元（120）进行读操作和写操作，进而在第一处理器（11）与第二处理器（13）之间传输待传输数据。通过上述方式，利用现场可编程门阵列作为从设备并作为两个处理器之间通讯的桥梁，使得两个处理器都可以作为通讯中的主设备，使得两个处理器之间的高速并行通讯成为可能。

Description

一种基于现场可编程门阵列的数字控制系统及其数据传输方法
【技术领域】
本发明实施例涉及数字控制领域，特别是涉及一种基于现场可编程门阵列的数字控制系统及其数据传输方法。
【背景技术】
数控系统是数字控制系统的简称，英文名称为（Numerical Control System），是一种根据计算机存储器中存储的控制程序，执行部分或全部数字控制功能，并配有接口电路和伺服驱动装置的专用计算机系统。主要通过利用数字、文字和符号组成的数字指令来实现一台或多台机械设备动作控制，它所控制的变量通常是位置、角度、速度等机械量和开关量。总线型数控是指控制系统与驱动器以及IO的通讯是通过总线通讯来实现的。总线型数控具有连线简单，接口方便，可靠性高等优势。由于总线型数控系统中处理器（例如，ARM或DSP）负担较大，实时性要求又高，一般的嵌入式单处理器方案难以实现如此复杂的进程调度、管理、3D显示、插补计算、总线通信以及错误处理等功能，因此系统中需要至少两个处理器来相互配合，共同实现总线型数控的全部功能。
若系统中存在两个处理器，二者为了能够默契配合就必须要通讯，而目前数控系统中的处理器之间的通讯方案大都使用主从串行的通讯方式，导致处理器的资源占用较多、数据传输速度慢。
【发明内容】
本发明实施例提供一种基于现场可编程门阵列的数字控制系统及其数据传输方法，以使得两个处理器之间的高速并行通讯成为可能。
为解决上述技术问题，本发明实施例采用的一个技术方案是：提供一种基于现场可编程门阵列的数字控制系统，包括第一处理器、第二处理器以及连接于第一处理器和第二处理器之间的现场可编程门阵列，其中现场可编程门阵列的内部设置有缓冲单元，第一处理器和第二处理器分别将自身作为主设备，将现场可编程门阵列作为从设备，并分别对缓冲单元进行读操作和写操作，进而在第一处理器与第二处理器之间传输待传输数据。
其中，缓冲单元包括先进先出存储器，其中第一处理器和第二处理器中的一个将待传输数据写入先进先出存储器，第一处理器和第二处理器中的另一个从先进先出存储器读取待传输数据。
其中，第一处理器和第二处理器中的一个在向先进先出存储器写入待传输数据前，首先读取先进先出存储器的状态中断，并判断先进先出存储器是否处于满状态，若先进先出存储器未处于满状态，则向先进先出存储器写入待传输数据。
其中，第一处理器和第二处理器中的一个在向先进先出存储器写入待传输数据后，启动定时器，并进一步判断是否接收到定时器的超时中断或者现场可编程门阵列反馈的接收完成中断或异常中断；若接收到接收完成中断，则关闭定时器，并校验写入的待传输数据是否正确，若写入的待传输数据正确，则生成正确标识，若写入的待传输数据不正确，则累加错误次数，并判断错误次数是否达到错误次数阈值，若达到错误次数阈值，则生成错误标识，若未达到错误次数阈值，则重新写入待传输数据；若接收到异常中断，则关闭定时器，累加错误次数，并判断错误次数是否达到错误次数阈值，若达到错误次数阈值，则生成错误标识，若未达到错误次数阈值，则重新写入待传输数据；若接收到定时器的超时中断，则累加超时次数，并判断定超时次数是否到达超时次数阈值，若达到超时次数阈值，则生成错误标识，若未达到超时次数阈值，则重新写入待传输数据。
其中，第一处理器和第二处理器中的另一个接收现场可编程门阵列的读取中断，并响应读取中断从先进先出存储器读取待传输数据。
其中，第一处理器和第二处理器中的另一个进一步校验读取的待传输数据是否正确，若读取的待传输数据正确，则返回正确标识，若读取的待传输数据不正确，则累加错误次数，并判断错误次数达到错误次数阈值，若达到错误次数阈值，则生成错误标识，若未达到错误次数阈值，则重新读取待传输数据。
其中，缓冲单元包括第一先进先出存储器和第二先进先出存储器，其中第一先进先出存储器允许第一处理器进行写操作，并允许第二处理器进行读操作，第二先进先出存储器允许第二处理器进行写操作，并允许第一处理器进行读操作。
其中，待传输数据为非周期性数据。
其中，缓冲单元包括寄存器，第一处理器和第二处理器周期性对寄存器进行写操作和读操作。
其中，缓冲单元包括第一寄存器和第二寄存器，其中第一寄存器允许第一处理器进行写操作，并允许第二处理器进行读操作，第二寄存器允许第二处理器进行写操作，并允许第一处理器进行读操作。
其中，缓冲单元进一步包括第三寄存器，第三寄存器允许第一处理器和第二处理器均进行写操作和/或读操作。
其中，待传输数据为周期性数据。
为解决上述技术问题，本发明实施例采用的一个技术方案是：提供一种基于现场可编程门阵列的数字控制系统的数据传输方法，该数字控制系统包括第一处理器、第二处理器以及连接于第一处理器和第二处理器之间的现场可编程门阵列，其中现场可编程门阵列的内部设置有缓冲单元，该方法包括：由第一处理器将自身作为主设备，并将现场可编程门阵列作为从设备，向缓冲单元写入待传输数据；由第二处理器将自身作为主设备，并将现场可编程门阵列作为从设备，从缓冲单元读取待传输数据。
其中，缓冲单元包括先进先出存储器；由第一处理器将自身作为主设备，并将现场可编程门阵列作为从设备，向缓冲单元写入待传输数据的步骤包括：读取先进先出存储器的状态中断，并判断先进先出存储器是否处于满状态，若先进先出存储器未处于满状态，则向先进先出存储器写入待传输数据。
其中，由第一处理器将自身作为主设备，并将现场可编程门阵列作为从设备，向缓冲单元写入待传输数据的步骤进一步包括：在向先进先出存储器写入待传输数据后，启动定时器；判断是否接收到定时器的超时中断或者现场可编程门阵列反馈的接收完成中断或异常中断；若接收到接收完成中断，则关闭定时器，并校验写入的待传输数据是否正确，若写入的待传输数据正确，则生成正确标识，若写入的待传输数据不正确，则累加错误次数，并判断错误次数是否达到错误次数阈值，若达到错误次数阈值，则生成错误标识，若未达到错误次数阈值，则重新写入待传输数据；若接收到异常中断，则关闭定时器，累加错误次数，并判断错误次数是否达到错误次数阈值，若达到错误次数阈值，则生成错误标识，若未达到错误次数阈值，则重新写入待传输数据；若接收到定时器的超时中断，则累加超时次数，并判断定超时次数是否到达超时次数阈值，若达到超时次数阈值，则生成错误标识，若未达到超时次数阈值，则重新写入待传输数据。
其中，由第二处理器将自身作为主设备，并将现场可编程门阵列作为从设备，从缓冲单元读取待传输数据的步骤包括：接收现场可编程门阵列的读取中断；响应读取中断从先进先出存储器读取待传输数据。
其中，由第二处理器将自身作为主设备，并将现场可编程门阵列作为从设备，从缓冲单元读取待传输数据的步骤包括：校验读取的待传输数据是否正确，若读取的待传输数据正确，则返回正确标识，若读取的待传输数据不正确，则累加错误次数，并判断错误次数达到错误次数阈值，若达到错误次数阈值，则生成错误标识，若未达到错误次数阈值，则重新读取待传输数据。
其中，待传输数据为非周期性数据。
其中，缓冲单元包括寄存器；由第一处理器将自身作为主设备，并将现场可编程门阵列作为从设备，向缓冲单元写入待传输数据的步骤包括：向缓冲单元周期性写入待传输数据；由第二处理器将自身作为主设备，并将现场可编程门阵列作为从设备，从缓冲单元读取待传输数据的步骤包括：从缓冲单元周期性读取待传输数据。
其中，待传输数据为周期性数据。
为解决上述技术问题，本发明实施例采用的一个技术方案是：一种数控机床，所述数控机床包括机床本体以及安装在所述机床本体上的数控系统，所述数控系统为上述技术方案所描述的一种基于现场可编程门阵列的数字控制系统。
本发明实施例的有益效果是：在本发明实施例所提供的基于现场可编程门阵列的数字控制系统及其数据传输方法中，利用现场可编程门阵列作为从设备并作为两个处理器之间通讯的桥梁，使得两个处理器都可以作为通讯中的主设备，使得两个处理器之间的高速并行通讯成为可能。
【附图说明】
图1是根据本发明第一实施例的数字控制系统的示意框图；
图2是根据本发明第二实施例的对先进先出存储器进行写操作的流程示意图；
图3是根据本发明第三实施例的对先进先出存储器进行读操作的流程示意图；
图4是根据本发明第四实施例的数字控制系统的数据传输方法的流程示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图1所示，图1是根据本发明第一实施例的数字控制系统的示意框图。本实施例的数字控制系统包括第一处理器11、第二处理器13以及连接于第一处理器11和第二处理器13之间的现场可编程门阵列（Field Programmable Gate Array，FPGA）12，其中现场可编程门阵列12的内部设置有缓冲单元120，第一处理器11和第二处理器13分别将自身作为主设备，将现场可编程门阵列12作为从设备，并分别对缓冲单元120进行读操作和写操作，进而在第一处理器11与第二处理器13之间传输待传输数据。
在本实施例中，第一处理器11和第二处理器13为两个嵌入式处理器，且在一具体实例中，第一处理器11采用DSP+ARM的双核处理器（例如，型号为DM8148），第二处理器13采用ARM处理器（例如，型号为AM3354），FPGA可选用Xilinx的Spartan-6系列。第一处理器11和第二处理器13优选通过自带的通用存储控制器（General Purpose Memmory Controller，GPMC）接口与现场可编程门阵列12连接。GPMC接口为一种高速并行接口，可支持8/16位复用的数据/地址总线，最大支持512MB的地址空间，最多支持8个片选，同时也支持非复用的数据/地址模式，其稳定的通讯速度可达到几十兆。因此，可以实现第一处理器11和第二处理器13之间的高速数据传输。
在本实施例的数字控制系统中，第一处理器11主要作为系统的主控制器，其中的ARM内核主要实现外设模块的控制、显示、错误处理等功能，DSP内核用来实现大量并且复杂的算法。第二处理器13来实现总线主站通讯、PLC的控制以及与主按键板和外部输入输出的通讯。现场可编程门阵列12用来作为控制系统的协处理器，实现第一处理器11与第二处理器13之间的高速数据传输，以及主轴的脉冲和反馈控制以及外部键盘的按键扫描等功能。
通过上述方式，利用现场可编程门阵列13作为从设备并作为第一处理器11与第二存储器13之间通讯的桥梁，使得第一处理器11和第二存储器13都可以作为通讯中的主设备，使得第一处理器11和第二存储器13之间的高速并行通讯成为可能。
根据数字控制系统要实现的功能，第一处理器11和第二处理器13要传输的数据分为下面两类：
1、非周期性数据（例如，命令数据）
这类数据是非周期性双向的，可以是第一处理器11发送给第二处理器13，也可以是第二处理器13发送给第一处理器11。这类数据的实时性要求较高，比如系统在出现异常状态时，第一处理器11会立刻发送断伺服命令给第二处理器13，第二处理器13通过现场总线发送给真正的执行机构。若这样的命令数据传输速度慢或者第二处理器13响应慢都会导致不可预料的错误出现。因此，对这类非周期性数据要求能够保证实时性，并且不能出现传输错误或丢失的情况。
2、周期性数据（例如，插补数据或位置反馈数据）
这类数据是周期性的，其中插补数据是第一处理器11的DSP内核算好后发送给第二处理器13，再由第二处理器13通过现场总线将该数据发送给真正的执行机构。位置反馈数据是第二处理器13从执行机构获取的反馈数据，第二处理器13将该数据发送给第一处理器11。这类数据的特点是刷新周期是固定的，因此第一处理器11和第二处理器13只要按时发送或接收即可。
因此，针对上述两类数据的特点，设计出不同的缓冲机制，当然本领域技术人员可以根据实际情况对上述两类数据的缓冲机制进行混用。
在本实施例中，针对非周期性数据，缓冲单元120进一步包括第一先进先出（First In First Out，FIFO）存储器121和第二先进先出存储器122，其中第一先进先出存储器121允许第一处理器11进行写操作，并允许第二处理器13进行读操作，即第一先进先出存储器121所限定的数据流向是从第一处理器11到第二处理器13。第二先进先出存储器122允许第二处理器13进行写操作，并允许第一处理器11进行读操作，即第二先进先出存储器122所限定的数据流向是从第二处理器13到第一处理器11。当然如本领域技术人员所理解的，可根据实际情况对第一先进先出存储器121和第二先进先出存储器122的数量进行任意设置，只需保证第一处理器11和第二处理器13中的一个将待传输数据写入先进先出存储器，第一处理器11和第二处理器13中的另一个从先进先出存储器读取待传输数据，例如在数据传输为单向时，也可以仅设置一个先进先出存储器。
下面将以从第一处理器11向第二处理器13进行数据传输为例，并进一步结合图2和图3对第一处理器11和第二处理器13的写操作和读操作进行详细描述，第二处理器13向第一处理器11的数据传输与下述情况基本类似，在此不再赘述。
如图2所示，图2是根据本发明第二实施例的对先进先出存储器进行写操作的流程示意图，具体包括以下步骤：
步骤201，读取第一先进先出存储器121的状态中断；
在本步骤，在第一处理器11通过计算或其他方式获得待传输数据，并需要传送到第二处理器13时，第一处理器11向现场可编程门阵列12发送写请求中断，现场可编程门阵列12根据第一先进先出存储器121的状态反馈状态中断，该状态中断用于表示第一先进先出存储器121是否处于满状态。
步骤202，根据状态中断判断第一先进先出存储器121是否处于满状态，若判断第一先进先出存储器121处于满状态，则返回步骤201，若判断第一先进先出存储器121未处于满状态，则执行步骤203；
步骤203，将待传输数据写入第一先进先出存储器121；
在本步骤中，第一处理器11连续向预定地址写入数据包长度的字节个数。
步骤204，在向第一先进先出存储器121写入待传输数据后，启动定时器；
在本步骤中，第一处理器11在完成写入动作后，启动硬件或软件定时器，定时器设定一个反馈时限，若定时器的计时时间超过该反馈时限，则反馈超时中断。
步骤205，判断是否接收到定时器的超时中断或者现场可编程门阵列12反馈的接收完成中断或异常中断；
在本步骤中，若接收到接收完成中断，则执行步骤206，若接收到异常中断，则执行步骤212，若接收到超时中断，则执行步骤213。
步骤206，若接收到接收完成中断，关闭定时器，以停止定时器的计时，并进行复位；
步骤207，校验写入的待传输数据是否正确，若写入的待传输数据正确，则执行步骤208，若写入的待传输数据不正确，则执行步骤209；
在本步骤中，可通过循环冗余校验(Cyclic Redundancy Check，CRC)来对写入的待传输数据进行校验。例如，由第一处理器11将从现场可编程门阵列12接收的CRC值与本地计算的CRC值进行比较，并根据比较结果来进行判断写入的待传输数据是否正确。当然，上述校验动作也可以由现场可编程门阵列12完成，并以中断形式反馈给第一处理器11。
步骤208，生成正确标识，并完成写操作；
在本步骤中，正确标识用于通知相应元件执行其他动作，例如由现场可编程门阵列12通知第二处理器13进行相应数据的读操作。
步骤209，累加错误次数；
步骤210，判断错误次数是否达到错误次数阈值，若达到错误次数阈值，则执行步骤211，若未达到错误次数阈值，则返回步骤203，重新写入待传输数据；
步骤211，生成错误标识；
在本步骤中，错误标识可反馈给任意元件，以通知该元件执行其他动作，例如由第一处理器11控制显示外设进行报错。
步骤212，若接收到异常中断，则关闭定时器，并进一步直接执行步骤209及后续步骤；
步骤213，若接收到定时器的超时中断，则关闭定时器；
步骤214，累加超时次数；
步骤215，判断定超时次数是否到达超时次数阈值，若达到超时次数阈值，则执行步骤211，生成错误标识，若未达到超时次数阈值，则返回步骤203，重新写入待传输数据。
如图3所示，图3是根据本发明第三实施例的对先进先出存储器进行读操作的流程示意图，具体包括以下步骤：
步骤301，接收现场可编程门阵列12的读取中断；
在本步骤中，在现场可编程门阵列12确认写入的待传输数据正确后，则发送读取中断到第二处理器13，以通知第二处理器13进行读操作。由于采用中断通讯方式，使得第一处理11完成写操作到第二处理器13接收到读取中断之间仅需要一个场可编程门阵列12的时钟周期，因此相较于轮询的方式也明显的提高了系统的通讯效率。
步骤302，响应读取中断从第一先进先出存储器121读取待传输数据；
步骤303，校验读取的待传输数据是否正确，若读取的待传输数据正确，则执行步骤304，若读取的待传输数据不正确，则执行步骤305；
在本步骤中，具体校验过程可以采用与上文类似的CRC校验方式，在此不再赘述。
步骤304，生成正确标识；
在本步骤中，正确标识用于通知相应元件执行其他动作，例如第二处理器13根据正确标识将相关命定发送到真正的执行机构，以执行相应的动作。
步骤305，累加错误次数；
步骤306，判断错误次数达到错误次数阈值，若达到错误次数阈值，则执行步骤307，生成错误标识，若未达到错误次数阈值，则返回步骤302，重新读取待传输数据；
步骤307，生成错误标识。
通过上述方式，利用先进先出存储器对连续的命令进行缓存，保证数据不会丢失，从而保证了系统的可靠性，并进一步以中断的方式通知相应的处理器执行相应的动作，保证对数据响应的实时性。进一步，无需处理器进行串并转换，减轻了处理器的负担。
在本实施例中，针对周期性数据，利用现场可编程门阵列13可作为双口RAM的特点，将待传输数据缓存在现场可编程门阵列13的内部寄存器中，并由第一处理器11和第二处理器13进行周期性的写操作和读操作。
具体来说，缓冲单元120进一步设置第一寄存器123、第二寄存器124、第三寄存器125，其中所述第一寄存器123允许第一处理器11进行写操作，并允许第二处理器13进行读操作，第二寄存器124允许第二处理器13进行写操作，并允许第一处理器11进行读操作，第三寄存器125允许所述第一处理器和所述第二处理器均进行写操作和/或读操作。其中，第一寄存器123用于存储从第一处理器11向第二处理器13传输的数据，第二寄存器124用于存储从第二处理器13向第一处理器11传输的数据、第三寄存器125用于存储现场可编程门阵列13，第一处理器11和第二处理器13都可以写操作和/或读操作，以判断或设置与FPGA相关任务的状态。当然如本领域技术人员所理解的，可根据实际情况对第一寄存器123、第二寄存器124以及第三寄存器125的数量进行任意设置。
通过上述方式，由于采用周期性的读写操作，第一处理器11和第二处理器13只需各自按照周期定时器进行写操作和/或读操作。第一处理器11和第二处理器13在读写时只需要一条指令就可以完成，且第一处理器11和第二处理器13对这类数据也不需要存储，第一处理器11和第二处理器13几乎不会增加任何通讯方面的负担。
如图4所示，图4根据本发明第四实施例的数字控制系统的数据传输方法的流程示意图。在本实施例中，针对图1所示的数字控制系统提供了一种数据传输方法，具体包括以下步骤：
步骤401，由第一处理器11将自身作为主设备，并将现场可编程门阵列12作为从设备，向现场可编程门阵列12的缓冲单元120写入待传输数据；
步骤402，由第二处理器13将自身作为主设备，并将现场可编程门阵列12作为从设备，从现场可编程门阵列12的缓冲单元120读取待传输数据。
步骤401和步骤402的具体实现过程以及缓冲单元120的具体架构在上文中已经进行了详细描述，在此不再赘述。
本发明实施例还提供一种数控机床，所述数控机床包括机床本体以及安装在所述机床本体上的数控系统，所述数控系统为上述技术方案所描述的一种基于现场可编程门阵列的数字控制系统。
综上所述，本领域技术人员容易理解，在本发明实施例所提供的基于现场可编程门阵列的数字控制系统及其数据传输方法中，利用现场可编程门阵列作为从设备并作为两个处理器之间通讯的桥梁，使得两个处理器都可以作为通讯中的主设备，使得两个处理器之间的高速并行通讯成为可能。进一步，本发明实施例针对待传输数据的不同类型，对周期性数据和非周期性数据的传输过程进行了优化设置。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (21)

  1. 一种基于现场可编程门阵列的数字控制系统，其特征在于，所述数字控制系统包括第一处理器、第二处理器以及连接于所述第一处理器和所述第二处理器之间的现场可编程门阵列，其中所述现场可编程门阵列的内部设置有缓冲单元，所述第一处理器和所述第二处理器分别将自身作为主设备，将所述现场可编程门阵列作为从设备，并分别对所述缓冲单元进行读操作和写操作，进而在所述第一处理器与所述第二处理器之间传输待传输数据。
  2. 根据权利要求1所述的数字控制系统，其特征在于，所述缓冲单元包括先进先出存储器，其中所述第一处理器和所述第二处理器中的一个将所述待传输数据写入所述先进先出存储器，所述第一处理器和所述第二处理器中的另一个从所述先进先出存储器读取所述待传输数据。
  3. 根据权利要求2所述的数字控制系统，其特征在于，所述第一处理器和所述第二处理器中的所述一个在向所述先进先出存储器写入所述待传输数据前，首先读取所述先进先出存储器的状态中断，并判断所述先进先出存储器是否处于满状态，若所述先进先出存储器未处于满状态，则向所述先进先出存储器写入所述待传输数据。
  4. 根据权利要求3所述的数字控制系统，其特征在于，所述第一处理器和所述第二处理器中的所述一个在向所述先进先出存储器写入所述待传输数据后，启动定时器，并进一步判断是否接收到所述定时器的超时中断或者所述现场可编程门阵列反馈的接收完成中断或异常中断；
    其中，若接收到接收完成中断，则关闭所述定时器，并校验写入的所述待传输数据是否正确，若写入的所述待传输数据正确，则生成正确标识，若写入的所述待传输数据不正确，则累加错误次数，并判断所述错误次数是否达到错误次数阈值，若达到所述错误次数阈值，则生成错误标识，若未达到所述错误次数阈值，则重新写入所述待传输数据；
    若接收到所述异常中断，则关闭所述定时器，累加错误次数，并判断所述错误次数是否达到错误次数阈值，若达到所述错误次数阈值，则生成所述错误标识，若未达到所述错误次数阈值，则重新写入所述待传输数据；
    若接收到所述定时器的超时中断，则累加超时次数，并判断定超时次数是否到达超时次数阈值，若达到超时次数阈值，则生成所述错误标识，若未达到超时次数阈值，则重新写入所述待传输数据。
  5. 根据权利要求2所述的数字控制系统，其特征在于，所述第一处理器和所述第二处理器中的另一个接收所述现场可编程门阵列的读取中断，并响应所述读取中断从所述先进先出存储器读取所述待传输数据。
  6. 根据权利要求5所述的数字控制系统，其特征在于，所述第一处理器和所述第二处理器中的另一个进一步校验读取的所述待传输数据是否正确，若读取的所述待传输数据正确，则返回正确标识，若读取的所述待传输数据不正确，则累加错误次数，并判断所述错误次数达到错误次数阈值，若达到错误次数阈值，则生成错误标识，若未达到错误次数阈值，则重新读取所述待传输数据。
  7. 根据权利要求2所述的数字控制系统，其特征在于，所述缓冲单元包括第一先进先出存储器和第二先进先出存储器，其中所述第一先进先出存储器允许所述第一处理器进行写操作，并允许所述第二处理器进行读操作，所述第二先进先出存储器允许所述第二处理器进行写操作，并允许所述第一处理器进行读操作。
  8. 根据权利要求2-7任一项所述的数字控制系统，其特征在于，所述待传输数据为非周期性数据。
  9. 根据权利要求1所述的数字控制系统，其特征在于，所述缓冲单元包括寄存器，所述第一处理器和所述第二处理器周期性对所述寄存器进行写操作和读操作。
  10. 根据权利要求5所述的数字控制系统，其特征在于，所述缓冲单元包括第一寄存器和第二寄存器，其中所述第一寄存器允许所述第一处理器进行写操作，并允许所述第二处理器进行读操作，所述第二寄存器允许所述第二处理器进行写操作，并允许所述第一处理器进行读操作。
  11. 根据权利要求10所述的数字控制系统，其特征在于，所述缓冲单元进一步包括第三寄存器，所述第三寄存器允许所述第一处理器和所述第二处理器均进行写操作和/或读操作。
  12. 根据权利要求9-11任一项所述的数字控制系统，其特征在于，所述待传输数据为周期性数据。
  13. 一种基于现场可编程门阵列的数字控制系统的数据传输方法，其特征在于，所述数字控制系统包括第一处理器、第二处理器以及连接于所述第一处理器和所述第二处理器之间的现场可编程门阵列，其中所述现场可编程门阵列的内部设置有缓冲单元，所述方法包括：
    由所述第一处理器将自身作为主设备，并将所述现场可编程门阵列作为从设备，向所述缓冲单元写入待传输数据；
    由所述第二处理器将自身作为主设备，并将所述现场可编程门阵列作为从设备，从所述缓冲单元读取所述待传输数据。
  14. 根据权利要求13所述的方法，其特征在于，所述缓冲单元包括先进先出存储器；
    所述由所述第一处理器将自身作为主设备，并将所述现场可编程门阵列作为从设备，向所述缓冲单元写入待传输数据的步骤包括：
    读取所述先进先出存储器的状态中断，并判断所述先进先出存储器是否处于满状态，若所述先进先出存储器未处于满状态，则向所述先进先出存储器写入所述待传输数据。
  15. 根据权利要求14所述的方法，其特征在于，所述由所述第一处理器将自身作为主设备，并将所述现场可编程门阵列作为从设备，向所述缓冲单元写入待传输数据的步骤进一步包括：
    在向所述先进先出存储器写入所述待传输数据后，启动定时器；
    判断是否接收到所述定时器的超时中断或者所述现场可编程门阵列反馈的接收完成中断或异常中断；
    其中，若接收到接收完成中断，则关闭所述定时器，并校验写入的所述待传输数据是否正确，若写入的所述待传输数据正确，则生成正确标识，若写入的所述待传输数据不正确，则累加错误次数，并判断所述错误次数是否达到错误次数阈值，若达到所述错误次数阈值，则生成错误标识，若未达到所述错误次数阈值，则重新写入所述待传输数据；
    若接收到所述异常中断，则关闭所述定时器，累加错误次数，并判断所述错误次数是否达到错误次数阈值，若达到所述错误次数阈值，则生成所述错误标识，若未达到所述错误次数阈值，则重新写入所述待传输数据；
    若接收到所述定时器的超时中断，则累加超时次数，并判断定超时次数是否到达超时次数阈值，若达到超时次数阈值，则生成所述错误标识，若未达到超时次数阈值，则重新写入所述待传输数据。
  16. 根据权利要求14所述的方法，其特征在于，所述由所述第二处理器将自身作为主设备，并将所述现场可编程门阵列作为从设备，从所述缓冲单元读取所述待传输数据的步骤包括：
    接收所述现场可编程门阵列的读取中断；
    响应所述读取中断从所述先进先出存储器读取所述待传输数据。
  17. 根据权利要求16所述的方法，其特征在于，所述由所述第二处理器将自身作为主设备，并将所述现场可编程门阵列作为从设备，从所述缓冲单元读取所述待传输数据的步骤包括：
    校验读取的所述待传输数据是否正确，若读取的所述待传输数据正确，则返回正确标识，若读取的所述待传输数据不正确，则累加错误次数，并判断所述错误次数达到错误次数阈值，若达到错误次数阈值，则生成错误标识，若未达到错误次数阈值，则重新读取所述待传输数据。
  18. 根据权利要求14所述的方法，其特征在于，所述待传输数据为非周期性数据。
  19. 根据权利要求13所述的方法，其特征在于，所述缓冲单元包括寄存器；
    所述由所述第一处理器将自身作为主设备，并将所述现场可编程门阵列作为从设备，向所述缓冲单元写入待传输数据的步骤包括：
    向所述缓冲单元周期性写入所述待传输数据；
    所述由所述第二处理器将自身作为主设备，并将所述现场可编程门阵列作为从设备，从所述缓冲单元读取所述待传输数据的步骤包括：
    从所述缓冲单元周期性读取所述待传输数据。
  20. 根据权利要求19所述的方法，其特征在于，所述待传输数据为周期性数据。
  21. 一种数控机床，其特征在于，所述数控机床包括机床本体以及安装在所述机床本体上的数控系统，所述数控系统为权利要求1-12任一项所述的一种基于现场可编程门阵列的数字控制系统。
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CN114003362A (zh) * 2021-10-29 2022-02-01 西安微电子技术研究所 一种多维度动态中断聚合方法、系统、设备及存储介质
CN114003362B (zh) * 2021-10-29 2024-03-19 西安微电子技术研究所 一种多维度动态中断聚合方法、系统、设备及存储介质

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