WO2018113182A1 - 一种测试向量的生成方法及装置、存储介质 - Google Patents

一种测试向量的生成方法及装置、存储介质 Download PDF

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Publication number
WO2018113182A1
WO2018113182A1 PCT/CN2017/085689 CN2017085689W WO2018113182A1 WO 2018113182 A1 WO2018113182 A1 WO 2018113182A1 CN 2017085689 W CN2017085689 W CN 2017085689W WO 2018113182 A1 WO2018113182 A1 WO 2018113182A1
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clock domain
clock
current
domains
domain
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PCT/CN2017/085689
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English (en)
French (fr)
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齐豫
葛一凡
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深圳市中兴微电子技术有限公司
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Publication of WO2018113182A1 publication Critical patent/WO2018113182A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G01R31/2837—Characterising or performance testing, e.g. of frequency response

Definitions

  • the present invention relates to a chip testing technology, and in particular, to a method and device for generating a test vector, and a storage medium.
  • the Design for Testability (DFT) of the chip is an important part of the chip design. By inserting various hardware logics for improving the testability of the chip in the original design of the chip, the chip can be easily tested and the chip test can be saved. cost. Among them, DFT mainly includes: low speed test and high speed test. For example, mainstream test related electronic design automation (EDA) tools can be used to generate corresponding test vectors for chip testing. With the increasingly fierce competition in the chip market, in order to shorten the cycle of chip-to-return, on the one hand, it is necessary to shorten the generation time of test vectors; on the other hand, it is necessary to minimize the number of test vectors while ensuring test coverage. This reduces the time cost incurred in testing DFT vectors for large-scale mass-produced chips.
  • EDA electronic design automation
  • test method based on test vector is the most commonly used test method in chip test technology.
  • the existing test vector generation methods mainly include the following two methods:
  • the embodiment of the present invention is to provide a method and a device for generating a test vector and a storage medium, which can not only effectively ensure the accuracy of generating a test vector, but also effectively improve the generation of test vectors in time. Sex.
  • An embodiment of the present invention provides a method for generating a test vector, where the method includes:
  • All clock domains are divided into multiple target sets; wherein, there is no interaction relationship between any two clock domains in each target set, and at least one target set includes clock domains of different clock domain types;
  • the dividing all clock domains into multiple target sets includes:
  • each clock domain has an interaction relationship with all clock domains in the set of clock domains corresponding to the clock domain;
  • All clock domains are divided into multiple target sets according to a set of clock domains corresponding to each clock domain.
  • the clock domain is divided into multiple target sets according to a set of clock domains corresponding to each clock domain, including:
  • the current clock domain is moved out of the entire clock domain into the current target set.
  • the clock domain is divided into multiple target sets according to a set of clock domains corresponding to each clock domain, including:
  • Each clock domain in each clock domain and its corresponding clock domain set is divided into one clock domain group; all clock domain groups are regarded as all current clock domain groups;
  • the first clock domain group includes: a first clock domain and the first clock The first paired clock domain corresponding to the domain;
  • the determining the first clock domain group in the current all clock domain includes:
  • All clock domains are sorted according to the number of occurrences of each clock domain in the current clock domain in the current all clock domain groups;
  • the first clock domain group is determined according to the sorting result.
  • An embodiment of the present invention further provides a device for generating a test vector, where the device includes: an acquiring unit, a dividing unit, and a generating unit;
  • the acquiring unit is configured to acquire all clock domains corresponding to the chip to be tested;
  • the dividing unit is configured to divide all clock domains into multiple target sets; wherein, there is no interaction relationship between any two clock domains in each target set, and at least one target set includes clocks of different clock domain types area;
  • the generating unit is configured to generate each test vector of the chip to be tested according to each target set.
  • the dividing unit includes: a determining subunit and a dividing subunit; wherein
  • the determining subunit is configured to determine a set of clock domains corresponding to each clock domain; wherein each clock domain has an interaction relationship with all clock domains in the set of clock domains corresponding to the clock domain;
  • the dividing subunit is configured to divide all clock domains into a plurality of target sets according to a set of clock domains corresponding to each clock domain.
  • the dividing unit further includes: a determining subunit; wherein
  • the determining subunit is configured to select one clock domain in the entire clock domain as the current clock domain when all the clock domains are not empty; and determine whether the total target set exists in the entire target set according to the clock domain set corresponding to the current clock domain. a current target set corresponding to the current clock domain; wherein the current clock domain does not have an interaction relationship with any one of the current target sets;
  • the dividing subunit is further configured to remove the current clock domain from all clock domains into the current target set when the current target set exists in all target sets.
  • the determining subunit is further configured to divide each clock domain in each clock domain and its own clock domain into a clock domain group; a current clock domain group; when all clock domains are not empty, determining a first clock domain and a first paired clock domain corresponding to the first clock domain in the current all clock domain; determining the first clock a target set corresponding to each of the domain and the first paired clock domain;
  • the dividing subunit is further configured to remove the first clock domain and the first paired clock domain from all clock domains into respective corresponding target sets; deleting the current clock domain group The first clock domain group; all clock domain groups after the first clock domain group is deleted are used as the current clock domain group.
  • the determining subunit is configured to sort all the clock domains according to the number of occurrences of each clock domain in the current all clock domains in the current all clock domain groups; The first clock domain and the first paired clock domain are described.
  • the embodiment of the present invention further provides a storage medium, which stores an executable program, and the executable program is executed by the processor to implement a method for generating a test vector provided by an embodiment of the present invention.
  • An embodiment of the present invention further provides a device for generating a test vector, including:
  • a memory for storing an executable program
  • the method for generating a test vector provided by the embodiment of the present invention is implemented when the processor is configured to run the executable program stored in the memory.
  • the solution is to first obtain all the clock domains corresponding to the chip to be tested, then divide all clock domains into multiple target sets, and finally generate a test vector of each chip to be tested according to each target set, that is, Each test vector may be generated according to multiple clock domains in each target set, and there is no interaction relationship between any two clock domains in each target set and at least one target set includes clock domains of different clock domain types.
  • the embodiment of the present invention can not only effectively ensure the accuracy of generating the test vector, but also can effectively improve the timeliness of generating the test vector; and the technical solution of the embodiment of the present invention is It is simple, convenient, and easy to popularize, and has a wider range of applications.
  • FIG. 1 is a schematic flowchart of an implementation process of a method for generating a test vector according to an embodiment of the present invention
  • FIG. 2 is a schematic flowchart of an implementation method for dividing all clock domains into multiple target sets according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a clock domain set corresponding to each clock domain in an embodiment of the present invention.
  • FIG. 4 is a schematic flowchart of a first implementation method for dividing all clock domains into multiple target sets according to an embodiment of the present invention
  • FIG. 5 is a schematic flowchart of a second implementation method for dividing all clock domains into multiple target sets according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of components of all clock domain groups in an embodiment of the present invention.
  • FIG. 7 is a schematic flowchart of a method for determining a first clock domain group according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a method for determining a first clock domain according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a method for determining a first paired clock domain according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram showing a first component structure of a test vector generating apparatus according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram showing a second component structure of a test vector generating apparatus according to an embodiment of the present invention.
  • FIG. 12 is a schematic structural diagram of hardware of a test vector generating apparatus according to an embodiment of the present invention.
  • the existing method for generating the first test vector since a test vector is generated for one clock domain, this will lengthen the time required to generate the test vector, which seriously reduces the test direction.
  • the generation efficiency of the quantity in the existing generation method of the second test vector, multiple clock domains are divided into the same clock domain type, and then a test vector is generated according to multiple clock domains in the same clock domain type, so The existing method for generating the second test vector generates a larger number of test vectors, which also reduces the efficiency of generating test vectors.
  • FIG. 1 is a schematic flowchart of an implementation process of a method for generating a test vector according to an embodiment of the present invention. As shown in FIG. 1, the method for generating a test vector includes the following steps:
  • Step 101 Acquire all clock domains corresponding to the chip to be tested.
  • all clock domains corresponding to the chip to be tested may be acquired first.
  • a static timing analysis (STA) tool can be used to obtain all clock domains corresponding to the chip to be tested.
  • STA static timing analysis
  • all clock domains corresponding to the chip to be tested are: ⁇ C 1 , C 2 , . . . , C n ⁇ , where n is a natural number greater than or equal to 1.
  • Step 102 Divide all clock domains into multiple target sets; wherein, there is no interaction relationship between any two clock domains in each target set, and at least one target set includes clock domains of different clock domain types.
  • all clock domains may be divided into multiple target sets; wherein any two clock domains in each target set are between There is no interaction and at least one target set includes clock domains of different clock domain types. That is to say, the clock domain in which there is no interaction relationship is divided into a target set, so that the clock domains in each target set do not affect each other when they are simultaneously turned on.
  • FIG. 2 is a schematic flowchart of an implementation method for dividing all clock domains into multiple target sets according to an embodiment of the present invention. As shown in FIG. 2, the method of dividing all clock domains into multiple target sets may include the following steps:
  • Step 102a Determine a clock domain set corresponding to each clock domain; wherein each clock domain has an interaction relationship with all clock domains in the clock domain set corresponding to itself (the clock domain itself).
  • the set of clock domains corresponding to each clock domain can be determined first.
  • a static timing analysis (STA) tool can be used to determine a set of clock domains corresponding to each clock domain.
  • FIG. 3 is a schematic structural diagram of a clock domain set corresponding to each clock domain in an embodiment of the present invention.
  • a static timing analysis tool can be used to determine a set of clock domains corresponding to m+i clock domains; wherein m and i are natural numbers greater than or equal to 1.
  • the set of clock domains corresponding to the m clock domains are: ⁇ G1, G2, ..., G m ⁇ ;
  • the set of clock domains corresponding to the i clock domains are: ⁇ H1, H2, ..., H i ⁇ .
  • each clock domain has an interaction relationship with all clock domains in the clock domain set corresponding to itself.
  • the set of clock domain clock domain C 1,1 corresponds to ⁇ C 1,1
  • Step 102b All clock domains are divided into multiple target sets according to a set of clock domains corresponding to each clock domain.
  • all clock domains may be divided into multiple target sets according to a set of clock domains corresponding to each clock domain. For example, as shown in FIG. 3, the determination of the corresponding clock domain C 1,1 set ⁇ C 1,1
  • the clock domain set divides the clock domain C 1,1 into the target set corresponding to the clock domain C 1,1 .
  • FIG. 4 is a schematic flowchart of a first implementation method for dividing all clock domains into multiple target sets according to an embodiment of the present invention. As shown in FIG. 4, the method of dividing all clock domains into multiple target sets according to a set of clock domains corresponding to each clock domain may include the following steps:
  • Step 401 When all clock domains are not empty, select one clock domain in all clock domains as the current clock domain.
  • one clock domain when all clock domains are not empty, one clock domain may be selected as the current clock domain in all clock domains.
  • the clock domain C 1,1 when all clock domains are not empty, the clock domain C 1,1 can be selected as the current clock domain.
  • Step 402 Determine, according to the clock domain set corresponding to the current clock domain, whether there is a current target set corresponding to the current clock domain in all the target sets.
  • the current clock domain does not have any interaction relationship with any one of the current target sets.
  • whether the current target set corresponding to the current clock domain exists in all target sets may be determined according to the set of clock domains corresponding to the current clock domain. For example, suppose C 1 and 1 are the current clock domain. In the initial state, there is no target set. In this case, the target set F[1] can be created first, and then C 1,1 is divided into the target set F[1]. Then, it is assumed that the clock domain C 1,2 is selected as the current clock domain, and it can be determined according to the clock domain set corresponding to the clock domain C 1,2 whether there is a current target set corresponding to the clock domain C 1,2 in all target sets.
  • the clock domain C 1,2 can be removed from the entire clock domain to the target set F[1]; when there is a clock domain in the target set F[1] that has an interaction relationship with the clock domain C 1,2 , Create a target set F[2], and so on.
  • Step 403 When the current target set exists in all the target sets, the current clock domain is removed from the entire clock domain to the current target set, and the process returns to step 401.
  • the current clock domain when the current target set exists in all the target sets, the current clock domain may be removed from the entire clock domain to the current target set, and the process returns to step 401; when all the target sets do not exist, When the target is set, a new target set can be created, and then the current clock domain is moved out of the entire clock domain to the new target set, and the process returns to step 401.
  • FIG. 5 is a schematic flowchart of a second implementation method for dividing all clock domains into multiple target sets according to an embodiment of the present invention. As shown in FIG. 5, the method for dividing all clock domains into multiple target sets according to a set of clock domains corresponding to each clock domain may include the following steps:
  • Step 501 Divide each clock domain in each clock domain and its corresponding clock domain set into one clock domain group; use all clock domain groups as the current all clock domain groups.
  • each clock domain and each clock domain in the clock domain set corresponding to the clock domain may be divided into one clock domain group;
  • the domain group acts as the current all clock domain group.
  • FIG. 6 is a schematic structural diagram of a composition of all clock domain groups in an embodiment of the present invention.
  • each clock domain in each clock domain and its corresponding clock domain set is divided into one clock domain group.
  • C 1,1 set ⁇ C 1,1
  • C 1,2 ⁇ ⁇
  • ⁇ ⁇
  • ⁇ ⁇ C 1,1
  • Step 502 When the current all the clock domain groups are not empty, determine the first clock domain group in all the current clock domain groups; wherein, the first clock domain group includes: the first clock domain and the first clock domain corresponding to The first paired clock domain.
  • the current clock domain group may be determined whether the current clock domain group is empty; when the current all clock domain groups are not empty, the first clock domain group may be determined in all current clock domain groups;
  • the first clock domain group includes: a first clock domain corresponding to the first clock domain and a first clock domain corresponding to the first clock domain.
  • FIG. 7 is a schematic flowchart of a method for determining a first clock domain group according to an embodiment of the present invention. As shown in FIG. 7, the method for determining the first clock domain group in all current clock domains may include the following steps:
  • Step 701 Sort all clock domains according to the number of occurrences of each clock domain in all current clock domains in all current clock domain groups.
  • the number of occurrences of each clock domain in all current clock domains in all current clock domain groups may be first counted; then all clock domains may be sorted according to the number of occurrences.
  • FIG. 8 is a schematic diagram of an implementation method for determining a first clock domain according to an embodiment of the present invention.
  • all clock domains can be sorted in descending order.
  • all the clock domains after sorting are: Clk 1 [0], Clk 2 [0], ..., Clk n [0], and the number of occurrences of each clock domain in all current clock domain groups is: M1[0 ], M2[0], ..., Mk[0].
  • Step 702 Determine a first clock domain group according to the sorting result.
  • the first clock domain group may be determined according to the sorting result. For example, after sorting all clock domains, the clock domain with the most occurrences can be selected as the first clock domain. For example, assuming that the clock domain Clk 1 [0] is the most frequently occurring clock domain, the clock domain Clk 1 [0] can be used as the first clock domain in this step.
  • FIG. 9 is a schematic diagram of a method for determining a first paired clock domain in an embodiment of the present invention.
  • the first clock domain group GH[0] is: ⁇ Clk 1 [0], Clk 1, A [0] ⁇ .
  • Step 503 Determine a target set corresponding to each of the first clock domain and the first paired clock domain, and remove the first clock domain and the first paired clock domain from the first clock domain group into respective target sets.
  • two target sets may be created first: F[1] and F[2]; then the first clock domain is removed from the first clock domain group to In the target set F[1], the first paired clock domain is removed from the first clock domain group to the target set F[2], that is, the target set F[1] is the target set corresponding to the first clock domain;
  • the set F[2] is a target set corresponding to the first paired clock domain.
  • the target sets F[1] and F[2] may also be defined as F out [1]; when the first clock domain exists in the target set F out [1] and the first paired clock domain does not exist, at the current All clock domain groups including the first paired clock domain are found in all clock domain groups, and it is determined that all clock domains except the first paired clock domain of all clock domain groups including the first paired clock domain are at least one In the target set F[1], if each of the clock domain groups including the first paired clock domain except the first paired clock domain does not exist in the target set F[1], the first The clock domain is moved out of the first clock domain group to the target set F[1]; if at least one of the clock domains except the first paired clock domain in the entire clock domain group including the first paired clock domain is in the target set F When present in [1], it is determined that all clock domains except the first paired clock domain of all clock domain groups including the first paired clock domain are at least one of them exists in the target set F[2],
  • the domain group determines whether at least one of all clock domains except the first clock domain of all clock domain groups including the first clock domain exists in the target set F[1], if all clock domains of the first clock domain are included Each clock domain except the first clock domain in the group does not exist in the target set F[1], and the first paired clock domain is removed from the first clock domain group to the target set F[1]; When at least one of the clock domains of the clock domain except the first clock domain exists in the target set F[1], it is determined that all the clock domain groups including the first clock domain are divided by the first clock.
  • All of the clock domains outside the domain are at least one of them in the target set F[2], and if all clock domains except the first paired clock domain in the entire clock domain group including the first clock domain are in the target Does not exist in the set F[2], will be the first pairing
  • the clock domain is removed from the first clock domain group into the target set F[2]; if at least one of the clock domains except the first paired clock domain in the entire clock domain group including the first clock domain is in the target set F
  • the target set F[3] is created, and the first paired clock domain is removed from the first clock domain group to the target set F[3].
  • the first paired clock domain and the first clock domain when the first paired clock domain and the first clock domain exist in the target set F out [1], it is indicated that the first clock domain and the first paired clock domain have been from the first clock domain group. Move out to the target set F out [1], at which point the first clock domain group can be deleted in all current clock domains.
  • the first paired clock domain and the first clock domain are not present in the target set F out [1] the first clock domain and the first paired clock domain are removed from the first clock domain group to their respective corresponding ones according to the above method. In the target collection.
  • Step 504 Delete the first clock domain group in all current clock domain groups; use all the clock domain groups after deleting the first clock domain group as the current clock domain group, and return to step 502.
  • the first clock may be deleted in all current clock domain groups.
  • the domain group is deleted. All clock domain groups after the first clock domain group are deleted as the current clock domain group. Go back to step 502.
  • Step 103 Generate, according to each target set, each test vector of the chip to be tested.
  • each test vector of the chip to be tested may be generated according to each target set.
  • a test vector is generated according to a clock domain; when multiple clock domains are included in the target set, a test vector is generated according to multiple clock domains. Since there is no interaction between any two clock domains in each target set, it can be ensured that the clock domains in each target set do not affect each other when they are simultaneously turned on.
  • the method for generating a test vector provided by the embodiment of the present invention first acquires all clock domains corresponding to the chip to be tested, then divides all clock domains into multiple target sets, and finally generates test vectors of the chips to be tested according to each target set. That is, in a specific embodiment of the present invention, each test vector may be generated according to multiple clock domains in each target set, and there is no interaction relationship between any two clock domains in each target set and at least one
  • the target set includes clock domains of different clock domain types.
  • multiple clock domains are divided into the same clock domain type, and then one test vector is generated according to multiple clock domains in the same clock domain type.
  • the method for generating a test vector provided by the embodiment of the present invention can not only effectively ensure the accuracy of generating a test vector, but also effectively improve the timeliness of generating a test vector; and, the implementation of the present invention
  • the technical solution of the example is simple and convenient, easy to popularize, and has a wider application range.
  • FIG. 10 is a schematic diagram showing a first composition structure of a test vector generating apparatus according to an embodiment of the present invention. As shown in FIG. 10, the apparatus includes: an obtaining unit 1001, a dividing unit 1002, and a generating unit 1003;
  • the acquiring unit 1001 is configured to acquire all clock domains corresponding to the chip to be tested;
  • the dividing unit 1002 is configured to divide all clock domains into multiple target sets; wherein, there is no interaction relationship between any two clock domains in each target set, and at least one target set includes different clock domain types.
  • Clock domain
  • the generating unit 1003 is configured to generate each test vector of the chip to be tested according to each target set.
  • FIG. 11 is a schematic diagram showing a second component structure of a test vector generating apparatus according to an embodiment of the present invention.
  • the dividing unit 1002 includes: a determining subunit 10021 and a dividing subunit 10022; wherein
  • the determining sub-unit 10021 is configured to determine a set of clock domains corresponding to each clock domain; wherein each clock domain has an interaction relationship with all clock domains in the set of clock domains corresponding to the clock domain;
  • the dividing subunit 10022 is configured to divide all clock domains into a plurality of target sets according to a clock domain set corresponding to each clock domain.
  • the dividing unit 1002 further includes: a determining subunit 10023; wherein
  • the determining sub-unit 10023 is configured to select one clock domain in the entire clock domain as the current clock domain when all the clock domains are not empty, and determine whether the target domain set is determined according to the clock domain set corresponding to the current clock domain. There is a current target set corresponding to the current clock domain; wherein the current clock domain does not have an interaction relationship with any one of the current target sets;
  • the dividing sub-unit 10022 is further configured to remove the current clock domain from all clock domains into the current target set when the current target set exists in all target sets.
  • the determining subunit 10021 is further configured to divide each clock domain in each clock domain and each clock domain in the set of clock domains into one clock domain group; and use all clock domain groups as the current clock domain group; Determining, in the current all clock domains, a first paired clock domain corresponding to the first clock domain and the first clock domain; determining the first clock domain and the first paired clock a set of targets corresponding to each domain;
  • the dividing subunit 10022 is further configured to remove the first clock domain and the first paired clock domain from all clock domains to respective target sets; delete the current clock domain group The first clock domain group; all clock domains after the first clock domain group will be deleted The group acts as the current clock domain group.
  • the determining sub-unit 10021 is configured to sort all clock domains according to the number of occurrences of each clock domain in the current all clock domain in the current all clock domain group; a first clock domain and the first paired clock domain.
  • the obtaining unit 1001, the dividing unit 1002, and the generating unit 1003 may each be programmable by a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field located at the mobile terminal.
  • CPU central processing unit
  • MPU microprocessor
  • DSP digital signal processor
  • FPGA Gate array
  • FIG. 12 is a schematic diagram of a hardware structure of a device for generating a test vector according to an embodiment of the present invention, including: at least one processor 1101, a memory 1102, and Network interface 1103.
  • the various components in the test vector generation device are coupled together by a bus system 1104.
  • the bus system 1104 is used to implement connection communication between these components.
  • the bus system 1104 includes a power bus, a control bus, and a status signal bus in addition to the data bus.
  • various buses are labeled as bus system 1104 in FIG.
  • the memory 1102 can be either volatile memory or non-volatile memory, and can include both volatile and nonvolatile memory.
  • the non-volatile memory may be a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), or an Erasable Programmable Read (EPROM). Only Memory).
  • ROM Read Only Memory
  • PROM Programmable Read-Only Memory
  • EPROM Erasable Programmable Read Only Memory
  • the memory 1102 described in the embodiments of the present invention is intended to include, but is not limited to, these and any other suitable types of memory.
  • the memory 1102 in the embodiment of the present invention is used to store various types of data to support the operation of the test vector generating device.
  • Examples of such data include any computer program for operating on a test vector generation device, such as operating system 11021 and program 11022.
  • the operating system 11021 includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks.
  • Program 11022 can include various programs, A program implementing the method of an embodiment of the present invention may be included in the program 11022.
  • the method disclosed in the foregoing embodiments of the present invention may be applied to the processor 1101 or implemented by the processor 1101.
  • the processor 1101 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the foregoing method may be completed by an integrated logic circuit of hardware in the processor 1101 or an instruction in a form of software.
  • the processor 1101 described above may be a general purpose processor, a digital signal processor (DSP), or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, or the like.
  • DSP digital signal processor
  • the processor 1101 can implement or perform the various methods, steps, and logic blocks disclosed in the embodiments of the present invention.
  • a general purpose processor can be a microprocessor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiment of the present invention may be directly implemented as a hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software module can reside in a storage medium, which is located in memory 1102, and processor 1101 reads the information in memory 1102, in conjunction with its hardware, to perform the steps of the foregoing method.
  • the test vector generating device may be configured by one or more Application Specific Integrated Circuits (ASICs), DSPs, Programmable Logic Devices (PLDs), and Complex Programmable Logic Devices.
  • ASICs Application Specific Integrated Circuits
  • DSPs Digital Signal processors
  • PLDs Programmable Logic Devices
  • Complex Programmable Logic Devices CPLD, Complex Programmable Logic Device
  • FPGA Field-Programmable Gate Array
  • controller controller
  • microcontroller MCU, Micro Controller Unit
  • microprocessor Microprocessor
  • Other electronic components are implemented to perform the aforementioned methods.
  • Embodiments of the present invention further provide a storage medium storing an executable program, and the executable program is implemented by a processor to implement a test vector generation method, as shown in FIG. 1, FIG. 2, FIG. 4, and FIG.
  • the method of generating the test vectors shown, the storage medium may be the various types of non-volatile storage media described above.
  • each test vector may be generated according to multiple clock domains in each target set, and there is no interaction relationship between any two clock domains in each target set and at least one
  • the target set includes clock domains of different clock domain types.
  • multiple clock domains are divided into the same clock domain type, and then one test vector is generated according to multiple clock domains in the same clock domain type.
  • the apparatus for generating test vectors provided by the embodiments of the present invention can not only effectively ensure the accuracy of generating test vectors, but also effectively improve the timeliness of generating test vectors; and, the present invention implements
  • the technical solution of the example is simple and convenient, easy to popularize, and has a wider application range.
  • the embodiment of the invention discloses a method and a device for generating a test vector and a storage medium.
  • the method includes: acquiring all clock domains corresponding to the chip to be tested; dividing all clock domains into multiple target sets; wherein each target set There is no interaction relationship between any two of the clock domains, and at least one target set includes clock domains of different clock domain types; each test vector of the chip to be tested is generated according to each target set.
  • the embodiment of the invention not only can effectively ensure the accuracy of generating test vectors, but also can effectively improve the timeliness of generating test vectors; and the technical solution is simple, convenient, popular, and applicable.

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Abstract

一种测试向量的生成方法及装置、存储介质，该方法包括：获取待测芯片对应的全部时钟域（101）；将全部时钟域划分到多个目标集合中；其中，各个目标集合中的任意两个时钟域之间均不存在交互关系且至少一个目标集合包括不同时钟域类型的时钟域（102）；根据各个目标集合生成所述待测芯片的各个测试向量（103）。

Description

一种测试向量的生成方法及装置、存储介质
相关申请的交叉引用
本申请基于申请号为201611197099.4、申请日为2016年12月22日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的内容在此引入本申请作为参考。
技术领域
本发明涉及芯片测试技术，尤其涉及一种测试向量的生成方法及装置、存储介质。
背景技术
芯片的可测性设计(Design for Testability，DFT)是芯片设计中的重要环节，通过在芯片原始设计中插入各种用于提高芯片可测试性的硬件逻辑，可以使芯片容易测试，节省芯片测试成本。其中DFT主要包括：低速测试和高速测试。例如，可以利用主流相关电子设计自动化(Electronic Design Automation，EDA)工具产生对应的测试向量进行芯片测试。随着芯片市场的竞争日益激烈，为了缩短芯片留片到回片的周期，一方面，需要缩短测试向量的产生时间；另一方面，需要在保证测试覆盖率的前提下尽量减少测试向量数目，从而降低在对大规模批量生产的芯片进行DFT向量的测试时产生的时间成本。
大规模的芯片时钟结构较为复杂，不同的时钟域之间可能存在交互路径，这些路径可能是真实路径，也可能是虚假路径；而且有些时钟域之间也存在没有交互路径的情况。对于存在虚假路径或者不存在交互路径的时钟域，如果时序分析文件对上述虚假路径或者无交互路径的时钟域关系定 义明确，则可以按照时序分析文件完成时序修复，这样就会大大减少芯片时序修复的工作量。
目前，基于测试向量的测试方法是芯片测试技术中最常用的测试方法，现有的测试向量的生成方法主要包括以下两种方法：
第一、根据一个时钟域生成一个测试向量。例如，针对一个时钟域生成一个测试向量，同时关闭其他时钟域，这样可以有效地保证芯片的测试质量；第二、根据多个时钟域生成一个测试向量。例如，先将多个时钟域划分到同一个时钟域类型中，然后根据同一时钟域类型中的多个时钟域生成一个测试向量。
发明内容
为至少解决上述的技术问题，本发明实施例期望提供一种测试向量的生成方法及装置、存储介质，不仅可以有效地保证生成测试向量的准确性，而且还可以有效地提高生成测试向量的及时性。
为达到上述目的，本发明实施例的技术方案是这样实现的：
本发明实施例提供了一种测试向量的生成方法，所述方法包括：
获取待测芯片对应的全部时钟域；
将全部时钟域划分到多个目标集合中；其中，各个目标集合中的任意两个时钟域之间均不存在交互关系且至少一个目标集合包括不同时钟域类型的时钟域；
根据各个目标集合生成所述待测芯片的各个测试向量。
在上述实施例中，所述将全部时钟域划分到多个目标集合中，包括：
确定各个时钟域对应的时钟域集合；其中，各个时钟域与自身对应的时钟域集合中的全部时钟域均存在交互关系；
根据各个时钟域对应的时钟域集合将全部时钟域划分到多个目标集合中。
在上述实施例中，所述根据各个时钟域对应的时钟域集合将全部时钟域划分到多个目标集合中，包括：
当全部时钟域不为空时，在全部时钟域中选择一个时钟域作为当前时钟域；
根据所述当前时钟域对应的时钟域集合判断在全部目标集合中是否存在所述当前时钟域对应的当前目标集合；其中，所述当前时钟域与所述当前目标集合中任意一个时钟域均不存在交互关系；
当全部目标集合中存在所述当前目标集合时，将所述当前时钟域从全部时钟域中移出到所述当前目标集合中。
在上述实施例中，所述根据各个时钟域对应的时钟域集合将全部时钟域划分到多个目标集合中，包括：
将各个时钟域与自身对应的时钟域集合中的各个时钟域划分为一个时钟域组；将全部时钟域组作为当前全部时钟域组；
当所述当前全部时钟域组不为空时，在所述当前全部时钟域组中确定第一时钟域组；其中，所述第一时钟域组包括：第一时钟域和所述第一时钟域对应的第一配对时钟域；
确定所述第一时钟域和所述第一配对时钟域各自对应的目标集合中，并将所述第一时钟域和所述第一配对时钟域从所述第一时钟域组中移出到各自对应的目标集合中；
在所述当前全部时钟域组中删除所述第一时钟域组；将删除所述第一时钟域组后的全部时钟域组作为当前时钟域组。
在上述实施例中，所述在所述当前全部时钟域中确定第一时钟域组，包括：
按照所述当前全部时钟域中各个时钟域在所述当前全部时钟域组中的出现次数对全部时钟域进行排序；
根据排序结果确定所述第一时钟域组。
本发明实施例还提供了一种测试向量的生成装置，所述装置包括：获取单元、划分单元和生成单元；其中，
所述获取单元，配置为获取待测芯片对应的全部时钟域；
所述划分单元，配置为将全部时钟域划分到多个目标集合中；其中，各个目标集合中的任意两个时钟域之间均不存在交互关系且至少一个目标集合包括不同时钟域类型的时钟域；
所述生成单元，配置为根据各个目标集合生成所述待测芯片的各个测试向量。
在上述实施例中，所述划分单元包括：确定子单元和划分子单元；其中，
所述确定子单元，配置为确定各个时钟域对应的时钟域集合；其中，各个时钟域与自身对应的时钟域集合中的全部时钟域均存在交互关系；
所述划分子单元，配置为根据各个时钟域对应的时钟域集合将全部时钟域划分到多个目标集合中。
在上述实施例中，所述划分单元还包括：判断子单元；其中，
所述判断子单元，配置为当全部时钟域不为空时，在全部时钟域中选择一个时钟域作为当前时钟域；根据所述当前时钟域对应的时钟域集合判断在全部目标集合中是否存在所述当前时钟域对应的当前目标集合；其中，所述当前时钟域与所述当前目标集合中任意一个时钟域均不存在交互关系；
所述划分子单元，还配置为当全部目标集合中存在所述当前目标集合时，将所述当前时钟域从全部时钟域中移出到所述当前目标集合中。
在上述实施例中，所述确定子单元，还配置为将各个时钟域与自身对应的时钟域集合中的各个时钟域划分为一个时钟域组；将全部时钟域组作 为当前全部时钟域组；当全部时钟域不为空时，在所述当前全部时钟域中确定第一时钟域和所述第一时钟域对应的第一配对时钟域；确定所述第一时钟域和所述第一配对时钟域各自对应的目标集合；
所述划分子单元，还配置为将所述第一时钟域和所述第一配对时钟域从全部时钟域中移出到各自对应的目标集合中；在所述当前全部时钟域组中删除所述第一时钟域组；将删除所述第一时钟域组后的全部时钟域组作为当前时钟域组。
在上述实施例中，所述确定子单元，具体配置为按照所述当前全部时钟域中各个时钟域在所述当前全部时钟域组中的出现次数对全部时钟域进行排序；根据排序结果确定所述第一时钟域和所述第一配对时钟域。
本发明实施例还提供了一种存储介质，存储有可执行程序，所述可执行程序被处理器运行时实现本发明实施例提供的测试向量的生成方法。
本发明实施例还提供了一种测试向量的生成装置，包括：
存储器，用于存储可执行程序；
处理器，配置为运行所述存储器存储的所述可执行程序时，实现本发明实施例提供的测试向量的生成方法。
本发明实施例中，提供先获取待测芯片对应的全部时钟域，然后将全部时钟域划分到多个目标集合中，最后根据各个目标集合生成待测芯片的各个测试向量的方案，也就是说，可以根据各个目标集合中的多个时钟域生成各个测试向量，而且各个目标集合中的任意两个时钟域之间均不存在交互关系且至少一个目标集合包括不同时钟域类型的时钟域。
而在相关技术中，将多个时钟域划分到同一时钟域类型中，然后根据同一时钟域类型中的多个时钟域生成一个测试向量。因此，和相关技术相比，本发明实施例不仅可以有效地保证生成测试向量的准确性，而且还可以有效地提高生成测试向量的及时性；并且，本发明实施例的技术方案实 现简单方便、便于普及，适用范围更广。
附图说明
图1为本发明实施例中测试向量的生成方法的实现流程示意图；
图2为本发明实施例中将全部时钟域划分到多个目标集合中的实现方法流程示意图；
图3为本发明实施例中各个时钟域对应的时钟域集合的组成结构示意图；
图4为本发明实施例中将全部时钟域划分到多个目标集合中的第一实现方法流程示意图；
图5为本发明实施例中将全部时钟域划分到多个目标集合中的第二实现方法流程示意图；
图6为本发明实施例中全部时钟域组的组成结构示意图；
图7为本发明实施例中确定第一时钟域组的实现方法流程示意图；
图8为本发明实施例中确定第一时钟域的实现方法示意图；
图9为本发明实施例中确定第一配对时钟域的实现方法示意图；
图10为本发明实施例中测试向量的生成装置的第一组成结构示意图；
图11为本发明实施例中测试向量的生成装置的第二组成结构示意图；
图12为本发明实施例提供的测试向量的生成装置的硬件结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
在实现本发明的过程中，发明人发现相关技术中至少存在如下问题：
在现有第一种测试向量的生成方法中，由于针对一个时钟域生成一个测试向量，这样就会延长生成测试向量所需要的时间，严重降低了测试向 量的生成效率；在现有第二种测试向量的生成方法中，将多个时钟域划分到同一时钟域类型中，然后根据同一时钟域类型中的多个时钟域生成一个测试向量，因此采用现有第二种测试向量的生成方法生成的测试向量数目较多，也会降低测试向量的生成效率。
图1为本发明实施例中测试向量的生成方法的实现流程示意图。如图1所示，测试向量的生成方法包括以下步骤：
步骤101、获取待测芯片对应的全部时钟域。
在本发明的具体实施例中，可以先获取待测芯片对应的全部时钟域。例如，可以利用静态时序分析(STA，Static Timing Analysis)工具获取待测芯片对应的全部时钟域。例如，待测芯片对应的全部时钟域为：{C1，C2，…，Cn}，其中，n为大于等于1的自然数。
步骤102、将全部时钟域划分到多个目标集合中；其中，各个目标集合中的任意两个时钟域之间均不存在交互关系且至少一个目标集合包括不同时钟域类型的时钟域。
在本发明的具体实施例中，在获取到待测芯片对应的全部时钟域之后，可以将全部时钟域划分到多个目标集合中；其中，各个目标集合中的任意两个时钟域之间均不存在交互关系且至少一个目标集合包括不同时钟域类型的时钟域。也就是说，将不存在交互关系的时钟域划分到一个目标集合中，这样可以保证各个目标集合内的时钟域在同时开启时不会相互影响。
图2为本发明实施例中将全部时钟域划分到多个目标集合中的实现方法流程示意图。如图2所示，将全部时钟域划分到多个目标集合中的方法可以包括以下步骤：
步骤102a、确定各个时钟域对应的时钟域集合；其中，各个时钟域与自身(时钟域自身)对应的时钟域集合中的全部时钟域均存在交互关系。
在本发明的具体实施例中，在将全部时钟域划分到多个目标集合中时， 可以先确定各个时钟域对应的时钟域集合。例如，可以利用静态时序分析(Static Timing Analysis，STA)工具确定各个时钟域对应的时钟域集合。
图3为本发明实施例中各个时钟域对应的时钟域集合的组成结构示意图。如图3所示，利用静态时序分析工具可以确定m+i个时钟域对应的时钟域集合；其中，m和i均为大于等于1的自然数。例如，m个时钟域对应的时钟域集合分别为：{G1、G2、…、Gm}；i个时钟域对应的时钟域集合分别为：{H1、H2、…、Hi}。在各个时钟域对应的时钟域集合中，各个时钟域与自身对应的时钟域集合中的全部时钟域均存在交互关系。
例如，在时钟域C1,1对应的时钟域集合{C1,1|C1,2，…，C1,α}中，C1,1与C1,2、…、C1,α均存在交互关系；在时钟域Cm+1,1对应的时钟域集合{Cm+1,1}中，时钟域Cm+1,1与待测芯片对应的全部时钟域均不存在交互关系。
步骤102b、根据各个时钟域对应的时钟域集合将全部时钟域划分到多个目标集合中。
在本发明的具体实施例中，在确定各个时钟域对应的时钟域集合之后，可以根据各个时钟域对应的时钟域集合将全部时钟域划分到多个目标集合中。例如，如图3所示，在确定了C1,1对应的时钟域集合{C1,1|C1,2，…，C1, α}之后，可以根据时钟域C1,1对应的时钟域集合，将时钟域C1,1划分到时钟域C1,1对应的目标集合中。
图4为本发明实施例中将全部时钟域划分到多个目标集合中的第一实现方法流程示意图。如图4所示，根据各个时钟域对应的时钟域集合将全部时钟域划分到多个目标集合中的方法可以包括以下步骤：
步骤401、当全部时钟域不为空时，在全部时钟域中选择一个时钟域作为当前时钟域。
在本发明的具体实施例中，当全部时钟域不为空时，可以先在全部时钟域中选择一个时钟域作为当前时钟域。例如，当全部时钟域不为空时， 可以选择时钟域C1,1作为当前时钟域。
步骤402、根据当前时钟域对应的时钟域集合判断在全部目标集合中是否存在当前时钟域对应的当前目标集合；其中，当前时钟域与当前目标集合中任意一个时钟域均不存在交互关系。
在本发明的具体实施例中，可以根据当前时钟域对应的时钟域集合判断在全部目标集合中是否存在当前时钟域对应的当前目标集合。例如，假设选择C1,1为当前时钟域，在初始状态下，不存在任何目标集合，此时可以先创建目标集合F[1]，然后将C1,1划分到目标集合F[1]中；然后假设选择时钟域C1,2为当前时钟域，可以根据时钟域C1,2对应的时钟域集合判断在全部目标集合中是否存在时钟域C1,2对应的当前目标集合。
例如，可以判断目标集合F[1]中是否存在与时钟域C1,2存在交互关系的时钟域；当目标集合F[1]中不存在与时钟域C1,2存在交互关系的时钟域时，可以将时钟域C1,2从全部时钟域中移出到目标集合F[1]中；当目标集合F[1]中存在与时钟域C1,2存在交互关系的时钟域时，可以创建目标集合F[2]，以此类推。
步骤403、当全部目标集合中存在当前目标集合时，将当前时钟域从全部时钟域中移出到当前目标集合中，返回执行步骤401。
在本发明的具体实施例中，当全部目标集合中存在当前目标集合时，可以将当前时钟域从全部时钟域中移出到当前目标集合中，返回执行步骤401；当当全部目标集合中不存在当前目标集合时，可以创建新的目标集合，然后将当前时钟域从全部时钟域中移出到新的目标集合中，返回执行步骤401。
根据上述的分析可知，通过上述的步骤401～403，可以实现将全部时钟域划分到多个目标集合中，以保证各个目标集合中的任意两个时钟域之间均不存在交互关系，从而可以根据各个目标集合生成所述待测芯片的各个 测试向量。
图5为本发明实施例中将全部时钟域划分到多个目标集合中的第二实现方法流程示意图。如图5所示，根据各个时钟域对应的时钟域集合将全部时钟域划分到多个目标集合中的方法可以包括以下步骤：
步骤501、将各个时钟域与自身对应的时钟域集合中的各个时钟域划分为一个时钟域组；将全部时钟域组作为当前全部时钟域组。
在本发明的具体实施例中，在确定各个时钟域对应的时钟域集合之后，可以将各个时钟域与自身对应的时钟域集合中的各个时钟域划分为一个时钟域组；此时将全部时钟域组作为当前全部时钟域组。
图6为本发明实施例中全部时钟域组的组成结构示意图。如图6所示，将各个时钟域与自身对应的时钟域集合中的各个时钟域划分为一个时钟域组。例如，在确定C1,1对应的时钟域集合{C1,1|C1,2，…，C1,α}之后，可以将C1,1分别与C1,2，…，C1,α分别划分为一个时钟域组，即：{C1,1|C1,2}、{C1,1|C1,3}，…，{C1,1|C1,α}。
步骤502、当所述当前全部时钟域组不为空时，在当前全部时钟域组中确定第一时钟域组；其中，第一时钟域组包括：第一时钟域和第一时钟域对应的第一配对时钟域。
在本发明的具体实施例中，可以先判断当前全部时钟域组是否为空；当所述当前全部时钟域组不为空时，可以在当前全部时钟域组中确定第一时钟域组；其中，第一时钟域组包括：第一时钟域和第一时钟域对应的第一配对时钟域。当所述当前全部时钟域组为空时，可以结束将全部时钟域划分到多个目标集合中的流程。
图7为本发明实施例中确定第一时钟域组的实现方法流程示意图。如图7所示，在当前全部时钟域中确定第一时钟域组的方法可以包括以下步骤：
步骤701、按照当前全部时钟域中各个时钟域在当前全部时钟域组中的出现次数对全部时钟域进行排序。
在本发明的具体实施例中，可以先统计当前全部时钟域中各个时钟域在当前全部时钟域组中的出现次数；然后可以根据出现次数对全部时钟域进行排序。
图8为本发明实施例中确定第一时钟域的实现方法示意图。如图8所示，在统计完成各个时钟域在当前全部时钟域组中的出现次数之后，可以按照从大到小的顺序将全部时钟域进行排序。例如，排序后的全部时钟域依次为：Clk1[0]、Clk2[0]、…、Clkn[0]，各个时钟域在当前全部时钟域组中的出现次数依次为：M1[0]、M2[0]、…、Mk[0]。
步骤702、根据排序结果确定第一时钟域组。
在本发明的具体实施例中，在对全部时钟域进行排序之后，可以根据排序结果确定第一时钟域组。例如，在对全部时钟域进行排序之后可以选择出现次数最多的时钟域作为第一时钟域。例如，假设时钟域Clk1[0]为出现次数最多的时钟域，则在本步骤中可以将时钟域Clk1[0]作为第一时钟域。
图9为本发明实施例中确定第一配对时钟域的实现方法示意图。如图9所示，在确定第一时钟域Clk1[0]之后，可以找出所有包含第一时钟域Clk1[0]的全部时钟域组，然后在所有包含第一时钟域Clk1[0]的全部时钟域组中找出出现次数最多的时钟域作为第一时钟域对应的第一配对时钟域；假设在包含第一时钟域Clk1[0]的全部时钟域组中时钟域Clk1,A[0]的出现次数最多，此时可以将时钟域Clk1,A[0]作为第一配对时钟域。因此，第一时钟域组GH[0]为：{Clk1[0],Clk1,A[0]}。
步骤503、确定第一时钟域和第一配对时钟域各自对应的目标集合中，并将第一时钟域和第一配对时钟域从第一时钟域组中移出到各自对应的目标集合中。
在本发明的具体实施例中，当不存在任何目标集合时，可以先创建两个目标集合：F[1]和F[2]；然后将第一时钟域从第一时钟域组中移出到目标集合F[1]中；将第一配对时钟域从第一时钟域组中移出到目标集合F[2]中，即：目标集合F[1]为第一时钟域对应的目标集合；目标集合F[2]为第一配对时钟域对应的目标集合。
此外，还可以将目标集合F[1]和F[2]定义为Fout[1]；当目标集合Fout[1]中存在第一时钟域且不存在第一配对时钟域时，在当前全部时钟域组中找出包含第一配对时钟域的全部时钟域组，判断包含第一配对时钟域的全部时钟域组中除第一配对时钟域之外的全部时钟域是中否至少有一个在目标集合F[1]中存在，如果包含第一配对时钟域的全部时钟域组中除第一配对时钟域之外的各个时钟域均在目标集合F[1]中不存在，将第一时钟域从第一时钟域组中移出到目标集合F[1]；如果包含第一配对时钟域的全部时钟域组中除第一配对时钟域之外的各个时钟域至少有一个在目标集合F[1]中存在时，判断包含第一配对时钟域的全部时钟域组中除第一配对时钟域之外的全部时钟域是中否至少有一个在目标集合F[2]中存在，如果包含第一配对时钟域的全部时钟域组中除第一配对时钟域之外的各个时钟域均在目标集合F[2]中不存在，将第一时钟域从第一时钟域组中移出到目标集合F[2]中；如果包含第一配对时钟域的全部时钟域组中除第一配对时钟域之外的各个时钟域至少有一个在目标集合F[2]中存在时，创建目标集合F[3]，将第一时钟域从第一时钟域组中移出到目标集合F[3]。
在本发明的具体实施例中，当目标集合Fout[1]中存在第一配对时钟域且不存在第一时钟域时，在当前全部时钟域组中找出包含第一时钟域的全部时钟域组，判断包含第一时钟域的全部时钟域组中除第一时钟域之外的全部时钟域是否至少有一个在目标集合F[1]中存在，如果包含第一时钟域的全部时钟域组中除第一时钟域之外的各个时钟域均在目标集合F[1]中不存 在，将第一配对时钟域从第一时钟域组中移出到目标集合F[1]；如果包含第一时钟域的全部时钟域组中除第一时钟域之外的各个时钟域至少有一个在目标集合F[1]中存在时，判断包含第一时钟域的全部时钟域组中除第一时钟域之外的全部时钟域是中否至少有一个在目标集合F[2]中存在，如果包含第一时钟域的全部时钟域组中除第一配对时钟域之外的各个时钟域均在目标集合F[2]中不存在，将第一配对时钟域从第一时钟域组中移出到目标集合F[2]中；如果包含第一时钟域的全部时钟域组中除第一配对时钟域之外的各个时钟域至少有一个在目标集合F[2]中存在时，创建目标集合F[3]，将第一配对时钟域从第一时钟域组中移出到目标集合F[3]。
在本发明的具体实施例中，当目标集合Fout[1]中存在第一配对时钟域和第一时钟域时，说明第一时钟域和第一配对时钟域已经从第一时钟域组中移出至目标集合Fout[1]中，此时可以在当前全部时钟域中删除第一时钟域组。当目标集合Fout[1]中均不存在第一配对时钟域和第一时钟域时，按照上述方法将第一时钟域和第一配对时钟域从第一时钟域组中移出到各自对应的目标集合中。
步骤504、在当前全部时钟域组中删除第一时钟域组；将删除第一时钟域组后的全部时钟域组作为当前时钟域组，返回执行步骤502。
在本发明的具体实施例中，在将第一时钟域和第一配对时钟域从第一时钟域组中移出到各自对应的目标集合中之后，可以在当前全部时钟域组中删除第一时钟域组；此时将删除第一时钟域组后的全部时钟域组作为当前时钟域组，返回执行步骤502。
根据上述的分析可知，通过上述的步骤501～504，可以实现将全部时钟域划分到多个目标集合中，以保证各个目标集合中的任意两个时钟域之间均不存在交互关系，从而可以根据各个目标集合生成所述待测芯片的各个测试向量。
步骤103、根据各个目标集合生成所述待测芯片的各个测试向量。
在本发明的具体实施例中，可以根据各个目标集合生成待测芯片的各个测试向量。当目标集合中包括一个时钟域时，此时根据一个时钟域生成一个测试向量；当目标集合中包括多个时钟域时，此时根据多个时钟域生成一个测试向量。由于各个目标集合中的任意两个时钟域之间均不存在交互关系，因此，可以保证各个目标集合内的时钟域在同时开启时不会相互影响。
本发明实施例提供的测试向量的生成方法，先获取待测芯片对应的全部时钟域，然后将全部时钟域划分到多个目标集合中，最后根据各个目标集合生成待测芯片的各个测试向量。也就是说，在本发明的具体实施例中，可以根据各个目标集合中的多个时钟域生成各个测试向量，而且各个目标集合中的任意两个时钟域之间均不存在交互关系且至少一个目标集合包括不同时钟域类型的时钟域。而在相关技术中，将多个时钟域划分到同一时钟域类型中，然后根据同一时钟域类型中的多个时钟域生成一个测试向量。因此，和相关技术相比，本发明实施例提供的测试向量的生成方法，不仅可以有效地保证生成测试向量的准确性，而且还可以有效地提高生成测试向量的及时性；并且，本发明实施例的技术方案实现简单方便、便于普及，适用范围更广。
图10为本发明实施例中测试向量的生成装置的第一组成结构示意图。如图10所示，所述装置包括：获取单元1001、划分单元1002和生成单元1003；其中，
所述获取单元1001，配置为获取待测芯片对应的全部时钟域；
所述划分单元1002，配置为将全部时钟域划分到多个目标集合中；其中，各个目标集合中的任意两个时钟域之间均不存在交互关系且至少一个目标集合包括不同时钟域类型的时钟域；
所述生成单元1003，配置为根据各个目标集合生成所述待测芯片的各个测试向量。
图11为本发明实施例中测试向量的生成装置的第二组成结构示意图。如图10所示，所述划分单元1002包括：确定子单元10021和划分子单元10022；其中，
所述确定子单元10021，配置为确定各个时钟域对应的时钟域集合；其中，各个时钟域与自身对应的时钟域集合中的全部时钟域均存在交互关系；
所述划分子单元10022，配置为根据各个时钟域对应的时钟域集合将全部时钟域划分到多个目标集合中。
可选的，所述划分单元1002还包括：判断子单元10023；其中，
所述判断子单元10023，配置为当全部时钟域不为空时，在全部时钟域中选择一个时钟域作为当前时钟域；根据所述当前时钟域对应的时钟域集合判断在全部目标集合中是否存在所述当前时钟域对应的当前目标集合；其中，所述当前时钟域与所述当前目标集合中任意一个时钟域均不存在交互关系；
所述划分子单元10022，还配置为当全部目标集合中存在所述当前目标集合时，将所述当前时钟域从全部时钟域中移出到所述当前目标集合中。
可选的，所述确定子单元10021，还配置为将各个时钟域与自身对应的时钟域集合中的各个时钟域划分为一个时钟域组；将全部时钟域组作为当前全部时钟域组；当全部时钟域不为空时，在所述当前全部时钟域中确定第一时钟域和所述第一时钟域对应的第一配对时钟域；确定所述第一时钟域和所述第一配对时钟域各自对应的目标集合；
所述划分子单元10022，还配置为将所述第一时钟域和所述第一配对时钟域从全部时钟域中移出到各自对应的目标集合中；在所述当前全部时钟域组中删除所述第一时钟域组；将删除所述第一时钟域组后的全部时钟域 组作为当前时钟域组。
可选的，所述确定子单元10021，具体配置为按照所述当前全部时钟域中各个时钟域在所述当前全部时钟域组中的出现次数对全部时钟域进行排序；根据排序结果确定所述第一时钟域和所述第一配对时钟域。
在实际应用中，所述获取单元1001、划分单元1002和生成单元1003均可由位于移动终端的中央处理器(CPU)、微处理器(MPU)、数字信号处理器(DSP)、或现场可编程门阵列(FPGA)等实现。
本发明的实施例还提供了一种测试向量的生成装置，参见图12，图12是本发明实施例提供的测试向量的生成装置的硬件结构示意图，包括：至少一个处理器1101、存储器1102和网络接口1103。测试向量的生成装置中的各个组件通过总线系统1104耦合在一起。可理解，总线系统1104用于实现这些组件之间的连接通信。总线系统1104除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图12中将各种总线都标为总线系统1104。
可以理解，存储器1102可以是易失性存储器或非易失性存储器，也可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(ROM，Read Only Memory)、可编程只读存储器(PROM，Programmable Read-Only Memory)、可擦除可编程只读存储器(EPROM，Erasable Programmable Read-Only Memory)。本发明实施例描述的存储器1102旨在包括但不限于这些和任意其它适合类型的存储器。
本发明实施例中的存储器1102用于存储各种类型的数据以支持测试向量的生成装置的操作。这些数据的示例包括：用于在测试向量的生成装置上操作的任何计算机程序，如操作系统11021和程序11022。其中，操作系统11021包含各种系统程序，例如框架层、核心库层、驱动层等，用于实现各种基础业务以及处理基于硬件的任务。程序11022可以包含各种程序， 实现本发明实施例方法的程序可以包含在程序11022中。
上述本发明实施例揭示的方法可以应用于处理器1101中，或者由处理器1101实现。处理器1101可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器1101中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器1101可以是通用处理器、数字信号处理器(DSP，Digital Signal Processor)，或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。处理器1101可以实现或者执行本发明实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本发明实施例所公开的方法的步骤，可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于存储介质中，该存储介质位于存储器1102，处理器1101读取存储器1102中的信息，结合其硬件完成前述方法的步骤。
在示例性实施例中，测试向量的生成装置可以被一个或多个应用专用集成电路(ASIC，Application Specific Integrated Circuit)、DSP、可编程逻辑器件(PLD，Programmable Logic Device)、复杂可编程逻辑器件(CPLD，Complex Programmable Logic Device)、现场可编程门阵列(FPGA，Field-Programmable Gate Array)、通用处理器、控制器、微控制器(MCU，Micro Controller Unit)、微处理器(Microprocessor)、或其他电子元件实现，用于执行前述方法。
本发明实施例还提供一种存储介质，存储有可执行程序，所述可执行程序被处理器运行时实现测试向量的生成方法，如图1、图2、图4和图5任一附图所示的测试向量的生成方法，存储介质可以为前述的各种类型的非易失性存储介质。
本发明实施例中，先获取待测芯片对应的全部时钟域，然后将全部时 钟域划分到多个目标集合中，最后根据各个目标集合生成待测芯片的各个测试向量。也就是说，在本发明的具体实施例中，可以根据各个目标集合中的多个时钟域生成各个测试向量，而且各个目标集合中的任意两个时钟域之间均不存在交互关系且至少一个目标集合包括不同时钟域类型的时钟域。而在相关技术中，将多个时钟域划分到同一时钟域类型中，然后根据同一时钟域类型中的多个时钟域生成一个测试向量。因此，和相关技术相比，本发明实施例提供的测试向量的生成装置，不仅可以有效地保证生成测试向量的准确性，而且还可以有效地提高生成测试向量的及时性；并且，本发明实施例的技术方案实现简单方便、便于普及，适用范围更广。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本发明实施例公开了一种测试向量的生成方法及装置、存储介质，该方法包括：获取待测芯片对应的全部时钟域；将全部时钟域划分到多个目标集合中；其中，各个目标集合中的任意两个时钟域之间均不存在交互关系且至少一个目标集合包括不同时钟域类型的时钟域；根据各个目标集合生成所述待测芯片的各个测试向量。本发明实施例不仅可以有效地保证生成测试向量的准确性，而且还可以有效地提高生成测试向量的及时性；并且，技术方案实现简单方便、便于普及，适用范围更广。

Claims (12)

  1. 一种测试向量的生成方法，所述方法包括：
    获取待测芯片对应的全部时钟域；
    将全部时钟域划分到多个目标集合中；其中，各个目标集合中的任意两个时钟域之间均不存在交互关系，且至少一个目标集合包括不同时钟域类型的时钟域；
    根据各个目标集合生成所述待测芯片的各个测试向量。
  2. 根据权利要求1所述的方法，其中，所述将全部时钟域划分到多个目标集合中，包括：
    确定各个时钟域对应的时钟域集合；其中，各个时钟域与对应的时钟域集合中的全部时钟域均存在交互关系；
    根据各个时钟域对应的时钟域集合，将全部时钟域划分到多个目标集合中。
  3. 根据权利要求2所述的方法，其中，所述根据各个时钟域对应的时钟域集合，将全部时钟域划分到多个目标集合中，包括：
    当全部时钟域不为空时，在全部时钟域中选择一个时钟域作为当前时钟域；
    根据所述当前时钟域对应的时钟域集合，判断在全部目标集合中是否存在所述当前时钟域对应的当前目标集合；其中，所述当前时钟域与所述当前目标集合中任意一个时钟域均不存在交互关系；
    当全部目标集合中存在所述当前目标集合时，将所述当前时钟域从全部时钟域中移出到所述当前目标集合中。
  4. 根据权利要求2所述的方法，其中，所述根据各个时钟域对应的时钟域集合将全部时钟域划分到多个目标集合中，包括：
    将各个时钟域与对应的时钟域集合中的各个时钟域，划分为一个时钟 域组；将全部时钟域组作为当前全部时钟域组；
    当所述当前全部时钟域组不为空时，在所述当前全部时钟域组中确定第一时钟域组；其中，所述第一时钟域组包括：第一时钟域和所述第一时钟域对应的第一配对时钟域；
    确定所述第一时钟域和所述第一配对时钟域各自对应的目标集合，并将所述第一时钟域和所述第一配对时钟域从所述第一时钟域组中移出到各自对应的目标集合中；
    在所述当前全部时钟域组中删除所述第一时钟域组；将删除所述第一时钟域组后的全部时钟域组，作为当前时钟域组。
  5. 根据权利要求4所述的方法，其中，所述在所述当前全部时钟域中确定第一时钟域组，包括：
    按照所述当前全部时钟域中各个时钟域在所述当前全部时钟域组中的出现次数，对全部时钟域进行排序；
    根据排序结果确定所述第一时钟域组。
  6. 一种测试向量的生成装置，所述装置包括：获取单元、划分单元和生成单元；其中，
    所述获取单元，配置为获取待测芯片对应的全部时钟域；
    所述划分单元，配置为将全部时钟域划分到多个目标集合中；其中，各个目标集合中的任意两个时钟域之间均不存在交互关系，且至少一个目标集合包括不同时钟域类型的时钟域；
    所述生成单元，配置为根据各个目标集合生成所述待测芯片的各个测试向量。
  7. 根据权利要求6所述的装置，其中，所述划分单元包括：确定子单元和划分子单元；其中，
    所述确定子单元，配置为确定各个时钟域对应的时钟域集合；其中， 各个时钟域与对应的时钟域集合中的全部时钟域均存在交互关系；
    所述划分子单元，配置为根据各个时钟域对应的时钟域集合，将全部时钟域划分到多个目标集合中。
  8. 根据权利要求7所述的装置，其中，所述划分单元还包括：判断子单元；其中，
    所述判断子单元，配置为当全部时钟域不为空时，在全部时钟域中选择一个时钟域作为当前时钟域；根据所述当前时钟域对应的时钟域集合，判断在全部目标集合中是否存在所述当前时钟域对应的当前目标集合；其中，所述当前时钟域与所述当前目标集合中任意一个时钟域均不存在交互关系；
    所述划分子单元，还配置为当全部目标集合中存在所述当前目标集合时，将所述当前时钟域从全部时钟域中移出到所述当前目标集合中。
  9. 根据权利要求7所述的装置，其中，所述确定子单元，还配置为将各个时钟域与自身对应的时钟域集合中的各个时钟域，划分为一个时钟域组；将全部时钟域组作为当前全部时钟域组；当全部时钟域不为空时，在所述当前全部时钟域中确定第一时钟域和所述第一时钟域对应的第一配对时钟域；确定所述第一时钟域和所述第一配对时钟域各自对应的目标集合；
    所述划分子单元，还配置为将所述第一时钟域和所述第一配对时钟域从全部时钟域中移出到各自对应的目标集合中；在所述当前全部时钟域组中删除所述第一时钟域组；将删除所述第一时钟域组后的全部时钟域组作为当前时钟域组。
  10. 根据权利要求9所述的装置，其中，所述确定子单元，具体配置为按照所述当前全部时钟域中各个时钟域在所述当前全部时钟域组中的出现次数，对全部时钟域进行排序；根据排序结果确定所述第一时钟域和所述第一配对时钟域。
  11. 一种存储介质，存储有可执行程序，所述可执行程序被处理器运行时实现权利要求1至5任一项所述的测试向量的生成方法。
  12. 一种测试向量的生成装置，包括：
    存储器，用于存储可执行程序；
    处理器，配置为运行所述存储器存储的所述可执行程序时，实现权利要求1至5任一项所述的测试向量的生成方法。
PCT/CN2017/085689 2016-12-22 2017-05-24 一种测试向量的生成方法及装置、存储介质 WO2018113182A1 (zh)

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