WO2018107667A1 - 柔性薄膜的制造方法 - Google Patents

柔性薄膜的制造方法 Download PDF

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WO2018107667A1
WO2018107667A1 PCT/CN2017/085622 CN2017085622W WO2018107667A1 WO 2018107667 A1 WO2018107667 A1 WO 2018107667A1 CN 2017085622 W CN2017085622 W CN 2017085622W WO 2018107667 A1 WO2018107667 A1 WO 2018107667A1
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layer
film
single crystal
crystal
buried layer
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PCT/CN2017/085622
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French (fr)
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陈龙
李成
袁理
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上海新微技术研发中心有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Definitions

  • the present invention relates to the field of semiconductor materials, and more particularly to a method of manufacturing a flexible film.
  • Crystalline film materials such as GaN
  • electronic components are placed under the protective coating of glass or sapphire, which raises compatibility issues, and the use of GaN avoids potential compatibility issues.
  • the wear resistance of GaN provides us with a way to replace a typical multilayer semiconductor device with a single layer of material with excellent optical, electrical and wear resistance.
  • Using GaN to build a complete device on a platform without multi-layer technology, as well as the ability to integrate electronics, light sensors and light emitters, will provide a new paradigm for designing devices. And because GaN can be made very thin and high strength, it will also accelerate the development of flexible electronic products.
  • GaN materials have excellent mechanical properties and can withstand large external forces without breaking or damaging. More importantly, GaN-based materials have a piezoelectric effect, and this combination of piezoelectric polarization and semiconductor properties gives us unprecedented performance. These properties have led to research interest in this emerging field. This provides many new ways to manipulate charge carrier conduction, generation, recombination, and separation under the control of flexible equipment under external mechanical action. However, due to the GaN growth process And the limitations of the device's process level make the development of flexible electronics based on GaN materials slow. In order to realize flexible GaN materials, people have explored them from different ways: a common method is to grow GaN materials on laser-peeled sapphire.
  • the main disadvantage of this method is that the peeling is easy to damage the GaN film, and the transferred film has high defect density and area.
  • Another method is ion implantation into the GaN bulk material by means of a bond transfer such as smart-cut, but the main disadvantage of this method is that the GaN film is difficult to be peeled off, the surface is uneven, and the defect density is high.
  • the technical problem to be solved by the present invention is to provide a simple and low cost method of manufacturing a flexible film.
  • the present invention provides a method of manufacturing a flexible film comprising the steps of: providing a substrate comprising a buried layer and a single crystal layer on a surface thereof; a single crystal layer on the substrate Forming a crystal film on the surface; forming a through hole from the surface of the crystal film to the surface of the buried layer; selectively etching the buried layer through the through hole to suspend the crystal film; The surface is coated with a polymeric carrier layer; the crystalline film and the polymeric carrier layer are removed from the surface of the substrate.
  • the material of the buried layer is an oxide; the material of the single crystal layer is Si, and the crystal orientation is (111); the material of the crystal thin film is a III-N semiconductor material selected from the group consisting of AlN and GaN. And one or more of the AlGaN materials.
  • the crystalline thin film is formed on the surface of the single crystal layer by epitaxial growth.
  • the single crystal layer is formed on the surface of the buried layer by bonding.
  • the material of the buried layer is any one of silicon oxide and silicon nitride.
  • the thickness of the crystalline film ranges from 200 nm to 1000 nm.
  • the material of the polymer carrier layer is selected from any one of PDMS and SU8 photoresist.
  • the above method is simple in process and low in cost, and can be used for preparing large-area, defect-free crystal flexible thin membrane.
  • FIG. 1 is a schematic view showing the implementation steps of an embodiment of the present invention.
  • FIGS. 2A through 2F are process flow diagrams showing an embodiment of the present invention.
  • step S10 providing a substrate, the substrate comprising a buried layer and a single crystal layer on the surface thereof; and step S11, in the substrate a surface of the single crystal layer is epitaxially formed into a crystalline film; in step S12, a through hole is formed from the surface of the crystal thin film to the surface of the buried layer; and in step S13, the buried layer is selectively etched through the through hole to make the buried layer
  • the crystal film is suspended; in step S14, a polymer carrier layer is applied on the surface of the crystal film; and in step S15, the crystal film and the polymer carrier layer are removed from the surface of the substrate.
  • a substrate 20 which includes a buried layer 202 and a single crystal layer 201 on the surface of the buried layer 202.
  • the material of the single crystal layer is selected from any one of single crystal silicon, single crystal GaN, and single crystal AlN, and is preferably silicon, and the crystal orientation is (111).
  • the material of the buried layer is an oxide or a nitride, and is preferably any one of silicon oxide and silicon nitride.
  • a crystal thin film 21 is epitaxially grown on the surface of the single crystal layer 201 of the substrate 20.
  • the thickness of the crystal thin film 21 ranges from 200 nm to 1000 nm, and the material is selected from any one of single crystal GaN and single crystal AlN.
  • the crystal thin film 21 is epitaxially formed on the surface of the single crystal layer 201.
  • the material of the buried layer 202 is any one of silicon oxide and silicon nitride.
  • the material of the buried layer 202 may also be any material that can be selectively etched with the crystal thin film 21 to be corroded and removed.
  • a through hole 24 is formed from the surface of the crystal thin film 21 to the surface of the buried layer 202.
  • the number of the through holes 24 is at least one, and preferably plural. Adjacent through hole 24 The distance between the selective etching solutions can be immersed.
  • the method of forming the through holes 24 may be a method such as photolithography or laser etching.
  • the vias 24 expose the buried layer 202 for subsequent selective etching.
  • the buried layer 202 is selectively etched through the via hole 24 to suspend the crystal thin film 21.
  • the selectively etched etching solution is capable of selectively etching the buried layer 202 to avoid etching the crystalline film 21.
  • the material of the buried layer 202 is any one of silicon oxide and silicon nitride, and the material of the crystal thin film 21 is selected from any one of single crystal silicon, single crystal GaN, and single crystal AlN.
  • the selective etching solution may be a hydrofluoric acid or hydrofluoric acid buffer. The crystal film 21 is suspended and adhered to the surface of the substrate 20 after etching.
  • a polymer carrier layer 26 is applied to the surface of the crystal thin film 21 with reference to step S14.
  • the material of the polymer carrier layer 26 is selected from any one of PDMS and SU8 photoresist, and is applied to the surface of the crystal thin film 21 by means of pasting or coating.
  • the crystal film 21 and the polymer carrier layer 26 are removed from the surface of the substrate 20 with reference to step S15.
  • the PDMS and SU8 photoresist materials are highly adsorptive to the crystalline material, so that the crystal thin film 21 can be separated from the surface of the substrate 20.
  • the composite film of the formed crystalline film 21 and the polymer carrier 26 can be subjected to operations such as bending, stretching, folding, and twisting.
  • the above method is simple in process and low in cost, and can be used for preparing a large-area, defect-free crystal flexible film.
  • an SOI substrate in which the top silicon and the supporting substrate are both Si (111) is used.
  • the epitaxial layer of single crystal GaN-based thin film is epitaxially grown by MOCVD to form a structure of single crystal GaN/HT-AlN/LT-AlN/Si.
  • the epitaxial steps include: 1. growing a 20 nm LT-AlN nucleation layer at 750 ° C, 60 mbar; 2. growing a 160 nm HT-AlN buffer layer at 1080 ° C, 50 mbar; 3. at 1050 ° C, 200 mbar Under conditions, a 400 nm single crystal GaN layer was grown.
  • the etch window is defined by lithography, the nitride epitaxial layer is etched by ICP, and the RIE is etched away. Top layer silicon.
  • the buried oxide layer of the SOI substrate is etched away by using hydrofluoric acid, so that the epitaxial layer is in virtual contact with the silicon substrate.
  • the coated PDMS is in intimate contact with the surface of the epitaxial layer and thereby transfers the epitaxial layer to the PDMS.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

提供了一种柔性薄膜的制造方法，包括如下步骤：提供衬底（20），衬底包括一埋层（202）和其表面的单晶层（201）；在衬底的单晶层表面外延一晶体薄膜（21）；形成从晶体薄膜表面至埋层表面的通孔（24）；通过通孔对埋层进行选择性腐蚀，使晶体薄膜悬空；在晶体薄膜的表面贴敷一聚合物载体层（26）；将晶体薄膜和聚合物载体层从衬底表面揭去。

Description

柔性薄膜的制造方法 技术领域
本发明涉及半导体材料领域，尤其涉及一种柔性薄膜的制造方法。
背景技术
当今电子技术发展的趋势是通过一定的手段，使系统避免刚性、易碎以及平面等特征，从而达到柔性、弹性、可拉伸、可扭曲以及可形变至曲面形状等特点。因此，柔性电子技术开始渐渐引起科学家们的关注。
柔性技术主要通过将传统刚性衬底上的功能材料及器件转移到柔性衬底上来实现。近年来，为了增强系统的柔性度，科学家们一直沿着从可弯曲、可拉伸、可折叠以及可扭曲这一技术路线发展。
晶体薄膜材料，例如GaN具有高硬度和高耐磨性能都会对电子和数码产品行业产生巨大的影响。在一个设备如智能手机，电子元件被安置在玻璃或蓝宝石的保护涂层下，这就提出了兼容性的问题，而使用GaN可以避免潜在的兼容性问题。GaN的耐磨性给我们提供了一种方法，运用具有优良的光学、电学性能和耐磨性的单层材料可以替代一个典型的多层半导体器件。使用GaN可以在没有多层技术的平台上建立一个完整的设备，以及可以集成电子、光传感器和光发射器，这将为设计设备提供一个新的范例。又因为GaN可以做得很薄且高强度，这也将加速柔性电子产品的开发。
此外，GaN材料具有优异的机械性能，可以承受较大外力作用而不破裂、损坏。更重要的是，GaN基材料具有压电效应，这种将压电极化性能和半导体特性结合在一起的材料带给我们许多前所未有的性能。这些性质引起人们这个新兴领域的研究兴趣。这给在外部机械作用下控制柔性设备提供了许多新的方法操纵电荷载流子传导、产生、复合以及分离。但是，由于GaN生长工艺 和器件工艺水平的制约，使得基于GaN材料的柔性电子学发展缓慢。为了实现柔性GaN材料，人们从不同途径进行了探索：常见的一种方法是激光剥离蓝宝石上生长GaN材料，这种方法的主要缺点是剥离容易损坏GaN薄膜、转移的薄膜缺陷密度高、面积受限；另一种方法是离子注入到GaN体材料内，通过smart-cut这类键合转移的方式，但是这种方法的主要缺点是GaN薄膜难以被剥离、表面不平整、缺陷密度高等。
发明内容
本发明所要解决的技术问题是，提供一种简单且成本较低的柔性薄膜的制造方法。
为了解决上述问题，本发明提供了一种柔性薄膜的制造方法，包括如下步骤：提供衬底，所述衬底包括一埋层和其表面的单晶层；在所述衬底的单晶层表面外延一晶体薄膜；形成从所述晶体薄膜表面至所述埋层表面的通孔；通过所述通孔对所述埋层进行选择性腐蚀，使所述晶体薄膜悬空；在所述晶体薄膜的表面贴敷一聚合物载体层；将所述晶体薄膜和所述聚合物载体层从所述衬底表面揭去。
可选的，所述埋层的材料为氧化物；所述单晶层材料为Si，晶向为(111)；所述晶体薄膜的材料为III-N族半导体材料，选自于AlN、GaN及AlGaN材料中的一种或多种。
可选的，所述晶体薄膜通过外延生长的方式形成于所述单晶层表面。
可选的，所述单晶层通过键合的方式形成于埋层表面。
可选的，所述埋层的材料为氧化硅和氮化硅中的任意一种。
可选的，所述晶体薄膜的厚度范围是200nm-1000nm。
可选的，所述聚合物载体层的材料选自于PDMS和SU8光刻胶中的任意一种。
上述方法工艺简单、成本低廉，可用于制备大面积、无缺陷的晶体柔性薄 膜。
附图说明
附图1所示是本发明一具体实施方式的实施步骤示意图；
附图2A至附图2F所示是本发明一具体实施方式的工艺流程图。
具体实施方式
下面结合附图对本发明提供的柔性薄膜的制造方法的具体实施方式做详细说明。
附图1所示是本发明一具体实施方式的实施步骤示意图，包括：步骤S10，提供衬底，所述衬底包括一埋层和其表面的单晶层；步骤S11，在所述衬底的单晶层表面外延一晶体薄膜；步骤S12，形成从所述晶体薄膜表面至所述埋层表面的通孔；步骤S13，通过所述通孔对所述埋层进行选择性腐蚀，使所述晶体薄膜悬空；步骤S14，在所述晶体薄膜的表面贴敷一聚合物载体层；步骤S15，将所述晶体薄膜和所述聚合物载体层从所述衬底表面揭去。
附图2A所示，参考步骤S10，提供衬底20，所述衬底20包括一埋层202和埋层202表面的单晶层201。所述单晶层的材料选自于单晶硅、单晶GaN、单晶AlN中的任意一种，并优选为硅，晶向为(111)。所述埋层的材料为氧化物或氮化物，并优选为氧化硅和氮化硅中的任意一种。
附图2B所示，参考步骤S11，在所述衬底20的单晶层201表面外延一晶体薄膜21。所述晶体薄膜21厚度范围是200nm-1000nm，材料选自于单晶GaN和单晶AlN中的任意一种。在本具体实施方式中，所述晶体薄膜21外延在所述单晶层201的表面。本具体实施方式中，所述埋层202的材料为氧化硅和氮化硅中的任意一种。所述埋层202的材料也可以是任何一种与晶体薄膜21之间可以进行选择性腐蚀，从而能够被腐蚀除去的材料。
附图2C所示，参考步骤S12，形成从所述晶体薄膜21表面至所述埋层202表面的通孔24。所述通孔24的数目至少是一个，并优选为多个。相邻通孔24 之间的距离以选择性腐蚀液可以浸入为准。形成所述通孔24的方法可以采用光刻或者激光刻蚀等方法。通孔24将埋层202暴露出来，用于后续的选择性腐蚀。
附图2D所示，参考步骤S13，通过所述通孔24对所述埋层202进行选择性腐蚀，使所述晶体薄膜21悬空。选择性腐蚀的腐蚀液是能够选择腐蚀埋层202而避免腐蚀晶体薄膜21的。本具体实施方式中，所述埋层202的材料为氧化硅和氮化硅中的任意一种，所述晶体薄膜21的材料选自于单晶硅、单晶GaN、单晶AlN中的任意一种，则选择性腐蚀液可以采用氢氟酸或者氢氟酸缓冲液。腐蚀后晶体薄膜21悬空并贴敷在衬底20表面。
附图2E所示，参考步骤S14，在所述晶体薄膜21的表面贴敷一聚合物载体层26。所述聚合物载体层26的材料选自于PDMS和SU8光刻胶中的任意一种，并采用粘帖或者涂覆的方式贴敷在晶体薄膜21的表面。
附图2F所示，参考步骤S15，将所述晶体薄膜21和所述聚合物载体层26从所述衬底20表面揭去。PDMS和SU8光刻胶材料与晶体材料的吸附性很强，因此可以将晶体薄膜21从衬底20表面分离开。形成的晶体薄膜21与聚合物载体26的复合膜可以被弯曲、拉伸、折叠以及扭曲等操作。
上述方法工艺简单、成本低廉，可用于制备大面积、无缺陷的晶体柔性薄膜。
以下给出一实施例对上述具体实施方式做具体说明。实施例的工艺参数仅用于举例说明，不用于限定本发明的任何内容。
第一步，采用顶层硅和支撑衬底都是Si(111)的SOI衬底。采用MOCVD外延单晶GaN基薄膜外延层，形成单晶GaN/HT-AlN/LT-AlN/Si的结构。外延步骤包括：1.在750℃、60mbar条件下，生长20nm的LT-AlN成核层；2.在1080℃、50mbar条件下，生长160nm的HT-AlN缓冲层；3.在1050℃、200mbar条件下，生长400nm的单晶GaN层。
第二步，采用光刻定义腐蚀窗口，ICP刻蚀掉氮化物外延层，RIE刻蚀掉 顶层硅。
第三步，采用氢氟酸腐蚀掉SOI衬底的埋氧层，使外延层与硅衬底虚接触。
第四步，涂覆PDMS与外延层表面紧密接触接触，并从而将外延层转移到PDMS上。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (8)

  1. 一种柔性薄膜的制造方法，其特征在于，包括如下步骤：
    提供衬底，所述衬底包括一埋层和其表面的单晶层；
    在所述衬底的单晶层表面外延一晶体薄膜；
    形成从所述晶体薄膜表面至所述埋层表面的通孔；
    通过所述通孔对所述埋层进行选择性腐蚀，使所述晶体薄膜悬空；
    在所述晶体薄膜的表面贴敷一聚合物载体层；
    将所述晶体薄膜和所述聚合物载体层从所述衬底表面揭去。
  2. 根据权利要求1所述的方法，其特征在于，所述埋层的材料为氧化物或氮化物；所述单晶层材料为Si，晶向为(111)；所述晶体薄膜的材料为III-N族半导体材料。
  3. 根据权利要求2所述的方法，其特征在于，所述晶体薄膜的材料选自于AlN、GaN及AlGaN材料中的一种或多种。
  4. 根据权利要求2所述的方法，其特征在于，所述晶体薄膜通过外延生长的方式形成于所述单晶层表面。
  5. 根据权利要求2所述的方法，其特征在于，所述单晶层通过键合的方式形成于埋层表面。
  6. 根据权利要求2所述的方法，其特征在于，所述埋层的材料为氧化硅和氮化硅中的任意一种。
  7. 根据权利要求1所述的方法，其特征在于，所述晶体薄膜的厚度范围是200nm-1000nm。
  8. 根据权利要求1所述的方法，其特征在于，所述聚合物载体层的材料选自于PDMS和SU8光刻胶中的任意一种。
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