WO2018086325A1 - 阵列基板、显示装置及其驱动方法 - Google Patents
阵列基板、显示装置及其驱动方法 Download PDFInfo
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- WO2018086325A1 WO2018086325A1 PCT/CN2017/084109 CN2017084109W WO2018086325A1 WO 2018086325 A1 WO2018086325 A1 WO 2018086325A1 CN 2017084109 W CN2017084109 W CN 2017084109W WO 2018086325 A1 WO2018086325 A1 WO 2018086325A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
Definitions
- At least one embodiment of the present disclosure is directed to an array substrate, a display device, and a method of driving the same.
- TFT-LCD Thin Film Transistor Liquid Crystal Display
- the picture quality still needs to be continuously improved to meet the demanding needs of consumers.
- the usual wide viewing angle technologies include Fringe Field Switching (FFS) and Advanced-Super Dimensional Switching (ADS).
- At least one embodiment of the present disclosure is directed to an array substrate, a display device, and a driving method thereof, which can prevent a gate signal from being delayed due to an influence of a gate line overlap on a gate signal at an instant of a gate signal transition.
- At least one embodiment of the present disclosure provides an array substrate, including:
- each of the gate line overlapping portions having a gate line perpendicular to the substrate substrate and a corresponding gate line thereof Overlapping part;
- a driver electrically connected to the plurality of gate line overlapping portions and configured to change at least one of a gate line corresponding to the overlap portion of the gate line from an on potential to an off potential and from an off potential to an on potential a timing of causing the gate line overlap portion to be in a floating state or to make a potential of the gate line overlap portion equal to a changed potential of a gate line corresponding thereto, the changed potential including the turn-on potential
- the off potential that changes to the off potential or the on potential that changes from the off potential to the on potential.
- At least one embodiment of the present disclosure also provides a display device including an embodiment in accordance with the present disclosure.
- Array substrate as described.
- At least one embodiment of the present disclosure further provides a driving method for a display device according to an embodiment of the present disclosure, including:
- the off potential changes to the turn-on potential of the turn-on potential.
- 1 is a schematic view of an array substrate
- FIG. 2 is a schematic diagram showing the arrangement of a portion of the array substrate in which the common electrode covers the gate line generates gate delay and light leakage;
- FIG 3 is a schematic diagram showing an ideal state of a signal input to a gate line and a signal input to a common electrode (corresponding to a case where the common electrode resistance is infinite);
- FIG. 4 is a schematic diagram of a signal input to a gate line and a signal input to a common electrode (corresponding to a case where the common electrode resistance is small);
- FIG. 5 is a schematic diagram of a signal input to a gate line and a signal input to a common electrode (corresponding to a case where the common electrode resistance is high);
- Figure 6 is a schematic diagram of gate signal delay
- FIG. 7 is a schematic diagram of an array substrate according to an embodiment of the present disclosure.
- FIG. 8 is a schematic diagram showing a partial structure of a display area of an array substrate according to an embodiment of the present disclosure.
- FIG. 9 is a schematic diagram showing a partial structure of a row of sub-pixels of a display area of an array substrate according to an embodiment of the present disclosure.
- FIG. 10 is a schematic diagram of another array substrate according to an embodiment of the present disclosure.
- FIG. 11 is a schematic diagram of a signal applied to a gate line overlapping portion and a gate line according to an embodiment of the present disclosure
- FIG. 12 is a schematic diagram showing voltages applied to the gate-on-phase and the gate line before and after the gate is turned on in FIG.
- FIG. 13 is a schematic diagram of another signal applied to a gate line overlapping portion and a gate line according to an embodiment of the present disclosure
- FIG. 14 is a schematic diagram showing voltages applied to a gate-on-phase and a gate line before and after the gate is turned on in FIG. 13;
- FIG. 15 is a schematic diagram of an array substrate according to another embodiment of the present disclosure.
- FIG. 16 is a schematic diagram of a driving method according to another embodiment of the present disclosure.
- an electric field formed between a pixel electrode and a common electrode is used to drive liquid crystal rotation for display.
- ADS advanced-Super Dimensional Switching
- HADS high aperture advanced super-dimensional switching
- the line 01 extends in the horizontal direction
- the data line 02 extends in the vertical direction
- the common electrode 03 includes a body portion 031 (a portion disposed in the pixel region) and a portion 032 covering the gate line, thereby causing the pixel electrode 04 (not shown in FIG. 1)
- an electric field is also formed between the portion 032 of the common electrode and the gate line, thereby increasing the aperture ratio and the liquid crystal efficiency.
- Gate line 01 is electrically coupled to the gate and is configured to input a signal to the gate to open the thin film transistor and transmit the signal to a pixel electrode that is electrically coupled to the drain of the transistor.
- the hollow region 0311 of the main portion 031 of the common electrode can be used for electrically connecting the pixel electrode to the drain of the thin film transistor that controls the pixel electrode, and the provision of the hollow region 0311 can prevent the common electrode from being electrically connected to the pixel electrode.
- the pixel electrode and the common electrode are insulated from each other.
- the body portion 031 of the common electrode is omitted in Fig. 2 for clarity of description. Due to the arrangement of the portion 032 of the common electrode covering the gate line, the signal input to the gate line causes a delay and affects the liquid crystal deflection, causing light leakage, resulting in a contrast ratio (CR) loss. Therefore, it is necessary to reduce the gate signal delay as much as possible.
- CR contrast ratio
- FIG. 1 A schematic diagram of an ideal state of a signal input to a gate line and a signal input to a common electrode is shown in FIG.
- the solid black line indicates the gate signal Sg
- the gray dotted line indicates the common electrode signal Sc.
- the timing at which the gate signal Sg changes from the off potential Vgl to the turn-on potential Vgh is also the time at which the common electrode signal Sc changes from the off potential to the on potential, and the gate signal Sg changes from the on potential Vgh to the off state.
- the common electrode signal Sc is also changed from the on potential to the off potential.
- the trip voltage ⁇ Vg of the gate signal Sg is equal to or approximately equal to the trip voltage ⁇ Vc of the common electrode signal Sc.
- the common electrode is applied with a signal, not in a floating state.
- the voltage of the common electrode is partially restored (gate turn-on phase a, the voltage of the common electrode is lowered), as shown in FIG.
- the turn-on potential Vgh, the off potential Vgl, and the trip voltage ⁇ Vg of the gate signal is also shown in FIG.
- Vgl for example, means that the gate signal is at a low level (off potential)
- Vgh for example, means that the gate signal is at a high level (on potential).
- the degree of voltage recovery of the common electrode has a large relationship with the resistance of the portion 032 of the common electrode covering the gate line.
- the degree of recovery of the voltage of the common electrode in the gate-on phase is inversely proportional to the resistance of the portion 032 of the common electrode covering the gate line at this stage. If the resistance of the portion 032 of the common electrode covering the gate line is infinitely large in the gate-on phase, that is, close to the ideal state, the voltage of the common electrode recovers (falls down) less during the gate-on phase (less decreases).
- the degree of recovery (fallback) of the voltage of the common electrode in the gate opening phase will be large (decreased more), as shown in the figure. 4 is shown. If the resistance of the portion 032 of the common electrode covering the gate line is not infinite, but a state in which the resistance is large (the resistance is between small and infinite), as shown in FIG. 5, the voltage of the common electrode is in the gate opening phase. The degree of recovery will be between Figure 3 and Figure 4.
- a state in which a voltage is applied to a portion 032 of the common electrode covering the gate line may correspond to a state in which the portion 032 of the common electrode covering the gate line has a small resistance, and the cover of the common electrode
- the state in which the voltage of the portion 032 of the gate line is not applied may correspond to a state in which the portion 032 of the common electrode covering the gate line is higher in resistance.
- the state in which the voltage is not applied to the portion 032 of the common electrode covering the gate line corresponds to the floating state (high resistance state).
- the state in which the voltage is applied to the portion 032 of the common electrode covering the gate line corresponds to a non-floating state (low resistance state, non-high resistance state).
- the portion 032 of the common electrode covering the gate line in the high resistance state will help to reduce the signal delay caused by the portion 032 of the common electrode covering the gate line, if In the gate-off phase b, the portion 032 of the common electrode covering the gate line in a low-resistance state will contribute to the recovery of the voltage of the common electrode, thereby reducing the resulting disadvantage, for example, preventing leakage due to common electrode voltage distortion.
- the voltage of the common electrode can be avoided or reduced as much as possible Problems with signal delays occur to minimize gate signal delay.
- 1H refers to, for example, the interval at which two adjacent gate lines are turned on.
- Fig. 6 shows the case where the gate signal is not delayed
- the right side of Fig. 6 shows the gate signal on the rising edge (changing from the off potential to the on potential) and the falling edge (changing from the on potential to the off) The potential) has a delay.
- the embodiment provides an array substrate, including:
- Substrate substrate 100 Substrate substrate 100,
- a plurality of gate line overlapping portions 102 are disposed on the base substrate 100 in one-to-one correspondence with the plurality of gate lines 101, and each of the gate line overlapping portions 102 is in a direction perpendicular to the substrate substrate 100 and a gate line corresponding thereto 101 has an overlapping portion 1012;
- the driver 103 is electrically connected to the plurality of gate line overlapping portions 102.
- the driver 103 is configured to cause the gate line overlap portion 102 to be in a floating state at a timing when the gate line 101 corresponding to the gate line overlapping portion 102 is changed from the on potential to the off potential, and/or the driver 103 The gate line overlapping portion 102 is placed in a floating state at a timing at which the gate line 101 corresponding to the gate line overlapping portion 102 is changed from the off potential to the on potential.
- the driver 103 is configured such that the gate line overlap portion 102 is in a floating state at the timing when the gate line 101 corresponding to the gate line overlapping portion 102 is changed from the on potential to the off potential, and the driver 103 is also configured.
- the gate line 101 corresponding to the gate line overlapping portion 102 changes from the off potential to the on potential, a signal is applied to the gate line overlapping portion 102, and the gate line overlapping portion 102 is placed in a non-floating state.
- the gate signal to jump (the transition includes changing from the on potential to the off potential, and/or from the off potential to the on potential) to avoid the gate signal from being affected by the gate line overlap portion 102. delay. It is also possible to reduce the large fluctuation of the voltage on the gate line overlapping portion 102 and adversely affect the display.
- a display area 01 and a peripheral area 02 are shown in FIG.
- the display area is configured to display and display
- the area includes a plurality of sub-pixel units 001 (see FIG. 9) arranged in an array, each of the sub-pixel units including a TFT as a switching element.
- the peripheral area 02 is disposed on at least one side of the display area 01.
- the peripheral zone 02 is configured to form a drive circuit that drives the components of the display zone to cause the display zone to be displayed.
- the array substrate further includes a plurality of gate line overlapping portion leads 104, and the plurality of gate line overlapping portions 102 are in one-to-one correspondence with the plurality of gate line overlapping portion leads 104, and each of the gate line overlapping portions 102 and The gate line overlap portion lead 104 is electrically connected thereto.
- each gate line overlap portion 102 and its corresponding gate line overlap portion lead 104 are located in the same row of sub-pixels.
- a plurality of gate line overlap portion leads 104 are electrically connected to the driver 103.
- the odd row gate line overlapping portion 102 is electrically connected to the driver 103 through the first thin film transistor 105
- the even row gate line overlapping portion 102 is electrically connected to the driver 103 through the second thin film transistor 106.
- a source 1052 and a drain 1053 of the first thin film transistor 105, and a source 1062 and a drain 1063 of the second thin film transistor 106 are shown in FIG.
- the source 1052 and the source 1062 can be electrically connected together through the source connection line 10520 so that the source signal can be commonly applied.
- the source 1052 and the source 1062 may not be electrically connected, and a signal is separately applied to the source 1052 and the source 1062.
- the drain 1053 is electrically connected to the first drain connection line 10530, and the odd-numbered gate line overlap portion lead 104 may be electrically connected to the first drain connection line 10530 via the first connection line 108 corresponding thereto.
- the drain 1063 is electrically connected to the second drain connection line 10630, and the even-numbered gate line overlap portion lead 104 can be electrically connected to the second drain connection line 10630 via the first connection line 108 corresponding thereto.
- the second drain connection line 10630 can be disposed in the same layer.
- the first gate line GT1, the second gate line GT2, ... the 2160th gate line GT2160 are shown in FIG. 7, and correspondingly, the first gate line overlap portion lead GO1 and the second line are shown in FIG.
- the gate line overlap portion lead GO2 ... the 2160th gate line overlap portion lead GO2160 which is described by way of example in the present embodiment, may also employ other numbers of gate lines and other numbers of gate line overlap portion leads.
- the array substrate of this embodiment can be used to manufacture a display device of high definition or ultra high definition.
- the nth gate line is referred to as GTn, and the nth gate line overlaps portion lead GOn. GTn corresponds to GOn. n is an integer greater than zero.
- the order of forming the gate line overlapping portion 102 and the gate line 101 is not limited.
- the gate line overlapping portion 102 may be formed first, then the gate line 101 may be formed, or the gate line 101 may be formed first, and then the gate line may be formed.
- Line overlapping portion 102 may be formed first, then the gate line 101 may be formed, or the gate line 101 may be formed first, and then the gate line may be formed.
- the plurality of gate lines 101 are electrically connected to the driving unit 107.
- the plurality of gate lines 101 may be electrically connected to the driving unit 107 through the second connection lines 109 corresponding thereto.
- the driving unit 107 can be, for example, a driving IC, and can also adopt a manner in which a gate driver is integrated on a gate driver on array (GOA).
- GOA gate driver on array
- the array substrate further includes a common electrode 1020, and the plurality of gate line overlapping portions 102 and the common electrode 1020 are insulated from each other, so that the gate line overlapping portion 102 and the common electrode 1020 can respectively apply signals.
- the common electrode 1020 may be arranged in the row direction as shown in FIG. 8, and arranged in the column direction. Of course, other arrangements may be employed.
- the row direction means, for example, a horizontal direction parallel to the paper surface
- the column direction means, for example, a vertical direction parallel to the paper surface.
- the common electrode 1020 is electrically connected to the common electrode line 1021.
- the common electrode line 1021 may be disposed in the row direction as shown in FIG. 8 or may not pass through the pixel region, but may be disposed on at least one of the common electrode 1020. side.
- the gate line overlapping portion 102 is electrically connected to the gate line overlapping portion lead 104 through the connection electrode 0102.
- the gate line overlapping portion 102, the connection electrode 0102, and the common electrode 1020 may be formed in the same layer, so that the process can be reduced.
- the gate line overlapping portion 102 is formed in the same layer as the common electrode 1020, and the pixel electrode 1120 is formed on the array substrate, and the connection electrode 0102 is formed in the same layer as the pixel electrode 1120, or the gate line overlapping portion is formed.
- connection electrode 0102 is formed in the same layer as the common electrode 1020, so that the aperture ratio can be improved and the liquid crystal efficiency can be improved.
- the two layers that require electrical connection can be electrically connected by vias through the insulating layer.
- Two sub-pixels 001 are shown in FIG.
- the pixel electrode 1120 in the pixel region is not electrically connected to the drain of the thin film transistor that controls the pixel electrode, and the hollow region of the common electrode 1020 at the pixel electrode 1120 and the drain electrical connection region is not shown.
- the pixel electrode 1120 and the common electrode 1020 are insulated from each other, and the pixel electrode and the gate line overlapping portion 102 are insulated from each other, and the pixel electrode and the common electrode are configured to form an electric field to drive the liquid crystal to rotate for display.
- the pixel electrode is located above the common electrode to form a slit electrode, but the embodiment is not limited thereto.
- the pixel electrode may be adjusted to other shapes, and the common electrode 1020 may be positioned above the pixel electrode 1120.
- each of the gate line overlapping portion leads 104 is electrically connected to a thin film transistor and connected to the odd-numbered gate line overlapping portion 102.
- the source 1052 of the first thin film transistor 105 and the source 1062 of each of the second thin film transistors 106 connected to the even-numbered gate line overlapping portion 102 are electrically connected through a source connection line 10520. Odd
- the gates of the respective first thin film transistors 105 connected to the gate line overlapping portion 102 are electrically connected together to form a gate electrode 1051; the gates of the respective second thin film transistors 106 connected to the even-numbered gate line overlapping portions 102 are electrically connected together to form a gate electrode 10; Gate 1061.
- FIG. 10 shows the TFT1 corresponding to the first row of sub-pixels, the TFT2 corresponding to the second row of sub-pixels, the TFT3 corresponding to the third row of sub-pixels, and the TFTn corresponding to the n-th row of sub-pixels.
- the drain 1053 of the odd-line first thin film transistor 105 is electrically connected to the first drain connection line 10530, and the odd-numbered gate-line overlap portion lead 104 can pass through the first connection line 108 corresponding thereto.
- a drain connection line 10530 is electrically connected.
- the drain 1063 of the even-line second thin film transistor 106 is electrically connected to the second drain connection line 10630, and the even-numbered gate-line overlap portion lead 104 can pass through the first connection line 108 and the second drain connection line 10630 corresponding thereto. Electrical connection.
- a plurality of gate line overlap portion leads 104, a plurality of gate lines 101, a gate electrode 1051, a gate electrode 1052, a source connection line 10520, a first drain connection line 10530, and a second drain connection are provided.
- Line 10630 can be placed in the same layer.
- drains 1053 of the odd-line thin film transistors 105 may not be electrically connected together.
- the drains 1063 of the even row thin film transistors 106 may also not be electrically connected together.
- the present embodiment provides an array substrate.
- the driver 103 is configured to cause the gate line 101 corresponding to the gate line overlapping portion 102 to change from the on potential to the off potential.
- the potential of the line overlapping portion 102 is equal to the off potential of the gate line 101 corresponding thereto.
- the gate signal is prevented from causing a delay in the gate signal due to the influence of the gate line overlapping portion 102 on the gate signal at the moment of the transition (change from the on potential to the off potential). It is also possible to reduce the large fluctuation of the voltage on the gate line overlapping portion 102 and adversely affect the display.
- the present embodiment provides an array substrate.
- the driver 103 is arranged to overlap the gate lines at the timing when the gate line 101 corresponding to the gate line overlapping portion 102 is changed from the off potential to the on potential.
- the potential of the portion 102 is equal to the on-potential of the gate line 101 corresponding thereto.
- This embodiment provides an array substrate which is a combination of Embodiments 3 and 4. That is, the driver 103 is disposed such that the potential of the gate line overlapping portion 102 and the off potential of the gate line 101 corresponding thereto are changed at the timing when the gate line 101 corresponding to the gate line overlapping portion 102 is changed from the on potential to the off potential. Equivalently and configured to make the potential of the gate line overlapping portion 102 equal to the on-potential of the gate line 101 corresponding thereto when the gate line 101 corresponding to the gate line overlapping portion 102 is changed from the off potential to the on potential . Thereby, the moment of the gate signal hopping prevents the gate line overlap portion 102 from affecting the gate signal to cause the gate signal delay. It is also possible to reduce the large fluctuation of the voltage on the gate line overlapping portion 102 and adversely affect the display.
- the embodiment provides a display device comprising any of the array substrates described in any one of embodiments 1 to 5.
- the display device of this embodiment can be a liquid crystal display of a mode such as an advanced-super-dimensional switching (ADS) display mode or a high aperture advanced super-dimensional switching (HADS). Device.
- ADS advanced-super-dimensional switching
- HADS high aperture advanced super-dimensional switching
- the display device may be a display device such as a liquid crystal display, and any display product or component such as a television, a digital camera, a mobile phone, a watch, a tablet, a notebook computer, a navigator, or the like including a liquid crystal display.
- a display device such as a liquid crystal display
- any display product or component such as a television, a digital camera, a mobile phone, a watch, a tablet, a notebook computer, a navigator, or the like including a liquid crystal display.
- the embodiment provides a driving method for driving a display device including the array substrate of the first embodiment or the second embodiment, including:
- the gate line overlapping portion 102 is in a floating state at the timing when the gate line 101 corresponding to the gate line overlapping portion 102 is changed from the on potential to the off potential, and/or the gate line corresponding to the gate line overlapping portion 102
- the timing at which the 101 is changed from the off potential to the on potential causes the gate line overlapping portion 102 to be in a floating state.
- the gate signal is delayed (the transition includes changing from the on potential to the off potential, or from the off potential to the on potential) to avoid the gate signal delay caused by the influence of the gate line overlap portion 102 on the gate signal. It is also possible to reduce the large fluctuation of the voltage on the gate line overlapping portion 102 and adversely affect the display.
- a square wave signal is applied to the gate line overlap portion 102.
- the square wave signal is a rectangle Square wave
- the low-level signal potential of the square wave signal is 0, the high-level signal potential is greater than 0, and the square-wave signal is a low-level signal
- the gate line overlapping portion 102 is in a floating state
- the square wave signal is high.
- the gate line overlapping portion 102 is in a voltage input state.
- the input voltage when the square wave signal is a high level signal may be the same as the voltage applied by the common electrode 1020.
- the opening interval of the adjacent two gate lines 101 is H
- the time at which each gate line 101 is at the on potential is at least 2H and is an integral multiple of H.
- the signals applied to the respective gate lines 101 and the gate line overlaps 102 may be as shown in FIG.
- a first square wave signal (DC COM1) is applied to the odd row gate line overlapping portion 102
- a second square wave signal (DC COM 2) is applied to the even row gate line overlapping portion 102, the first square wave signal and the second square wave
- the wave signals have the same frequency and opposite phases.
- the period of the first square wave signal and the second square wave signal is 2H.
- the time at which each gate line 101 is at the on potential is 4H and 5H as an example, but other values may be used, for example, 2H, 3H, 7H, and the like.
- ⁇ x indicates the time during which the gate line overlapping portion 102 is in a floating state (no signal is applied to the gate line overlapping portion 102 or the applied signal is 0), and ⁇ y indicates the time at which the gate line overlapping portion 102 is in a non-floating state (right)
- the gate line overlapping portion 102 applies a signal, or the applied signal is not 0).
- the opening interval of the adjacent two gate lines 101 is H
- the time at which each gate line 101 is at the on potential is 4H
- the period of the first square wave signal and the second square wave signal is 2H.
- the first square wave signal can be obtained by controlling the on and off of the first thin film transistor 105.
- the source electrode 1052 can be applied with a constant applied voltage, for example, EX DC 9V, by applying a repeated signal from Vgh1 to Vgl1 to the gate electrode 1051 of the first thin film transistor 105 (for example, Vgh1-Vgl1-Vgh1-Vgl1). ... Vgh1 - Vgl1, iteratively) causes the gate line overlapping portion 102 of the odd rows to apply the first square wave signal (DC COM1).
- EX DC 9V EX DC 9V
- the second square wave signal can be obtained by controlling the on and off of the second thin film transistor 106.
- the source 1062 can be applied with a constant applied voltage, for example, EX DC 9V, but is not limited thereto.
- a continuously repeated signal for example, Vgl1 - Vgh1 - Vgl1 - Vgh1 ... Vgl1 - Vgh1, repeated
- DC COM2 Two square wave signal
- the voltage applied to the source electrode 1052 and the source electrode 1062 is not limited to the illustrated case.
- the manner in which the first square wave signal and the second square wave signal are obtained is not limited to the illustrated case.
- FIG. Situation The voltage change of the gate line overlapping portion 102 before and after the gate line opening time corresponding thereto is shown in FIG. Situation.
- the gate line overlapping portion 102 is in a floating state at the timing of the gate signal hopping, and there is almost no delay of the gate signal, the setting of the gate line overlapping portion 102 to the gate signal can be substantially avoided. The negative impact.
- the voltage recovery value in the ⁇ x period is small, and the voltage recovery value of the gate line overlap portion 102 in the ⁇ x period is larger than the voltage recovery value in the ⁇ y period. a lot less.
- the voltage is fully recovered, and after the time T2, the recovered voltage is maintained. Thereby, the influence of the setting of the gate line overlapping portion 102 on the display can be reduced.
- the aperture ratio and the liquid crystal efficiency can be improved as compared with the case where the gate line overlapping portion 102 is not provided.
- the same common voltage signal is applied as compared with the gate line overlapping portion 102 being electrically connected to the common electrode, and the voltage on the gate line overlapping portion 102 can be reduced by reducing the voltage fluctuation on the gate line overlapping portion 102. Fluctuations and adverse effects on the display, such as light leakage.
- the time at which each gate line 101 is at the on potential is 5H, and the gate line 101 corresponding to the gate line overlap portion 102 is changed by the off potential.
- the gate line overlapping portion 102 is not in a floating state.
- the gate line overlapping portion 102 is in a floating state only when the gate line 101 corresponding to the gate line overlapping portion 102 is changed from the on potential to the off potential.
- the gate line overlapping portion 102 in the period from T3 to T4, since the gate line overlapping portion 102 is not in a floating state, the arrangement of the gate line overlapping portion 102 has a delay with respect to the gate signal, and at this stage, the gate line overlapping portion 102 has almost no voltage. Variety.
- the gate line overlapping portion 102 is in a floating state, the gate signal variation width ⁇ Vg00 causes the gate line overlapping portion 102 voltage fluctuation ( ⁇ Vc00) to occur, and the gate line overlapping portion 102 is in a floating state during the period from T4 to T5.
- the arrangement of the gate line overlaps 102 is no longer delayed for the gate signal. Thereby, the delay of the gate signal can be partially alleviated, and the influence on the charging problem can be reduced.
- the GOA method since the GOA pre-opens the gate signal, the delay of the gate signal in the period from T3 to T4 does not occur, and the charging problem does not occur. Or, even if there is a gate signal delay, the effect on charging is small.
- the period from T4 to T6 reference may be made to the time period T1 to T2 of FIG. 12, and details are not described herein again.
- the voltage change value ⁇ Vg00 of the gate signal may be equal to or substantially equal to the voltage change value ⁇ Vc00 of the gate line overlapping portion 102.
- the grid line The voltage change value ⁇ Vc0 of the overlapping portion 102 may be equal to or substantially equal to the voltage change value ⁇ Vg0 of the gate signal.
- both DC COM1 and DC COM2 are continuous, and the intermediate discontinuous portion is omitted.
- the high level signals of DC COM1 and DC COM2 may be larger than the turn-on potential of the gate signal, but are not limited thereto.
- the present embodiment provides a driving method, which can be used to drive a display device including the array substrate of the third embodiment, including:
- the potential of the gate line overlapping portion 102 and the off potential of the gate line 101 corresponding thereto are made equal.
- the gate signal is prevented from causing a delay in the gate signal due to the influence of the gate line overlapping portion 102 on the gate signal at the moment of the transition (change from the on potential to the off potential). It is also possible to reduce the large fluctuation of the voltage on the gate line overlapping portion 102 and adversely affect the display.
- a signal is applied to the gate line overlapping portion 102 such that the potential of the gate line overlapping portion 102 is equal to the on-potential of the gate line 101 corresponding thereto.
- the signal applied to the gate line overlapping portion 102 is adjusted so that the gate line 101 corresponding to the gate line overlapping portion 102 is turned on.
- the potential of the gate line overlapping portion 102 is equal to the off potential of the gate line 101 corresponding thereto.
- the method of the present embodiment can also be used to drive a general display device, and the corresponding effects can be achieved.
- the method of the present embodiment can also be used to drive a display device having a structure in which the gate line overlapping portion 102 is electrically connected to the common electrode to be applied with the same common voltage signal.
- the array substrate of the display device can be as shown in FIG.
- the reference numerals in Fig. 15 can be as described above.
- the embodiment provides a driving method for driving display of the array substrate including the fourth embodiment.
- Devices including:
- the potential of the gate line overlapping portion 102 is made equal to the on potential of the gate line 101 corresponding thereto.
- the gate signal hopping (changing from the off potential to the on potential) instantaneously prevents the gate line overlap portion 102 from affecting the gate signal to cause a gate signal delay. It is also possible to reduce the large fluctuation of the voltage on the gate line overlapping portion 102 and adversely affect the display.
- a signal is applied to the gate line overlapping portion 102 such that the potential of the gate line overlapping portion 102 is equal to the on-potential of the gate line 101 corresponding thereto.
- the signal applied to the gate line overlapping portion 102 is adjusted so that the gate line 101 corresponding to the gate line overlapping portion 102 is disconnected.
- the potential of the gate line overlapping portion 102 is equal to the on-potential of the gate line 101 corresponding thereto.
- the method of the present embodiment can also be used to drive a general display device, and the corresponding effects can be achieved.
- the method of the present embodiment can also be used to drive a display device of the structure: in the array substrate included in the display device, the gate line overlapping portion 102 is electrically connected to the common electrode to be applied with the same common voltage signal.
- the array substrate of the display device can also be as shown in FIG.
- the reference numerals in Fig. 15 can be as described above.
- the embodiment provides a driving method for driving a display device including the array substrate of the fifth embodiment, including:
- the potential of the gate line overlapping portion 102 is equal to the off potential of the gate line 101 corresponding thereto; and, in the gate When the gate line 101 corresponding to the line overlapping portion 102 changes from the off potential to the on potential, the potential of the gate line overlapping portion 102 is made equal to the on potential of the gate line 101 corresponding thereto.
- the gate signal is prevented from causing the gate signal delay due to the influence of the gate line overlapping portion 102 on the gate signal at the moment of the transition (change from the on potential to the off potential and from the off potential to the on potential). late. It is also possible to reduce the large fluctuation of the voltage on the gate line overlapping portion 102 and adversely affect the display.
- the signal applied to the gate line overlapping portion 102 is adjusted so that the gate line 101 corresponding to the gate line overlapping portion 102 is turned on.
- the potential of the gate line overlapping portion 102 is equal to the off potential of the gate line 101 corresponding thereto.
- the signal applied to the gate line overlapping portion 102 is adjusted so that the gate line 101 corresponding to the gate line overlapping portion 102 is disconnected.
- the potential of the gate line overlapping portion 102 is equal to the on-potential of the gate line 101 corresponding thereto.
- the gate line overlapping portion 102 signals the time change.
- the gate signal Sg and the gate line overlapping portion 102 signals Sc, a1, a2, b1, b2, c1, c2, d1, and d2 are different timings, respectively.
- the gate line overlap portion 102 may be signaled with a change in time as a whole. "c2" time (when the gate signal changes from the off potential to the on potential, Vgl ⁇ Vgh), the voltage of the gate line overlapping portion 102 is already in the Vgh state, and the gate line overlapping portion 102 and the corresponding gate line 101 are equal.
- the GTn and GO n voltages are different, and the power supply is also in a separated state; at the time c2, GTn and GOn are the same voltage, and the same power source can be used; x time, GTn and voltage For the GOn separation of Vgh, the voltage is Vgl, the voltage is in the separated state; the GTn and GOn voltages are the same at the time d1, and the same power source can be used; at the time d2, the GTn and GOn voltages are different, and the voltage is in a separated state.
- the driver 103 may employ a driving IC, but is not limited thereto.
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Abstract
Description
Claims (19)
- 一种显示装置的驱动方法,该显示装置包括阵列基板,所述阵列基板,包括:衬底基板,多条栅线,设置在所述衬底基板上;多个栅线重叠部,其设置在所述衬底基板上,与所述多条栅线一一对应,每个栅线重叠部在垂直于衬底基板的方向上和与其对应的栅线具有重叠部分;该驱动方法包括:对所述多条栅线逐行扫描以进行显示一帧画面,在与所述栅线重叠部对应的栅线由接通电位变化到断开电位和由断开电位变化到接通电位至少之一的时刻,使得所述栅线重叠部处于浮置状态或使得所述栅线重叠部的电位和与其对应的栅线的变化后的电位相等,所述变化后的电位包括由所述接通电位变化到所述断开电位的所述断开电位或由所述断开电位变化到所述接通电位的所述接通电位。
- 权利要求1所述的驱动方法,其中,在与所述栅线重叠部对应的栅线由接通电位变化到断开电位的时刻,使得所述栅线重叠部处于浮置状态,在与所述栅线重叠部对应的栅线由断开电位变化到接通电位的时刻,对所述栅线重叠部施加信号。
- 权利要求1所述的驱动方法,其中,对所述栅线重叠部施加方波信号,以使得在与所述栅线重叠部对应的栅线由接通电位变化到断开电位和由断开电位变化到接通电位至少之一的时刻,所述栅线重叠部处于浮置状态。
- 权利要求3所述的驱动方法,其中,所述方波信号为矩形方波,所述方波信号的低电平信号电位为0,高电平信号电位大于0,所述方波信号为低电平信号的情况下,所述栅线重叠部处于浮置状态,所述方波信号为高电平信号的情况下,所述栅线重叠部处于电压输入状态。
- 权利要求3或4所述的驱动方法,其中,对奇数行栅线重叠部施加第一方波信号,对偶数行栅线重叠部施加第二方波信号,所述第一方波信号和所述第二方波信号的频率相同,相位相反。
- 权利要求5所述的驱动方法,其中,相邻两条栅线的开启间隔为H,每条栅线处于接通电位的时间至少为2H且为H的整数倍,所述第一方波信号和所述第二方波信号的周期为2H。
- 权利要求1所述的驱动方法,其中,调整对所述栅线重叠部施加的信号,使得在与所述栅线重叠部对应的栅线由接通电位变化到断开电位和由断开电位变化到接通电位至少之一的时刻,所述栅线重叠部的电位和与其对应的栅线的所述变化后的电位相等。
- 权利要求7所述的驱动方法,其中,在所述栅线重叠部对应的栅线由接通电位变化到断开电位之前,调整对所述栅线重叠部施加的信号,使得在所述栅线重叠部对应的栅线由接通电位变化到断开电位的时刻,所述栅线重叠部的电位和与其对应的栅线的断开电位相等。
- 权利要求7或8所述的驱动方法,其中,在所述栅线重叠部对应的栅线由断开电位变化到接通电位之前,调整对所述栅线重叠部施加的信号,使得在所述栅线重叠部对应的栅线由断开电位变化到接通电位的时刻,所述栅线重叠部的电位和与其对应的栅线的接通电位相等。
- 一种阵列基板,包括:衬底基板,多条栅线,设置在所述衬底基板上;多个栅线重叠部,其设置在所述衬底基板上,与所述多条栅线一一对应,每个栅线重叠部在垂直于衬底基板的方向上和与其对应的栅线具有重叠部分;驱动器,与所述多个栅线重叠部电连接,并被配置来在与栅线重叠部对应的栅线由接通电位变化到断开电位和由断开电位变化到接通电位至少之一的时刻,使得所述栅线重叠部处于浮置状态或使所述栅线重叠部的电位和与其对应的栅线的变化后的电位相等,所述变化后的电位包括由所述接通电位变化到所述断开电位的所述断开电位或由所述断开电位变化到所述接通电位的所述接通电位。
- 根据权利要求10所述的阵列基板,还包括多条栅线重叠部引线,其中,所述多个栅线重叠部与所述多条栅线重叠部引线一一对应,每个所述栅线重叠部和与其对应的栅线重叠部引线电连接。
- 根据权利要求11所述的阵列基板,其中,奇数行栅线重叠部通过第一薄膜晶体管与所述驱动器电连接,偶数行栅线重叠部通过第二薄膜晶体管与所述驱动器电连接。
- 根据权利要求12所述的阵列基板,其中,所述多条栅线重叠部引线、所述多条栅线、所述第一薄膜晶体管的栅极和所述第二薄膜晶体管的栅极同层设置。
- 根据权利要求11所述的阵列基板,其中,每条所述栅线重叠部引线分别通过薄膜晶体管与所述驱动器电连接,各薄膜晶体管的源极电连接在一起,与奇数行栅线重叠部相连的各薄膜晶体管的栅极电连接在一起;与偶数行栅线重叠部相连的各薄膜晶体管的栅极电连接在一起。
- 根据权利要求14所述的阵列基板,其中,所述多条栅线重叠部引线、所述多条栅线、与奇数行栅线重叠部相连的各薄膜晶体管的栅极和与偶数行栅线重叠部相连的各薄膜晶体管的栅极同层设置。
- 根据权利要求10-15任一项所述的阵列基板,还包括公共电极,其中,所述多个栅线重叠部与所述公共电极彼此绝缘。
- 根据权利要求16所述的阵列基板,还包括公共电极线,其中,所述公共电极与所述公共电极线电连接。
- 根据权利要求10所述的阵列基板,其中,所述驱动器被配置来在与栅线重叠部对应的栅线由接通电位变化到断开电位的时刻,使得所述栅线重叠部处于浮置状态,所述驱动器还被配置来在与所述栅线重叠部对应的栅线由断开电位变化到接通电位的时刻,对所述栅线重叠部施加信号使得所述栅线重叠部处于非浮置状态。
- 一种显示装置,包括权利要求10-18任一项所述的阵列基板。
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JP2016071082A (ja) * | 2014-09-29 | 2016-05-09 | パナソニック液晶ディスプレイ株式会社 | 表示装置 |
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US20180357973A1 (en) | 2018-12-13 |
US10339885B2 (en) | 2019-07-02 |
CN108073004B (zh) | 2019-09-03 |
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