WO2018084143A1 - Electronic component package, circuit module, and method for producing electronic component package - Google Patents

Electronic component package, circuit module, and method for producing electronic component package Download PDF

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Publication number
WO2018084143A1
WO2018084143A1 PCT/JP2017/039330 JP2017039330W WO2018084143A1 WO 2018084143 A1 WO2018084143 A1 WO 2018084143A1 JP 2017039330 W JP2017039330 W JP 2017039330W WO 2018084143 A1 WO2018084143 A1 WO 2018084143A1
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WO
WIPO (PCT)
Prior art keywords
electronic component
component package
exposed
package according
resin sealing
Prior art date
Application number
PCT/JP2017/039330
Other languages
French (fr)
Japanese (ja)
Inventor
喜孝 松川
雄也 江下
Original Assignee
株式会社村田製作所
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Filing date
Publication date
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Publication of WO2018084143A1 publication Critical patent/WO2018084143A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings

Definitions

  • the present invention relates to an electronic component package in which an electronic component is sealed with a resin, a circuit module including the electronic component package, and a method for manufacturing the electronic component package.
  • an electronic component package that does not have a support substrate in which an electronic component such as a semiconductor element is sealed with a resin is known.
  • This electronic component package is mounted on, for example, a high-frequency circuit module.
  • it is required to reduce the height of electronic component packages and circuit modules.
  • Patent Document 1 discloses that a wiring layer is formed on a conductive support substrate, and the electronic component is mounted on the support substrate so as to be connected to a part of the wiring layer. After sealing the resin on the support substrate so as to cover the electronic component, the support substrate is removed to expose the wiring layer, and an external connection member (solder ball) and an insulating layer are provided under the exposed wiring layer.
  • a method of forming is disclosed.
  • an electronic component package having no support substrate can be formed.
  • Patent Document 2 discloses that one surface of a conductive support substrate is half-etched with a predetermined pattern, and then the electronic component is mounted on the support substrate using solder. After mounting one side of the support substrate with resin so as to cover this electronic component, the other side of the support substrate is polished and removed to a half-etched height position, thereby A method of forming a portion as an external connection member (conductive path) is disclosed.
  • the electronic component package formed by the manufacturing method shown in Patent Document 1 has a wiring layer between the electronic component and the external connecting member in addition to the external connecting member, and an insulating layer below the wiring layer. Therefore, there is a problem that the height of the electronic component package is increased. Further, since the wiring layer is provided, there is a problem that the wiring path becomes long and an electrical loss (wiring loss) is likely to occur.
  • the electronic component package formed by the manufacturing method shown in Patent Document 2 has a problem that the height of the electronic component package is increased because a part of the support substrate remains under the solder.
  • the present invention has been made in view of such problems, and an object thereof is to provide a low-profile electronic component package, a circuit module, and the like.
  • an electronic component package includes an electronic component having a plurality of external terminals, a plurality of conducting members connected to the plurality of external terminals, and the plurality of conducting members. And a resin sealing member that covers the electronic component, the resin sealing member has a mounting surface provided on the mounting side, and the plurality of conductive members are exposed from the mounting surface. Has an exposed part.
  • the conductive member connected to the external terminal of the electronic component is exposed from the mounting surface of the resin sealing member, the conductive member exposed on the mounting surface is used as the mounting substrate.
  • the electronic component package can be reduced in height. Further, since the conductive member connected to the external terminal has the exposed portion, it is possible to energize the electronic component with little loss from the exposed portion, and suppress electrical loss of the electronic component package. be able to.
  • the exposed portion may have a flat exposed surface.
  • the electronic component package has a flat exposed surface, when the electronic component package is mounted on the mounting substrate, the posture of the electronic component package is easily stabilized. Thereby, the electronic component package which can improve the mounting precision on a mounting board
  • the exposed portion may protrude outward from the mounting surface.
  • the electronic component package can be easily connected to the mounting board using, for example, solder.
  • the electronic component package which can improve the connection precision with a mounting board
  • the conducting member is columnar, one end surface of the conducting member is in contact with the external terminal of the electronic component, a part of the side surface of the conducting member is covered with the resin sealing member, The other end surface of the conducting member may be included in the exposed portion.
  • the other end face of the exposed conductive member can be connected to the mounting board, and the electrical connection between the external terminal and the mounting board can be established, and the electronic component package can be reduced in height.
  • the mounting surface may be flat, and the exposed surface of the exposed portion may be formed flush with the mounting surface.
  • the height of the electronic component package can be reduced.
  • the conducting member is columnar, one end surface of the conducting member is in contact with the external terminal of the electronic component, and all of the side surfaces of the conducting member are covered with the resin sealing member, The other end surface of the member may be the exposed surface.
  • the other end face of the exposed conductive member can be connected to the mounting board, and the electrical connection between the external terminal and the mounting board can be established, and the electronic component package can be reduced in height.
  • the area of the cross section at the center of the side surface of the conducting member may be larger than the areas of the cross sections of the one end face and the other end face.
  • the electrical resistance of the conducting member can be reduced.
  • a wiring layer parallel to the mounting surface does not exist between the external terminal and the exposed portion, and the conductive member may be connected in a state of being in contact with the external terminal.
  • the exposed portion may be provided at a position overlapping the external terminal when viewed from a direction perpendicular to the mounting surface.
  • the exposed portion of the conductive member and the external terminal can be connected with the shortest distance, and the electrical resistance of the conductive member can be reduced.
  • the distance between adjacent exposed portions is the same as the distance between adjacent external terminals, and the electronic component package can be reduced in size.
  • the conducting member may be formed of a metal material containing Sn.
  • an alloy layer made of Sn and Cu may be formed on the exposed portion.
  • the alloy layer is formed on the exposed portion, it is possible to prevent the solder from jumping out and spreading when the electronic component package is mounted on the mounting board.
  • the conductive member may be formed by a solder bump.
  • the resin sealing member may have a top surface and a side wall surface perpendicular to the mounting surface, and the top surface and the side wall surface may be covered with a shield film.
  • the shielding performance of the electronic component package can be improved.
  • the resin sealing member may include a shield connecting member having electrical conductivity, and the shield connecting member may be exposed at a part of the side wall surface and in contact with the shield film.
  • the connectivity between the shielding film and the ground of the mounting substrate can be improved, and the shielding performance of the electronic component package can be improved.
  • a circuit module may include the electronic component package and the mounting substrate on which the electronic component package is directly mounted.
  • the circuit module can be reduced in height by directly mounting the reduced-profile electronic component package.
  • a method for manufacturing an electronic component package comprising: connecting an electronic component to a metal foil base through a plurality of conductive members; and covering the electronic component and the plurality of conductive members. Forming a resin sealing member on the metal foil base; removing the metal foil base in contact with the resin sealing member and the conductive member; and Exposing a region in contact with the metal foil base to the surface of the resin sealing member.
  • the height of the electronic component package can be reduced by removing the metal foil substrate to form the electronic component package.
  • the conductive member may be a solder bump.
  • the conduction member of the electronic component package can be easily formed.
  • the present invention can suppress electrical loss of the electronic component package and the circuit module. Moreover, the present invention can reduce the height of the electronic component package and the circuit module.
  • FIG. 1 is a cross-sectional view schematically showing an electronic component package according to the first embodiment.
  • FIG. 2 is a cross-sectional view schematically showing the circuit module according to the first embodiment.
  • FIG. 3 is a flowchart showing a method for manufacturing the electronic component package according to the first embodiment.
  • FIG. 4A is a diagram showing a part of the method for manufacturing the electronic component package according to Embodiment 1 and a step of forming a thin film on the metal foil base.
  • FIG. 4B is a diagram illustrating a process of forming a hole in the thin film following FIG. 4A.
  • FIG. 4C is a diagram illustrating a process of performing solder printing on the holes following FIG. 4B.
  • FIG. 4A is a diagram showing a part of the method for manufacturing the electronic component package according to Embodiment 1 and a step of forming a thin film on the metal foil base.
  • FIG. 4B is a diagram illustrating a process of forming a hole in the thin
  • FIG. 4D is a diagram illustrating a process of mounting and reflowing an electronic component on the metal foil base following FIG. 4C.
  • FIG. 4E is a diagram illustrating a process of resin-sealing an electronic component following FIG. 4D.
  • FIG. 4F is a diagram illustrating a process of removing the metal foil base and the thin film by etching following FIG. 4E.
  • FIG. 5 is a cross-sectional view schematically showing an electronic component package according to the second embodiment.
  • FIG. 6 is a flowchart showing a method for manufacturing an electronic component package according to the second embodiment.
  • FIG. 7 is a cross-sectional view schematically showing an electronic component package according to the third embodiment.
  • FIG. 8 is a cross-sectional view schematically showing a circuit module according to the third embodiment.
  • FIG. 9 is a cross-sectional view schematically showing an electronic component package according to another embodiment.
  • the electronic component package according to the present embodiment is formed by resin-sealing an electronic component.
  • the electronic component package is directly mounted on a mounting substrate, and is used as, for example, a component of a high-frequency circuit module.
  • the electronic component package according to the present embodiment does not have a substrate. Therefore, the height of the electronic component package itself and the circuit module on which the electronic component package is mounted can be reduced.
  • FIG. 1 is a cross-sectional view schematically showing an electronic component package 10.
  • the electronic component package 10 includes an electronic component 20 having a plurality of external terminals 21, a plurality of conducting members 30 connected corresponding to each of the plurality of external terminals 21, a part of each of the conducting members 30, and an electronic component
  • the resin sealing member 40 which covers 20 is provided.
  • the electronic component 20 is, for example, a semiconductor element or a chip component such as a capacitor or an inductor.
  • Each of the external terminals 21 is provided on the bottom surface 20 b of the electronic component 20.
  • each of the external terminals 21 is formed inside the bottom surface 20 b of the electronic component 20.
  • the electronic component package 10 shown in FIG. 1 has two electronic components 20, the number of electronic components 20 included in the electronic component package 10 may be one or three or more. .
  • Resin sealing member 40 is formed of an insulating material such as epoxy resin, for example.
  • the resin sealing member 40 has a rectangular parallelepiped shape, a flat mounting surface 40b provided on the mounting side of the electronic component package 10, a top surface 40a opposite to the mounting surface 40b, and the top surface 40a and the mounting surface 40b.
  • the side wall surface 40c is perpendicular to.
  • the mounting surface 40b is a surface that faces the main surface 51a of the mounting substrate 51 when the electronic component package 10 is mounted on the mounting substrate 51 via solder or the like (see FIG. 2).
  • a shield film 45 made of Cu, Ag, Ni, Fe or the like is formed on the top surface 40a and the side wall surface 40c of the resin sealing member 40, for example.
  • the shield film 45 is not formed on the mounting surface 40b, and the mounting surface 40b itself is exposed.
  • Each of the conductive members 30 is directly connected to each of the external terminals 21 in a one-to-one correspondence.
  • the conducting member 30 has a cylindrical shape and has an exposed portion 31 exposed from the mounting surface 40b.
  • the exposed portion 31 of the present embodiment protrudes outside the mounting surface 40b, and has an exposed surface 31f that is parallel to and flat with the mounting surface 40b.
  • the one end face 30a of the conducting member 30 is in contact with and connected to the external terminal 21 of the electronic component 20.
  • a part of the side surface 30 c of the conducting member 30 is covered with the resin sealing member 40.
  • the other end surface 30b of the conducting member 30 is included in the exposed portion 31 and is located outside the mounting surface 40b.
  • the conducting member 30 is arranged such that the direction of the axis Z1 of the conducting member 30 is perpendicular to the mounting surface 40b, and the exposed portion 31 is a position overlapping the external terminal 21 when viewed from the direction perpendicular to the mounting surface 40b. Is provided.
  • each of the exposed portions 31 corresponds to the position where the plurality of external terminals 21 are arranged, and is arranged at the same distance (pitch) as the distance (pitch) between the adjacent external terminals 21. Further, there is no wiring layer parallel to the mounting surface 40b as shown in the prior art between the external terminal 21 and the exposed portion 31, and the conductive member 30 is directly connected in a state of being in contact with the external terminal 21. Has been.
  • the conductive member 30 is formed of a solder bump, and the center of the side surface 30c is expanded, and the area of the cross section at the center of the side surface 30c is larger than the area of each of the one end surface 30a and the other end surface 30b (area of the cross section). large.
  • the height (the length in the axis Z1 direction) of the conducting member 30 is, for example, 50 ⁇ m or more and 500 ⁇ m or less.
  • the distance by which the exposed part 31 protrudes from the mounting surface 40b is, for example, not less than 0.2 ⁇ m and not more than 10 ⁇ m.
  • the conductive member 30 includes a metal layer M1 in contact with the external terminal 21 of the electronic component 20 and an alloy layer A1 in contact with the metal layer M1.
  • the metal layer M1 is formed of a metal material containing Sn
  • the alloy layer A1 is formed of an alloy composed of Sn and Cu.
  • the alloy layer A1 is formed on the exposed portion 31 and exposed from the mounting surface 40b.
  • the thickness of the alloy layer A1 is, for example, not less than 0.1 ⁇ m and not more than 5 ⁇ m.
  • the alloy layer A1 in FIG. 1 is formed outside the mounting surface 40b, but may be formed from the exposed surface 31f to the inside of the mounting surface 40b.
  • the conductive member 30 connected to the external terminal 21 of the electronic component 20 is exposed from the mounting surface 40b of the resin sealing member 40.
  • the conductive member 30 exposed on the mounting surface 40b can be directly connected to the mounting substrate 51, and the electronic component package 10 can be reduced in height.
  • wiring loss in the electronic component package 10 can be reduced.
  • the conducting member 30 exposed on the mounting surface 40b is directly connected to the external terminal 21 instead of using a plurality of conducting members, connection loss in the electronic component package 10 can be reduced.
  • FIG. 2 is a cross-sectional view schematically showing a circuit module 50 including the electronic component package 10.
  • the circuit module 50 includes an electronic component package 10 and a mounting substrate 51 on which the electronic component package 10 is mounted.
  • An example of the mounting substrate 51 is a printed circuit board.
  • the electronic component package 10 and the connector 52 are mounted on one main surface 51 a of the mounting substrate 51.
  • An electronic component 54 different from the electronic component package 10 is mounted on the other main surface 51 b of the mounting substrate 51.
  • a coil electrode 53 for an antenna is formed on the one main surface 51a and the other main surface 51b.
  • the electronic component package 10 is connected to a wiring pattern (not shown) on the mounting substrate 51 through the solder 55.
  • the shield film 45 of the electronic component package 10 is connected to a ground pattern (not shown) on the mounting substrate 51 by a fillet-like solder 55.
  • the electronic component package 10 is mounted on the mounting substrate 51 with the mounting surface 40b of the electronic component package 10 and the one main surface 51a of the mounting substrate 51 facing each other.
  • a gap is formed between the mounting surface 40b and the one main surface 51a.
  • the present invention is not limited to this, and the mounting surface 40b and the one main surface 51a may be in contact with each other. Further, an underfill agent may be filled between the mounting surface 40b and the one main surface 51a.
  • the circuit module 50 does not have a supporting substrate for the electronic component package itself between the resin sealing member 40 and the mounting substrate 51, and the mounting surface 40 b of the resin sealing member 40 and the mounting substrate 51 are not provided. On the other hand, the main surface 51a is directly opposed. With this structure, the circuit module 50 can be reduced in height.
  • the connector 52 and the coil electrode 53 for the antenna are sealed with the resin. Without stopping, it is possible to realize the circuit module 50 in which only the necessary electronic component 20 is sealed with resin.
  • FIG. 3 is a flowchart showing a method for manufacturing the electronic component package 10.
  • the manufacturing method of the electronic component package 10 includes the step S1 of forming the thin film 62 on the metal foil base 61, the step S2 of forming the hole 63 in the thin film 62, the solder printing step S3, and the electronic component 20 and then reflowing.
  • Step S4 resin sealing step S5, step S6 of removing the metal foil base 61 and the thin film 62 by etching, and step S7 of forming the shield film 45.
  • a thin film 62 is formed on a metal foil base 61 (S1).
  • the metal foil base 61 is a metal foil having a thickness of 40 ⁇ m to 100 ⁇ m.
  • the metal foil substrate 61 of the present embodiment is a copper foil, and is formed of a material that easily wets the solder containing Sn (contact angle with the solder is 10 ° or less).
  • the metal foil base 61 is supported by a transfer tray (not shown).
  • the thin film 62 is formed on one main surface 61a of the metal foil base 61 by, for example, vapor deposition or sputtering.
  • the thin film 62 of the present embodiment is an aluminum film having a thickness of 0.1 ⁇ m to 10 ⁇ m.
  • the material of the thin film 62 may be any material that can repel solder more than the metal foil base 61 (contact angle of 90 ° or more with the solder), and is not limited to aluminum, and may be stainless steel or resin resist. .
  • the plurality of holes 63 are formed by irradiating the thin film 62 with laser and removing the thin film 62 in the laser irradiated region.
  • the plurality of holes 63 are formed at positions corresponding to the external terminals 21 of the electronic component 20 to be mounted in step S4.
  • As the laser for example, a YAG laser or CO 2 laser is used.
  • the thin film 62 can be separated at the interface between the thin film 62 and the metal foil base 61 by adjusting the spot diameter, laser output, and the like upon laser irradiation. By separating the thin film 62 at the interface, the one main surface 61a of the metal foil base 61 in the region where the hole 63 is formed becomes flat.
  • a resist pattern for patterning the solder described later is formed by removing a predetermined region of the thin film 62 with a laser.
  • a position recognition mark is also formed on the metal foil base 61 when the laser is irradiated.
  • solder printing is performed to form solder (solder film) 64 in the plurality of holes 63 (S3).
  • solder 64 is filled in each of the holes 63 by screen printing a solder paste using a metal mask. Since the metal foil base 61 is made of a material that easily wets the solder, the printed solder paste is filled so as to fill the hole 63 while in contact with the metal foil base 61.
  • the electronic component 20 is mounted on the metal foil base 61 and reflowed (S4).
  • the electronic component 20 with the solder (solder bump) 65 is mounted so that the external terminal 21 of the electronic component 20 corresponds to the area where the solder 64 is formed.
  • the position recognition mark described above is recognized by a camera, and the solder 64 on the metal foil base 61 and the electronic component 20 are aligned.
  • Solder (solder bump) 65 is provided on each of the external terminals 21 before mounting the electronic component 20, and the electronic component 20 is temporarily fixed to the metal foil base 61 by being pressed against the solder 64.
  • the solder 65 may be provided on a region on the metal foil base 61 where the solder 64 is formed.
  • the metal foil base 61 on which the electronic component 20 is mounted is placed in a reflow furnace and heated.
  • the solders 64 and 65 melt when heated.
  • the thin film 62 on the metal foil base 61 is formed of a material that easily repels solder, and the solders 64 and 65 do not flow out to the surface of the thin film 62 but are positioned within the region where the hole 63 is formed. .
  • the electronic component 20 is self-aligned based on the solders 64 and 65 whose positions are regulated. Since the position of the hole 63 is formed by laser with high positional accuracy, the electronic component 20 is fixed on the metal foil base 61 with high positional accuracy.
  • an alloy layer A1 made of Sn and Cu is formed at the interface between the solders 64 and 65 and the metal foil base 61.
  • the alloy layer A1 is formed thinner than the thin film 62 in FIG. 4D, but may be thicker than the thin film 62, that is, may be formed closer to the electronic component 20 than the upper surface of the thin film 62.
  • the solders 64 and 65 are cooled and solidified. By melting and solidifying the solders 64 and 65, the shape of the side surface and the bottom surface of the hole 63 is transferred to the bottoms of the solders 64 and 65. Since the shape of the one main surface 61a of the metal foil base 61 is flat, the bottoms of the solders 64 and 65 are also formed flat.
  • the solders 64 and 65 have a columnar shape in which the center of the side surface 30c swells. One end surface 30 a of the solders 64 and 65 is in contact with the external terminal 21 of the electronic component 20, and the other end surface 30 b of the solders 64 and 65 is in contact with one main surface 61 a of the metal foil base 61.
  • the conductive member 30 described above is formed. Note that a region C1 in FIG. 4D is a region where the conductive member 30 and the metal foil base 61 are in contact with each other.
  • the electronic component 20 is resin-sealed (S5).
  • the electronic component 20 and the metal foil base 61 are covered with a resin material by a resin molding method using a liquid resin, a transfer molding method, or a compression molding method using a solid resin, and then the resin is cured. Thereby, the resin sealing member 40 which covers the electronic component 20 and the side surface 30c of the conduction member 30 is formed.
  • the metal foil base 61 and the thin film 62 are removed by etching (S6).
  • the metal foil base 61 is removed using an etching solution (for example, cupric chloride solution) that removes the copper material that is the metal foil base 61.
  • the thin film 62 is removed using an etching solution (for example, ferric chloride solution) that removes the aluminum material that is the thin film 62. Note that a chemical solution that does not dissolve the resin sealing member 40 is used as the etching solution.
  • the exposed portion 31 of the conductive member 30 is formed on the mounting surface 40b of the resin sealing member 40 by removing the metal foil base 61 and the thin film 62. That is, in this step, the metal foil base 61 is removed, and the region C1 of the conductive member 30 where the conductive member 30 and the metal foil base 61 are in contact with the surface (mounting surface 40b) of the resin sealing member 40. Expose.
  • the exposed portion 31 protrudes outward from the mounting surface 40b and has a flat exposed surface 31f.
  • the alloy layer A1 described above is formed on the exposed portion 31. Since the alloy layer A1 is difficult to remove with the etching solution, it is possible to suppress the elution of the conductive member 30 during the etching.
  • the shield film 45 is formed on the top surface 40a and the side wall surface 40c of the resin sealing member 40 (S7).
  • the shield film 45 is formed using, for example, a sputtering apparatus. At that time, the mounting surface 40b of the resin sealing member 40 is sputtered in a masked state.
  • the thickness of the shield film 45 is 10 ⁇ m, for example.
  • As a material of the shield film 45 for example, Cu, Ag, Ni or the like is used.
  • the shield film 45 may be formed by laminating a plurality of types of metals. Through these steps S1 to S7, the electronic component package 10 is manufactured.
  • the electronic component package 10 includes an electronic component 20 having a plurality of external terminals 21, a plurality of conducting members 30 connected to the plurality of external terminals 21, and a part of each of the plurality of conducting members 30. And the resin sealing member 40 that covers the electronic component 20, the resin sealing member 40 has a mounting surface 40b provided on the mounting side, and the plurality of conductive members 30 are exposed portions exposed from the mounting surface 40b. 31. Since the electronic component package 10 does not have a substrate, the height of the electronic component package 10 itself can be reduced. Further, since the conductive member 30 connected to the external terminal 21 of the electronic component 20 is exposed from the mounting surface 40b of the resin sealing member 40, the exposed conductive member 30 can be connected to the mounting substrate 51.
  • the height of the electronic component package 10 can be reduced.
  • the conductive member 30 connected to the external terminal 21 does not have a wiring layer as shown in the prior art, but has an exposed portion 31 exposed from the mounting surface 40b. Therefore, it becomes possible to energize the electronic component 20 from the exposed portion 31 with little loss, and the electrical loss of the electronic component package 10 can be suppressed.
  • the circuit module 50 includes the electronic component package 10 and a mounting substrate 51 on which the electronic component package 10 is mounted. Since the electronic component package 10 having a reduced height is mounted on the mounting substrate 51, the circuit module 50 can be reduced in height.
  • the method for manufacturing the electronic component package 10 covers the step of connecting the electronic component 20 to the metal foil base 61 via the plurality of conductive members 30 and covers the electronic component 20 and the plurality of conductive members 30.
  • the step of forming the resin sealing member 40 on the metal foil base 61 and the metal foil base 61 in contact with the resin sealing member 40 and the conductive member 30 are removed, and the conductive member 30 of the conductive member 30 is removed.
  • a step of exposing the region C1 where the metal foil base 61 is in contact with the surface of the resin sealing member 40 By using this manufacturing method, the electronic component package 10 with a reduced height can be formed.
  • the exposed surface 31f of the exposed portion 31 is formed flush with the mounting surface 40b.
  • FIG. 5 is a cross-sectional view schematically showing the electronic component package 10A.
  • the electronic component package 10 ⁇ / b> A covers an electronic component 20 having a plurality of external terminals 21, a plurality of conducting members 30 connected to each of the plurality of external terminals 21, a part of each of the conducting members 30 and the electronic component 20. And a resin sealing member 40.
  • the conducting member 30 has a columnar shape and has an exposed portion 31 exposed from the mounting surface 40b.
  • the exposed portion 31 of the present embodiment does not protrude from the mounting surface 40b, and the exposed surface 31f is formed flush with the mounting surface 40b.
  • the entire side surface 30c (the whole) of the conductive member 30 is covered with the resin sealing member 40, and the other end surface 30b of the conductive member 30 itself is an exposed surface 31f.
  • the exposed surface 31f being formed flush with the mounting surface 40b means that the exposed surface 31f and the mounting surface 40b are formed on the same surface, and formed substantially on the same surface. It is also included.
  • FIG. 6 is a diagram showing a flowchart of a manufacturing method of the electronic component package 10A.
  • the exposed surface 31f of the electronic component package 10 is formed by the step S6A of removing the metal foil base 61 and the thin film 62 by polishing.
  • the electronic component package 10A is polished from the opposite side of the top surface 40a, and the metal foil base 61 and the thin film 62 are removed. Thereby, the electronic component package 10A in which the exposed surface 31f and the mounting surface 40b exist on the same surface is formed. Both the exposed surface 31f and the mounting surface 40b formed by polishing are flat.
  • an alloy layer made of Sn and Cu is not formed on the exposed portion 31, but an alloy layer is included in the exposed portion 31 by forming a thick alloy layer during reflow. It is good also as a structure.
  • the conductive member 30 connected to the external terminal 21 of the electronic component 20 is exposed from the mounting surface 40b of the resin sealing member 40.
  • the exposed conductive member 30 can be directly connected to the mounting substrate 51, and the height of the electronic component package 10A can be reduced.
  • wiring loss in the electronic component package 10A can be reduced.
  • the conductive member 30 exposed on the mounting surface 40b is directly connected to the external terminal 21 instead of using a plurality of conductive members, connection loss in the electronic component package 10A can be reduced.
  • the electronic component package 10 ⁇ / b> B according to the third embodiment includes a shield connection member 46 that is connected to the shield film 45.
  • FIG. 7 is a cross-sectional view schematically showing the electronic component package 10B.
  • FIG. 8 is a cross-sectional view schematically showing a circuit module 50B on which the electronic component package 10B is mounted.
  • the resin sealing member 40 of the electronic component package 10B includes a shield connecting member 46 having electrical conductivity.
  • the side surface 46 c of the shield connection member 46 is exposed to a part of the side wall surface 40 c of the resin sealing member 40 and is in contact with the shield film 45. Further, the bottom of the shield connection member 46 is exposed to the mounting surface 40b.
  • the electronic component package 10B is mounted on the mounting substrate 51, and the shield connection member 46 is connected to a ground pattern (not shown) on the mounting substrate 51.
  • the connectivity between the shield film 45 and the ground of the mounting substrate 51 can be improved, and the shielding property of the electronic component package 10B can be improved.
  • the shield film 45 of the electronic component package 10B is not connected to the mounting substrate 51 via the fillet-like solder 55 as in the first embodiment, but is mounted via the shield connecting member 46 and the solder 47. It is connected to 51 ground patterns (not shown). Thereby, the mounting area when the electronic component package 10B is mounted on the mounting substrate 51 can be reduced, and the circuit module 50B can be reduced in size.
  • FIG. 9 is a cross-sectional view schematically showing an electronic component package 10C according to another embodiment.
  • the shield film 45 is not formed on the resin sealing member 40, and the top surface 40a and the side wall surface 40c of the resin sealing member 40 are exposed.
  • the conductive member 30 connected to the external terminal 21 of the electronic component 20 is exposed from the mounting surface 40 b of the resin sealing member 40, the exposed conductive member 30 is directly attached to the mounting substrate 51.
  • the electronic component package 10C can be reduced in height.
  • the present invention is not limited to this, and a plurality of electronic component packages 10 may be formed based on a parent substrate.
  • the steps S1 to S5 are formed with the metal foil base 61 as the parent substrate, the parent substrate is separated into pieces by dicing, and the metal foil base 61 and the like of the separated electronic component package 10 are removed by etching.
  • the electronic component package 10 may be formed.
  • the steps S1 to S6 are formed with the metal foil base 61 serving as a parent substrate, the metal foil base 61 and the like are removed by etching, and then diced into individual pieces, whereby the electronic component package 10 is formed. It may be formed.
  • the thin film 62 is separated at the interface between the thin film 62 and the metal foil base 61 when forming the hole 63 with a laser.
  • the hole 63 may be formed by digging a part of the one main surface 61a.
  • the thin film 62 may be removed by mask etching instead of using a laser.
  • step S3 can be omitted.
  • solder (solder bump) 65 having a sufficient amount of solder is provided on the electronic component 20
  • the solder is filled into the hole 63 during reflow without performing solder printing in step S 3, and the metal foil.
  • the base 61 and the electronic component 20 can be joined with the solder 65.
  • step S4 the boundary between the metal layer M1 and the alloy layer A1 is expressed in a straight line, but is not limited thereto, and the actual boundary is formed in a curved line shape. Also good.
  • the metal layer M1 and the alloy layer A1 may change in a gradation without having a clear boundary.
  • step SS4 the electronic component 20 and the metal foil base 61 may be flux cleaned.
  • the present invention can be applied to the case where the electronic component package and the circuit module are reduced in height and the electric device is reduced in size. Further, the present invention can be applied to a case where a connector, an antenna, a sensor, a MEMS, or the like cannot be sealed with a resin on a mounting board.

Abstract

This electronic component package comprises: an electronic component (20) that has a plurality of external terminals (21); a plurality of conduction members (30) that are connected to the plurality of external terminals (21); and a resin sealing member (40) that covers the electronic component (20) and a part of each one of the plurality of conduction members (30). The resin sealing member (40) has a mounting surface (40b) that is on the mounting side thereof; and the plurality of conduction members (30) have exposure parts (31) that are exposed from the mounting surface (40b).

Description

電子部品パッケージ、回路モジュール、および、電子部品パッケージの製造方法Electronic component package, circuit module, and method of manufacturing electronic component package
　本発明は、電子部品を樹脂封止した電子部品パッケージ、この電子部品パッケージを備える回路モジュール、および、電子部品パッケージの製造方法に関する。 The present invention relates to an electronic component package in which an electronic component is sealed with a resin, a circuit module including the electronic component package, and a method for manufacturing the electronic component package.
　従来、半導体素子などの電子部品を樹脂封止した支持基板を有しない電子部品パッケージが知られている。この電子部品パッケージは、例えば高周波用の回路モジュールなどに実装される。近年の電子機器の小型化に伴い、電子部品パッケージおよび回路モジュールを低背化することが求められている。 Conventionally, an electronic component package that does not have a support substrate in which an electronic component such as a semiconductor element is sealed with a resin is known. This electronic component package is mounted on, for example, a high-frequency circuit module. With recent miniaturization of electronic devices, it is required to reduce the height of electronic component packages and circuit modules.
　電子部品パッケージを製造する方法の一例として、特許文献１には、導電性を有する支持基板上に配線層を形成し、この配線層の一部と接続するように電子部品を支持基板に搭載し、この電子部品を覆うように支持基板上に樹脂を封止した後、支持基板を除去して配線層を露出させ、さらに、露出した配線層の下に外部接続部材（はんだボール）および絶縁層を形成する方法が開示されている。 As an example of a method for manufacturing an electronic component package, Patent Document 1 discloses that a wiring layer is formed on a conductive support substrate, and the electronic component is mounted on the support substrate so as to be connected to a part of the wiring layer. After sealing the resin on the support substrate so as to cover the electronic component, the support substrate is removed to expose the wiring layer, and an external connection member (solder ball) and an insulating layer are provided under the exposed wiring layer. A method of forming is disclosed.
　特許文献１に示す製造方法によれば、支持基板を有しない電子部品パッケージを形成することができる。 According to the manufacturing method shown in Patent Document 1, an electronic component package having no support substrate can be formed.
　また、電子部品パッケージを製造する方法の他の一例として、特許文献２には、導電性を有する支持基板の一方面を所定パターンでハーフエッチングした後、はんだを用いて電子部品を支持基板の一方面側に搭載し、この電子部品を覆うように支持基板の一方面を樹脂で封止した後、支持基板の他方面を、ハーフエッチングした高さ位置まで研磨除去することで、支持基板の一部を外部接続部材（導電路）として形成する方法が開示されている。 As another example of a method for manufacturing an electronic component package, Patent Document 2 discloses that one surface of a conductive support substrate is half-etched with a predetermined pattern, and then the electronic component is mounted on the support substrate using solder. After mounting one side of the support substrate with resin so as to cover this electronic component, the other side of the support substrate is polished and removed to a half-etched height position, thereby A method of forming a portion as an external connection member (conductive path) is disclosed.
　特許文献２に示す製造方法によれば、支持基板の厚みを薄くした電子部品パッケージを形成することができる。 According to the manufacturing method shown in Patent Document 2, an electronic component package in which the thickness of the support substrate is reduced can be formed.
特許第３２４７３８４号公報Japanese Patent No. 3247384 特開２００２－２６１８０号公報JP 2002-26180 A
　しかしながら、特許文献１に示す製造方法で形成される電子部品パッケージは、外部接続部材の他に、電子部品と外部接続部材との間に配線層を有し、また、配線層の下に絶縁層を有しているので、電子部品パッケージの高さが高くなるという問題がある。また、配線層を有しているため、配線経路が長くなって電気的損失（配線ロス）が発生しやすいという問題がある。 However, the electronic component package formed by the manufacturing method shown in Patent Document 1 has a wiring layer between the electronic component and the external connecting member in addition to the external connecting member, and an insulating layer below the wiring layer. Therefore, there is a problem that the height of the electronic component package is increased. Further, since the wiring layer is provided, there is a problem that the wiring path becomes long and an electrical loss (wiring loss) is likely to occur.
　また、特許文献２に示す製造方法で形成される電子部品パッケージは、はんだの下に支持基板の一部が残っているため、電子部品パッケージの高さが高くなるという問題がある。 Further, the electronic component package formed by the manufacturing method shown in Patent Document 2 has a problem that the height of the electronic component package is increased because a part of the support substrate remains under the solder.
　また、これらの電子部品パッケージを実装した回路モジュールにおいても、回路モジュールの高さが高くなるという問題がある。 Also, there is a problem that the height of the circuit module is increased even in the circuit module in which these electronic component packages are mounted.
　そこで、本発明は、このような問題点に鑑みてなされたものであり、低背化された電子部品パッケージおよび回路モジュール等を提供することを目的とする。 Therefore, the present invention has been made in view of such problems, and an object thereof is to provide a low-profile electronic component package, a circuit module, and the like.
　上記目的を達成するために、本発明の一形態に係る電子部品パッケージは、複数の外部端子を有する電子部品と、前記複数の外部端子に接続される複数の導通部材と、前記複数の導通部材のそれぞれの一部および前記電子部品を覆う樹脂封止部材とを備え、前記樹脂封止部材は、実装側に設けられた実装面を有し、前記複数の導通部材は、前記実装面から露出する露出部を有す。 In order to achieve the above object, an electronic component package according to an aspect of the present invention includes an electronic component having a plurality of external terminals, a plurality of conducting members connected to the plurality of external terminals, and the plurality of conducting members. And a resin sealing member that covers the electronic component, the resin sealing member has a mounting surface provided on the mounting side, and the plurality of conductive members are exposed from the mounting surface. Has an exposed part.
　このように、本発明の電子部品パッケージは、電子部品の外部端子に接続される導通部材が、樹脂封止部材の実装面から露出しているので、実装面に露出した導通部材を実装基板に実装することができ、電子部品パッケージを低背化することができる。また、外部端子に接続される導通部材が上記露出部を有しているので、この露出部からロスが少ない状態で電子部品に通電することが可能となり、電子部品パッケージの電気的損失を抑制することができる。 Thus, in the electronic component package of the present invention, since the conductive member connected to the external terminal of the electronic component is exposed from the mounting surface of the resin sealing member, the conductive member exposed on the mounting surface is used as the mounting substrate. The electronic component package can be reduced in height. Further, since the conductive member connected to the external terminal has the exposed portion, it is possible to energize the electronic component with little loss from the exposed portion, and suppress electrical loss of the electronic component package. be able to.
　また、前記露出部は、平坦な露出面を有していてもよい。 Further, the exposed portion may have a flat exposed surface.
　このように、電子部品パッケージが平坦な露出面を有することで、電子部品パッケージを実装基板に搭載した場合に、電子部品パッケージの姿勢が安定しやすくなる。これにより、実装基板上における実装精度を向上させることができる電子部品パッケージを提供することができる。 As described above, since the electronic component package has a flat exposed surface, when the electronic component package is mounted on the mounting substrate, the posture of the electronic component package is easily stabilized. Thereby, the electronic component package which can improve the mounting precision on a mounting board | substrate can be provided.
　また、前記露出部は、前記実装面よりも外側に突出していてもよい。 Further, the exposed portion may protrude outward from the mounting surface.
　このように、露出部が外側に突出していることで、例えば、はんだ等を用いて電子部品パッケージを実装基板に接続しやすくなる。これにより、実装基板との接続精度を向上させることができる電子部品パッケージを提供することができる。 Thus, since the exposed portion protrudes to the outside, the electronic component package can be easily connected to the mounting board using, for example, solder. Thereby, the electronic component package which can improve the connection precision with a mounting board | substrate can be provided.
　また、前記導通部材は、柱状であり、前記導通部材の一方端面は、前記電子部品の前記外部端子に当接し、前記導通部材の側面の一部は、前記樹脂封止部材で覆われ、前記導通部材の他方端面は、前記露出部に含まれていてもよい。 The conducting member is columnar, one end surface of the conducting member is in contact with the external terminal of the electronic component, a part of the side surface of the conducting member is covered with the resin sealing member, The other end surface of the conducting member may be included in the exposed portion.
　これによれば、露出した導通部材の他方端面を実装基板に接続して、外部端子と実装基板との導通をとることができ、電子部品パッケージを低背化することができる。 According to this, the other end face of the exposed conductive member can be connected to the mounting board, and the electrical connection between the external terminal and the mounting board can be established, and the electronic component package can be reduced in height.
　また、前記実装面は平坦であり、前記露出部の前記露出面は、前記実装面と面一に形成されていてもよい。 Further, the mounting surface may be flat, and the exposed surface of the exposed portion may be formed flush with the mounting surface.
　このように、導通部材の露出面を実装面と面一とすることで、電子部品パッケージを低背化することができる。 Thus, by making the exposed surface of the conductive member flush with the mounting surface, the height of the electronic component package can be reduced.
　また、前記導通部材は、柱状であり、前記導通部材の一方端面は、前記電子部品の前記外部端子に当接し、前記導通部材の側面の全部は、前記樹脂封止部材で覆われ、前記導通部材の他方端面は、前記露出面であってもよい。 The conducting member is columnar, one end surface of the conducting member is in contact with the external terminal of the electronic component, and all of the side surfaces of the conducting member are covered with the resin sealing member, The other end surface of the member may be the exposed surface.
　これによれば、露出した導通部材の他方端面を実装基板に接続して、外部端子と実装基板との導通をとることができ、電子部品パッケージを低背化することができる。 According to this, the other end face of the exposed conductive member can be connected to the mounting board, and the electrical connection between the external terminal and the mounting board can be established, and the electronic component package can be reduced in height.
　また、前記導通部材の前記側面の中央における横断面の面積は、前記一方端面および前記他方端面におけるそれぞれの横断面の面積よりも大きくてもよい。 The area of the cross section at the center of the side surface of the conducting member may be larger than the areas of the cross sections of the one end face and the other end face.
　これによれば、導通部材の電気抵抗を小さくすることができる。 According to this, the electrical resistance of the conducting member can be reduced.
　また、前記外部端子と前記露出部との間には、前記実装面に平行な配線層が存在せず、前記導通部材は、前記外部端子に当接した状態で接続されていてもよい。 Further, a wiring layer parallel to the mounting surface does not exist between the external terminal and the exposed portion, and the conductive member may be connected in a state of being in contact with the external terminal.
　これによれば、外部端子と露出部との間に配線層を有していないので、電子部品パッケージ内の配線ロスを低減することができる。 According to this, since there is no wiring layer between the external terminal and the exposed portion, wiring loss in the electronic component package can be reduced.
　また、前記露出部は、前記実装面に垂直な方向から見た場合、前記外部端子と重なる位置に設けられていてもよい。 Further, the exposed portion may be provided at a position overlapping the external terminal when viewed from a direction perpendicular to the mounting surface.
　これによれば、導通部材の露出部と外部端子とを最短距離で繋ぐことができ、導通部材の電気抵抗を小さくすることができる。また、隣り合う露出部同士の距離が、隣り合う外部端子同士の距離と同じになり、電子部品パッケージを小型化することができる。 According to this, the exposed portion of the conductive member and the external terminal can be connected with the shortest distance, and the electrical resistance of the conductive member can be reduced. In addition, the distance between adjacent exposed portions is the same as the distance between adjacent external terminals, and the electronic component package can be reduced in size.
　また、前記導通部材は、Ｓｎを含む金属材料で形成されていてもよい。 Further, the conducting member may be formed of a metal material containing Sn.
　これによれば、実装基板に実装しやすい電子部品パッケージを提供することができる。 According to this, it is possible to provide an electronic component package that can be easily mounted on a mounting board.
　また、前記露出部には、ＳｎおよびＣｕからなる合金層が形成されていてもよい。 Moreover, an alloy layer made of Sn and Cu may be formed on the exposed portion.
　このように、露出部に合金層が形成されていることで、電子部品パッケージを実装基板に実装した際に、はんだが飛び出して広がることを抑制することができる。 As described above, since the alloy layer is formed on the exposed portion, it is possible to prevent the solder from jumping out and spreading when the electronic component package is mounted on the mounting board.
　また、前記導通部材は、はんだバンプにより形成されていてもよい。 Further, the conductive member may be formed by a solder bump.
　これによれば、実装基板に実装しやすく、また、導通部材を容易に形成することができる電子部品パッケージを提供することができる。 According to this, it is possible to provide an electronic component package that can be easily mounted on a mounting substrate and can easily form a conductive member.
　また、前記樹脂封止部材は、天面、および、前記実装面に垂直な側壁面を有し、前記天面および前記側壁面は、シールド膜によって覆われていてもよい。 Further, the resin sealing member may have a top surface and a side wall surface perpendicular to the mounting surface, and the top surface and the side wall surface may be covered with a shield film.
　これによれば、電子部品パッケージのシールド性を向上させることができる。 According to this, the shielding performance of the electronic component package can be improved.
　また、前記樹脂封止部材は、導通性を有するシールド接続用部材を含み、前記シールド接続用部材は、前記側壁面の一部に露出して前記シールド膜に接していてもよい。 Further, the resin sealing member may include a shield connecting member having electrical conductivity, and the shield connecting member may be exposed at a part of the side wall surface and in contact with the shield film.
　これによれば、例えば、シールド膜と実装基板のグランドとの接続性を高め、電子部品パッケージのシールド性を向上させることができる。 According to this, for example, the connectivity between the shielding film and the ground of the mounting substrate can be improved, and the shielding performance of the electronic component package can be improved.
　また、本発明の一形態に係る回路モジュールは、上記電子部品パッケージと、前記電子部品パッケージが直接実装された前記実装基板とを備えていてもよい。 In addition, a circuit module according to an aspect of the present invention may include the electronic component package and the mounting substrate on which the electronic component package is directly mounted.
　これのように、低背化された電子部品パッケージを直接実装することで、回路モジュールを低背化することができる。 As described above, the circuit module can be reduced in height by directly mounting the reduced-profile electronic component package.
　また、本発明の一形態に係る電子部品パッケージの製造方法は、電子部品を、複数の導通部材を介して金属箔基体に接続する工程と、前記電子部品および前記複数の導通部材を覆うように、前記金属箔基体上に樹脂封止部材を形成する工程と、前記樹脂封止部材と前記導通部材とに接する前記金属箔基体を除去して、前記導通部材のうちの、前記導通部材と前記金属箔基体とが接していた領域を前記樹脂封止部材の表面に露出させる工程とを含む。 According to another aspect of the present invention, there is provided a method for manufacturing an electronic component package, comprising: connecting an electronic component to a metal foil base through a plurality of conductive members; and covering the electronic component and the plurality of conductive members. Forming a resin sealing member on the metal foil base; removing the metal foil base in contact with the resin sealing member and the conductive member; and Exposing a region in contact with the metal foil base to the surface of the resin sealing member.
　このように、金属箔基体を除去して電子部品パッケージを形成することで、電子部品パッケージを低背化することができる。 Thus, the height of the electronic component package can be reduced by removing the metal foil substrate to form the electronic component package.
　また、前記導通部材は、はんだバンプであってもよい。 Further, the conductive member may be a solder bump.
　これによれば、電子部品パッケージの導通部材を容易に形成することができる。 According to this, the conduction member of the electronic component package can be easily formed.
　本発明は、電子部品パッケージおよび回路モジュールの電気的損失を抑制することができる。また、本発明は、電子部品パッケージおよび回路モジュールを低背化することができる。 The present invention can suppress electrical loss of the electronic component package and the circuit module. Moreover, the present invention can reduce the height of the electronic component package and the circuit module.
図１は、実施の形態１に係る電子部品パッケージを模式的に示す断面図である。FIG. 1 is a cross-sectional view schematically showing an electronic component package according to the first embodiment. 図２は、実施の形態１に係る回路モジュールを模式的に示す断面図である。FIG. 2 is a cross-sectional view schematically showing the circuit module according to the first embodiment. 図３は、実施の形態１に係る電子部品パッケージの製造方法を示すフローチャートである。FIG. 3 is a flowchart showing a method for manufacturing the electronic component package according to the first embodiment. 図４Ａは、実施の形態１に係る電子部品パッケージの製造方法の一部であって、金属箔基体に薄膜を形成する工程を示す図である。FIG. 4A is a diagram showing a part of the method for manufacturing the electronic component package according to Embodiment 1 and a step of forming a thin film on the metal foil base. 図４Ｂは、図４Ａにつづき、薄膜に穴を形成する工程を示す図である。FIG. 4B is a diagram illustrating a process of forming a hole in the thin film following FIG. 4A. 図４Ｃは、図４Ｂにつづき、穴に、はんだ印刷する工程を示す図である。FIG. 4C is a diagram illustrating a process of performing solder printing on the holes following FIG. 4B. 図４Ｄは、図４Ｃにつづき、金属箔基体に電子部品を搭載し、リフローする工程を示す図である。FIG. 4D is a diagram illustrating a process of mounting and reflowing an electronic component on the metal foil base following FIG. 4C. 図４Ｅは、図４Ｄにつづき、電子部品を樹脂封止する工程を示す図である。FIG. 4E is a diagram illustrating a process of resin-sealing an electronic component following FIG. 4D. 図４Ｆは、図４Ｅにつづき、金属箔基体および薄膜をエッチングで除去する工程を示す図である。FIG. 4F is a diagram illustrating a process of removing the metal foil base and the thin film by etching following FIG. 4E. 図５は、実施の形態２に係る電子部品パッケージを模式的に示す断面図である。FIG. 5 is a cross-sectional view schematically showing an electronic component package according to the second embodiment. 図６は、実施の形態２に係る電子部品パッケージの製造方法を示すフローチャートである。FIG. 6 is a flowchart showing a method for manufacturing an electronic component package according to the second embodiment. 図７は、実施の形態３に係る電子部品パッケージを模式的に示す断面図である。FIG. 7 is a cross-sectional view schematically showing an electronic component package according to the third embodiment. 図８は、実施の形態３に係る回路モジュールを模式的に示す断面図である。FIG. 8 is a cross-sectional view schematically showing a circuit module according to the third embodiment. 図９は、その他の形態に係る電子部品パッケージを模式的に示す断面図である。FIG. 9 is a cross-sectional view schematically showing an electronic component package according to another embodiment.
　以下、本発明の実施の形態に係る電子部品パッケージ等について、図面を用いて詳細に説明する。なお、以下で説明する実施の形態は、いずれも本発明の好ましい一具体例を示すものである。以下の実施の形態で示される数値、形状、材料、構成要素、構成要素の配置位置および接続形態、ステップ、ステップの順序等は、一例であり、本発明を限定する主旨ではない。また、以下の実施の形態における構成要素のうち、本発明の最上位概念を示す独立請求項に記載されていない構成要素については、より好ましい形態を構成する任意の構成要素として説明される。 Hereinafter, electronic component packages and the like according to embodiments of the present invention will be described in detail with reference to the drawings. Each of the embodiments described below shows a preferred specific example of the present invention. Numerical values, shapes, materials, constituent elements, arrangement positions and connection forms of constituent elements, steps, order of steps, and the like shown in the following embodiments are merely examples, and are not intended to limit the present invention. In addition, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept of the present invention are described as optional constituent elements that constitute a more preferable embodiment.
　（実施の形態１）
　［１－１．電子部品パッケージの構成］
　本実施の形態に係る電子部品パッケージは、電子部品を樹脂封止することで形成される。電子部品パッケージは、実装基板に直接実装され、例えば、高周波用の回路モジュールの部品として用いられる。本実施の形態に係る電子部品パッケージは、基板を有していない。そのため、電子部品パッケージ自身、および、電子部品パッケージを実装した回路モジュールを低背化することができる。 (Embodiment 1)
[1-1. Configuration of electronic component package]
The electronic component package according to the present embodiment is formed by resin-sealing an electronic component. The electronic component package is directly mounted on a mounting substrate, and is used as, for example, a component of a high-frequency circuit module. The electronic component package according to the present embodiment does not have a substrate. Therefore, the height of the electronic component package itself and the circuit module on which the electronic component package is mounted can be reduced.
　図１は、電子部品パッケージ１０を模式的に示す断面図である。 FIG. 1 is a cross-sectional view schematically showing an electronic component package 10.
　電子部品パッケージ１０は、複数の外部端子２１を有する電子部品２０と、複数の外部端子２１のそれぞれに対応して接続される複数の導通部材３０と、導通部材３０のそれぞれの一部および電子部品２０を覆う樹脂封止部材４０とを備えている。 The electronic component package 10 includes an electronic component 20 having a plurality of external terminals 21, a plurality of conducting members 30 connected corresponding to each of the plurality of external terminals 21, a part of each of the conducting members 30, and an electronic component The resin sealing member 40 which covers 20 is provided.
　電子部品２０は、例えば、半導体素子、または、コンデンサ、インダクタなどのチップ部品である。外部端子２１のそれぞれは、電子部品２０の底面２０ｂに設けられている。例えば、電子部品２０が角状の半導体素子である場合、外部端子２１のそれぞれは、電子部品２０の底面２０ｂより内側に形成されている。図１に示す電子部品パッケージ１０は２つの電子部品２０を有しているが、電子部品パッケージ１０が有する電子部品２０の数は、１つであってもよいし３つ以上であってもよい。 The electronic component 20 is, for example, a semiconductor element or a chip component such as a capacitor or an inductor. Each of the external terminals 21 is provided on the bottom surface 20 b of the electronic component 20. For example, when the electronic component 20 is a square semiconductor element, each of the external terminals 21 is formed inside the bottom surface 20 b of the electronic component 20. Although the electronic component package 10 shown in FIG. 1 has two electronic components 20, the number of electronic components 20 included in the electronic component package 10 may be one or three or more. .
　樹脂封止部材４０は、例えば、エポキシ樹脂などの絶縁材料により形成される。樹脂封止部材４０は、直方体状であり、電子部品パッケージ１０の実装側に設けられた平坦な実装面４０ｂ、実装面４０ｂと反対側の天面４０ａ、および、天面４０ａと実装面４０ｂとに垂直な側壁面４０ｃを有している。なお、実装面４０ｂとは、電子部品パッケージ１０がはんだ等を介して実装基板５１に実装される際に、実装基板５１の主面５１ａと向き合う面である（図２参照）。 Resin sealing member 40 is formed of an insulating material such as epoxy resin, for example. The resin sealing member 40 has a rectangular parallelepiped shape, a flat mounting surface 40b provided on the mounting side of the electronic component package 10, a top surface 40a opposite to the mounting surface 40b, and the top surface 40a and the mounting surface 40b. The side wall surface 40c is perpendicular to. The mounting surface 40b is a surface that faces the main surface 51a of the mounting substrate 51 when the electronic component package 10 is mounted on the mounting substrate 51 via solder or the like (see FIG. 2).
　樹脂封止部材４０の天面４０ａおよび側壁面４０ｃには、例えば、Ｃｕ、Ａｇ、Ｎｉ、Ｆｅなどのシールド膜４５が形成されている。実装面４０ｂには、シールド膜４５は形成されておらず、実装面４０ｂそのものが露出している。 A shield film 45 made of Cu, Ag, Ni, Fe or the like is formed on the top surface 40a and the side wall surface 40c of the resin sealing member 40, for example. The shield film 45 is not formed on the mounting surface 40b, and the mounting surface 40b itself is exposed.
　導通部材３０のそれぞれは、外部端子２１のそれぞれに１対１対応で直接接続されている。導通部材３０は、円柱状であり、実装面４０ｂから露出する露出部３１を有している。本実施の形態の露出部３１は、実装面４０ｂの外側に突出しており、実装面４０ｂと平行でかつ平坦な露出面３１ｆを有している。 Each of the conductive members 30 is directly connected to each of the external terminals 21 in a one-to-one correspondence. The conducting member 30 has a cylindrical shape and has an exposed portion 31 exposed from the mounting surface 40b. The exposed portion 31 of the present embodiment protrudes outside the mounting surface 40b, and has an exposed surface 31f that is parallel to and flat with the mounting surface 40b.
　具体的には、導通部材３０の一方端面３０ａは、電子部品２０の外部端子２１に当接し、接続されている。導通部材３０の側面３０ｃの一部は、樹脂封止部材４０で覆われている。導通部材３０の他方端面３０ｂは、露出部３１に含まれ、実装面４０ｂより外側に位置している。そして、導通部材３０は、導通部材３０の軸Ｚ１方向が実装面４０ｂに垂直となるように配置され、露出部３１は、実装面４０ｂに垂直な方向から見た場合、外部端子２１と重なる位置に設けられている。すなわち、露出部３１のそれぞれは、複数の外部端子２１が配置されている位置に対応し、隣り合う外部端子２１同士の距離（ピッチ）と、同じ距離（ピッチ）で配置されている。また、外部端子２１と露出部３１との間には、従来技術に示すような実装面４０ｂに平行な配線層が存在せず、導通部材３０は、外部端子２１に当接した状態で直接接続されている。 Specifically, the one end face 30a of the conducting member 30 is in contact with and connected to the external terminal 21 of the electronic component 20. A part of the side surface 30 c of the conducting member 30 is covered with the resin sealing member 40. The other end surface 30b of the conducting member 30 is included in the exposed portion 31 and is located outside the mounting surface 40b. The conducting member 30 is arranged such that the direction of the axis Z1 of the conducting member 30 is perpendicular to the mounting surface 40b, and the exposed portion 31 is a position overlapping the external terminal 21 when viewed from the direction perpendicular to the mounting surface 40b. Is provided. That is, each of the exposed portions 31 corresponds to the position where the plurality of external terminals 21 are arranged, and is arranged at the same distance (pitch) as the distance (pitch) between the adjacent external terminals 21. Further, there is no wiring layer parallel to the mounting surface 40b as shown in the prior art between the external terminal 21 and the exposed portion 31, and the conductive member 30 is directly connected in a state of being in contact with the external terminal 21. Has been.
　導通部材３０は、はんだバンプにより形成され、側面３０ｃの中央が膨らんでおり、側面３０ｃの中央における横断面の面積は、一方端面３０ａおよび他方端面３０ｂのそれぞれの面積（横断面の面積）よりも大きい。導通部材３０の高さ（軸Ｚ１方向の長さ）は、例えば、５０μｍ以上５００μｍ以下である。露出部３１が実装面４０ｂから突出する距離は、例えば、０．２μｍ以上１０μｍ以下である。 The conductive member 30 is formed of a solder bump, and the center of the side surface 30c is expanded, and the area of the cross section at the center of the side surface 30c is larger than the area of each of the one end surface 30a and the other end surface 30b (area of the cross section). large. The height (the length in the axis Z1 direction) of the conducting member 30 is, for example, 50 μm or more and 500 μm or less. The distance by which the exposed part 31 protrudes from the mounting surface 40b is, for example, not less than 0.2 μm and not more than 10 μm.
　また、導通部材３０は、電子部品２０の外部端子２１に接する金属層Ｍ１と、金属層Ｍ１に接する合金層Ａ１とで構成される。金属層Ｍ１は、Ｓｎを含む金属材料で形成され、合金層Ａ１は、ＳｎおよびＣｕからなる合金により形成される。合金層Ａ１は、露出部３１に形成され、実装面４０ｂから露出している。合金層Ａ１の厚みは、例えば、０．１μｍ以上５μｍ以下である。なお、図１における合金層Ａ１は、実装面４０ｂよりも外側に形成されているが、露出面３１ｆから実装面４０ｂの内側にわたって形成されていてもよい。 Further, the conductive member 30 includes a metal layer M1 in contact with the external terminal 21 of the electronic component 20 and an alloy layer A1 in contact with the metal layer M1. The metal layer M1 is formed of a metal material containing Sn, and the alloy layer A1 is formed of an alloy composed of Sn and Cu. The alloy layer A1 is formed on the exposed portion 31 and exposed from the mounting surface 40b. The thickness of the alloy layer A1 is, for example, not less than 0.1 μm and not more than 5 μm. The alloy layer A1 in FIG. 1 is formed outside the mounting surface 40b, but may be formed from the exposed surface 31f to the inside of the mounting surface 40b.
　本実施の形態に係る電子部品パッケージ１０は、電子部品２０の外部端子２１に接続されている導通部材３０が、樹脂封止部材４０の実装面４０ｂから露出している。この構造によれば、実装面４０ｂに露出した導通部材３０を実装基板５１に直接接続することができ、電子部品パッケージ１０を低背化することができる。また、外部端子２１と露出部３１との間に、実装面４０ｂと平行な配線層を有していないので、電子部品パッケージ１０内の配線ロスを低減することができる。また、複数の導通部材を用いるのでなく、実装面４０ｂに露出した導通部材３０を、外部端子２１に直接接続しているので、電子部品パッケージ１０内の接続ロスを低減することができる。 In the electronic component package 10 according to the present embodiment, the conductive member 30 connected to the external terminal 21 of the electronic component 20 is exposed from the mounting surface 40b of the resin sealing member 40. According to this structure, the conductive member 30 exposed on the mounting surface 40b can be directly connected to the mounting substrate 51, and the electronic component package 10 can be reduced in height. In addition, since there is no wiring layer parallel to the mounting surface 40b between the external terminal 21 and the exposed portion 31, wiring loss in the electronic component package 10 can be reduced. Moreover, since the conducting member 30 exposed on the mounting surface 40b is directly connected to the external terminal 21 instead of using a plurality of conducting members, connection loss in the electronic component package 10 can be reduced.
　［１－２．回路モジュールの構成］
　次に、本実施の形態に係る回路モジュールについて説明する。図２は、電子部品パッケージ１０を備える回路モジュール５０を模式的に示す断面図である。 [1-2. Configuration of circuit module]
Next, the circuit module according to the present embodiment will be described. FIG. 2 is a cross-sectional view schematically showing a circuit module 50 including the electronic component package 10.
　回路モジュール５０は、電子部品パッケージ１０と、電子部品パッケージ１０が実装される実装基板５１とを有している。実装基板５１の一例は、プリント基板である。 The circuit module 50 includes an electronic component package 10 and a mounting substrate 51 on which the electronic component package 10 is mounted. An example of the mounting substrate 51 is a printed circuit board.
　図２に示すように、実装基板５１の一方主面５１ａには、電子部品パッケージ１０およびコネクタ５２が実装されている。実装基板５１の他方主面５１ｂには、電子部品パッケージ１０と異なる電子部品５４が実装されている。また、一方主面５１ａおよび他方主面５１ｂには、アンテナ用のコイル電極５３が形成されている。 As shown in FIG. 2, the electronic component package 10 and the connector 52 are mounted on one main surface 51 a of the mounting substrate 51. An electronic component 54 different from the electronic component package 10 is mounted on the other main surface 51 b of the mounting substrate 51. Further, a coil electrode 53 for an antenna is formed on the one main surface 51a and the other main surface 51b.
　電子部品パッケージ１０は、はんだ５５を介して実装基板５１上の配線パターン（図示省略）に接続される。電子部品パッケージ１０のシールド膜４５は、フィレット状のはんだ５５によって実装基板５１上のグランドパターン（図示省略）に接続される。 The electronic component package 10 is connected to a wiring pattern (not shown) on the mounting substrate 51 through the solder 55. The shield film 45 of the electronic component package 10 is connected to a ground pattern (not shown) on the mounting substrate 51 by a fillet-like solder 55.
　電子部品パッケージ１０は、電子部品パッケージ１０の実装面４０ｂと実装基板５１の一方主面５１ａとが互いに向き合った状態で、実装基板５１上に実装されている。図２では、実装面４０ｂと一方主面５１ａとの間に隙間が形成されているが、それに限られず、実装面４０ｂと一方主面５１ａとが接していてもよい。また、実装面４０ｂと一方主面５１ａとの間にアンダーフィル剤が充填されていてもよい。 The electronic component package 10 is mounted on the mounting substrate 51 with the mounting surface 40b of the electronic component package 10 and the one main surface 51a of the mounting substrate 51 facing each other. In FIG. 2, a gap is formed between the mounting surface 40b and the one main surface 51a. However, the present invention is not limited to this, and the mounting surface 40b and the one main surface 51a may be in contact with each other. Further, an underfill agent may be filled between the mounting surface 40b and the one main surface 51a.
　本実施の形態の回路モジュール５０は、樹脂封止部材４０と実装基板５１との間に、電子部品パッケージ自身の支持基板を有さず、樹脂封止部材４０の実装面４０ｂと実装基板５１の一方主面５１ａとが直接向き合った構造をしている。この構造により、回路モジュール５０を低背化することができる。 The circuit module 50 according to the present embodiment does not have a supporting substrate for the electronic component package itself between the resin sealing member 40 and the mounting substrate 51, and the mounting surface 40 b of the resin sealing member 40 and the mounting substrate 51 are not provided. On the other hand, the main surface 51a is directly opposed. With this structure, the circuit module 50 can be reduced in height.
　また、本実施の形態によれば、ＷｉＧｉｇ（登録商標）などの高周波用の回路モジュール５０にコネクタ５２やアンテナ用のコイル電極５３を有する場合であっても、コネクタ５２やコイル電極５３を樹脂封止することなく、必要な電子部品２０にだけ樹脂封止した回路モジュール５０を実現することができる。 Further, according to the present embodiment, even when the high frequency circuit module 50 such as WiGig (registered trademark) has the connector 52 and the coil electrode 53 for the antenna, the connector 52 and the coil electrode 53 are sealed with the resin. Without stopping, it is possible to realize the circuit module 50 in which only the necessary electronic component 20 is sealed with resin.
　［１－３．電子部品パッケージの製造方法］
　以下、本実施の形態の電子部品パッケージ１０の製造方法について説明する。 [1-3. Manufacturing method of electronic component package]
Hereinafter, a method for manufacturing the electronic component package 10 of the present embodiment will be described.
　図３は、電子部品パッケージ１０の製造方法を示すフローチャートである。 FIG. 3 is a flowchart showing a method for manufacturing the electronic component package 10.
　電子部品パッケージ１０の製造方法は、金属箔基体６１に薄膜６２を形成する工程Ｓ１と、薄膜６２に穴６３を形成する工程Ｓ２と、はんだ印刷工程Ｓ３と、電子部品２０を搭載した後、リフローする工程Ｓ４と、樹脂封止工程Ｓ５と、金属箔基体６１および薄膜６２をエッチングで除去する工程Ｓ６と、シールド膜４５を形成する工程Ｓ７とを含む。 The manufacturing method of the electronic component package 10 includes the step S1 of forming the thin film 62 on the metal foil base 61, the step S2 of forming the hole 63 in the thin film 62, the solder printing step S3, and the electronic component 20 and then reflowing. Step S4, resin sealing step S5, step S6 of removing the metal foil base 61 and the thin film 62 by etching, and step S7 of forming the shield film 45.
　まず、図４Ａに示すように、金属箔基体６１に薄膜６２を形成する（Ｓ１）。 First, as shown in FIG. 4A, a thin film 62 is formed on a metal foil base 61 (S1).
　金属箔基体６１は、厚さ４０μｍ～１００μｍの金属箔である。本実施の形態の金属箔基体６１は銅箔であり、Ｓｎを含有するはんだが濡れやすい材料（はんだとの接触角１０°以下）により形成されている。金属箔基体６１は、図示しない搬送用トレイに支持されている。 The metal foil base 61 is a metal foil having a thickness of 40 μm to 100 μm. The metal foil substrate 61 of the present embodiment is a copper foil, and is formed of a material that easily wets the solder containing Sn (contact angle with the solder is 10 ° or less). The metal foil base 61 is supported by a transfer tray (not shown).
　この工程では、金属箔基体６１の一方主面６１ａに、例えば蒸着またはスパッタによって、薄膜６２を形成する。本実施の形態の薄膜６２は、厚さ０．１μｍ～１０μｍのアルミニウム膜である。なお、薄膜６２の材料としては、金属箔基体６１よりも、はんだをはじきやすい材料（はんだとの接触角９０°以上）であればよく、アルミニウムに限られず、ステンレスまたは樹脂レジストであってもよい。 In this step, the thin film 62 is formed on one main surface 61a of the metal foil base 61 by, for example, vapor deposition or sputtering. The thin film 62 of the present embodiment is an aluminum film having a thickness of 0.1 μm to 10 μm. The material of the thin film 62 may be any material that can repel solder more than the metal foil base 61 (contact angle of 90 ° or more with the solder), and is not limited to aluminum, and may be stainless steel or resin resist. .
　次に、図４Ｂに示すように、薄膜６２に複数の穴６３を形成する（Ｓ２）。 Next, as shown in FIG. 4B, a plurality of holes 63 are formed in the thin film 62 (S2).
　複数の穴６３は、薄膜６２にレーザを照射し、レーザ照射した領域の薄膜６２を除去することで形成される。複数の穴６３は、工程Ｓ４にて搭載する電子部品２０の外部端子２１のそれぞれに対応する位置に形成される。レーザとしては、例えば、ＹＡＧレーザまたはＣＯ２レーザなどが用いられる。レーザ照射する際のスポット径およびレーザ出力などを調整することで、薄膜６２と金属箔基体６１との界面で、薄膜６２を分離することができる。薄膜６２を上記界面で分離することで、穴６３が形成された領域の金属箔基体６１の一方主面６１ａは平坦状となる。 The plurality of holes 63 are formed by irradiating the thin film 62 with laser and removing the thin film 62 in the laser irradiated region. The plurality of holes 63 are formed at positions corresponding to the external terminals 21 of the electronic component 20 to be mounted in step S4. As the laser, for example, a YAG laser or CO 2 laser is used. The thin film 62 can be separated at the interface between the thin film 62 and the metal foil base 61 by adjusting the spot diameter, laser output, and the like upon laser irradiation. By separating the thin film 62 at the interface, the one main surface 61a of the metal foil base 61 in the region where the hole 63 is formed becomes flat.
　すなわち、この工程では、薄膜６２の所定領域をレーザで除去することで、後述するはんだをパターニングするためのレジストパターンを形成している。なお、この工程では、レーザを照射する際に、金属箔基体６１に位置認識マークも形成する。 That is, in this step, a resist pattern for patterning the solder described later is formed by removing a predetermined region of the thin film 62 with a laser. In this step, a position recognition mark is also formed on the metal foil base 61 when the laser is irradiated.
　次に、図４Ｃに示すように、はんだ印刷を行って、複数の穴６３にはんだ（はんだ膜）６４を形成する（Ｓ３）。 Next, as shown in FIG. 4C, solder printing is performed to form solder (solder film) 64 in the plurality of holes 63 (S3).
　具体的には、メタルマスクを用いてはんだペーストをスクリーン印刷することで、穴６３のそれぞれにはんだ６４を充填する。金属箔基体６１は、はんだが濡れやすい材料によって形成されているので、印刷されたはんだペーストは、金属箔基体６１に接しながら穴６３を満たすように充填される。 Specifically, solder 64 is filled in each of the holes 63 by screen printing a solder paste using a metal mask. Since the metal foil base 61 is made of a material that easily wets the solder, the printed solder paste is filled so as to fill the hole 63 while in contact with the metal foil base 61.
　次に、図４Ｄに示すように、金属箔基体６１上に電子部品２０を搭載し、リフローする（Ｓ４）。 Next, as shown in FIG. 4D, the electronic component 20 is mounted on the metal foil base 61 and reflowed (S4).
　この工程では、まず、はんだ６４が形成された領域に、電子部品２０の外部端子２１が対応するように、はんだ（はんだバンプ）６５付きの電子部品２０を搭載する。実装機を用いて電子部品２０を搭載する場合は、前述した位置認識マークをカメラで認識して、金属箔基体６１上のはんだ６４と電子部品２０との位置合わせを行う。はんだ（はんだバンプ）６５は、電子部品２０を搭載する前の外部端子２１のそれぞれに設けられ、電子部品２０は、はんだ６４に押し付けられることで金属箔基体６１に仮固定される。なお、はんだ６５を電子部品２０の外部端子２１に設けるのでなく、金属箔基体６１上のはんだ６４が形成された領域に設けてもよい。 In this step, first, the electronic component 20 with the solder (solder bump) 65 is mounted so that the external terminal 21 of the electronic component 20 corresponds to the area where the solder 64 is formed. When the electronic component 20 is mounted using a mounting machine, the position recognition mark described above is recognized by a camera, and the solder 64 on the metal foil base 61 and the electronic component 20 are aligned. Solder (solder bump) 65 is provided on each of the external terminals 21 before mounting the electronic component 20, and the electronic component 20 is temporarily fixed to the metal foil base 61 by being pressed against the solder 64. Instead of providing the solder 65 on the external terminal 21 of the electronic component 20, the solder 65 may be provided on a region on the metal foil base 61 where the solder 64 is formed.
　次に、電子部品２０が搭載された金属箔基体６１をリフロー炉に入れて加熱する。はんだ６４、６５（６４および６５）は、加熱されることで溶融する。金属箔基体６１上の薄膜６２は、はんだをはじきやすい材料によって形成されており、はんだ６４、６５は薄膜６２の表面に流れ出さずに、穴６３が形成されている領域内に位置規制される。電子部品２０は、位置規制されたはんだ６４、６５を基にセルフアライメントされる。穴６３の位置は、レーザによって位置精度よく形成されているので、電子部品２０は、金属箔基体６１上に位置精度よく固定される。 Next, the metal foil base 61 on which the electronic component 20 is mounted is placed in a reflow furnace and heated. The solders 64 and 65 (64 and 65) melt when heated. The thin film 62 on the metal foil base 61 is formed of a material that easily repels solder, and the solders 64 and 65 do not flow out to the surface of the thin film 62 but are positioned within the region where the hole 63 is formed. . The electronic component 20 is self-aligned based on the solders 64 and 65 whose positions are regulated. Since the position of the hole 63 is formed by laser with high positional accuracy, the electronic component 20 is fixed on the metal foil base 61 with high positional accuracy.
　また、はんだ６４、６５を溶融することで、はんだ６４、６５と金属箔基体６１との界面に、ＳｎおよびＣｕからなる合金層Ａ１が形成される。合金層Ａ１は、図４Ｄにおいて薄膜６２の厚さよりも薄く形成されているが、薄膜６２の厚さよりも厚く、すなわち薄膜６２の上面よりも電子部品２０側に形成されていてもよい。 Also, by melting the solders 64 and 65, an alloy layer A1 made of Sn and Cu is formed at the interface between the solders 64 and 65 and the metal foil base 61. The alloy layer A1 is formed thinner than the thin film 62 in FIG. 4D, but may be thicker than the thin film 62, that is, may be formed closer to the electronic component 20 than the upper surface of the thin film 62.
　リフロー後、はんだ６４、６５は冷却固化される。はんだ６４、６５を溶融した後、固化することで、はんだ６４、６５の底部には、穴６３の側面および底面の形状が転写される。金属箔基体６１の一方主面６１ａの形状は平坦状なので、はんだ６４、６５の底部も平坦状に形成される。はんだ６４、６５は、側面３０ｃの中央が膨らんだ円柱状の形状をしている。はんだ６４、６５の一方端面３０ａは、電子部品２０の外部端子２１に当接し、はんだ６４、６５の他方端面３０ｂは、金属箔基体６１の一方主面６１ａに当接している。このように、はんだ６４、６５を溶融した後、固化することで、前述した導通部材３０が形成される。なお、図４Ｄにおける領域Ｃ１は、導通部材３０と金属箔基体６１とが接する領域である。 After reflow, the solders 64 and 65 are cooled and solidified. By melting and solidifying the solders 64 and 65, the shape of the side surface and the bottom surface of the hole 63 is transferred to the bottoms of the solders 64 and 65. Since the shape of the one main surface 61a of the metal foil base 61 is flat, the bottoms of the solders 64 and 65 are also formed flat. The solders 64 and 65 have a columnar shape in which the center of the side surface 30c swells. One end surface 30 a of the solders 64 and 65 is in contact with the external terminal 21 of the electronic component 20, and the other end surface 30 b of the solders 64 and 65 is in contact with one main surface 61 a of the metal foil base 61. Thus, after the solders 64 and 65 are melted and solidified, the conductive member 30 described above is formed. Note that a region C1 in FIG. 4D is a region where the conductive member 30 and the metal foil base 61 are in contact with each other.
　次に、図４Ｅに示すように、電子部品２０を樹脂封止する（Ｓ５）。 Next, as shown in FIG. 4E, the electronic component 20 is resin-sealed (S5).
　この工程では、液状樹脂を用いた樹脂モールド法、トランスファーモールド法または、固形樹脂を用いたコンプレッションモールド法などによって、電子部品２０および金属箔基体６１を樹脂材料で覆った後、樹脂硬化する。これにより、電子部品２０および導通部材３０の側面３０ｃを覆う樹脂封止部材４０を形成する。 In this step, the electronic component 20 and the metal foil base 61 are covered with a resin material by a resin molding method using a liquid resin, a transfer molding method, or a compression molding method using a solid resin, and then the resin is cured. Thereby, the resin sealing member 40 which covers the electronic component 20 and the side surface 30c of the conduction member 30 is formed.
　次に、図４Ｆに示すように、金属箔基体６１および薄膜６２をエッチングで除去する（Ｓ６）。 Next, as shown in FIG. 4F, the metal foil base 61 and the thin film 62 are removed by etching (S6).
　まず、金属箔基体６１である銅材料を除去するエッチング液（例えば塩化第二銅溶液）を用いて、金属箔基体６１を除去する。次に、薄膜６２であるアルミニウム材料を除去するエッチング液（例えば塩化第二鉄溶液）を用いて、薄膜６２を除去する。なお、エッチング液としては、樹脂封止部材４０を溶かさない薬液が用いられる。 First, the metal foil base 61 is removed using an etching solution (for example, cupric chloride solution) that removes the copper material that is the metal foil base 61. Next, the thin film 62 is removed using an etching solution (for example, ferric chloride solution) that removes the aluminum material that is the thin film 62. Note that a chemical solution that does not dissolve the resin sealing member 40 is used as the etching solution.
　金属箔基体６１および薄膜６２が除去されることで、樹脂封止部材４０の実装面４０ｂに導通部材３０の露出部３１が形成される。すなわち、この工程で金属箔基体６１を除去して、導通部材３０のうちの、導通部材３０と金属箔基体６１とが接していた領域Ｃ１を樹脂封止部材４０の表面（実装面４０ｂ）に露出させる。 The exposed portion 31 of the conductive member 30 is formed on the mounting surface 40b of the resin sealing member 40 by removing the metal foil base 61 and the thin film 62. That is, in this step, the metal foil base 61 is removed, and the region C1 of the conductive member 30 where the conductive member 30 and the metal foil base 61 are in contact with the surface (mounting surface 40b) of the resin sealing member 40. Expose.
　露出部３１は、実装面４０ｂよりも外側に突出しており、平坦な露出面３１ｆを有している。なお、前述した合金層Ａ１は、露出部３１に形成されている。合金層Ａ１はエッチング液で除去されにくいので、エッチング時において導通部材３０が溶出することを抑制することができる。 The exposed portion 31 protrudes outward from the mounting surface 40b and has a flat exposed surface 31f. The alloy layer A1 described above is formed on the exposed portion 31. Since the alloy layer A1 is difficult to remove with the etching solution, it is possible to suppress the elution of the conductive member 30 during the etching.
　次に、樹脂封止部材４０の天面４０ａおよび側壁面４０ｃにシールド膜４５を形成する（Ｓ７）。 Next, the shield film 45 is formed on the top surface 40a and the side wall surface 40c of the resin sealing member 40 (S7).
　シールド膜４５は、例えば、スパッタ装置を用いて成膜される。その際、樹脂封止部材４０の実装面４０ｂは、マスキングされた状態でスパッタリングされる。シールド膜４５の厚みは、例えば１０μｍである。シールド膜４５の材料としては、例えば、Ｃｕ、Ａｇ、Ｎｉなどが用いられる。シールド膜４５は、複数種類の金属を積層することで形成されてもよい。これらの工程Ｓ１～Ｓ７により、電子部品パッケージ１０が作製される。 The shield film 45 is formed using, for example, a sputtering apparatus. At that time, the mounting surface 40b of the resin sealing member 40 is sputtered in a masked state. The thickness of the shield film 45 is 10 μm, for example. As a material of the shield film 45, for example, Cu, Ag, Ni or the like is used. The shield film 45 may be formed by laminating a plurality of types of metals. Through these steps S1 to S7, the electronic component package 10 is manufactured.
　［１－４．効果等］
　本実施の形態に係る電子部品パッケージ１０は、複数の外部端子２１を有する電子部品２０と、複数の外部端子２１に接続される複数の導通部材３０と、複数の導通部材３０のそれぞれの一部および電子部品２０を覆う樹脂封止部材４０とを備え、樹脂封止部材４０は、実装側に設けられた実装面４０ｂを有し、複数の導通部材３０は、実装面４０ｂから露出する露出部３１を有する。電子部品パッケージ１０が基板を有していないので、電子部品パッケージ１０自身を低背化することができる。また、電子部品２０の外部端子２１に接続されている導通部材３０が、樹脂封止部材４０の実装面４０ｂから露出しているので、露出した導通部材３０を実装基板５１に接続することができ、電子部品パッケージ１０を低背化することができる。また、外部端子２１に接続される導通部材３０が、従来技術に示すような配線層を有せず、実装面４０ｂから露出する露出部３１を有している。そのため、露出部３１からロスが少ない状態で電子部品２０に通電することが可能となり、電子部品パッケージ１０の電気的損失を抑制することができる。 [1-4. Effect]
The electronic component package 10 according to the present embodiment includes an electronic component 20 having a plurality of external terminals 21, a plurality of conducting members 30 connected to the plurality of external terminals 21, and a part of each of the plurality of conducting members 30. And the resin sealing member 40 that covers the electronic component 20, the resin sealing member 40 has a mounting surface 40b provided on the mounting side, and the plurality of conductive members 30 are exposed portions exposed from the mounting surface 40b. 31. Since the electronic component package 10 does not have a substrate, the height of the electronic component package 10 itself can be reduced. Further, since the conductive member 30 connected to the external terminal 21 of the electronic component 20 is exposed from the mounting surface 40b of the resin sealing member 40, the exposed conductive member 30 can be connected to the mounting substrate 51. Thus, the height of the electronic component package 10 can be reduced. Further, the conductive member 30 connected to the external terminal 21 does not have a wiring layer as shown in the prior art, but has an exposed portion 31 exposed from the mounting surface 40b. Therefore, it becomes possible to energize the electronic component 20 from the exposed portion 31 with little loss, and the electrical loss of the electronic component package 10 can be suppressed.
　本実施の形態に係る回路モジュール５０は、上記電子部品パッケージ１０と、電子部品パッケージ１０が実装された実装基板５１とを備える。実装基板５１に低背化された電子部品パッケージ１０が実装されるので、回路モジュール５０を低背化することができる。 The circuit module 50 according to the present embodiment includes the electronic component package 10 and a mounting substrate 51 on which the electronic component package 10 is mounted. Since the electronic component package 10 having a reduced height is mounted on the mounting substrate 51, the circuit module 50 can be reduced in height.
　本実施の形態に係る電子部品パッケージ１０の製造方法は、電子部品２０を、複数の導通部材３０を介して金属箔基体６１に接続する工程と、電子部品２０および複数の導通部材３０を覆うように、金属箔基体６１上に樹脂封止部材４０を形成する工程と、樹脂封止部材４０と導通部材３０とに接する金属箔基体６１を除去して、導通部材３０のうちの、導通部材３０と金属箔基体６１とが接していた領域Ｃ１を樹脂封止部材４０の表面に露出させる工程とを含む。この製造方法を用いることで、低背化した電子部品パッケージ１０を形成することができる。 The method for manufacturing the electronic component package 10 according to the present embodiment covers the step of connecting the electronic component 20 to the metal foil base 61 via the plurality of conductive members 30 and covers the electronic component 20 and the plurality of conductive members 30. In addition, the step of forming the resin sealing member 40 on the metal foil base 61 and the metal foil base 61 in contact with the resin sealing member 40 and the conductive member 30 are removed, and the conductive member 30 of the conductive member 30 is removed. And a step of exposing the region C1 where the metal foil base 61 is in contact with the surface of the resin sealing member 40. By using this manufacturing method, the electronic component package 10 with a reduced height can be formed.
　（実施の形態２）
　実施の形態２に係る電子部品パッケージ１０Ａは、露出部３１の露出面３１ｆが実装面４０ｂと面一に形成されている。 (Embodiment 2)
In the electronic component package 10A according to the second embodiment, the exposed surface 31f of the exposed portion 31 is formed flush with the mounting surface 40b.
　図５は、電子部品パッケージ１０Ａを模式的に示す断面図である。 FIG. 5 is a cross-sectional view schematically showing the electronic component package 10A.
　電子部品パッケージ１０Ａは、複数の外部端子２１を有する電子部品２０と、複数の外部端子２１のそれぞれに接続される複数の導通部材３０と、導通部材３０のそれぞれの一部および電子部品２０を覆う樹脂封止部材４０とを備えている。 The electronic component package 10 </ b> A covers an electronic component 20 having a plurality of external terminals 21, a plurality of conducting members 30 connected to each of the plurality of external terminals 21, a part of each of the conducting members 30 and the electronic component 20. And a resin sealing member 40.
　導通部材３０のそれぞれは、複数の外部端子２１のそれぞれに１対１対応で直接接続されている。導通部材３０は、円柱状の形状を有し、実装面４０ｂから露出する露出部３１を有している。本実施の形態の露出部３１は、実装面４０ｂから突出せず、露出面３１ｆが実装面４０ｂと面一に形成されている。具体的には、導通部材３０の側面３０ｃの全部（全体）は、樹脂封止部材４０で覆われ、導通部材３０の他方端面３０ｂそのものが、露出面３１ｆとなっている。なお、露出面３１ｆが実装面４０ｂに面一に形成されているとは、露出面３１ｆと実装面４０ｂとが同一面上に形成されていることを意味し、実質的に同一面上に形成されていることも含む。 Each of the conducting members 30 is directly connected to each of the plurality of external terminals 21 in a one-to-one correspondence. The conducting member 30 has a columnar shape and has an exposed portion 31 exposed from the mounting surface 40b. The exposed portion 31 of the present embodiment does not protrude from the mounting surface 40b, and the exposed surface 31f is formed flush with the mounting surface 40b. Specifically, the entire side surface 30c (the whole) of the conductive member 30 is covered with the resin sealing member 40, and the other end surface 30b of the conductive member 30 itself is an exposed surface 31f. The exposed surface 31f being formed flush with the mounting surface 40b means that the exposed surface 31f and the mounting surface 40b are formed on the same surface, and formed substantially on the same surface. It is also included.
　図６は、電子部品パッケージ１０Ａの製造方法のフローチャートを示す図である。 FIG. 6 is a diagram showing a flowchart of a manufacturing method of the electronic component package 10A.
　電子部品パッケージ１０の露出面３１ｆは、金属箔基体６１および薄膜６２を研磨で除去する工程Ｓ６Ａによって形成される。例えば、実施の形態１の図４Ｅで示す工程Ｓ５の後、電子部品パッケージ１０Ａを天面４０ａの反対側から研磨し、金属箔基体６１および薄膜６２を除去する。これにより、露出面３１ｆと実装面４０ｂとが同一面上に存在する電子部品パッケージ１０Ａを形成する。研磨により形成された露出面３１ｆおよび実装面４０ｂは、ともに平坦である。 The exposed surface 31f of the electronic component package 10 is formed by the step S6A of removing the metal foil base 61 and the thin film 62 by polishing. For example, after step S5 shown in FIG. 4E of Embodiment 1, the electronic component package 10A is polished from the opposite side of the top surface 40a, and the metal foil base 61 and the thin film 62 are removed. Thereby, the electronic component package 10A in which the exposed surface 31f and the mounting surface 40b exist on the same surface is formed. Both the exposed surface 31f and the mounting surface 40b formed by polishing are flat.
　なお、図５に示す電子部品パッケージ１０Ａでは、露出部３１にＳｎおよびＣｕからなる合金層が形成されていないが、リフロー時に合金層を厚く形成することで、露出部３１に合金層が含まれる構造としてもよい。 In the electronic component package 10A shown in FIG. 5, an alloy layer made of Sn and Cu is not formed on the exposed portion 31, but an alloy layer is included in the exposed portion 31 by forming a thick alloy layer during reflow. It is good also as a structure.
　本実施の形態に係る電子部品パッケージ１０Ａは、電子部品２０の外部端子２１に接続されている導通部材３０が、樹脂封止部材４０の実装面４０ｂから露出している。この構造によれば、露出した導通部材３０を実装基板５１に直接接続することができ、電子部品パッケージ１０Ａを低背化することができる。また、外部端子２１と露出部３１との間に、実装面４０ｂと平行な配線層を有していないので、電子部品パッケージ１０Ａ内の配線ロスを低減することができる。また、複数の導通部材を用いるのでなく、実装面４０ｂに露出した導通部材３０を、外部端子２１に直接接続しているので、電子部品パッケージ１０Ａ内の接続ロスを低減することができる。 In the electronic component package 10A according to the present embodiment, the conductive member 30 connected to the external terminal 21 of the electronic component 20 is exposed from the mounting surface 40b of the resin sealing member 40. According to this structure, the exposed conductive member 30 can be directly connected to the mounting substrate 51, and the height of the electronic component package 10A can be reduced. In addition, since there is no wiring layer parallel to the mounting surface 40b between the external terminal 21 and the exposed portion 31, wiring loss in the electronic component package 10A can be reduced. Further, since the conductive member 30 exposed on the mounting surface 40b is directly connected to the external terminal 21 instead of using a plurality of conductive members, connection loss in the electronic component package 10A can be reduced.
　（実施の形態３）
　実施の形態３に係る電子部品パッケージ１０Ｂは、シールド膜４５と接続するシールド接続用部材４６を有している。 (Embodiment 3)
The electronic component package 10 </ b> B according to the third embodiment includes a shield connection member 46 that is connected to the shield film 45.
　図７は、電子部品パッケージ１０Ｂを模式的に示す断面図である。図８は、電子部品パッケージ１０Ｂが実装された回路モジュール５０Ｂを模式的に示す断面図である。 FIG. 7 is a cross-sectional view schematically showing the electronic component package 10B. FIG. 8 is a cross-sectional view schematically showing a circuit module 50B on which the electronic component package 10B is mounted.
　図７に示すように、電子部品パッケージ１０Ｂの樹脂封止部材４０は、導通性を有するシールド接続用部材４６を含んでいる。シールド接続用部材４６の側面４６ｃは、樹脂封止部材４０の側壁面４０ｃの一部に露出して、シールド膜４５に接している。また、シールド接続用部材４６の底部は、実装面４０ｂに露出している。 As shown in FIG. 7, the resin sealing member 40 of the electronic component package 10B includes a shield connecting member 46 having electrical conductivity. The side surface 46 c of the shield connection member 46 is exposed to a part of the side wall surface 40 c of the resin sealing member 40 and is in contact with the shield film 45. Further, the bottom of the shield connection member 46 is exposed to the mounting surface 40b.
　実施の形態３では、図８に示すように、電子部品パッケージ１０Ｂを実装基板５１に実装して、シールド接続用部材４６を実装基板５１上のグランドパターン（図示省略）に接続している。これにより、シールド膜４５と実装基板５１のグランドとの接続性を高め、電子部品パッケージ１０Ｂのシールド性を向上させることができる。 In Embodiment 3, as shown in FIG. 8, the electronic component package 10B is mounted on the mounting substrate 51, and the shield connection member 46 is connected to a ground pattern (not shown) on the mounting substrate 51. Thereby, the connectivity between the shield film 45 and the ground of the mounting substrate 51 can be improved, and the shielding property of the electronic component package 10B can be improved.
　また、電子部品パッケージ１０Ｂのシールド膜４５は、実施の形態１のようにフィレット状のはんだ５５を介して実装基板５１に接続されるのでなく、シールド接続用部材４６およびはんだ４７を介して実装基板５１のグランドパターン（図示省略）に接続される。これにより、電子部品パッケージ１０Ｂを実装基板５１に実装した場合の実装面積を小さくすることができ、回路モジュール５０Ｂを小型化することができる。 Further, the shield film 45 of the electronic component package 10B is not connected to the mounting substrate 51 via the fillet-like solder 55 as in the first embodiment, but is mounted via the shield connecting member 46 and the solder 47. It is connected to 51 ground patterns (not shown). Thereby, the mounting area when the electronic component package 10B is mounted on the mounting substrate 51 can be reduced, and the circuit module 50B can be reduced in size.
　（その他の形態）
　以上、本発明に係る電子部品パッケージ１０、１０Ａ、１０Ｂについて、実施の形態１～３に基づいて説明したが、本発明は、これらの実施の形態１～３に限定されない。本発明の主旨を逸脱しない限り、当業者が思いつく各種変形を実施の形態に施したものや、実施の形態１～３における一部の構成要素を組み合わせて構築される別の形態も、本発明の範囲内に含まれる。 (Other forms)
The electronic component packages 10, 10A, and 10B according to the present invention have been described based on the first to third embodiments. However, the present invention is not limited to these first to third embodiments. Without departing from the spirit of the present invention, various modifications conceived by those skilled in the art have been made in the embodiments, and other forms constructed by combining some of the constituent elements in the first to third embodiments are also applicable to the present invention. It is included in the range.
　図９は、その他の形態に係る電子部品パッケージ１０Ｃを模式的に示す断面図である。この電子部品パッケージ１０Ｃは、樹脂封止部材４０にシールド膜４５が形成されておらず、樹脂封止部材４０の天面４０ａおよび側壁面４０ｃが露出している。この電子部品パッケージ１０Ｃにおいても、電子部品２０の外部端子２１に接続する導通部材３０が、樹脂封止部材４０の実装面４０ｂから露出しているので、露出した導通部材３０を実装基板５１に直接接続することができ、電子部品パッケージ１０Ｃを低背化することができる。 FIG. 9 is a cross-sectional view schematically showing an electronic component package 10C according to another embodiment. In the electronic component package 10C, the shield film 45 is not formed on the resin sealing member 40, and the top surface 40a and the side wall surface 40c of the resin sealing member 40 are exposed. Also in this electronic component package 10 </ b> C, since the conductive member 30 connected to the external terminal 21 of the electronic component 20 is exposed from the mounting surface 40 b of the resin sealing member 40, the exposed conductive member 30 is directly attached to the mounting substrate 51. The electronic component package 10C can be reduced in height.
　また、実施の形態１では、１つの電子部品パッケージ１０を形成する例について説明したが、それに限られず、親基板をもとに複数の電子部品パッケージ１０を形成してもよい。例えば、工程Ｓ１～工程Ｓ５までを親基板となる金属箔基体６１で形成した後、ダイシングによって親基板を個片化し、個片化された電子部品パッケージ１０の金属箔基体６１等をエッチングで除去することで、電子部品パッケージ１０を形成してもよい。また、例えば、工程Ｓ１～工程Ｓ６までを親基板となる金属箔基体６１で形成し、金属箔基体６１等をエッチングで除去した後、ダイシングして個片化することで、電子部品パッケージ１０を形成してもよい。 In the first embodiment, an example in which one electronic component package 10 is formed has been described. However, the present invention is not limited to this, and a plurality of electronic component packages 10 may be formed based on a parent substrate. For example, after the steps S1 to S5 are formed with the metal foil base 61 as the parent substrate, the parent substrate is separated into pieces by dicing, and the metal foil base 61 and the like of the separated electronic component package 10 are removed by etching. Thus, the electronic component package 10 may be formed. Further, for example, the steps S1 to S6 are formed with the metal foil base 61 serving as a parent substrate, the metal foil base 61 and the like are removed by etching, and then diced into individual pieces, whereby the electronic component package 10 is formed. It may be formed.
　また、実施の形態１の工程Ｓ２では、レーザで穴６３を形成する際に、薄膜６２と金属箔基体６１との界面にて薄膜６２を分離しているが、それに限られず、金属箔基体６１の一方主面６１ａの一部を掘り込んで、穴６３を形成してもよい。また、工程Ｓ２は、レーザでなく、マスクエッチングで薄膜６２を除去加工してもよい。 In the step S2 of the first embodiment, the thin film 62 is separated at the interface between the thin film 62 and the metal foil base 61 when forming the hole 63 with a laser. Alternatively, the hole 63 may be formed by digging a part of the one main surface 61a. In step S2, the thin film 62 may be removed by mask etching instead of using a laser.
　また、実施の形態１の工程Ｓ３において、はんだ印刷を行っているが、工程Ｓ３を省略することも可能である。例えば、十分なはんだ量を有するはんだ（はんだバンプ）６５を電子部品２０に設けた場合には、工程Ｓ３で、はんだ印刷をしなくても、リフロー時に穴６３に、はんだが充填され、金属箔基体６１と電子部品２０とをはんだ６５で接合することができる。 In addition, although solder printing is performed in step S3 of the first embodiment, step S3 can be omitted. For example, when a solder (solder bump) 65 having a sufficient amount of solder is provided on the electronic component 20, the solder is filled into the hole 63 during reflow without performing solder printing in step S 3, and the metal foil. The base 61 and the electronic component 20 can be joined with the solder 65.
　実施の形態１の工程Ｓ４（図４Ｄ参照）では、金属層Ｍ１と合金層Ａ１との境界が直線状に表されているが、それに限られず、実際の境界は、曲線状に形成されていてもよい。また、金属層Ｍ１と合金層Ａ１との間が、明確な境界を有さずにグラデーション状に変化する態様であってもよい。 In step S4 (see FIG. 4D) of the first embodiment, the boundary between the metal layer M1 and the alloy layer A1 is expressed in a straight line, but is not limited thereto, and the actual boundary is formed in a curved line shape. Also good. In addition, the metal layer M1 and the alloy layer A1 may change in a gradation without having a clear boundary.
　また、工程ＳＳ４のリフロー後に、電子部品２０および金属箔基体６１をフラックス洗浄してもよい。 Further, after the reflow in step SS4, the electronic component 20 and the metal foil base 61 may be flux cleaned.
　本発明は、電子部品パッケージおよび回路モジュールを低背化し、電気機器を小型化する場合に適用できる。また、実装基板にコネクタ、アンテナ、センサ、ＭＥＭＳなど、樹脂で封止することができない場合において適用することができる。 The present invention can be applied to the case where the electronic component package and the circuit module are reduced in height and the electric device is reduced in size. Further, the present invention can be applied to a case where a connector, an antenna, a sensor, a MEMS, or the like cannot be sealed with a resin on a mounting board.
　１０、１０Ａ、１０Ｂ、１０Ｃ　電子部品パッケージ
　２０　　電子部品
　２０ｂ　底面
　２１　　外部端子
　３０　　導通部材
　３０ａ　一方端面
　３０ｂ　他方端面
　３０ｃ　側面
　３１　　露出部
　３１ｆ　露出面
　４０　　樹脂封止部材
　４０ａ　天面
　４０ｂ　実装面
　４０ｃ　側壁面
　４５　　シールド膜
　４６　　シールド接続用部材
　４６ｃ　シールド接続用部材の側面
　４７　　はんだ
　５０、５０Ｂ　回路モジュール
　５１　　実装基板
　５１ａ　一方主面
　５１ｂ　他方主面
　５２　　コネクタ
　５３　　コイル電極
　５４　　電子部品
　５５　　はんだ
　６１　　金属箔基体
　６１ａ　一方主面
　６２　　薄膜
　６３　　穴
　６４　　はんだ（はんだ膜）
　６５　　はんだ（はんだバンプ）
　Ａ１　　合金層
　Ｃ１　　金属箔基体と接する領域
　Ｍ１　　金属層
　Ｚ１　　導通部材の軸方向 10, 10A, 10B, 10C Electronic component package 20 Electronic component 20b Bottom surface 21 External terminal 30 Conductive member 30a One end surface 30b The other end surface 30c Side surface 31 Exposed portion 31f Exposed surface 40 Resin sealing member 40a Top surface 40b Mounting surface 40c Side wall surface 45 Shield film 46 Shield connection member 46c Side surface of shield connection member 47 Solder 50, 50B Circuit module 51 Mounting substrate 51a One main surface 51b Other main surface 52 Connector 53 Coil electrode 54 Electronic component 55 Solder 61 Metal foil base 61a One main surface 62 Thin film 63 Hole 64 Solder (solder film)
65 Solder (solder bump)
A1 Alloy layer C1 Region in contact with metal foil base M1 Metal layer Z1 Axial direction of conducting member

Claims (17)

  1. 　複数の外部端子を有する電子部品と、
    　前記複数の外部端子に接続される複数の導通部材と、
    　前記複数の導通部材のそれぞれの一部および前記電子部品を覆う樹脂封止部材と
    　を備え、
    　前記樹脂封止部材は、実装側に設けられた実装面を有し、
    　前記複数の導通部材は、前記実装面から露出する露出部を有す
    　電子部品パッケージ。     An electronic component having a plurality of external terminals;
    A plurality of conducting members connected to the plurality of external terminals;
    A resin sealing member that covers a part of each of the plurality of conductive members and the electronic component;
    The resin sealing member has a mounting surface provided on the mounting side,
    The plurality of conductive members are electronic component packages having exposed portions exposed from the mounting surface.
  2. 　前記露出部は、平坦な露出面を有する
    　請求項１に記載の電子部品パッケージ。     The electronic component package according to claim 1, wherein the exposed portion has a flat exposed surface.
  3. 　前記露出部は、前記実装面よりも外側に突出している
    　請求項１または２に記載の電子部品パッケージ。     The electronic component package according to claim 1, wherein the exposed portion protrudes outward from the mounting surface.
  4. 　前記導通部材は、柱状であり、
    　前記導通部材の一方端面は、前記電子部品の前記外部端子に当接し、
    　前記導通部材の側面の一部は、前記樹脂封止部材で覆われ、
    　前記導通部材の他方端面は、前記露出部に含まれる
    　請求項３に記載の電子部品パッケージ。     The conducting member is columnar,
    One end surface of the conducting member abuts on the external terminal of the electronic component,
    A part of the side surface of the conducting member is covered with the resin sealing member,
    The electronic component package according to claim 3, wherein the other end surface of the conducting member is included in the exposed portion.
  5. 　前記実装面は平坦であり、
    　前記露出部の前記露出面は、前記実装面と面一に形成されている
    　請求項２に記載の電子部品パッケージ。     The mounting surface is flat;
    The electronic component package according to claim 2, wherein the exposed surface of the exposed portion is formed flush with the mounting surface.
  6. 　前記導通部材は、柱状であり、
    　前記導通部材の一方端面は、前記電子部品の前記外部端子に当接し、
    　前記導通部材の側面の全部は、前記樹脂封止部材で覆われ、
    　前記導通部材の他方端面は、前記露出面である
    　請求項５に記載の電子部品パッケージ。     The conducting member is columnar,
    One end surface of the conducting member abuts on the external terminal of the electronic component,
    The entire side surface of the conducting member is covered with the resin sealing member,
    The electronic component package according to claim 5, wherein the other end surface of the conducting member is the exposed surface.
  7. 　前記導通部材の前記側面の中央における横断面の面積は、前記一方端面および前記他方端面におけるそれぞれの横断面の面積よりも大きい
    　請求項４または６に記載の電子部品パッケージ。     The electronic component package according to claim 4 or 6, wherein an area of a cross section at a center of the side surface of the conducting member is larger than an area of each cross section of the one end face and the other end face.
  8. 　前記外部端子と前記露出部との間には、前記実装面に平行な配線層が存在せず、
    　前記導通部材は、前記外部端子に当接した状態で接続されている
    　請求項１～７のいずれか１項に記載の電子部品パッケージ。     Between the external terminal and the exposed portion, there is no wiring layer parallel to the mounting surface,
    The electronic component package according to any one of claims 1 to 7, wherein the conductive member is connected in contact with the external terminal.
  9. 　前記露出部は、前記実装面に垂直な方向から見た場合、前記外部端子と重なる位置に設けられている
    　請求項１～８のいずれか１項に記載の電子部品パッケージ。     The electronic component package according to any one of claims 1 to 8, wherein the exposed portion is provided at a position overlapping the external terminal when viewed from a direction perpendicular to the mounting surface.
  10. 　前記導通部材は、Ｓｎを含む金属材料で形成されている
    　請求項１～９のいずれか１項に記載の電子部品パッケージ。     The electronic component package according to any one of claims 1 to 9, wherein the conductive member is made of a metal material containing Sn.
  11. 　前記露出部には、ＳｎおよびＣｕからなる合金層が形成されている
    　請求項１～１０のいずれか１項に記載の電子部品パッケージ。     The electronic component package according to any one of claims 1 to 10, wherein an alloy layer made of Sn and Cu is formed on the exposed portion.
  12. 　前記導通部材は、はんだバンプにより形成される
    　請求項１～１１のいずれか１項に記載の電子部品パッケージ。     The electronic component package according to claim 1, wherein the conductive member is formed by a solder bump.
  13. 　前記樹脂封止部材は、天面、および、前記実装面に垂直な側壁面を有し、
    　前記天面および前記側壁面は、シールド膜によって覆われている
    　請求項１～１２のいずれか１項に記載の電子部品パッケージ。     The resin sealing member has a top surface and a side wall surface perpendicular to the mounting surface,
    The electronic component package according to any one of claims 1 to 12, wherein the top surface and the side wall surface are covered with a shield film.
  14. 　前記樹脂封止部材は、導通性を有するシールド接続用部材を含み、
    　前記シールド接続用部材は、前記側壁面の一部に露出して前記シールド膜に接している
    　請求項１３に記載の電子部品パッケージ。     The resin sealing member includes a shield connecting member having conductivity,
    The electronic component package according to claim 13, wherein the shield connection member is exposed to a part of the side wall surface and is in contact with the shield film.
  15. 　請求項１～１４のいずれか１項に記載の電子部品パッケージと、
    　前記電子部品パッケージが直接実装された実装基板と
    　を備える回路モジュール。     The electronic component package according to any one of claims 1 to 14,
    A circuit module comprising: a mounting substrate on which the electronic component package is directly mounted.
  16. 　電子部品を、複数の導通部材を介して金属箔基体に接続する工程と、
    　前記電子部品および前記複数の導通部材を覆うように、前記金属箔基体上に樹脂封止部材を形成する工程と、
    　前記樹脂封止部材と前記導通部材とに接する前記金属箔基体を除去して、前記導通部材のうちの、前記導通部材と前記金属箔基体とが接していた領域を前記樹脂封止部材の表面に露出させる工程と
    　を含む電子部品パッケージの製造方法。     Connecting the electronic component to the metal foil base via a plurality of conductive members;
    Forming a resin sealing member on the metal foil base so as to cover the electronic component and the plurality of conductive members;
    The metal foil base in contact with the resin sealing member and the conductive member is removed, and a region of the conductive member in which the conductive member and the metal foil base are in contact with each other is a surface of the resin sealing member. A method for manufacturing an electronic component package, comprising: exposing to an electronic component package.
  17. 　前記導通部材は、はんだバンプである
    　請求項１６に記載の電子部品パッケージの製造方法。     The method of manufacturing an electronic component package according to claim 16, wherein the conductive member is a solder bump.
PCT/JP2017/039330 2016-11-02 2017-10-31 Electronic component package, circuit module, and method for producing electronic component package WO2018084143A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112652573A (en) * 2020-12-07 2021-04-13 海光信息技术股份有限公司 Packaging method and chip
WO2021215108A1 (en) * 2020-04-24 2021-10-28 株式会社村田製作所 High frequency module and communication device
WO2022065395A1 (en) * 2020-09-25 2022-03-31 株式会社村田製作所 Electronic component module and method for manufacturing electronic component module

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011142159A (en) * 2010-01-06 2011-07-21 Hitachi Chem Co Ltd Apparatus including electronic circuit element and method of manufacturing the same, wiring base material for connection of the electronic circuit element, as well as wiring board with the apparatus including the electronic circuit element and method of manufacturing the same
JP2012028700A (en) * 2010-07-27 2012-02-09 Denso Corp Semiconductor device
WO2012137714A1 (en) * 2011-04-04 2012-10-11 ローム株式会社 Semiconductor device and method for manufacturing semiconductor device
JP2016149386A (en) * 2015-02-10 2016-08-18 パイオニア株式会社 Semiconductor device, electronic device and semiconductor device manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011142159A (en) * 2010-01-06 2011-07-21 Hitachi Chem Co Ltd Apparatus including electronic circuit element and method of manufacturing the same, wiring base material for connection of the electronic circuit element, as well as wiring board with the apparatus including the electronic circuit element and method of manufacturing the same
JP2012028700A (en) * 2010-07-27 2012-02-09 Denso Corp Semiconductor device
WO2012137714A1 (en) * 2011-04-04 2012-10-11 ローム株式会社 Semiconductor device and method for manufacturing semiconductor device
JP2016149386A (en) * 2015-02-10 2016-08-18 パイオニア株式会社 Semiconductor device, electronic device and semiconductor device manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021215108A1 (en) * 2020-04-24 2021-10-28 株式会社村田製作所 High frequency module and communication device
WO2022065395A1 (en) * 2020-09-25 2022-03-31 株式会社村田製作所 Electronic component module and method for manufacturing electronic component module
CN112652573A (en) * 2020-12-07 2021-04-13 海光信息技术股份有限公司 Packaging method and chip

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