JP2012028700A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which increases freedom in routing of a low-current wiring part.SOLUTION: The semiconductor device comprises an insulation base material, a wiring part provided at the insulation base material and a semiconductor chip 30 in which a power transistor is formed and sealed in the insulation base material. The wiring part is provided with a high-current wiring part (an emitter terminal 41, a collector terminal 42, an interlayer connection part 60) including a conductor layer electrically connected to high-current electrodes (an emitter electrode 32, a collector electrode 33) of the semiconductor chip 30 and facing the high-current electrodes, and a low-current wiring part including a conductor pattern 50 electrically connected to a low-current electrodes (sensor electrodes 361, 362, a gate electrode) of the semiconductor chip 30 and insulated from the high-current wiring part by the insulation base material and the interlayer connection part 60.

Description

  The present invention relates to a semiconductor device including a semiconductor chip provided with electrodes on both sides and a high-current wiring electrically connected to each electrode.

  Conventionally, there has been a semiconductor device disclosed in Patent Document 1 as an example of a semiconductor device including a semiconductor chip provided with electrodes on both surfaces and a wiring for high current electrically connected to each electrode.

  This semiconductor device includes a semiconductor chip having a plurality of cell blocks on the main surface side, and first to third bonded to both main surfaces of the semiconductor chip via first to third conductive bonding members, respectively. These metal bodies (large current wiring portions) are molded with resin.

Japanese Patent Laying-Open No. 2005-167075

  However, in the semiconductor device, the first and second metal bodies are provided on both main surfaces of the semiconductor chip, and the semiconductor chip and the first to third metal bodies are molded with resin. As described above, since the first and second metal bodies are provided on both main surfaces of the semiconductor chip, a signal is transmitted to the electrode of the temperature sensor or the signal electrode of the semiconductor chip (for example, a gate electrode, a small current electrode). It is necessary to provide a pad connected via a wiring for wiring (small current wiring portion) on the outer peripheral portion (end portion) of the semiconductor chip. In addition, since the semiconductor chip and the first to third metal bodies are molded with resin, the signal wiring portion needs to be routed in the semiconductor chip and conducted to the pads provided on the outer peripheral portion of the semiconductor chip. was there. Further, this pad needs to be wire-bonded to the signal terminal of the semiconductor device while avoiding the first to third metal bodies.

  The present invention has been made in view of the above problems, and in a semiconductor device including a semiconductor chip provided with electrodes on both surfaces and a wiring for high current electrically connected to each electrode, An object is to improve the degree of freedom in routing the wiring portion and to reduce the ineffective area on the semiconductor chip by omitting the wiring on the semiconductor chip.

In order to achieve the above object, a semiconductor device according to claim 1,
An insulating substrate;
A wiring portion provided on an insulating substrate and including a conductor layer disposed in a stacked manner and an interlayer connection portion formed in a via hole;
A semiconductor chip in which an element is formed and sealed in an insulating substrate;
With
Semiconductor chip
A power transistor as an element;
A large current electrode provided on each of both surfaces orthogonal to the lamination direction of the conductor layer, through which a large current flows in the power transistor;
A small-current electrode provided on at least one of the two surfaces, through which a smaller current flows than the large-current electrode,
The large current electrode provided on the same surface as the small current electrode is provided so as to surround the small current electrode,
The wiring part is electrically connected to the large current electrode and includes a conductor layer facing the large current electrode and the large current wiring part, and is electrically connected to the small current electrode. A small current wiring portion including a wiring portion for wiring and an insulated conductor layer and an interlayer connection portion;
It is characterized by providing.

  As described above, the large current electrode is provided so as to surround the small current electrode, and the conductor layer and the interlayer connection portion arranged in a stacked manner are provided as the small current wiring portion electrically connected to the small current electrode. By including it, the small current wiring portion can be routed in the direction in which the conductor layers are laminated and in the direction perpendicular to the lamination direction. Therefore, even when the large current wiring portion including the conductor layer facing the large current electrode is provided, the degree of freedom in routing can be improved as compared with the small current wiring portion being routed in the semiconductor chip. . Furthermore, since the wiring on the semiconductor chip (that is, the wiring on the surface orthogonal to the stacking direction in the semiconductor chip) can be omitted, the ineffective area on the semiconductor chip can be reduced.

  According to a second aspect of the present invention, a signal corresponding to the temperature of the semiconductor chip is output, and a temperature sensor disposed at the center of the surface of the semiconductor chip is provided. You may make it include the electrode for sensors.

  By doing in this way, the wiring part for small currents (conductor layer and interlayer connection part) electrically connected to the sensor electrode can be routed in the stacking direction of the conductor layer and in the direction orthogonal to the stacking direction. . Therefore, it becomes easy to arrange the temperature sensor at the center of the surface of the semiconductor chip. As described above, by arranging the temperature sensor at the center of the surface of the semiconductor chip, the temperature of the portion of the semiconductor chip where the temperature is highest can be measured. Therefore, it is preferable because the temperature of the semiconductor chip can be accurately measured.

  According to a third aspect of the present invention, the power transistor includes a plurality of transistor structures, and the small current electrode is electrically connected to each gate of the plurality of transistor structures, and the surface of the semiconductor chip A gate electrode may be included in the central portion.

  By doing so, the small current wiring portion (conductor layer and interlayer connection portion) electrically connected to the gate electrode can be routed in the stacking direction of the conductor layer and in the direction orthogonal to the stacking direction. Therefore, it becomes easy to arrange the gate electrode at the center of the surface of the semiconductor chip. Thus, by disposing the gate electrode at the center of the surface of the semiconductor chip, the difference in distance between the gate electrode and the gate of each transistor structure can be minimized. Therefore, it is preferable because variations in the transmission time of the gate signal to each transistor structure can be suppressed and each transistor structure can be easily operated uniformly.

  According to a fourth aspect of the present invention, the small current wiring portion includes a conductor layer and an interlayer connection portion, has a columnar portion extending along the stacking direction, and is provided on the side where the small current electrode is provided. The high-current wiring part may be provided so as to penetrate the columnar part through the stacking direction.

  In this way, the small current wiring portion (conductor layer and interlayer connection portion) can be routed in the stacking direction of the conductor layer through the portion where the large current wiring portion penetrates. The degree of freedom in routing the part can be further improved.

  Further, as shown in claim 5, the conductor layer facing the large current electrode may be thicker in the stacking direction than the other conductor layers.

  By doing so, the wiring resistance of the large current wiring portion can be reduced. In addition, since the current capacity can be increased, an increase in the size of the semiconductor device can be suppressed while suppressing disconnection due to Joule heat.

  According to a sixth aspect of the present invention, the conductor layer facing the large current electrode may be wider in width along the direction perpendicular to the stacking direction than the other conductor layers.

  By doing so, the wiring resistance of the large current wiring portion can be reduced.

  According to a seventh aspect of the present invention, the high current wiring portion may include an interlayer connection portion in addition to the conductor layer.

  Moreover, when taking out the wiring part for small currents and the wiring part for large currents outside the insulating substrate, as shown in claim 8, the wiring part for small currents and the wiring part for large currents include a metal piece. A part of the metal piece may be disposed in the insulating base material, and the other part may be provided to protrude outside the insulating base material. Or as shown in Claim 9, you may make it the wiring part for small currents and the wiring part for large currents provide the exposed part exposed outside the insulating base material. Moreover, the wiring part for small current and the wiring part for large current include the conductor layer and the interlayer connection part, so that any direction of the insulating base (that is, both surfaces orthogonal to the stacking direction in the insulating base, It can be taken out (from any direction on the side surface along the stacking direction).

  In addition, as shown in claim 10, the insulating base material includes the thermoplastic resin film while the thermoplastic resin film containing the thermoplastic resin is positioned at least every other layer and is positioned adjacent to the semiconductor chip. A plurality of substrate films may be laminated and the substrate films may be bonded to each other.

  By doing in this way, a semiconductor device can be collectively formed by pressurization and heating, sealing a semiconductor chip, and a manufacturing process can be simplified.

It is a top view which shows schematic structure of the semiconductor device in embodiment of this invention. 1 is a plan view showing a schematic configuration of a semiconductor chip in an embodiment of the present invention, (a) is a plan view on an emitter electrode side, and (b) is a plan view on a collector electrode side. It is sectional drawing which follows the III-III line of FIG. It is sectional drawing which follows the IV-IV line of FIG. It is an exploded sectional view showing a schematic structure of a semiconductor device in an embodiment of the invention. It is a top view which shows schematic structure of the terminal in embodiment of this invention, (a) is a top view of the terminal for emitters, (b) is a top view of the terminal for collectors. (A), (b) is sectional drawing which shows schematic structure of the semiconductor device in the modification 1. FIG. It is sectional drawing which shows schematic structure of the semiconductor device in the modification 2 (emitter terminal side). It is sectional drawing which shows schematic structure of the semiconductor device in the modification 2 (collector terminal side). It is sectional drawing which shows schematic structure of the semiconductor device in the modification 3 (emitter terminal side). It is sectional drawing which shows schematic structure of the semiconductor device in the modification 3 (collector terminal side). 10 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to Modification 4. FIG. 10 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to Modification 5. FIG. 10 is a plan view illustrating a schematic configuration of a semiconductor device according to Modification 6. FIG. It is sectional drawing which follows the XV-XV line | wire of FIG. It is a top view which shows schematic structure of the metal piece in the modification 6, (a) is a top view of the terminal for collectors, (b) is a top view of the connection part for midpoints, (c) is a midpoint It is a top view of the terminal for operation | use, (d) is a top view of the terminal for emitters. 10 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to Modification 7. FIG. 10 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to Modification 8. FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments of the present invention are not limited to the following examples, and can take various forms as long as they belong to the technical scope of the present invention. Further, the thickness direction of the insulating base material 20 (in other words, the lamination direction of a plurality of resin films) is simply referred to as a lamination direction, and the direction orthogonal to the lamination direction is simply referred to as an orthogonal direction.

  As shown in FIGS. 1, 3, 4, etc., the semiconductor device 10 according to the present embodiment is embedded in the insulating base material 20 and the insulating base material 20 as basic constituent elements incorporating the semiconductor chip 30. A built-in semiconductor chip 30, a conductor pattern 50 / interlayer connection 60 provided on the insulating base material 20, and a plurality of terminals 41 to 45 are provided. That is, the semiconductor device 10 includes an insulating base material 20, a wiring provided on the insulating base material 20, and including a conductor layer (conductor pattern 50, terminals 41 to 45) arranged in a stacked manner and an interlayer connection 60 formed in the via hole. And a semiconductor chip 30 formed with an element (a plurality of transistor structure portions not shown) and sealed with an insulating base material 20. The terminal 41 is an emitter terminal that is electrically connected to the emitter electrode of the semiconductor chip 30. The terminal 42 is a collector terminal that is electrically connected to the collector electrode of the semiconductor chip 30. The terminals 43 and 44 are sensor terminals that are electrically connected to the sensor electrodes 361 and 362 of the temperature sensor 35 disposed at the center of the surface of the semiconductor chip 30. The terminal 45 is a gate terminal that is electrically connected to the gate electrode 34 disposed at the center of the surface of the semiconductor chip 30. The semiconductor chip 30 will be described in detail later.

  First, the insulating base material 20 will be described. The insulating base material 20 is made of an electrically insulating material. In the example shown in FIGS. 1, 3 and 4 except for the insulating base material 20, the semiconductor chip 30, the conductor pattern 50, the interlayer connection portion 60, and the terminals 41 to 41 are used. In addition to serving as a base material that holds 45 in a predetermined position, the semiconductor chip 30 is held and protected therein.

  The insulating base material 20 mainly contains a resin, and at least a thermoplastic resin as the resin. A plurality of resin films including a thermoplastic resin film are laminated, and are bonded and integrated by pressing and heating. Being done. The reason for including the thermoplastic resin is that, when forming the insulating base material 20 in a batch in the pressurizing / heating process described later, it is resistant to high temperatures and uses the softened thermoplastic resin as an adhesive and a sealing material. is there.

  For this reason, as the plurality of resin films, a thermoplastic resin film may be included so as to be adjacent to the semiconductor chip 30 while being positioned at least every other sheet in a laminated state. For example, it is good also as a structure containing only a thermoplastic resin film, and good also as a structure containing a thermosetting resin film with a thermoplastic resin film.

  As the thermoplastic resin film, at least one of a film containing an inorganic material such as glass fiber and aramid fiber and a film made of a thermoplastic resin not containing an inorganic material can be employed together with the thermoplastic resin. Similarly, as the thermosetting resin film, at least one of a film containing the inorganic material and a film made of a thermosetting resin not containing the inorganic material can be employed together with the thermosetting resin.

  As shown in FIGS. 3 and 4, the insulating base material 20 according to the present embodiment is formed by laminating a total of 11 resin films in the order of thermoplastic resin films 201 to 211 from the one surface side in the laminating direction. Note that a thermoplastic resin film 20a (two layers here) is provided in the opening 413 of the emitter terminal 41, which will be described later.

  Further, as the thermoplastic resin films 201-211, 20 a, 30% by weight of polyetheretherketone (PEEK) and polyetherimide (without including an inorganic material such as glass fiber or an inorganic filler for adjusting the linear expansion coefficient) PEI) A resin film composed of 70% by weight is employed. In addition, the constituent material of a thermoplastic resin film is not limited to the said example. For example, even if it consists of PEEK / PEI, you may employ | adopt the thing from which a ratio differs from the said example. Moreover, you may employ | adopt constituent materials other than PEEK / PEI, for example, a liquid crystal polymer (LCP).

  Moreover, as shown in FIG. 5, the resin film which comprises the insulating base material 20 is die-cut according to the external shape of the part arrange | positioned inside the insulating base material 20 in the terminals 41-45 (partially cut). (Removed)) including the terminal arrangement portions 2021, 2041, 2051, 2091, and 2101 that have been performed. Further, the resin film constituting the insulating base material 20 includes a resin film provided with a through hole 2071 that is die-cut (partially cut (removed)) according to the outer shape of the semiconductor chip 30.

  The number of resin films forming the terminal arrangement portion is determined according to the thickness (thickness in the stacking direction) of the portion of the terminals 41 to 45 arranged inside the insulating base material 20. In the present embodiment, as shown in FIG. 5, terminal arrangement portions 2021, 2041, 2051, 2091, and 2101 are formed on the thermoplastic resin films 202, 204, 205, 209, and 210. Similarly, the number of resin films forming the through hole is determined according to the thickness of the semiconductor chip 30 (thickness in the stacking direction). In the present embodiment, as shown in FIG. 5, a through hole 2071 is formed in the thermoplastic resin film 207.

  Next, the semiconductor chip 30 will be described. The semiconductor chip 30 has a plurality of transistor structures formed on a rectangular semiconductor substrate 31 made of silicon or the like. In other words, it is an IC chip (bare chip) in which a power transistor element used for power control of a load such as a motor, such as a power MOSFET or IGBT, is configured. Further, as shown in FIG. 2 (a), the temperature of the semiconductor chip 30 is at the center of one surface of the semiconductor chip 30 (the surface that is arranged in the insulating base material 20 and orthogonal to the stacking direction). A temperature sensor 35 is provided for outputting a signal corresponding to the above. The semiconductor chip 30 is sealed with the insulating base material 20 (the thermoplastic resin constituting the insulating base material 20).

  In the present embodiment, an IGBT is employed as the power transistor element. The semiconductor chip 30 is provided with a signal processing circuit unit (large scale integrated circuit) in which elements other than the power transistor element, for example, elements such as a diode, a resistor, a capacitor, a CMOS, and a bipolar transistor are integrated. Can also be adopted.

  As shown in FIGS. 2A and 2B, both surfaces of the semiconductor chip 30 (both surfaces orthogonal to the stacking direction in the state of being disposed in the insulating base material 20) are connected to the outside. For this purpose, an electrode made of a Ni-based material is formed. This electrode is provided on each of both surfaces, and is provided on a large current electrode (emitter electrode 32, collector electrode 33) through which a large current flows in the IGBT, and at least one of both surfaces. There are provided small current electrodes (gate electrode 34, sensor electrodes 361, 362) through which a smaller current flows than the electrodes.

  As described above, the IGBT includes a plurality of transistor structures. And in the center part of the surface (surface orthogonal to the lamination direction in the state arrange | positioned in the insulating base material 20) of the semiconductor chip 30, it is for the small current electrically connected to each gate in several transistor structure parts A gate electrode 34 as an electrode is disposed. Further, as described above, the temperature sensor 35 is also disposed at the center of one surface of the semiconductor chip 30 (the surface orthogonal to the stacking direction in the state of being disposed in the insulating base material 20). As a result, the sensor electrodes 361 and 362 of the temperature sensor 35 are arranged as small current electrodes at the center of the surface of the semiconductor chip 30. That is, the gate electrode 34 and the sensor electrodes 361 and 362 are provided adjacent to each other at the center of the surface of the semiconductor chip 30 (the surface orthogonal to the stacking direction in the state of being disposed in the insulating base material 20).

  As shown in FIG. 2A, the large current electrode (emitter electrode 32) provided on the same surface as the small current electrode (gate electrode 34, sensor electrode 361, 362) is a small current electrode. (Gate electrode 34, sensor electrodes 361, 362) are provided so as to surround. That is, the emitter electrode 32 is provided in an annular shape. In other words, the small current electrodes (gate electrode 34, sensor electrodes 361, 362) are arranged in the opening 321 provided in the center of the emitter electrode 32.

  The emitter electrode 32 corresponds to a large current electrode provided on the same surface as the small current electrode. As shown in FIG. 2A, provided on one surface of the semiconductor substrate 31 (a surface orthogonal to the stacking direction in a state of being disposed in the insulating base material 20) in a wide range excluding the opening 321 and the edge. It has been. As shown in FIG. 2B, the collector electrode 33 has a wide range excluding the edge on the other surface of the semiconductor substrate 31 (the surface disposed in the insulating base material 20 and orthogonal to the stacking direction). Is provided.

  These electrodes 32 to 34, 361, and 362 are connected to an interlayer connection 60 described later. Then, metal diffusion formed by mutually diffusing Sn and Ni at the interface between the electrodes 32 to 34, 361 and 362 made of Ni-based material and the interlayer connection portion 60 made of Ag-Sn alloy as will be described later. A layer (Ni-Sn alloy layer) is formed. Thereby, the connection reliability of the electrodes 32-34, 361, 362 and the interlayer connection part 60 is improved.

  Next, each element constituting the wiring part will be described. The wiring portion includes a conductor pattern 50 (conductor layer), an interlayer connection portion 60 (interlayer connection portion), and terminals 41 to 45 (conductor layer). Further, it has an interlayer connection portion 60 electrically connected to the large current electrodes (emitter electrode 32, collector electrode 33) and a portion facing the large current electrode, and is connected to the large current via the interlayer connection portion 60. The large current wiring portion including the terminals 41 and 42 connected to the electrodes and the small current electrodes (gate electrode 34, sensor electrodes 361 and 362) are electrically connected to the large current wiring by the insulating substrate 20. And a small current wiring portion including a conductor pattern 50 insulated from the portion, an interlayer connection portion 60, and terminals 43 to 45.

  The conductor pattern 50 is formed by patterning a conductor foil, and is used as a wiring portion that electrically connects the semiconductor chip 30 and the outside. The interlayer connection portion 60 is a resin film in which a conductive paste is filled in via holes (through holes) provided along the thickness direction (lamination direction), and the conductive particles in the conductive paste are pressed and heated. Sintered. The interlayer connection portion 60 is also used as a wiring portion that electrically connects the semiconductor chip 30 and the outside together with the conductor pattern 50.

  The terminals 41 to 45 are metal pieces (metal plates) on a flat plate made of Cu, Au, Ag, Al, or an alloy containing at least one of these metals. Here, as the terminals 41 to 45, metal pieces made of Cu are employed. The terminals 41 and 42 are large wirings that electrically connect the large current electrodes (emitter electrode 32, collector electrode 33) of the semiconductor chip 30 and the outside of the wiring portion that electrically connects the semiconductor chip 30 and the outside. It is used as a part of the current wiring portion. The terminal 41 is an emitter terminal electrically connected to the emitter electrode 32, and the terminal 42 is a collector terminal electrically connected to the collector electrode 33. The emitter terminal 41 and the collector terminal 42 also function as a heat sink.

  As shown in FIG. 6A, the emitter terminal 41 is included in the large current wiring portion on the side where the small current electrode is provided. The emitter terminal 41 is a part that is electrically connected to the emitter electrode 32 of the semiconductor chip 30 via the interlayer connection part 60, and a connection part 412 disposed in the insulating base material 20, and a part thereof is an insulating base material. 20 includes a terminal portion 411 that projects from the side wall (surface along the stacking direction) of 20 and is electrically connected to an external device of the semiconductor device 10. In addition, the connection portion 412 of the emitter terminal 41 is disposed to face the emitter electrode 32 in a state where the connection portion 412 is disposed in the insulating base material 20. Further, the connection portion 412 of the emitter terminal 41 is provided with an opening 413 penetrating in the stacking direction in a state where the connection portion 412 is disposed in the insulating base material 20. In the opening 413, a columnar portion 5060, which will be described later, is provided in a state of being disposed in the insulating base material 20. That is, the emitter terminal 41 is provided so as to surround a columnar portion 5060 described later in a state where it is arranged in the insulating base material 20. In addition, the connection portion 412 is wider than the terminal portion 411 along the orthogonal direction.

  The connecting portion 412 and the emitter electrode 32 have the same planar shape along the orthogonal direction, and the plane area is also substantially the same. In addition, the interlayer connection portion 60 that electrically connects the connection portion 412 and the emitter electrode 32 and the emitter electrode 32 have the same planar shape along the orthogonal direction, and the plane area is also the same. The connection portion 412 of the emitter terminal 41 corresponds to a conductor layer facing the large current electrode.

  On the other hand, as shown in FIG. 6B, the collector terminal 42 is a portion that is electrically connected to the collector electrode 33 of the semiconductor chip 30 via the interlayer connection portion 60 and is disposed in the insulating base material 20. The connection part 422 includes a terminal part 421 that is a part of which protrudes to the outside from a side wall (a surface along the stacking direction) of the insulating base material 20 and is electrically connected to an external device of the semiconductor device 10. In addition, the connecting portion 422 of the collector terminal 42 is disposed so as to face the collector electrode 33 in a state where it is disposed in the insulating base material 20. Further, the connection portion 422 has a width along the orthogonal direction wider than the terminal portion 421.

  The connecting portion 422 and the collector electrode 33 have the same planar shape along the orthogonal direction, and the planar areas are also substantially the same. In addition, the interlayer connection portion 60 that electrically connects the connection portion 422 and the collector electrode 33 and the collector electrode 33 have the same planar shape along the orthogonal direction, and the plane area is also the same.

  Thus, the large current electrode includes the emitter electrode 32 and the collector electrode 33. The large current wiring portion includes an emitter terminal 41, an interlayer connection portion 60 that electrically connects the emitter terminal 41 and the emitter electrode 32 of the semiconductor chip 30, a collector terminal 42, a collector terminal 42, and the semiconductor chip 30. It includes an interlayer connection 60 that electrically connects the collector electrode 33.

  The emitter terminal 41 and the collector terminal 42 allow current to flow in the orthogonal direction. On the other hand, an interlayer connection 60 that electrically connects the emitter terminal 41 and the emitter electrode 32 of the semiconductor chip 30, and an interlayer connection 60 that electrically connects the collector terminal 42 and the collector electrode 33 of the semiconductor chip 30. Is to flow current in the stacking direction. Therefore, in other words, the emitter terminal 41 and the collector terminal 42 are lateral wiring portions (orthogonal wiring portions) in the large current wiring portion. On the other hand, an interlayer connection 60 that electrically connects the emitter terminal 41 and the emitter electrode 32 of the semiconductor chip 30, and an interlayer connection 60 that electrically connects the collector terminal 42 and the collector electrode 33 of the semiconductor chip 30. Is a vertical wiring portion (stacking wiring portion) in the large current wiring portion.

  The terminals 43 and 44 are small current wiring portions that electrically connect the small current electrodes (sensor electrodes 361 and 362) and the outside of the wiring portions that electrically connect the semiconductor chip 30 and the outside. It is used as a part. Further, a part of the terminals 43 and 44 are disposed in the insulating base material 20, and other portions are provided so as to protrude outside from the side wall (surface along the stacking direction) of the insulating base material 20. The terminals 43 and 44 are sensor terminals that are electrically connected to the sensor electrodes 361 and 362.

  As shown in FIG. 3, the small current wiring portion includes a columnar portion 5060 including the conductor pattern 50 and the interlayer connection portion 60 in addition to the sensor terminal 43 and extending in the stacking direction. The sensor terminal 43 and the sensor electrode 361 are electrically connected through the columnar portion 5060. The columnar portion 5060 is provided immediately above the sensor electrode 361. The columnar portion 5060 in the present embodiment includes a three-layer conductor pattern 50, an interlayer connection portion 60 that connects the sensor electrode 361 and the conductor pattern 50, two interlayer connection portions 60 that connect the conductor patterns 50, And the interlayer connection part 60 which connects the conductor pattern 50 and the sensor terminal 43 is included. However, the number of the conductor patterns 50 and the interlayer connection portions 60 constituting the columnar portion 5060 is not limited to this.

  Similarly, the sensor terminal 44 and the sensor electrode 362 are electrically connected via the columnar portion 5060. In the present embodiment, a cross-sectional view showing that the sensor terminal 44 and the sensor electrode 362 are electrically connected via the columnar portion 5060 and detailed description thereof are omitted.

  The terminal 45 is a small current wiring portion that electrically connects the small current electrode (gate electrode 34) of the semiconductor chip 30 and the outside of the wiring portion that electrically connects the semiconductor chip 30 and the outside. It is used as a part of Further, a part of the terminal 45 is disposed in the insulating base material 20, and the other part is provided so as to protrude outside from the side wall (surface along the stacking direction) of the insulating base material 20. This terminal 45 is a gate terminal electrically connected to the gate electrode 34.

  As shown in FIG. 4, the small current wiring portion includes a columnar portion 5060 including the conductor pattern 50 and the interlayer connection portion 60 in addition to the gate terminal 45 and extending along the stacking direction. The gate terminal 45 and the gate electrode 34 are electrically connected through the columnar portion 5060. This columnar portion 5060 is provided immediately above the gate electrode 34. The columnar portion 5060 in the present embodiment includes a three-layer conductor pattern 50, an interlayer connection portion 60 that connects the gate electrode 34 and the conductor pattern 50, two interlayer connection portions 60 that connect the conductor patterns 50, and It includes an interlayer connection 60 that connects the conductor pattern 50 and the gate terminal 45. However, the number of the conductor patterns 50 and the interlayer connection portions 60 constituting the columnar portion 5060 is not limited to this.

  As described above, the small current electrode includes the gate electrode 34 and the sensor electrodes 361 and 362. The small current wiring portion electrically connects the sensor terminal 43, the columnar portion 5060 that electrically connects the sensor terminal 43 and the sensor electrode 361, the sensor terminal 44, the sensor terminal 44, and the sensor electrode 362. A columnar portion 5060 connected to the gate terminal 45, a gate terminal 45, and a columnar portion 5060 that electrically connects the gate terminal 45 and the gate electrode 34.

  The sensor terminals 43 and 44 and the gate terminal 45 flow current in the orthogonal direction. On the other hand, a columnar portion 5060 that electrically connects the sensor terminal 43 and the sensor electrode 361, a columnar portion 5060 that electrically connects the sensor terminal 44 and the sensor electrode 362, the gate terminal 45 and the gate electrode 34. The columnar portions 5060 that electrically connect the two flow current in the stacking direction. Therefore, in other words, the sensor terminals 43 and 44 and the gate terminal 45 are lateral wiring sections (orthogonal wiring sections) in the small current wiring section. On the other hand, a columnar portion 5060 that electrically connects the sensor terminal 43 and the sensor electrode 361, a columnar portion 5060 that electrically connects the sensor terminal 44 and the sensor electrode 362, the gate terminal 45 and the gate electrode 34. The columnar portion 5060 that electrically connects to each other is a vertical wiring portion (stacking direction wiring portion) in the small current wiring portion.

  In the present embodiment, the conductor pattern 50 is configured by patterning a copper (Cu) foil. The interlayer connection portion 60 is made of an Ag—Sn alloy.

  The terminals 41 to 45 are flat plate members made of Cu. Further, the terminals 41 to 45 are provided with a uniform thickness along the laminating direction. An emitter terminal 41 that is a conductor layer facing the emitter electrode 32 and a collector terminal 42 that is a conductor layer facing the collector electrode 33 are a conductor pattern 50 that is another conductor layer, and a small current terminal (for sensor). The thickness along the stacking direction is thicker than the terminals 43 and 44 and the gate terminal 45). By doing so, the wiring resistance of the large current wiring portion can be reduced. In addition, since the current capacity can be increased, an increase in the size of the semiconductor device 10 can be suppressed while suppressing disconnection due to Joule heat.

  However, the emitter terminal 41, which is a conductor layer facing the emitter electrode 32, and the collector terminal 42, which is a conductor layer facing the collector electrode 33, are composed of conductor patterns, and conductor patterns 50, which are other conductor layers, The width along the direction orthogonal to the stacking direction may be wider than the small current terminals (sensor terminals 43 and 44, gate terminal 45). By doing so, the wiring resistance of the large current wiring portion can be reduced.

  In the present embodiment, the large current terminals of the emitter terminal 41 and the collector terminal 42 have substantially the same thickness as the two thermoplastic resin films. On the other hand, the small current terminals of the gate terminal 34 and the sensor terminals 361 and 362 have substantially the same thickness as that of one thermoplastic resin film.

  In addition, a metal diffusion layer (Cu—Sn alloy layer) formed by mutual diffusion of Cu and Sn is formed at the interface between the conductor pattern 50 made of Cu and the interlayer connection portion 60 made of an Ag—Sn alloy, Thereby, the connection reliability of the conductor pattern 50 and the interlayer connection part 60 is improved. Also, a metal diffusion layer (Cu—Sn alloy layer) in which Cu and Sn diffuse to each other also at the interface between the terminals 41 to 45 which are metal pieces made of Cu and the interlayer connection portion 60 made of an Ag—Sn alloy. As a result, the connection reliability between the terminals 41 to 45 and the interlayer connection 60 is improved.

  Here, based on FIG. 5, the manufacturing method of the above-described semiconductor device 10 will be described. In FIG. 5, reference numeral 60 is a conductive paste constituting the interlayer connection 60, but for convenience, the same reference numeral as that of the interlayer connection 60 is given.

  When the semiconductor device 10 is manufactured (molded) using the thermoplastic resin films 201 to 211 described above, it can be manufactured by a batch hot press known as PALAP. Therefore, as the basic configuration and manufacturing method of the semiconductor device 10, unless otherwise specified, the configuration related to PALAP that has been filed by the present applicant can be adopted as appropriate. Therefore, since the semiconductor device 10 can be manufactured (molded) in a lump, it is possible to reduce man-hours and satisfy the condition that the insulating base material 20 has flexibility. PALAP is a registered trademark of Denso Corporation.

  First, in order to form the semiconductor device 10 by pressurizing and heating the stacked body, elements constituting the stacked body are prepared. In addition, a laminated body is a state before the pressurization and heating process described later, and is a state in which the thermoplastic resin films 201 to 211 and 20a, the semiconductor chip 30, and the terminals 41 to 45 constituting the semiconductor device 10 are laminated. Is.

  In this preparation step, as is well known by the batch lamination method known as PALAP, the conductor pattern 50 (for example, Cu foil) is applied to the thermoplastic resin films 201 to 211 constituting the insulating base 20 before the batch lamination. ) Or by filling the via holes with a conductive paste 60 (for example, an Ag—Sn alloy) that becomes the interlayer connection 60 by sintering. In addition, the number of thermoplastic resin films (here, the thermoplastic resin film 207) corresponding to the thickness of the semiconductor chip 30 includes through holes 2071 (hollow portions) corresponding to the outer shape of the semiconductor chip 30. Is formed. That is, the die is cut according to the outer shape of the semiconductor chip. In other words, it is cut (removed) according to the outer shape of the semiconductor chip 30. The through hole 2071 can be formed on the thermoplastic resin film by mechanical processing such as punching or drilling, or laser light irradiation. The through hole 2071 is for housing the semiconductor chip 30.

  In addition, the number of thermoplastic resin films (here, the thermoplastic resin film 202 corresponding to the terminals 43 to 45 and the heat corresponding to the terminals 41) according to the thickness of the terminals 41 to 45 (for example, metal pieces made of Cu). The thermoplastic resin films 204 and 205 and the thermoplastic resin films 209 and 210) corresponding to the terminals 42 are terminals that are cut-out portions corresponding to the outer shapes of the portions of the terminals 41 to 45 disposed inside the insulating base 20. Arrangement units 2021, 2041, 2051, 2091, and 2101 are provided. In other words, the terminals 41 to 45 are punched in accordance with the outer shape of the portion arranged inside the insulating base material 20. In other words, the terminals 41 to 45 are cut (removed) according to the outer shape of the portion disposed inside the insulating base material 20. The terminal arrangement portions 2021, 2041, 2051, 2091, and 2101 can be formed on a thermoplastic resin film by mechanical processing such as punching or drilling, or laser light irradiation. In addition, this terminal arrangement | positioning part 2021,2041,2051,2091,2101 is for accommodating the terminals 41-45.

  Moreover, the conductor pattern 50 can be formed by patterning the conductor foil affixed on the surface of the thermoplastic resin film. The plurality of thermoplastic resin films constituting the insulating base material 20 may include a thermoplastic resin film having a conductor pattern 50. For example, a configuration in which all thermoplastic resin films have a conductor pattern 50, a part of the thermoplastic resin film, or the like. A configuration in which the thermoplastic resin film does not have the conductor pattern 50 can also be employed. In FIG. 5, the conductor pattern 50 is formed only on the thermoplastic resin film 206 and the two thermoplastic resin films 20a.

  Moreover, as a thermoplastic resin film which has the conductor pattern 50, both the thermoplastic resin film which has the conductor pattern 50 only on one side, and the thermoplastic resin film which has the conductor pattern 50 on both surfaces in the lamination direction are employable.

  On the other hand, the conductive paste constituting the interlayer connection portion 60 is obtained by adding ethyl cellulose resin or acrylic resin to the conductive particles for imparting shape retention and kneading in an organic solvent such as terpineol. Can do. Then, via holes penetrating the resin film are formed by a carbon dioxide laser or the like, and the conductive paste is filled into the via holes by screen printing or the like. The via hole may be formed with the conductor pattern 50 as the bottom surface (for example, the thermoplastic resin films 206 and 20a), or the via hole may be formed at a position where the conductor pattern 50 is not present (for example, the thermoplastic resin film). 203, 208, 206).

  When a via hole is formed on the conductor pattern 50, the conductive paste 60 can be retained in the via hole because the conductor pattern 50 forms the bottom. On the other hand, when a via hole is formed at a position different from the formation position of the conductor pattern 50 while having a conductor film 50 or a resin film having no conductor pattern 50, the conductive film is not conductive in the bottomless via hole. In order to fasten the paste 60, the conductive paste 60 described in Japanese Patent Application No. 2008-296074 by the present applicant is used. Further, as an apparatus (method) for filling the conductive paste 60, an apparatus (method) described in Japanese Patent Application No. 2009-75034 by the present applicant may be employed.

  The conductive paste 60 decomposes or volatilizes the conductive particles at a temperature lower than the sintering temperature of the conductive particles, becomes a molten state at a temperature lower than the temperature and higher than the room temperature, and is solid at room temperature. A low melting point room temperature solid resin that is in a state is added. An example of the low melting point room temperature solid resin is paraffin. According to this, by heating at the time of filling, the low melting point room temperature solid resin is melted to become a paste, and in the cooling after filling, the low melting point room temperature solid resin is solidified to solidify the conductive paste 60, It can be held in the via hole. When filling, one end of the via hole may be closed with a flat member.

  Next, a stacking process for forming a stacked body is performed. In this step, as shown in FIG. 5, the semiconductor chip 30 is arranged in the through hole 2071 and the terminals 41 to 45 are arranged in the terminal arrangement portions 2021, 2041, 2051, 2091, and 2101 as described above. The thermoplastic resin films 201 to 211, 20a prepared in the above are laminated from one end side in the laminating direction to form a laminated body. At this time, the emitter electrode 32, the collector electrode 33, the gate electrode 34, the sensor electrodes 361 and 362 of the semiconductor chip 30 disposed in the through hole 2071 and the conductive paste 60 face each other. Further, a part of the terminals 41 to 45 arranged at the terminal arrangement portions 2021, 2041, 2051, 2091, and 2101 (for example, the connection portion 412 of the emitter terminal 41 and the connection portion 422 of the collector terminal 42) and the conductivity The paste 60 faces. In addition, a thermoplastic resin film 20 a is disposed in the opening 413 of the emitter terminal 41.

  Next, a pressurizing / heating process is performed in which the laminate is heated from above and below while heating the laminate using a vacuum hot press. That is, a pressurizing / heating process is performed in which the thermoplastic resin films 201 to 211, 20a in the laminate are heated from above and below in the laminating direction. In this step, the thermoplastic resin is softened and the plurality of thermoplastic resin films 201 to 211, 20a are integrated together, and the conductive particles in the conductive paste 60 are used as a sintered body. A wiring portion having the conductor pattern 50 is formed, and the conductive paste 60 and the electrode of the semiconductor chip 30 are electrically connected. Moreover, the part arrange | positioned in the terminal arrangement | positioning part 2021,2041,2051,2091,101 in the terminals 41-45 and the electrically conductive paste 60 are electrically connected.

  In this pressurizing / heating step, the resin films are integrated together to form the insulating base material 20, and the conductive particles in the conductive paste 60 are sintered to form the sintered body. A temperature of not less than the glass transition point and not more than the melting point of the plastic resin and a pressure of several MPa are maintained for a predetermined time. In the present embodiment, a press temperature of 280 ° C. to 330 ° C. and a pressure of 4 to 5 MPa are maintained for 5 minutes or longer (for example, 10 minutes).

  Here, the connection of the thermoplastic resin film part in a pressurization and a heating process is demonstrated. The laminated thermoplastic resin films 201 to 211, 20a are softened by the heating. At this time, since the pressure is applied, the softened thermoplastic resin films 201 to 211 and 20a are in close contact with the adjacent thermoplastic resin films 201 to 211 and 20a. Thereby, a plurality of thermoplastic resin films are integrated together, and the insulating base material 20 is formed.

  Moreover, the thermoplastic resin film adjacent to the site | part arrange | positioned at the cut-out part in the terminals 41-45 is a site | part arrange | positioned at the cut-out part in the terminals 41-45, receiving the pressure while flowing softened by heating. , It adheres to the entire surface except the part where the interlayer connection 60 is connected. That is, before the pressurizing / heating step, there is a gap between the portions arranged in the terminal arrangement portions 2021, 2041, 2051, 2091, and 2101 in the terminals 41 to 45 and the thermoplastic resin film. However, this gap is filled with a thermoplastic resin film (thermoplastic resin) after the pressurizing / heating step. In this way, the portions disposed in the terminal placement portions 2021, 2041, 2051, 2091, and 2101 in the terminals 41 to 45, such as the connection portions between the terminals 41 to 45 and the interlayer connection portion 60 (wiring portion), are thermoplastic resin. It can be sealed with a film (thermoplastic resin), and connection reliability can be improved.

  The same applies to the semiconductor chip 30. That is, the thermoplastic resin film adjacent to the semiconductor chip 30 disposed in the through hole 2071 is softened by heating and flows under pressure, and excludes a portion where the interlayer connection portion 60 in the semiconductor chip 30 is connected. Adheres to the entire surface. That is, there is a gap between the semiconductor chip 30 and the thermoplastic resin film before the pressurizing / heating step. However, this gap is filled with a thermoplastic resin film (thermoplastic resin) after the pressurizing / heating step. In this way, the semiconductor chip 30 can be sealed with the thermoplastic resin film (thermoplastic resin).

  Next, connection of the terminals 41 to 45, the conductor pattern 50, and the interlayer connection portion 60 in the pressurizing / heating step will be described. By the above heating, Sn (melting point: 232 ° C.) in the conductive paste 60 is melted and diffused to Ag particles in the conductive paste 60 to form an Ag—Sn alloy (melting point: 480 ° C.). Further, since pressure is applied to the conductive paste 60, an interlayer connection portion 60 made of an alloy integrated by sintering is formed in the via hole.

  Further, the melted Sn also interdiffuses with Cu constituting the conductor pattern 50. Thereby, a metal diffusion layer (Cu—Sn alloy layer) is formed at the interface between the interlayer connection portion 60 and the conductor pattern 50. Further, the melted Sn also interdiffuses with Cu constituting the terminals 41 to 45. Thereby, a metal diffusion layer (Cu—Sn alloy layer) is formed at the interface between the interlayer connection 60 and the terminals 41 to 45. Further, the melted Sn also interdiffuses with Ni constituting the electrodes 32 to 34, 361 and 362, whereby a metal diffusion layer (Ni--) is formed at the interface between the interlayer connection 60 and the electrodes 32 to 34, 361 and 362. Sn alloy layer) is formed.

  Next, the effect of the characteristic part in the semiconductor device 10 shown in the above embodiment will be described. As described above, the emitter electrode 32 which is a large current electrode is provided so as to surround the gate electrode 34 which is a small current electrode and the sensor electrodes 361 and 362. Furthermore, by including the conductor pattern 50, the terminals 43 to 45, and the interlayer connection portion 60 arranged in a stacked manner as a small current wiring portion electrically connected to the gate electrode 34 and the sensor electrodes 361 and 362, The small current wiring portion can be routed in the stacking direction and the orthogonal direction.

  Thus, even when the large current wiring portion (interlayer connection portion 60, emitter terminal 41, collector terminal 42) is provided to face the emitter electrode 32 and the collector electrode 33, which are large current electrodes, Rather than routing the small current wiring portion in the semiconductor chip 30, the degree of freedom in routing the small current wiring can be improved.

  As in the prior art, the small current wiring portion is routed in the semiconductor chip 30 in order to conduct the small current electrode provided on the semiconductor chip 30 and the pad provided on the outer peripheral portion of the semiconductor chip 30. In this case, it is necessary to provide the emitter electrode 32 so as to avoid the small current wiring portion. That is, the emitter electrode 32 cannot be provided in a ring shape. On the other hand, in the present embodiment, the degree of freedom of routing of the small current wiring can be improved, so that it is not necessary to route the small current wiring within the semiconductor chip 30. Therefore, as shown in FIG. 2A, the emitter electrode 32 can be provided in an annular shape. Therefore, the energization region can be expanded as compared with the prior art.

  In the present embodiment, a signal corresponding to the temperature of the semiconductor chip 30 is output, and the temperature sensor 35 disposed at the center of the surface of the semiconductor chip 30 is provided. An example including sensor electrodes 361 and 362 of the sensor 35 is employed. As described above, the small current wiring portion (sensor terminals 43 and 44, columnar portion 5060 (conductor pattern 50 and interlayer connection portion 60) electrically connected to the sensor electrodes 361 and 362 of the temperature sensor 35, as described above. ) Can also be routed in the stacking direction and in the orthogonal direction. Therefore, it becomes easy to arrange the temperature sensor 35 at the center of the surface of the semiconductor chip 30. In this manner, a signal corresponding to the temperature of the semiconductor chip 30 is output, and the temperature sensor 35 having the sensor electrodes 361 and 362 as the small current electrodes is arranged at the center of the surface of the semiconductor chip 30. This is preferable because the temperature of the portion of the semiconductor chip 30 where the temperature is highest can be measured. Even if the semiconductor device does not have the temperature sensor 35 or the semiconductor device in which the temperature sensor 35 is not arranged at the center of the surface of the semiconductor chip 30, the object of the present invention can be achieved.

  In the present embodiment, the IGBT includes a plurality of transistor structures, and the small current electrodes are electrically connected to the gates of the plurality of transistor structures, and are formed on the surface of the semiconductor chip 30. The example including the gate electrode 34 disposed in the center is adopted. As described above, with respect to the small current wiring portion (gate terminal 45, columnar portion 5060 (conductor pattern 50 and interlayer connection portion 60)) electrically connected to the gate electrode 34, the stacking direction and the orthogonal direction are also provided. Can be routed to. Therefore, it becomes easy to arrange the gate electrode 34 as the small current electrode at the center of the surface of the semiconductor chip 30. Thus, by disposing the gate electrode 34 in the center of the surface of the semiconductor chip 30, the difference in distance between the gate electrode 34 and the gate of each transistor structure can be minimized. Therefore, it is preferable because variations in the transmission time of the gate signal to each transistor structure can be suppressed and each transistor structure can be easily operated uniformly. Note that the object of the present invention can be achieved even in a semiconductor device in which the gate electrode 34 is not disposed at the center of the surface of the semiconductor chip 30.

  In the present embodiment, the small current wiring portion includes the conductor pattern 50 and the interlayer connection portion 60, has the columnar portion 5060 extending along the stacking direction, and is provided with the small current electrode. The large current wiring portion (emitter terminal 41) on the side is provided so as to penetrate the column direction (having an opening 413) and surround the columnar portion 5060. As a result, the small current wiring portion can be routed in the stacking direction through the portion through which the large current wiring portion penetrates, so that the degree of freedom in routing the small current wiring portion can be further improved. Note that the object of the present invention can be achieved even in a semiconductor device that does not include the columnar portion 5060 or the emitter terminal 41 having the opening 413.

  In addition, the small current wiring portion and the large current wiring portion include the conductor layer and the interlayer connection portion, so that both directions perpendicular to the stacking direction of the insulating base material 20 are obtained. It can be taken out (from any direction on the surface, side surface along the stacking direction).

  In the semiconductor device 10 according to the present embodiment, the insulating base material 20 includes at least a thermoplastic resin, and the semiconductor chip 30 is sealed with the thermoplastic resin of the insulating base material 20. Such a semiconductor device 10 can be formed by a batch stacking method known as PALAP as described above. Therefore, the manufacturing process of the semiconductor device 10 can be simplified.

  Further, as described above, the gate electrode 34 and the sensor electrodes 361 and 362 are provided on the surface of the semiconductor chip 30 perpendicular to the stacking direction, but the gate electrode 34 and the sensor electrodes 361 and 362 are provided on the surface. There is no need to provide a small current wiring portion to be connected. Thus, since the wiring on the semiconductor chip 30 (that is, the small current wiring portion on the surface orthogonal to the stacking direction in the semiconductor chip 30) can be omitted, the ineffective area on the semiconductor chip can be reduced.

(Modification 1)
In the above-described embodiment, the interlayer connecting portion 60 that connects the emitter electrode 32 and the connecting portion 412 of the emitter terminal 41 has the same planar shape as that of the emitter electrode 32 along the orthogonal direction. An example in which the area is the same as that of the emitter electrode 32 is adopted. Similarly, the interlayer connection portion 60 that connects the collector electrode 33 and the connection portion 422 of the collector terminal 42 has the same planar shape as the collector electrode 33 along the orthogonal direction, and the same planar area as the collector electrode 33. An example is adopted. However, the present invention is not limited to this.

  As shown in FIGS. 7A and 7B, in the semiconductor device 11 according to the first modification, the interlayer connection portion 60 that connects the emitter electrode 32 and the connection portion 412 of the emitter terminal 41 is along the orthogonal direction. A plane shape and a plane area different from those of the emitter electrode 32 are employed. Similarly, the interlayer connection portion 60 that connects the collector electrode 33 and the connection portion 412 of the collector terminal 42 is different from the collector electrode 33 in the shape of the plane along the orthogonal direction and the area of the plane.

  That is, as shown in FIGS. 7A and 7B, the emitter electrode 32 and the connection portion 412 of the emitter terminal 41 have a plurality of plane shapes and plane areas that are different from the emitter electrode 32 in the orthogonal direction. The interlayer connection portion 60 may be used for connection. Further, the collector electrode 33 and the connection portion 422 of the collector terminal 42 may be connected by a plurality of interlayer connection portions 60 having a planar shape along the orthogonal direction and a plane area different from that of the collector electrode 33. .

  7A and 7B, the emitter terminal 41 employs an example having an opening 413 for passing the columnar portion 5060, but the emitter terminal does not have the opening 413. Even 41 can be adopted. For example, the emitter electrode 32 and the emitter terminal 41 are connected by a plurality of layers of conductor patterns 50 and interlayer connection portions 60. A small-current wiring portion is provided between the emitter electrode 32 and the emitter terminal 41 in the stacking direction and between the conductor pattern 50 and the interlayer connection portion 60 connected to the emitter electrode 32 and the emitter terminal 41. .

  7A corresponds to FIG. 3 in the above-described embodiment, and FIG. 7B corresponds to FIG. 4 in the above-described embodiment. Further, the semiconductor device 11 in the first modification is the same as the semiconductor device 10 in the above-described embodiment except for the interlayer connection portion 60.

(Modification 2)
In addition, in the above-mentioned embodiment, although the terminals 41-45 which consist of metal pieces were employ | adopted, this invention is not limited to this.

  As shown in FIGS. 8 and 9, in the semiconductor device 12 in Modification 2, solder balls provided on the surface orthogonal to the stacking direction of the insulating base material 20 are employed as the terminals 71 to 74.

  In the second modification, as shown in FIG. 8, the large current wiring portion connected to the emitter electrode 32 includes an emitter terminal 71 made of a solder ball and an interlayer connection connected to the emitter electrode 32 of the semiconductor chip 30. A part 60; a metal piece 71a connected to the interlayer connection part 60; a conductor pattern 50 connecting the metal piece 71a and the emitter terminal 71; and an interlayer connection part 60.

  Similarly to the emitter terminal 41 described above, the metal piece 71a is a metal piece (metal plate) on a flat plate made of Cu, Au, Ag, Al, or an alloy containing at least one of these metals. Is uniformly provided as a whole. A connection portion connected to the emitter electrode 32 via the interlayer connection portion 60 and a portion (corresponding to the above-described terminal portion) extending from the connection portion in the orthogonal direction are provided. Further, the connection portion is provided with an opening 71a3 for enclosing the columnar portion 5060. However, unlike the above-described emitter terminal 41, the metal piece 71a is not exposed to the outside of the insulating base material 20.

  The conductor pattern 50 and the interlayer connection portion 60 that connect the metal piece 71a and the emitter terminal 71 connect the extended portion of the metal piece 71a and the emitter terminal 71. Here, the conductor pattern 50 and the interlayer connection portion 60 that connect the metal piece 71a and the emitter terminal 71 are regions facing the surface along the orthogonal direction of the extended portion of the metal piece 71a, and the semiconductor chip 30. It arrange | positions in the area | region between the side wall (surface which follows a lamination direction) and the side wall (surface which follows a lamination direction) of the insulating base material 20. FIG.

  As shown in FIG. 8, the interlayer connection portion 60 provided in the thermoplastic resin film 206 has one end connected to the extended portion of the metal piece 71a and the other end connected to the thermoplastic resin film. It is connected to a conductor pattern 50 disposed between 206 and the thermoplastic resin film 207. In addition, the interlayer connection part 60 provided in this thermoplastic resin film 206 is connected to the same surface as the surface where the interlayer connection part 60 connected to the emitter electrode 32 in the metal piece 71a is connected.

  Further, the interlayer connection portion 60 provided in the thermoplastic resin film 207 has one end connected to the conductor pattern 50 disposed between the thermoplastic resin film 206 and the thermoplastic resin film 207, and the other end. The portion is connected to the conductor pattern 50 disposed between the thermoplastic resin film 207 and the thermoplastic resin film 208.

  Further, the interlayer connection portion 60 provided in the thermoplastic resin film 208 has one end connected to the conductor pattern 50 disposed between the thermoplastic resin film 207 and the thermoplastic resin film 208, and the other end. The portion is connected to the conductor pattern 50 disposed between the thermoplastic resin film 208 and the thermoplastic resin film 209.

  Further, the interlayer connection portion 60 provided on the thermoplastic resin film 209 has one end connected to the conductor pattern 50 disposed between the thermoplastic resin film 208 and the thermoplastic resin film 209, and the other end. The portion is connected to the conductor pattern 50 disposed between the thermoplastic resin film 209 and the thermoplastic resin film 210.

  Further, the interlayer connection portion 60 provided in the thermoplastic resin film 210 has one end connected to the conductor pattern 50 disposed between the thermoplastic resin film 209 and the thermoplastic resin film 210 and the other end. The portion is connected to the conductor pattern 50 disposed between the thermoplastic resin film 210 and the thermoplastic resin film 211.

  The interlayer connection portion 60 provided on the thermoplastic resin film 211 has one end connected to the conductor pattern 50 disposed between the thermoplastic resin film 210 and the thermoplastic resin film 211, and the other end. The portion is connected to the emitter terminal 71.

  As shown in FIG. 8, the conductor pattern 50, the interlayer connection portion 60, and the emitter terminal 71 that connect the emitter electrode 32 and the emitter terminal 71 in each of the thermoplastic resin films 207 to 211 are formed on the thermoplastic resin film 206. It is provided on the same straight line along the stacking direction with respect to each provided interlayer connection 60. The five-layer conductor pattern 50 that connects the metal piece 71a and the emitter terminal 71 preferably has the same area and shape of the surface along the orthogonal direction as the extended part of the metal piece 71a.

  FIG. 8 is a cross-sectional view in which three interlayer connection portions 60 are provided as interlayer connection portions for connecting the emitter electrode 32 and the emitter terminal 71 to each of the thermoplastic resin films 206 to 211. ing. However, each of the thermoplastic resin films 206 to 211 is provided with a large number of interlayer connection portions 60 instead of only three as a large current wiring portion connected to the emitter electrode 32 in order to ensure current capacity. It is. Therefore, not only three emitter terminals 71 but also a large number are provided.

  That is, the thermoplastic resin film 206 has a large number of interlayer connections as a large current wiring portion connected to the emitter electrode 32 according to the size of the surface along the orthogonal direction of the extended portion of the metal piece 71a. A portion 60 is provided.

  In the second modification, as shown in FIG. 9, the large current wiring portion connected to the collector electrode 33 is connected to the collector terminal 72 made of a solder ball and the collector electrode 33 of the semiconductor chip 30. Interlayer connection portion 60, metal piece 72 a connected to this interlayer connection portion 60, and interlayer connection portion 60 that connects this metal piece 72 a and collector terminal 72 are included.

  Similarly to the collector terminal 42 described above, the metal piece 72a is a metal piece (metal plate) on a flat plate made of Cu, Au, Ag, Al, or an alloy containing at least one of these metals. Is uniformly provided as a whole. A connection portion connected to the collector electrode 33 via the interlayer connection portion 60 and a portion (corresponding to the above-described terminal portion) extending from the connection portion in the orthogonal direction are provided. However, unlike the collector terminal 42 described above, the metal piece 72 a is not exposed to the outside of the insulating base material 20.

  The interlayer connection portion 60 that connects the metal piece 72a and the collector terminal 72 connects the connection portion and the extended portion of the metal piece 72a to the collector terminal 72. In other words, the interlayer connection portion 60 provided on the thermoplastic resin film 211 has one end connected to the connection portion and the extended portion of the metal piece 72 a and the other end connected to the collector terminal 72. Is done. In addition, here, the interlayer connection portion 60 that connects the metal piece 72a and the collector terminal 72 is disposed in a region facing the surface along the orthogonal direction of the metal piece 72a. The interlayer connection 60 that connects the metal piece 72a and the collector terminal 72 is connected to the opposite surface of the surface of the metal piece 72a to which the interlayer connection 60 connected to the collector electrode 33 is connected.

  FIG. 9 shows a cross-sectional view in which eleven interlayer connection portions 60 are provided as interlayer connection portions for connecting the collector electrode 33 and the collector terminal 72 to the thermoplastic resin film 211. . However, in order to ensure current capacity, the thermoplastic resin film 211 is provided with not only 11 but also a large number of interlayer connection portions 60 as large current wiring portions connected to the collector electrode 33. Therefore, not only 11 collector terminals 72 but also many are provided.

  That is, the thermoplastic resin film 211 is provided with a large number of interlayer connection portions 60 according to the size of the surface along the orthogonal direction of the connection portion and the extended portion of the metal piece 72a. And the emitter terminal 71 is provided on the same straight line along a lamination direction with respect to each interlayer connection part 60 provided in the thermoplastic resin film 211. FIG.

  In the second modification, as shown in FIG. 8, the small current wiring portion connected to the sensor electrode 361 is connected to the sensor terminal 73 made of a solder ball and the sensor electrode 361 of the semiconductor chip 30. The columnar portion 5060, the metal piece 73a connected to the columnar portion 5060, the conductor pattern 50 that connects the metal piece 73a and the sensor terminal 73, and the interlayer connection portion 60 are included. Since the same applies to the small current wiring portion connected to the sensor electrode 362, detailed description and illustration are omitted. Further, as shown in FIG. 9, the same applies to the small current wiring portion connected to the gate electrode 34, and thus detailed description thereof is omitted. However, regarding the small current wiring portion connected to the gate electrode 34, the metal piece 74a is used instead of the metal piece 73a, and the gate terminal 74 is used instead of the sensor terminal 73.

  Similarly to the sensor terminal 43 described above, the metal piece 73a is a metal piece (metal plate) on a flat plate made of Cu, Au, Ag, Al, or an alloy containing at least one of these metals. Is uniformly provided as a whole. However, unlike the sensor terminal 43 described above, the metal piece 73 a is not exposed to the outside of the insulating base material 20. Moreover, the interlayer connection part 60 which comprises the columnar part 5060 among the interlayer connection parts 60 provided in the thermoplastic resin film 203 is connected to one edge part in the orthogonal direction of the metal piece 73a. On the other hand, an interlayer connection portion 60 that connects the metal piece 73a and the sensor terminal 73 among the interlayer connection portions 60 provided on the thermoplastic resin film 203 is connected to the other end portion in the orthogonal direction of the metal piece 73a. Is done.

  The conductor pattern 50 and the interlayer connection portion 60 that connect the metal piece 73 a and the sensor terminal 73 connect a part of the metal piece 73 a and the sensor terminal 73. Here, the conductor pattern 50 and the interlayer connection portion 60 that connect the metal piece 73a and the sensor terminal 73 are regions facing the surface along the orthogonal direction of the end portion (the above-described opposite end portion) of the metal piece 73a. It is arranged in a region between the side wall (surface along the stacking direction) of the semiconductor chip 30 and the side wall (surface along the stacking direction) of the insulating substrate 20.

  As shown in FIG. 8, the interlayer connection portion 60 provided in the thermoplastic resin film 203 has one end connected to a part of the metal piece 73a and the other end connected to the thermoplastic resin film 203 and the thermoplastic resin. It is connected to the conductor pattern 50 arranged between the resin film 204. In addition, the interlayer connection part 60 provided in this thermoplastic resin film 203 is connected to the same surface as the surface where the interlayer connection part 60 which comprises the columnar part 5060 in the metal piece 73a was connected.

  Moreover, the interlayer connection part 60 provided in the thermoplastic resin film 204 has one end connected to the conductor pattern 50 disposed between the thermoplastic resin film 203 and the thermoplastic resin film 204, and the other end. The portion is connected to the conductor pattern 50 disposed between the thermoplastic resin film 204 and the thermoplastic resin film 205.

  Further, the interlayer connection portion 60 provided in the thermoplastic resin film 205 has one end connected to the conductor pattern 50 disposed between the thermoplastic resin film 204 and the thermoplastic resin film 205, and the other end. The portion is connected to the conductor pattern 50 disposed between the thermoplastic resin film 205 and the thermoplastic resin film 206.

  Further, the interlayer connection portion 60 provided in the thermoplastic resin film 206 has one end connected to the conductor pattern 50 disposed between the thermoplastic resin film 205 and the thermoplastic resin film 206, and the other end. The portion is connected to the conductor pattern 50 disposed between the thermoplastic resin film 206 and the thermoplastic resin film 207.

  Further, the interlayer connection portion 60 provided in the thermoplastic resin film 207 has one end connected to the conductor pattern 50 disposed between the thermoplastic resin film 206 and the thermoplastic resin film 207, and the other end. The portion is connected to the conductor pattern 50 disposed between the thermoplastic resin film 207 and the thermoplastic resin film 208.

  Further, the interlayer connection portion 60 provided in the thermoplastic resin film 208 has one end connected to the conductor pattern 50 disposed between the thermoplastic resin film 207 and the thermoplastic resin film 208, and the other end. The portion is connected to the conductor pattern 50 disposed between the thermoplastic resin film 208 and the thermoplastic resin film 209.

  Further, the interlayer connection portion 60 provided on the thermoplastic resin film 209 has one end connected to the conductor pattern 50 disposed between the thermoplastic resin film 208 and the thermoplastic resin film 209, and the other end. The portion is connected to the conductor pattern 50 disposed between the thermoplastic resin film 209 and the thermoplastic resin film 210.

  Further, the interlayer connection portion 60 provided in the thermoplastic resin film 210 has one end connected to the conductor pattern 50 disposed between the thermoplastic resin film 209 and the thermoplastic resin film 210 and the other end. The portion is connected to the conductor pattern 50 disposed between the thermoplastic resin film 210 and the thermoplastic resin film 211.

  The interlayer connection portion 60 provided on the thermoplastic resin film 211 has one end connected to the conductor pattern 50 disposed between the thermoplastic resin film 210 and the thermoplastic resin film 211, and the other end. Is connected to the sensor terminal 73.

  As shown in FIG. 8, the interlayer connection portion 60 of each thermoplastic resin film 204 to 211 and the sensor terminal 73 are the same along the stacking direction with respect to each interlayer connection portion 60 provided on the thermoplastic resin film 203. It is provided on a straight line.

  By doing in this way, since the terminal does not protrude from the side wall of the insulating base material 20, it is preferable because a large number of semiconductor devices 12 can be formed integrally and divided into each semiconductor device 12. That is, it is preferable because a large number of semiconductor devices 12 can be fixed from a large substrate on which a large number of semiconductor devices 12 are formed.

  In addition, in FIG. 8, sectional drawing with which the one interlayer connection part 60 is provided in each thermoplastic resin film 203-211 is shown. However, each of the thermoplastic resin films 203 to 211 may be provided with not only one but a plurality of interlayer connection portions 60 as a small current wiring portion connected to the sensor electrode 361. Therefore, a plurality of sensor terminals 73 may be provided instead of only one.

  That is, the thermoplastic resin film 203 may be provided with a plurality of interlayer connection portions 60 according to the size of the surface along the orthogonal direction of the end portion of the metal piece 73a. And the interlayer connection part 60 of each thermoplastic resin film 204-211 and the terminal 73 for sensors are provided on the same straight line along a lamination direction with respect to each interlayer connection part 60 provided in the thermoplastic resin film 203. FIG. You may do it.

  8 corresponds to FIG. 3 in the above-described embodiment, and FIG. 9 corresponds to FIG. 4 in the above-described embodiment. In addition, the semiconductor device 12 in Modification 2 is the same as the semiconductor device 10 in the above-described embodiment except for the small current wiring portion and the large current wiring portion. Also in the second modification, as in the first modification, the emitter electrode 32 and the metal piece 71a, and the collector electrode 33 and the metal piece 72a may be connected by a plurality of interlayer connection portions 60.

  A metal piece may be used in place of the conductor pattern 50 and the interlayer connection portion 60 that connect the metal piece 71a and the emitter terminal 71 in the second modification. As the metal piece, for example, a metal piece having a columnar shape or a quadrangular prism shape, which is equivalent to the area of the portion where the surface facing the extended portion is extended, can be employed. Further, the length of the metal piece in the stacking direction can be set to the extent that the plurality of conductor patterns 50 and the interlayer connection portion 60 are added.

  Similarly, a metal piece may be used in place of the conductor pattern 50 and the interlayer connection portion 60 that connect the metal piece 73 a and the sensor terminal 73. Similarly, a metal piece may be used instead of a part of the conductor pattern 50 and the interlayer connection portion 60 that connect the metal piece 74 a and the gate terminal 74.

  Moreover, although the example which connects the metal piece 72a and the collector terminal 72 by the interlayer connection part 60 provided in the thermoplastic resin film 211 of one layer was employ | adopted, the metal piece 71a and the emitter terminal 71 are connected. As in the case of the conductor pattern 50 and the interlayer connection portion 60, a plurality of layers of conductor patterns 50 may be connected to the interlayer connection portion 60. In this case as well, a metal piece may be used in place of the conductor pattern 50 and the interlayer connection portion 60 that connect the metal piece 72 a and the collector terminal 72.

(Modification 3)
In the second modification described above, the terminals 71 to 74 made of solder balls are employed, but the present invention is not limited to this.

  As shown in FIGS. 10 and 11, in the semiconductor device 13 in Modification 3, Cu, Au, Ag, Al, or the like provided as a terminal so as to protrude from the surface orthogonal to the stacking direction of the insulating base material 20. The terminals 711 to 741 made of metal pieces made of an alloy containing at least one kind of these metals are employed.

  In the third modification, as shown in FIG. 10, the large current wiring portion connected to the emitter electrode 32 includes an emitter terminal 711 made of a metal piece and an interlayer connection connected to the emitter electrode 32 of the semiconductor chip 30. Part 60, metal piece 711a connected to this interlayer connection part 60, and interlayer connection part 60 connecting this metal piece 711a and emitter terminal 711.

  Since the metal piece 711a is the same as the metal piece 71a in the second modification, the description thereof is omitted. However, in the metal piece 11a, reference numeral 711a3 is given to an opening for enclosing the columnar portion 5060. On the other hand, the metal piece used as the emitter terminal 711 has a cylindrical shape or a quadrangular prism shape, for example, the area of the surface facing the extended portion is equal to the area of the extended portion. A part of the metal piece used as the emitter terminal 711 is disposed inside the insulating base material 20, and the other part is provided so as to protrude outside the insulating base material 20. Further, the metal piece 711 a and the emitter terminal 711 are connected by an interlayer connection portion 60 provided on the thermoplastic resin film 206. In addition, the interlayer connection part 60 provided in this thermoplastic resin film 206 is connected to the same surface as the surface to which the interlayer connection part 60 connected to the emitter electrode 32 in the metal piece 711a is connected.

  It should be noted that a large number of interlayer connection portions 60 for connecting the metal piece 711a and the emitter terminal 711 are provided as a large current wiring portion connected to the emitter electrode 32 in order to secure a current capacity. Is. That is, a large number of interlayer connection portions 60 that connect the metal piece 711a and the emitter terminal 711 are provided according to the size of the surface along the orthogonal direction of the extended portion of the metal piece 711a.

  Further, in Modification 3, as shown in FIG. 11, the large current wiring portion connected to the collector electrode 33 is connected to the collector terminal 721 made of a metal piece and the collector electrode 33 of the semiconductor chip 30. It includes an interlayer connection 60, a metal piece 721 a connected to the interlayer connection 60, and an interlayer connection 60 that connects the metal piece 721 a and the collector terminal 721.

  Since the metal piece 721a is the same as the metal piece 72a in the modification 2, description is abbreviate | omitted. Further, the metal piece used as the collector terminal 721 is the same as the above-described emitter terminal 711, and thus the description thereof is omitted. A part of the metal piece used as the collector terminal 721 is disposed in the insulating base material 20, and the other part is provided so as to protrude outside the insulating base material 20. Further, the metal piece 721a and the collector terminal 721 are connected by an interlayer connection portion 60 provided on the thermoplastic resin film 211. In addition, the interlayer connection part 60 provided in this thermoplastic resin film 211 is connected to the surface opposite to the surface where the interlayer connection part 60 connected to the collector electrode 33 in the metal piece 721a is connected.

  It should be noted that a large number of interlayer connection portions 60 for connecting the metal pieces 721a and the collector terminals 721 are provided in addition to three as large current wiring portions connected to the collector electrode 32 in order to ensure current capacity. Is. That is, a large number of interlayer connection portions 60 that connect the metal piece 721a and the collector terminal 721 are provided according to the size of the surface along the orthogonal direction of the extended portion of the metal piece 721a.

  Further, in the third modification, in order to support the collector terminal 721, the thermoplastic resin film is increased by one sheet as compared with the above-described embodiment and the first and second modifications. Therefore, the semiconductor device 13 includes the thermoplastic resin films 201 to 212 as the insulating base material 20.

  Further, in the third modification, as shown in FIG. 10, the small current wiring portion connected to the sensor electrode 361 is connected to the sensor terminal 731 made of a metal piece and the sensor electrode 361 of the semiconductor chip 30. The columnar part 5060, the metal piece 731a connected to the columnar part 5060, the conductor pattern 50 and the interlayer connection part 60 connecting the metal piece 731a and the sensor terminal 731 are included.

  Since the metal piece 731a is the same as the metal piece 73a in the modification 2, description is abbreviate | omitted. On the other hand, the metal piece used as the sensor terminal 731 has, for example, a cylindrical shape or a quadrangular prism shape. A part of the metal piece used as the sensor terminal 731 is disposed inside the insulating base material 20, and the other part is provided so as to protrude outside the insulating base material 20. In addition, the metal piece 731a and the sensor terminal 731 are connected by the interlayer conductor 60 provided on the three layers of the conductor pattern 50 and the thermoplastic resin films 203 to 206. In addition, the interlayer connection part 60 provided in this thermoplastic resin film 203 is connected to the same surface as the surface to which the columnar part 5060 in the metal piece 731a is connected.

  Since the same applies to the small current wiring portion connected to the sensor electrode 362, detailed description and illustration are omitted. Further, as shown in FIG. 11, the same applies to the small current wiring portion connected to the gate electrode 34, and thus detailed description thereof is omitted. However, regarding the small current wiring portion connected to the gate electrode 34, the metal piece 741a is used instead of the metal piece 731a, and the gate terminal 741 is used instead of the sensor terminal 731.

  In addition, the emitter terminal 711 and the collector terminal 721 used as the large current wiring section are sufficiently thicker than the sensor terminal 731 and the gate terminal 741 used as the small current wiring section in order to secure current capacity. A piece of metal (large volume) is used. Similarly, the metal pieces 711a and 721a used as the large current wiring portions are sufficiently thicker (larger in volume) than the metal pieces 731a and 741a used as the small current wiring portions in order to ensure current capacity. Is used.

  Note that FIG. 10 corresponds to FIG. 3 in the above-described embodiment, and FIG. 11 corresponds to FIG. 4 in the above-described embodiment. The semiconductor device 13 in the third modification is the same as the semiconductor device 12 in the second modification except for the small current wiring portion and the large current wiring portion. Also in the third modification, similarly to the first modification, the emitter electrode 32 and the metal piece 711 a and the collector electrode 33 and the metal piece 721 a may be connected by a plurality of interlayer connection portions 60.

(Modification 4)
In the second modification described above, the emitter terminal 71 and the collector terminal 72 which are part of the large current wiring part, and the sensor terminal 73 and the gate terminal 74 which are part of the small current wiring part. The example which provided so that it may protrude outside from the same surface of the insulating base material 20 was employ | adopted. However, the present invention is not limited to this.

  As shown in FIG. 12, in the semiconductor device 14 according to the modified example 4, the emitter terminal 71 and the collector terminal 72 which are part of the large current wiring part, and the sensor part which is a part of the small current wiring part. Terminals 73 are provided so as to protrude from different surfaces of the insulating base material 20 to the outside. Although not shown in FIG. 12, the terminal connected to the sensor electrode 362 and the gate terminal 74 are similarly configured as an emitter terminal 71 and a collector terminal 72 which are part of the large current wiring portion. Protrudes from different surfaces. FIG. 12 corresponds to FIG. 3 in the above-described embodiment.

  The semiconductor device 14 in the modification 4 is the same as the semiconductor device 12 in the modification 2 described above except for the protruding direction of a terminal (for example, the terminal 73) that is a part of the small current wiring portion. In the fourth modification, as in the first modification, the emitter electrode 32 and the metal piece 71a, and the collector electrode 33 and the metal piece 72a may be connected by a plurality of interlayer connection portions 60.

(Modification 5)
In the third modification described above, the emitter terminal 711 and the collector terminal 721 which are part of the large current wiring part, and the sensor terminal 73 and the gate terminal 74 which are part of the small current wiring part. The example which provided so that it may protrude outside from the same surface of the insulating base material 20 was employ | adopted. However, the present invention is not limited to this.

  As shown in FIG. 13, in the semiconductor device 15 according to the modified example 5, the emitter terminal 711 and the collector terminal 721 (hidden in the emitter terminal 711) which are part of the large current wiring portion, and the small current The sensor terminal 731 which is a part of the wiring part for the sensor is provided so as to protrude outside from a different surface of the insulating substrate 20. In addition, although not shown in FIG. 13, the terminal connected to the sensor electrode 362 and the gate terminal 741 are also the emitter terminal 711 and the collector terminal 721 which are part of the large current wiring portion. Protrudes from different surfaces. FIG. 13 corresponds to FIG. 3 in the above-described embodiment.

  Further, the semiconductor device 15 in the modification 5 is the same as the semiconductor device 13 in the modification 3 described above except for the protruding direction of a terminal (for example, the terminal 731) which is a part of the small current wiring portion. Also in the fifth modification, as in the first modification, the emitter electrode 32 and the metal piece 711a, and the collector electrode 33 and the metal piece 721a may be connected by a plurality of interlayer connection portions 60.

(Modification 6)
Moreover, in the above-mentioned embodiment and the modifications 1-5, although the semiconductor device 10-15 which embedded one semiconductor chip 30 in the inside of the insulating base material 20, ie, was incorporated, this invention is limited to this. Is not to be done.

  As shown in FIG. 14, in the semiconductor device 16 in Modification 6, a plurality of semiconductor chips 30 (here, two semiconductor chips 30) are embedded, that is, built in the insulating base material 20. The semiconductor device 16 is a system-in-package (SiP) having a so-called 2in1Package structure. That is, the semiconductor device 16 constitutes one of the U-phase arm, V-phase arm, and W-phase arm of the inverter circuit. In the semiconductor device 16, as shown in FIG. 15, the semiconductor chips 30 are arranged in the same direction on the same virtual plane along the orthogonal direction. That is, the emitter electrode 32 of each semiconductor chip 30 faces the same direction in the stacking direction.

  As shown in FIG. 14, the semiconductor device 16 includes sensor terminals 43 and 44 connected to the sensor electrodes 361 and 362 of each semiconductor chip 30 and each semiconductor chip as a part of the small current wiring portion. A gate terminal 45 connected to 30 gate electrodes 34 is provided. Since the sensor terminals 43 and 44 and the gate terminal 45 are the same as those in the above-described embodiment, the description thereof is omitted.

  As shown in FIGS. 14 and 15, the semiconductor device 16 includes an emitter terminal 41 a and an interlayer connecting the emitter electrode 32 of one semiconductor chip 30 and the emitter terminal 41 a as a part of the large current wiring portion. A connection portion 60, a midpoint terminal 46b, and an interlayer connection portion 60 for connecting the collector electrode 33 of the semiconductor chip 30 and the midpoint terminal 46b are provided. Further, the semiconductor device 16 includes, as part of a large current wiring portion, a midpoint connection portion 46a, an interlayer connection portion 60 that connects the emitter electrode 32 of the other semiconductor chip 30 and the midpoint connection portion 46a, Conductor pattern 50 and interlayer connection 60 that connect point connection 46a and midpoint terminal 46b, collector terminal 42a, and interlayer connection 60 that connects collector electrode 33 of semiconductor chip 30 and collector terminal 42a. Is provided.

  As shown in FIG. 16D, the emitter terminal 41a includes a terminal portion 41a1, a connection portion 41a2, and an opening portion 41a3, and the shape thereof is slightly different from that of the emitter terminal 41 in the above-described embodiment. Since the basic configuration is substantially the same, description thereof is omitted. Further, as shown in FIG. 16A, the collector terminal 42a includes a terminal portion 42a1 and a connection portion 42a2. Although the shape is slightly different from the collector terminal 42 in the above-described embodiment, Since the configuration is substantially the same, the description is omitted. Further, as shown in FIG. 16 (c), the midpoint terminal 46b includes a terminal portion 46b1 and a connection portion 46b2, and is slightly different in shape from the collector terminal 42a in the above-described embodiment. Since the general configuration is substantially the same, the description is omitted.

  The midpoint connection portion 46a is a metal piece (metal plate) on a flat plate made of Cu, Au, Ag, Al, or an alloy containing at least one of these metals, and has a thickness along the stacking direction as a whole. Uniformly provided. As shown in FIG. 16 (b), in the state of being arranged in the insulating base material 20, it is arranged to face the collector electrode 33, and the collector electrode 33 of the semiconductor chip 30 via the interlayer connection portion 60. A connecting portion 46a1 that is a portion electrically connected to the opening and an opening 46a2 penetrating in the stacking direction are provided in a state where the connecting portion 46a1 is disposed in the insulating base material 20. In the opening 46 a 2, a columnar portion 5060 (not shown) is provided in a state of being disposed in the insulating base material 20.

  In addition, the area of the plane along the orthogonal direction of the connecting portion 46a1 is larger than the area of the plane along the orthogonal direction of the collector electrode 33. Therefore, a part of the connection part 46 a 1 is connected to the collector electrode 33 via the interlayer connection part 60.

  The midpoint connection portion 46 a extends from a region facing the one semiconductor chip 30 to a region between the semiconductor chips 30. Similarly, the midpoint terminal 46 b extends from a region facing the other semiconductor chip 30 to a region between the semiconductor chips 30. The midpoint connection portion 46 a and the midpoint terminal 46 b are connected via the conductor pattern 50 and the interlayer connection portion 60 in the region between the semiconductor chips 30. Thereby, the two semiconductor chips 30 are connected.

  The semiconductor device 16 according to the modified example 6 has the above-described basic configuration except that the semiconductor device 16 includes a plurality of semiconductor chips 30 and the midpoint connection portion 46a and the midpoint terminal 46b. This is the same as the semiconductor device 10 in the embodiment. Also in the modified example 6, as in the modified example 1, the emitter electrode 32 and the emitter terminal 41a, the emitter electrode 32 and the midpoint connection portion 46a, the collector electrode 33 and the collector terminal 42a, the collector electrode 33 and the midpoint Each of the terminals 46b may be connected by a plurality of interlayer connection portions 60.

(Modification 7)
Further, in the above-described modified example 6, the example in which the semiconductor chips 30 are connected via the midpoint connection portion 46a, the conductor pattern 50, and the interlayer connection portion 60 is employed, but the present invention is limited to this. Is not to be done. That is, the wiring method between the semiconductor chips 30 is not limited to that shown in the sixth modification.

  The difference between the semiconductor device 17 in the modified example 7 and the semiconductor device 16 in the modified example 6 is a wiring structure between the semiconductor chips 30 (a structure in which wiring is performed without using the midpoint connection portion). Since the other points are the same, the description is omitted. In FIG. 17, reference numeral 41b is an emitter terminal, and reference numeral 42b is a collector terminal. Since the emitter terminal 41b and the collector terminal 42b are the same as the above-described emitter terminal and collector terminal, description thereof will be omitted.

  As shown in FIG. 17, in the semiconductor device 17 according to the modified example 7, each semiconductor chip 30 is arranged in the opposite direction on the same virtual plane along the orthogonal direction. That is, the emitter electrode 32 of each semiconductor chip 30 faces in the opposite direction in the stacking direction.

  As shown in FIG. 17, the midpoint terminal 46c (high current wiring portion) is a metal piece (metal plate) on a flat plate made of Cu, Au, Ag, Al, or an alloy containing at least one of these metals. ), And the thickness along the stacking direction is uniformly provided as a whole. The midpoint terminal 46 c is provided so as to straddle the two semiconductor chips 30. The midpoint terminal 46 c is connected to the collector electrode 33 of one semiconductor chip 30 via the interlayer connection portion 60 and is connected to the emitter electrode 32 of the other semiconductor chip 30 via the interlayer connection portion 60. The The midpoint terminal 46c includes an opening (not shown) in which the columnar portion 5060 is disposed.

  As described above, even if the semiconductor chips 30 are connected to each other by the midpoint terminal 46c without using the midpoint connection portion, the 2in1Package structure can be obtained.

  Also in the modified example 7, as in the modified example 1, the collector electrode 33 of one semiconductor chip 30, the emitter electrode 32 and the midpoint terminal 46 c of the other semiconductor chip 30, and the emitter electrode 32 of the one semiconductor chip 30. And the emitter terminal 41b, the collector electrode 33 of the other semiconductor chip 30 and the collector terminal 42b may be connected by a plurality of interlayer connection portions 60.

(Modification 8)
Moreover, in the above-mentioned embodiment and the modifications 1-7, although the semiconductor device 10-17 which embed | buries, ie, incorporates the 1 or 2 semiconductor chip 30 inside the insulating base material 20, was adopted. It is not limited to this.

  As shown in FIG. 18, in the semiconductor device 18 according to the modified example 8, six semiconductor chips 30 are embedded, that is, built in the insulating base material 20. The semiconductor device 16 is a system-in-package (SiP) having a so-called 6in1Package structure. Therefore, three semiconductor devices 16 of the above-described modification 6 are connected to form a single chip. That is, the semiconductor device 16 constitutes an inverter circuit including a U-phase arm, a V-phase arm, and a W-phase arm. In the semiconductor device 18, as shown in FIG. 18, the semiconductor chips 30 are arranged in the same direction on the same virtual plane along the orthogonal direction. That is, the emitter electrode 32 of each semiconductor chip 30 faces the same direction in the stacking direction.

  The semiconductor device 18 has, as a large current wiring portion, midpoint connection portions 46d1 to 46d3, midpoint terminals 46e1 to 46e3, which connect the emitter electrode 32 and the collector electrode 33 of the two semiconductor chips 30, and A conductor pattern 50 and an interlayer connection 60 are provided to connect the midpoint connection portions 46d1 to 46d3 and the midpoint terminals 46e1 to 46e3. Further, three emitter vertical connection portions 41 c 1 connected to the emitter electrodes 32 of the three semiconductor chips 30 via the interlayer connection portion 60, and connections to the collector electrodes 33 of the three semiconductor chips 30 via the interlayer connection portion 60. The three collector vertical connection portions 42c1, the interlayer connection 60 connecting the emitter electrode 32 and the emitter vertical connection portion 41c1, and the interlayer connection connecting the collector electrode 33 and the collector vertical connection portion 42c1. The unit 60 is provided. Further, an emitter terminal 41c2 disposed across the three emitter vertical connection portions 41c1, an interlayer connection portion 60 connecting the three emitter vertical connection portions 41c1 and the emitter terminal 41c2, and three A collector terminal 42c2 disposed across the collector vertical connection 42c1 and an interlayer connection 60 for connecting the three collector vertical connection 42c1 and the collector terminal 42c2 are provided.

  These midpoint connection portions 46d1 to 46d3, midpoint terminals 46e1 to 46e3, emitter vertical connection portions 41c1, collector vertical connection portions 42c1, emitter terminals 41c2, and collector terminals 42c2 are Cu, Au, Ag. , Al, or a metal piece (metal plate) on a flat plate made of an alloy containing at least one of these metals, and has a uniform thickness along the stacking direction. Further, the midpoint connection portions 46d1 to 46d3, the midpoint terminals 46e1 to 46e3, the emitter terminal 41c2, and the collector terminal 42c2 are slightly different from those described above, but the basic configuration is substantially the same. Description is omitted.

  The emitter vertical connection portion 41c1 and the collector vertical connection portion 42c1 are provided in the insulating base material 20 with an opening for the columnar portion 5060, similarly to the midpoint connection portion. is there. The metal piece is used to connect the emitter electrode 32 and the emitter terminal 41c2 and the collector electrode 33 and the collector terminal 42c2. However, the emitter electrode 32 and the emitter terminal 41 c 2 may be connected via the conductor pattern 50 and the interlayer connection portion 60. Similarly, the collector electrode 33 and the collector terminal 42c2 may be connected via the conductor pattern 50 and the interlayer connection portion 60.

  In the modified example 8, similarly to the modified example 1, the emitter electrode 32 and each metal piece, the collector electrode 33 and each metal piece, and the metal piece and the metal piece are connected by a plurality of interlayer connection portions 60. It may be.

  In the above-described embodiment and Modifications 1 to 8, the terminals (metal pieces and solder balls) that are part of the small current wiring portion and the large current wiring portion protrude from the insulating substrate 20. However, the present invention is not limited to this. In the present invention, a part of the small current wiring part and the large current wiring part may include an exposed part that is exposed to the outside of the insulating base material 20 and functions as a terminal.

  In other words, the portions functioning as terminals of the small current wiring portion and the large current wiring portion are provided so as to be exposed to the outside of the insulating base material 20 at a position recessed by one step from the surface of the insulating base material 20. May be. In other words, the terminals that are part of the small current wiring portion and the large current wiring portion may be provided at a position recessed with respect to the surface of the surrounding insulating base material 20.

  Further, the semiconductor device may be provided with a female connector in which a portion functioning as a terminal of the small current wiring portion and the large current wiring portion is exposed on the wall surface of the hole provided in the insulating base material 20. . A male terminal is inserted into the hole in which the portions functioning as terminals of the small current wiring portion and the large current wiring portion are exposed.

  In addition, although the modifications 1-8 demonstrated so far can also each be implemented independently, it is also possible to implement combining suitably.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not restrict | limited to the embodiment mentioned above at all, and various deformation | transformation are possible in the range which does not deviate from the meaning of this invention.

  10-18 Semiconductor device, 20 Insulating substrate, 201-212, 20a Thermoplastic resin film, 2021, 2041, 2051, 2091, 2101 Terminal arrangement part, 2071 Through hole, 30 Semiconductor chip, 31 Semiconductor substrate, 32 Emitter electrode, 321 opening, 33 collector electrode, 34 gate electrode, 35 temperature sensor, 361, 362 sensor electrode, 71a-74a metal piece, 711a-741a metal piece, 41, 41a, 41b, 41c2, 71, 711 emitter terminal, 411, 41a1 terminal, 412, 41a2 connection, 413, 41a3 opening, 41c1 emitter vertical connection, 42, 42a, 42b, 42c2, 72, 721 collector terminal, 421, 42a1 terminal, 422, 42a2 Connection part, 42c1 collection Vertical connection part, 43, 44, 73, 731 Sensor terminal, 45, 74, 741 Gate terminal, 46a, 46d1-46d3 Middle point connection part, 46a1 connection part, 46a2 opening part, 46b, 46c, 46e1 ˜46e3 Middle point terminal, 46b1 terminal part, 46b2 connection part, 50 conductor pattern, 60 interlayer connection part, 5060 columnar part

Claims (10)

An insulating substrate;
A wiring portion provided on the insulating base material and including a conductor layer disposed in a stacked manner and an interlayer connection portion formed in a via hole;
A semiconductor chip in which an element is formed and sealed in the insulating substrate;
With
The semiconductor chip is
A power transistor as the element;
A large current electrode provided on each of both surfaces orthogonal to the laminating direction of the conductor layer, through which a large current flows in the power transistor;
A small current electrode provided on at least one of the two surfaces, through which a smaller current flows than the large current electrode; and
The large current electrode provided on the same surface as the small current electrode is provided so as to surround the small current electrode,
The wiring portion is electrically connected to the large current electrode, and is electrically connected to the large current wiring portion including the conductor layer facing the large current electrode, and the small current electrode, A small current wiring portion including the conductor layer and the interlayer connection portion insulated from the large current wiring portion by an insulating base;
A semiconductor device comprising: A signal corresponding to the temperature of the semiconductor chip is output, and includes a temperature sensor disposed at the center of the surface of the semiconductor chip,
The semiconductor device according to claim 1, wherein the small current electrode includes a sensor electrode of the temperature sensor. The power transistor includes a plurality of transistor structures,
3. The small current electrode includes a gate electrode electrically connected to each gate of the plurality of transistor structure portions and disposed at a central portion of the surface of the semiconductor chip. The semiconductor device described. The small current wiring portion includes the conductor layer and the interlayer connection portion, and includes a columnar portion extending along the stacking direction,
4. The large current wiring portion on the side where the small current electrode is provided is provided so as to penetrate in the stacking direction and surround the columnar portion. The semiconductor device according to item.   5. The semiconductor device according to claim 1, wherein the conductor layer facing the large current electrode is thicker in the stacking direction than the other conductor layers.   The width of the said conductor layer facing the said electrode for large currents along the direction orthogonal to the said lamination direction is wider than the said other conductor layer, The Claim 1 characterized by the above-mentioned. Semiconductor device.   The semiconductor device according to claim 1, wherein the high current wiring portion includes the interlayer connection portion in addition to the conductor layer. The small current wiring portion and the large current wiring portion include a metal piece,
8. The metal piece according to claim 1, wherein a part of the metal piece is disposed in the insulating base material and the other part is provided to protrude outside the insulating base material. Semiconductor device.   The semiconductor device according to claim 1, wherein the small current wiring portion and the large current wiring portion each include an exposed portion exposed to the outside of the insulating base material.   The insulating substrate includes a plurality of substrate films including the thermoplastic resin film while thermoplastic resin films including a thermoplastic resin are positioned at least every other layer and positioned adjacent to the semiconductor chip. The semiconductor device according to claim 1, wherein the semiconductor devices are laminated and the base films are bonded to each other.

Images