CN112652573A - Packaging method and chip - Google Patents

Packaging method and chip Download PDF

Info

Publication number
CN112652573A
CN112652573A CN202011420770.3A CN202011420770A CN112652573A CN 112652573 A CN112652573 A CN 112652573A CN 202011420770 A CN202011420770 A CN 202011420770A CN 112652573 A CN112652573 A CN 112652573A
Authority
CN
China
Prior art keywords
chip
target chip
plastic package
package body
peripheral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011420770.3A
Other languages
Chinese (zh)
Inventor
陈伯昌
李成
陆洋
董建
曹啸
魏淼辰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Haiguang Information Technology Co Ltd
Original Assignee
Haiguang Information Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Haiguang Information Technology Co Ltd filed Critical Haiguang Information Technology Co Ltd
Priority to CN202011420770.3A priority Critical patent/CN112652573A/en
Publication of CN112652573A publication Critical patent/CN112652573A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits

Abstract

The embodiment of the application discloses a packaging method and a chip, relates to the technical field of chip packaging, and aims to reduce the complexity of substrate wiring. The packaging method comprises the following steps: arranging a target chip and corresponding peripheral elements on a slide through a sacrificial layer; performing plastic package on the target chip and peripheral elements corresponding to the target chip on the slide to obtain a plastic package body; and carrying out wiring interconnection on the target chip in the plastic package body and the corresponding peripheral elements thereof. The application is applicable to packaging chips.

Description

Packaging method and chip
Technical Field
The present disclosure relates to the field of chip packaging technologies, and in particular, to a packaging method and a chip.
Background
With the progress of science and technology, chips are more and more widely used, and in order to avoid the damage of the outside to the chips and the consideration of heat dissipation, the chips need to be packaged, and the packaging substrate is an important component of chip packaging, and circuit design is performed on the substrate to realize the signal transmission between the chips and the outside.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide a packaging method and a chip, which are convenient for reducing the complexity of substrate wiring.
In a first aspect, an embodiment of the present application provides a packaging method, including: arranging a target chip and corresponding peripheral elements on a slide through a sacrificial layer; performing plastic package on the target chip and peripheral elements corresponding to the target chip on the slide to obtain a plastic package body; and carrying out wiring interconnection on the target chip in the plastic package body and the corresponding peripheral elements thereof.
According to a specific implementation manner of the embodiment of the present application, the disposing the target chip and the corresponding peripheral element on the carrier through the sacrificial layer includes: arranging an adhesive film on the slide; and respectively arranging the target chip and the bonding pads of the corresponding peripheral elements at preset positions on the adhesive film in a downward mode.
According to a particular implementation of the embodiments of the present application, the peripheral element includes a passive element; the step of respectively arranging the target chip and the corresponding pad of the peripheral element at preset positions on the adhesive film in a way that the surface is downward comprises the following steps: depositing preset metal on the slide glass at the position corresponding to the bonding pad of the passive element; welding the passive element on the preset metal through a bonding pad; and arranging the bonding pad of the target chip on the corresponding position of the target chip on the slide glass in a face-down manner.
According to a specific implementation manner of the embodiment of the present application, the peripheral element further includes a high bandwidth memory HBM device; after depositing a preset metal on the slide at the position corresponding to the bonding pad of the passive element, the method further comprises the following steps: and arranging the bonding pads of the HBM device on the corresponding positions of the HBM device on the slide chip in a downward mode.
According to a specific implementation manner of the embodiment of the present application, after the target chip and the peripheral elements corresponding to the target chip are plastically packaged on the chip carrier to obtain a plastic package body, and before the target chip and the peripheral elements corresponding to the target chip in the plastic package body are wired and interconnected, the method further includes: and stripping the plastic package body from the slide glass.
According to a specific implementation manner of the embodiment of the present application, the routing and interconnecting the target chip and the corresponding peripheral element in the plastic package body includes: turning over the plastic package body so that the bonding pads of the target chip and the bonding pads of the peripheral elements face upwards and the plastic package body is exposed; metal interconnections are made between the target chip and the peripheral components in accordance with the circuit design.
According to a specific implementation manner of the embodiment of the present application, after the metal interconnection is performed between the target chip and the peripheral component according to the circuit design, the method further includes: and respectively manufacturing bumps on the bonding pad of the target chip and the bonding pad of the peripheral element.
According to a specific implementation manner of the embodiment of the present application, before the plastic package body is peeled off from the carrier sheet, the method further includes: and thinning the plastic package body until the upper surface of the target chip is exposed.
An embodiment of the present application further provides a packaging method, including: arranging metal interconnection lines between a target chip and peripheral elements on a chip through a sacrificial layer according to the layout and wiring plan of the target chip and the peripheral elements corresponding to the target chip; according to the layout and wiring plan, arranging a target chip and corresponding peripheral elements on the sacrificial layer and electrically connecting the target chip and the corresponding peripheral elements with the metal interconnection lines; and plastically packaging the target chip and the peripheral elements corresponding to the target chip on the slide to obtain a plastic package body.
According to a specific implementation manner of the embodiment of the present application, the setting, according to the layout and routing plan, a target chip and peripheral elements corresponding to the target chip on the sacrificial layer to be electrically connected to the metal interconnection lines includes: according to the layout and wiring plan, arranging the surface of the salient point on the target chip on the sacrificial layer in a downward mode, and electrically connecting the metal interconnection line; the peripheral element is electrically connected with the metal interconnection line.
According to a specific implementation of an embodiment of the present application, the peripheral element includes a high bandwidth memory HBM device; the peripheral element is electrically connected to the metal interconnection line, and includes: and the salient points on the HBM device are electrically connected with the metal interconnection lines respectively.
According to a specific implementation manner of the embodiment of the application, after the target chip and the peripheral element corresponding to the target chip are plastically packaged on the chip carrier to obtain a plastic package body, the method further includes: and stripping the plastic package body from the slide glass.
According to a specific implementation manner of the embodiment of the application, after the plastic package body is peeled off from the slide, the method further includes: and respectively manufacturing bumps on the bonding pad of the target chip and the bonding pad of the peripheral element.
In a second aspect, an embodiment of the present application provides a chip, where the chip is packaged by using the packaging method described in any of the foregoing implementation manners.
According to the packaging method and the chip provided by the embodiment of the application, the target chip and the corresponding peripheral elements thereof are arranged on the slide glass through the sacrificial layer, the target chip and the corresponding peripheral elements thereof are plastically packaged on the slide glass to obtain the plastic package body, and the target chip and the corresponding peripheral elements thereof in the plastic package body are wired and interconnected.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic flow chart of a packaging method according to an embodiment of the present application;
fig. 2 is a schematic flow chart of a packaging method according to another embodiment of the present application;
FIG. 3a is a schematic structural view of a carrier and a high temperature adhesive film according to an embodiment of the present disclosure;
FIG. 3b is a schematic structural diagram of a slide, a high temperature adhesive film, and a NiPd-Au sheet according to an embodiment of the present application;
FIG. 3c is a schematic structural diagram of a chip, a chip carrier, a high temperature adhesive film, a NiPd-Au aluminum sheet, and peripheral components of the chip according to an embodiment of the present application;
FIG. 3d is a schematic diagram of an embodiment of the present application before packaging;
FIG. 3e is a cross-sectional view of an encapsulated embodiment of the present application;
FIG. 3f is a cross-sectional view of FIG. 3e after thinning;
FIG. 3g is a schematic diagram of a plastic package body with wires rewired after being peeled from a carrier according to an embodiment of the present application;
FIG. 3h is a schematic view of an implanted bump according to an embodiment of the present application;
FIG. 3i is a schematic top view of an embodiment of the present application after bump implantation;
FIG. 3j is a schematic diagram illustrating a packaged chip according to an embodiment of the present application;
FIG. 4a is a schematic structural view of a carrier and a high temperature adhesive film according to another embodiment of the present disclosure;
FIG. 4b is a schematic structural diagram of a slide, a high temperature adhesive film, and a NiPd-Au sheet according to yet another embodiment of the present application;
FIG. 4c is a schematic structural diagram of a slide, a high temperature adhesive film, NiPd-Au aluminum sheet, and peripheral components of a chip according to yet another embodiment of the present application;
FIG. 4d is a schematic diagram of a chip mounted device according to yet another embodiment of the present application;
FIG. 4e is a schematic illustration of the HBM installed in FIG. 4 d;
FIG. 4f is a cross-sectional view of a packaged device according to yet another embodiment of the present application;
FIG. 4g is a cross-sectional view of FIG. 4f after thinning;
FIG. 4h is a schematic view of a plastic package body rewired after being peeled from a slide according to yet another embodiment of the present application;
FIG. 4i is a schematic view of an implanted bump according to yet another embodiment of the present application;
FIG. 4j is a schematic top view of another embodiment of the present application after bump implantation;
FIG. 4k is a schematic diagram of a packaged chip of yet another embodiment of the present application;
fig. 5 is a schematic flowchart of a packaging method according to another embodiment of the present application;
FIG. 6a is a schematic view of wiring on a chip according to an embodiment of the present application;
FIG. 6b is a schematic view of a chip and its peripheral components mounted thereon according to an embodiment of the present application;
FIG. 6c is a schematic view of an embodiment of the present application after molding;
FIG. 6d is a schematic view of the plastic package being peeled off and the bump being implanted according to an embodiment of the present application;
FIG. 6e is a top view of a board level fan-out integration in accordance with an embodiment of the present application;
FIG. 7a is a schematic diagram of the wiring on a plate-level chip according to an embodiment of the present application;
FIG. 7b is a schematic view of a mounted chip and its peripheral components according to an embodiment of the present application;
FIG. 7c is a schematic view of an embodiment of the present application after molding;
FIG. 7d is a schematic view of the bump implanted after peeling off the plastic package body according to an embodiment of the present application;
fig. 7e is a top view of a board level fan-out integrated body according to an embodiment of the present application.
Detailed Description
The embodiments of the present application will be described in detail below with reference to the accompanying drawings.
It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The existing packaging process of the CPU comprises the following steps: chip incoming material inspection → substrate incoming material inspection → passive device Surface Mounting Technology (SMT) → flip chip bonding → reflow → underfill → heat dissipation glue → heat dissipation cover black glue → heat dissipation cover paste, in the CPU package, the passive capacitor device playing the role of filtering is the device which cannot be avoided at present in the whole circuit, in the existing packaging process, a passive device and a chip are not integrated and separately placed, the passive device needs to avoid a chip mounting area, an underfill diffusion area and a heat dissipation cover mounting area and is exposed in the air without being wrapped and protected, the packaging mode relates to the rule reason that the whole packaging area is large, the whole packaging size cannot be reduced, the laminated wiring of the substrate is complex, the passive device exposed outside is in indium Ball Grid Array (BGA) packaging, and sputtering during indium reflow is easy to cause short circuit of the passive device.
With the rapid development of GPU video card chips, the industry has higher and higher requirements for information transmission speed, and the traditional GPU Chip in combination with the fifth version of Graphics Double Data Rate Memory (GDDR5, Graphics Double Data Rate, version 5) has been unable to meet the requirements for transmission speed in the industry, so that the 2.5D package of a System-on-Chip (SOC) Chip with a GPU in combination with a High Bandwidth Memory (HBM) Chip has become mature and is used in some GPU models. In the existing 2.5D package, after the GPU SOC and the HBM are connected by a silicon interposer technology, they are used as a package for a subsequent packaging process. After the GPU SOC chip and the HBM chip are connected and packaged through the silicon adapter plate in the 2.5D packaging mode, subsequent and passive devices and the substrate are packaged, the packaging mode needs a large-area silicon adapter plate to be interconnected, all signals of the SOC going out need to be connected with the HBM and the substrate through TSV technology due to the existence of the silicon adapter plate, the size and the thickness of the whole packaging are increased, the processing cost of the silicon adapter plate is very high, the packaging processing cost is increased, the whole 2.5D packaging process is very complex, the whole packaging time is long, and the size of the whole packaging is difficult to shrink.
In view of the above, the inventor found in the research that the complexity of substrate routing can be reduced by re-wiring and fanning out after wafer-level or board-level integration of the chip and the passive device, the integrated fanning-out area can be freely controlled, and the problem of sputtering short circuit in the indium heat dissipation BGA package can be solved after the passive device is wrapped.
In order to make those skilled in the art better understand the technical concepts, embodiments and advantages of the examples of the present application, the following detailed description is given by way of specific examples.
The embodiment of the application provides a packaging method which is convenient for reducing the complexity of substrate wiring.
Fig. 1 is a schematic flow chart of a packaging method according to an embodiment of the present application, and as shown in fig. 1, the packaging method according to the embodiment may include:
and S101, arranging the target chip and the corresponding peripheral elements on the chip through the sacrificial layer.
The target chip may be a chip to be packaged; the target chip may be a chip die; the elements may include capacitors, resistors, transistors, any combination thereof, and the like, and may further include a chip connected to the target chip to implement a specific function, as well as registers, memories, and the like.
The slide glass can be a metal slide glass or a glass slide glass. The cross-sectional shape of the carrier sheet can be round, and can also be rectangular or square.
The sacrificial layer may be an auxiliary layer that facilitates placement of the target chip and its peripheral components on the carrier and that facilitates separation of the carrier from the entirety of the target chip and peripheral components. In one example, the sacrificial layer may be an adhesive film.
S102, carrying out plastic package on the target chip and the peripheral elements corresponding to the target chip on the slide glass to obtain a plastic package body.
The target chip and the corresponding peripheral elements thereof can be plastically packaged by adopting materials such as plastics, ceramics, glass, metal and the like, so as to obtain a plastic package body.
The plastic package body can comprise a plastic package material, a target chip and peripheral elements corresponding to the target chip.
And S103, wiring and interconnecting the target chip in the plastic package body and the corresponding peripheral elements.
According to the connection relationship between the target chip and the peripheral elements in the actual design, the target chip and the peripheral elements corresponding to the target chip are wired, and the target chip and the peripheral elements corresponding to the target chip are interconnected.
In this embodiment, the target chip and its corresponding peripheral elements are disposed on the carrier sheet through the sacrificial layer, and the target chip and its corresponding peripheral elements are plastically packaged on the carrier sheet to obtain a plastic package body, the target chip and its corresponding peripheral elements in the plastic package body are interconnected by wiring, and the target chip and its corresponding peripheral elements in the plastic package body are interconnected by wiring, so that the circuit wiring in the substrate does not need to be disposed with the connection relationship between the chip and its corresponding peripheral elements, which is convenient for reducing the complexity of substrate wiring, and avoids the problem of complicated substrate wiring design caused by the fact that the peripheral elements of the chip need to avoid the chip mounting region, the underfill diffusion region and the heat dissipation cover mounting region in the existing packaging technology, and in addition, the chip and its peripheral elements are integrally packaged by plastic, thereby avoiding the peripheral elements of the chip from being exposed, in the subsequent assembly process, short circuit of peripheral elements caused by sputtering can not occur, the fan-out area can be adjusted according to the whole packaging size, and meanwhile, because no chip or peripheral elements are exposed outside, the reliability of the product can be improved.
Another embodiment of the present application is substantially the same as the above embodiments, except that the disposing the target chip and the corresponding peripheral devices on the chip carrier through the sacrificial layer (S101) of the present embodiment includes:
s101, 101a, arranging an adhesive film on the slide glass.
The adhesive film can be a high temperature resistant adhesive film.
S101b, the target chip and the corresponding peripheral element are respectively arranged at the preset positions on the adhesive film with the bonding pad surfaces facing downwards.
The pads, which may also be referred to as pads, may be components used to implement the solder joint. The bonding pads of the target chip may be bonding members provided to achieve connection with devices other than the target chip, and the bonding pads of the peripheral elements corresponding to the chip may also be bonding portions provided to achieve connection with devices other than the peripheral elements. It is understood that the bonding pad can be directly bonded to the external device, or can be bonded to the external device through other components.
The predetermined position may be a planned position of the target chip and the corresponding peripheral component on the adhesive film, and the plan may specify a relative positional relationship between the target chip and the corresponding peripheral component.
In some examples, the peripheral elements include passive elements; the method for respectively arranging the target chip and the corresponding peripheral element at the preset positions (S101b) with the pads facing downwards on the adhesive film comprises the following steps:
step 1, depositing preset metal on the position corresponding to the bonding pad of the passive element on the slide glass.
The passive elements can comprise resistance type elements, inductance type elements and capacitance type elements, and are characterized in that the passive elements can work in the presence of signals without adding a power supply in a circuit. The metal can be nickel-palladium-gold aluminum sheet; the size of the preset metal can be suitable for the size of the positive and negative terminals of the passive element, and the thickness can meet the bottom filling requirement of the plastic package material.
A pre-set metal may be deposited on the carrier sheet at a temperature using a processing machine, the pre-set metal being located on the carrier sheet at a position corresponding to a position of the pad of the passive component on the carrier sheet.
And 2, welding the passive element on the preset metal through the bonding pad.
After the preset metal is brushed with the solder paste in a steel mesh mode, the passive element is attached to the preset metal, and the passive element and the preset metal are welded through a reflow soldering process after the passive element is attached to the preset metal.
And 3, arranging the bonding pad of the target chip on the corresponding position of the target chip on the slide glass in a downward mode.
The target chip can be arranged at a corresponding position on the slide according to the plan, and the bonding pad of the target chip is arranged on the surface of the target chip.
In still other examples, the peripheral elements further include high bandwidth memory HBM devices;
after depositing a predetermined metal on the carrier at a position corresponding to the bonding pad of the passive component (step 1), the method further comprises:
and 4, arranging the bonding pad of the HBM device on the corresponding position of the HBM device on the slide with the surface facing downwards.
In practical use, when the chip is a GPU display chip, the GPU SOC chip can be configured with a High Bandwidth Memory (HBM) to meet the requirement of transmission speed.
The HBM device may be placed in a corresponding position on the carrier, as planned, with the bond pads of the HBM device facing down.
It is understood that the process described in step 4 can be located at any position after step 1, i.e. between step 1 and step 2, between step 2 and step 3, or after step 3.
Fig. 2 is a schematic flow chart of a packaging method according to another embodiment of the present application, and as shown in fig. 2, the another embodiment of the present application is basically the same as the above embodiments, except that after the target chip and the peripheral component corresponding to the target chip are plastically packaged on the chip carrier to obtain a plastic package body (S102), and before the target chip and the peripheral component corresponding to the target chip in the plastic package body are interconnected by wires (S103), the method further includes:
and S104, stripping the plastic package body from the slide glass.
The plastic package body can be separated from the slide glass by a bonding-detaching method.
In order to facilitate the implementation of the subsequent heat dissipation process, before the plastic package body is peeled off from the slide, the method further comprises the following steps: and thinning the plastic package body until the upper surface of the target chip is exposed.
The target chip generates heat in the working process to raise the temperature of the target chip, and the normal operation of the target chip is influenced by overhigh temperature, so that the target needs to be considered for heat dissipation in the design process. And thinning the plastic package body until the upper surface of the target chip is exposed, and performing heat dissipation process treatment through the upper surface of the target chip.
Peeling the plastic package body from the carrier to facilitate further processing of the plastic package body, and further, the wiring interconnection (S103) of the target chip in the plastic package body and the corresponding peripheral elements thereof includes:
s103a, overturning the plastic package body so that the bonding pads of the target chip and the bonding pads of the peripheral elements face upwards and the plastic package body is exposed.
Before the plastic package body is turned over, the bonding pads of the target chip and the bonding pads of the peripheral elements are located face down, the bonding pads of the target chip and the bonding pads of the peripheral elements are located face up by turning over the plastic package body, and the chip and the peripheral elements in the plastic package body are exposed.
And S103b, according to the circuit design, carrying out metal interconnection between the target chip and the peripheral elements.
The target chip and the peripheral elements are connected in accordance with the circuit design.
The packaging method in one example, after the step 103b, further includes:
and 105, respectively manufacturing bumps on the bonding pad of the target chip and the bonding pad of the peripheral element.
The bumps may be used to connect the target chip and peripheral components to other external devices. In one example, copper bumps or solder balls are implanted into openings of the pads of the target chip and the pads of the peripheral components.
In this embodiment, bumps are respectively formed on the bonding pads of the target chip and the bonding pads of the peripheral component, so that the target chip and the peripheral component can be assembled and connected with other devices in the following process.
In order to improve efficiency, a plurality of sets of target chips and corresponding peripheral elements thereof may be placed on the slide, each set of target chips and corresponding peripheral elements thereof being independent of each other set of target chips and corresponding peripheral elements thereof, and each set of target chips and corresponding peripheral elements thereof may be performed according to the method of the above embodiment.
On the basis of the above embodiments, whether the back-gold process is performed on the back surface of the plastic package body can be selected according to the final heat dissipation requirement, and if no back-gold is needed, the plastic package body can be directly cut to obtain an integrated body of each group of chips and peripheral elements thereof.
The following describes the embodiments of the present application in detail with reference to two specific examples.
The first embodiment is as follows:
in the CPU packaging technology, the chip and peripheral elements thereof are subjected to wafer-level or board-level integration and then re-wiring and fan-out, and the chip and the peripheral elements are taken as a whole package to be subjected to subsequent assembly procedures. The wafer-level integration may refer to placing a plurality of groups of chips and corresponding peripheral elements on a carrier with a circular cross section for packaging, and the board-level integration may refer to placing a plurality of groups of chips and corresponding peripheral elements on a carrier with a square or rectangular cross section for packaging. Each group of target chips and the corresponding peripheral elements thereof are independent of other groups of target chips and the peripheral elements thereof.
FIG. 3a is a schematic structural view of a carrier and a high temperature adhesive film according to an embodiment of the present disclosure; FIG. 3b is a schematic structural diagram of a slide, a high temperature adhesive film, and a NiPd-Au sheet according to an embodiment of the present application; FIG. 3c is a schematic structural diagram of a chip, a chip carrier, a high temperature adhesive film, a NiPd-Au aluminum sheet, and peripheral components of the chip according to an embodiment of the present application; FIG. 3d is a schematic diagram of an embodiment of the present application before packaging; FIG. 3e is a cross-sectional view of an encapsulated embodiment of the present application; FIG. 3f is a cross-sectional view of FIG. 3e after thinning; FIG. 3g is a schematic diagram of a plastic package body after being peeled off from a slide according to an embodiment of the present application; FIG. 3h is a schematic view of an implanted bump according to an embodiment of the present application; FIG. 3i is a schematic view of an embodiment of the present application after bump implantation; fig. 3j is a schematic diagram of a packaged chip according to an embodiment of the present application. The processes shown in fig. 3a to 3j form a process flow diagram of the packaging method of the present embodiment.
The specific process steps are as follows:
(1) a12-inch metal slide 1 is prepared, and a high-temperature-resistant adhesive film 2 is attached to the metal slide.
The carrier may also be a glass carrier, and the present embodiment is described as a metal carrier.
(2) Selecting a nickel palladium gold aluminum sheet 3 with the size suitable for the sizes of the anode and cathode terminals of the element at the periphery of the chip, wherein the thickness of the aluminum sheet is required to meet the bottom filling requirement of the plastic package material, and sticking the nickel palladium gold sheet to the high-temperature-resistant adhesive film 2 with the upward nickel palladium gold layer according to the design matrix.
In this embodiment, the nipd-au aluminum sheet is attached to the high temperature resistant adhesive film according to the design matrix.
(3) And brushing tin paste on the nickel-palladium-gold aluminum sheet 3 in a steel mesh mode, then attaching the elements 4 around the chip to the nickel-palladium-gold aluminum sheet 3, and then welding the elements 4 around the chip and the nickel-palladium-gold aluminum sheet 3 in a reflow soldering mode.
(4) After the CPU SOC chip 5 is subjected to wafer singulation, the circuit surface is attached to the high temperature resistant adhesive film 2 in a downward mode according to a design matrix.
The CPU SOC chip 5 is a chip bare chip, i.e., a chip to be packaged. A circuit is etched on the CPU SOC chip 5, and the circuit is attached to the high temperature resistant adhesive film with the surface facing downwards.
(5) Using a wafer level plastic package, the chip and its surrounding components are packaged together as a whole plastic package body, as shown in fig. 3 e.
(6) And thinning the plastic package body to the upper surface of the leaky chip so as to facilitate the subsequent heat dissipation process.
(7) And after the metal slide is subjected to bonding removal and separation with the plastic package body, the plastic package body is turned over, the aluminum pads on the surface of the chip and the patch aluminum pads of the elements around the chip are exposed, and the chip and the elements around the chip are connected in a wiring manner according to circuit design.
Since the carrier has a circular cross section and the carrier in this embodiment has a plurality of sets of chips and their surrounding elements, the plastic package can be called a wafer-level plastic package.
(8) After wiring is finished, a bump process is carried out on the chip in the plastic package body and the elements around the chip, and copper bumps or solder balls are implanted into the corresponding pad openings, so that circuit connection of subsequent assembly is facilitated.
(9) The back-gold process can be selected according to the final heat dissipation requirement, if the back-gold is not needed, the wafer-level plastic package body can be directly subjected to wafer cutting, and the fan-out integrated body is separated.
In the fan-out plastic package body after singulation, the chip and the elements around the chip are sealed into a whole by the plastic package material, so that the passive device is prevented from being exposed, the passive device short circuit caused by sputtering is not considered in the subsequent assembly process, the wiring complexity of the substrate is reduced after wafer-level wiring, and the fan-out area can be adjusted according to the whole packaging size.
The CPU packaging scheme changes the exposed design of elements around the existing chip into integral fan-out integration, the chip and the elements around the chip are integrally packaged and fanned out, the short circuit of a passive device caused by sputtering in indium BGA packaging is avoided, meanwhile, the design rule of peripheral element arrangement is avoided, the fan-out area can be adjusted according to the design and reliability requirements, the wafer-level rewiring of the wafer fan-out enables the lamination wiring of the substrate to be simplified, the integral packaging size is reduced, the lamination number of the substrate is reduced, the integral packaging cost is reduced, no chip and peripheral elements are exposed, and the packaging reliability can be improved.
The second embodiment is as follows:
FIG. 4a is a schematic structural view of a carrier and a high temperature adhesive film according to another embodiment of the present disclosure; FIG. 4b is a schematic structural diagram of a slide, a high temperature adhesive film, and a NiPd-Au sheet according to yet another embodiment of the present application; FIG. 4c is a schematic structural diagram of a slide, a high temperature adhesive film, NiPd-Au aluminum sheet, and peripheral components of a chip according to yet another embodiment of the present application; fig. 4d is a schematic diagram of a chip mounted according to another embodiment of the present application, and fig. 4e is a schematic diagram of a HBM mounted in fig. 4 d; FIG. 4f is a cross-sectional view of a packaged device according to yet another embodiment of the present application; FIG. 4g is a cross-sectional view of FIG. 4f after thinning; fig. 4h is a schematic view of a plastic package body after being peeled off from a slide according to another embodiment of the present application; FIG. 4i is a schematic view of an implanted bump according to yet another embodiment of the present application; FIG. 4j is a schematic view of another embodiment of the present application after bump implantation; fig. 4k is a schematic diagram of a packaged chip according to yet another embodiment of the present application. The processes shown in fig. 4a to 4k form a process flow diagram of the packaging method of the present embodiment.
In the GPU packaging technology, the GPU SOC chip, the needed HBM and peripheral elements are subjected to wafer-level or board-level integration and then are re-wired and fanned out, and the integrated chip is used as a whole package to be subjected to subsequent assembly procedures. The specific process steps are as follows:
(1) 12 inches of metal is prepared, and a high-temperature-resistant adhesive film is attached to the metal.
(2) And (3) sticking the nickel-palladium-gold aluminum sheet with the size suitable for the size of the positive and negative terminals of the passive device to the high-temperature-resistant adhesive film, wherein the thickness of the aluminum sheet is required to meet the bottom filling requirement of the plastic package material, and the nickel-palladium-gold layer faces upwards according to the designed matrix.
(3) And after the nickel-palladium-gold aluminum sheet is brushed with the tin paste in a steel mesh mode, the passive device is attached to the nickel-palladium-gold aluminum sheet, and after the passive device is attached to the nickel-palladium-gold aluminum sheet in a reflow soldering mode, the passive device and the nickel-palladium-gold aluminum sheet are soldered.
(4) And after the GPU SOC chip is subjected to wafer singulation, the circuit surface is attached to a high-temperature-resistant adhesive film in a downward mode according to the design matrix.
(5) HBM without salient points (bump) is pasted on a high temperature resistant adhesive film with a circuit surface facing downwards according to a design matrix.
(6) And packaging the passive device and the chip together by using wafer-level plastic package to form the whole plastic package body.
(7) And thinning the plastic package body to the upper surface of the leaky chip so as to facilitate the subsequent heat dissipation process.
(8) And after the metal or glass carrier is subjected to bonding removal and is separated from the plastic package body, the plastic package body is turned over, the chip surface aluminum pad and the passive device chip aluminum pad are leaked, and rewiring is carried out according to circuit design.
(9) After the rewiring is finished, a bump process is performed on the wafer, and the copper bumps or the solder balls are implanted into the corresponding pad openings, so that the circuit connection of subsequent assembly is facilitated.
(10) The back-gold process can be selected according to the final heat dissipation requirement, if the back-gold is not needed, the wafer-level plastic package body can be directly subjected to wafer cutting, and the fan-out integrated body is separated.
In the fan-out plastic package body after singulation, the passive device and the chip are sealed into a whole by the plastic package material, so that the passive device is prevented from being exposed, the passive device short circuit caused by sputtering is not considered in the subsequent assembly process, the wiring complexity of the substrate is reduced after wafer-level rewiring, and the fan-out area can be adjusted according to the whole packaging size.
In the GPU packaging scheme, a GPU SOC chip, a required HBM chip and elements on the periphery of the chip are used as a whole to be subjected to wafer-level fan-out, the whole packaging thickness is effectively controlled due to the fact that no silicon adapter plate is arranged, meanwhile, the design rule of peripheral element arrangement is avoided, the fan-out area can be adjusted according to the design and reliability requirements, wafer-level rewiring of the wafer fan-out enables laminated wiring of a corresponding substrate to be simplified, the whole packaging size is reduced, the number of laminated substrates is reduced, the whole packaging cost is reduced, meanwhile, no chip and peripheral elements of the chip are exposed outside, and packaging reliability can be improved.
Fig. 5 is a schematic flow chart of a packaging method according to another embodiment of the present application, and as shown in fig. 5, the packaging method according to this embodiment may include:
s201, arranging metal interconnection lines between a target chip and peripheral elements on a slide through a sacrificial layer according to the layout and wiring plan of the target chip and the peripheral elements corresponding to the target chip.
The layout and routing plan may include the relative positions of the target chip and its corresponding peripheral elements on the carrier, and the connection relationship between the target chip and its corresponding peripheral elements.
The target chip may be a chip to be packaged; the target chip may be a chip die; the elements may include capacitors, resistors, transistors, any combination thereof, and the like, and may further include a chip connected to the target chip to implement a specific function, as well as registers, memories, and the like.
The slide glass can be a metal slide glass or a glass slide glass. The cross-sectional shape of the carrier sheet can be round, and can also be rectangular or square.
The sacrificial layer may be an auxiliary layer that facilitates placement of the target chip and its peripheral components on the carrier and that facilitates separation of the carrier from the entirety of the target chip and peripheral components. In one example, the sacrificial layer may be an adhesive film.
The metal interconnection line is used for connecting the target chip and the peripheral element.
S202, arranging the target chip and the corresponding peripheral elements on the sacrificial layer according to the layout and wiring plan, and electrically connecting the target chip and the corresponding peripheral elements with the metal interconnection lines.
In one example, the bumps may be formed on the target chip, and the bumps on the target chip may be connected to the corresponding positions of the metal interconnection lines according to the layout, or the peripheral components may be placed at the corresponding positions of the metal interconnection lines according to the layout.
And S203, carrying out plastic package on the target chip and the peripheral elements corresponding to the target chip on the slide glass to obtain a plastic package body.
The target chip and the corresponding peripheral elements thereof can be plastically packaged by adopting materials such as plastics, ceramics, glass, metal and the like, so as to obtain a plastic package body.
The plastic package body can comprise a plastic package material, a target chip and peripheral elements corresponding to the target chip.
In this embodiment, according to the layout and wiring plan of the target chip and its corresponding peripheral elements, the metal interconnection line between the target chip and the peripheral elements is disposed on the chip carrier through the sacrificial layer, and then the target chip and its corresponding peripheral elements are disposed on the sacrificial layer and electrically connected to the metal interconnection line according to the layout and wiring plan, and finally, the target chip and its corresponding peripheral elements are plastic-encapsulated on the chip carrier to obtain a plastic-encapsulated body, because the target chip and its corresponding peripheral elements are already interconnected by wiring in the plastic-encapsulated body, in this way, the circuit wiring in the substrate can be free of the connection relationship between the chip and its corresponding peripheral elements, which is convenient for reducing the complexity of substrate wiring, avoiding the situation that the peripheral elements of the chip need to avoid the chip mounting area, underfill diffusion area and heat dissipation cover mounting area in the existing packaging technology, the problem that the substrate wiring design is complex is caused, in addition, the chip and the peripheral elements are sealed into a whole in a plastic mode, the peripheral elements of the chip are prevented from being exposed, the peripheral element short circuit caused by sputtering cannot occur in the subsequent assembly process, in addition, the fan-out area can be adjusted according to the whole packaging size, and meanwhile, the reliability of the product can be improved because no chip and the peripheral elements are exposed outside.
In an embodiment of the present application, substantially the same as the above-mentioned embodiment, except that, according to a layout and routing plan, a target chip and its corresponding peripheral components are disposed on the sacrificial layer and electrically connected to the metal interconnection lines (S202), the method includes:
and according to the layout and wiring plan, arranging the salient points on the target chip on the sacrificial layer in a downward mode, wherein the salient points are electrically connected with the metal interconnection lines, and the peripheral elements are electrically connected with the metal interconnection lines.
In order to facilitate reliable connection with metal interconnects, bumps are fabricated on the target chip, which may be fabricated on a wafer. In one example, copper bumps or solder balls are implanted into openings of the pads of the target chip and the pads of the peripheral components.
In yet another example, the peripheral elements include high bandwidth memory HBM devices; the peripheral element is electrically connected to the metal interconnection line, and includes:
and the salient points on the HBM device are electrically connected with the metal interconnection lines.
In practical use, when the chip is a GPU display chip, the GPU SOC chip can be configured with a High Bandwidth Memory (HBM) to meet the requirement of transmission speed.
It is understood that the HBM device may be bumped.
Another embodiment of the present application is substantially the same as the above embodiments, except that the packaging method of the present embodiment further includes, after plastic-encapsulating the target chip and the corresponding peripheral element on the carrier to obtain a plastic-encapsulated body:
and S204, stripping the plastic package body from the slide glass.
The plastic package body can be separated from the slide glass by a bonding-detaching method.
In order to facilitate the implementation of the subsequent heat dissipation process, before the plastic package body is peeled off from the slide, the method further comprises the following steps: and thinning the plastic package body until the upper surface of the target chip is exposed.
The target chip generates heat in the working process to raise the temperature of the target chip, and the normal operation of the target chip is influenced by overhigh temperature, so that the target needs to be considered for heat dissipation in the design process. And thinning the plastic package body until the upper surface of the target chip is exposed, and performing heat dissipation process treatment through the upper surface of the target chip.
The packaging method in one example, after step S104, further includes:
and 105, respectively manufacturing bumps on the bonding pad of the target chip and the bonding pad of the peripheral element.
The bumps may be used to connect the target chip and peripheral components to other external devices. In one example, copper bumps or solder balls are implanted into openings of the pads of the target chip and the pads of the peripheral components.
In this embodiment, bumps are respectively formed on the bonding pads of the target chip and the bonding pads of the peripheral component, so that the target chip and the peripheral component can be assembled and connected with other devices in the following process.
In order to improve efficiency, a plurality of sets of target chips and corresponding peripheral elements thereof may be placed on the slide, each set of target chips and corresponding peripheral elements thereof being independent of each other set of target chips and corresponding peripheral elements thereof, and each set of target chips and corresponding peripheral elements thereof may be performed according to the method of the above embodiment.
On the basis of the above embodiments, whether the back-gold process is performed on the back surface of the plastic package body can be selected according to the final heat dissipation requirement, and if no back-gold is needed, the plastic package body can be directly cut to obtain an integrated body of each group of chips and peripheral elements thereof.
The following describes the embodiments of the present application in detail with reference to two specific examples.
The first embodiment is as follows:
the shape of the glass slide glass is changed into the glass slide glass with the square design in the CPU packaging of the embodiment, the wafer level fan-out integration is changed into the board level fan-out integration, the number of the patches is increased, and the output is improved.
FIG. 6a is a schematic view of wiring on a chip according to an embodiment of the present application; FIG. 6b is a schematic view of a chip and its peripheral components mounted thereon according to an embodiment of the present application; FIG. 6c is a schematic view of an embodiment of the present application after molding; FIG. 6d is a schematic view of an implanted bump according to an embodiment of the present application; fig. 6e is a top view of a board level fan-out integrated body according to an embodiment of the present application. The processes shown in fig. 6a to 6d are schematic process flow diagrams of the packaging method of the present embodiment.
(1) Firstly, a bump (bumping) process is carried out on an original CPU SOC wafer, and the CPU SOC wafer is cut into single pieces.
(2) Firstly, rewiring is carried out on a glass slide, after the rewiring is finished, the realizability is considered, elements around a chip are firstly attached to corresponding pads of the glass slide in a surface mounting mode according to a design matrix, the surface of a CPU SOC with salient points (bump) is downward after the CPU SOC is cut, the CPU SOC is attached to the corresponding pads of the glass slide according to the design matrix, and then plate-level integral plastic package is carried out to obtain a plastic package body.
(3) And (4) separating the slide glass from the plastic package body by debonding the bond.
(4) And turning over the plastic package body to perform a bumping process.
The second embodiment is as follows:
in the GPU packaging process, the glass slide is changed into the glass slide with a square design, wafer-level fan-out integration is changed into board-level fan-out integration, the number of patches is increased, and output is improved.
FIG. 7a is a schematic view of wiring on a chip according to an embodiment of the present application; FIG. 7b is a schematic view of a mounted chip and its peripheral components according to an embodiment of the present application; FIG. 7c is a schematic view of an embodiment of the present application after molding; FIG. 7d is a schematic view of an implanted bump according to an embodiment of the present application; fig. 7e is a top view of a board level fan-out integrated body according to an embodiment of the present application. The processes shown in fig. 7a to 7d are schematic process flow diagrams of the packaging method of the present embodiment.
(1) Firstly, a bump (bumping) process is carried out on the original GPU SOC wafer, and the GPU SOC wafer is cut into single pieces.
(2) Firstly, rewiring is carried out on a glass slide, after the rewiring is finished, the realizability is considered, elements on the periphery of a chip are firstly attached to corresponding pads of the glass slide in a surface mounting mode according to a design matrix, after the rewiring is finished, the surface of a GPU SOC with salient points (bump) is downwardly attached to the corresponding pads of the glass slide according to the design matrix, then the surface of the HBM bump with the salient points is downwardly attached to the corresponding pads of the glass slide according to the design matrix, and then plate-level integral plastic package is carried out.
(3) And (4) separating the slide glass from the plastic package body by debonding the bond.
(4) And turning over the plastic package body to perform a bumping process.
The embodiment of the application also provides a chip which is packaged by using the packaging method provided by any one of the embodiments.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term "comprising", without further limitation, means that the element so defined is not excluded from the group consisting of additional identical elements in the process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.
In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
For convenience of description, the above devices are described separately in terms of functional division into various units/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations when the present application is implemented.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (14)

1. A method of packaging, comprising:
arranging a target chip and corresponding peripheral elements on a slide through a sacrificial layer;
performing plastic package on the target chip and peripheral elements corresponding to the target chip on the slide to obtain a plastic package body;
and carrying out wiring interconnection on the target chip in the plastic package body and the corresponding peripheral elements thereof.
2. The packaging method according to claim 1, wherein the disposing the target chip and its corresponding peripheral element on the carrier chip through the sacrificial layer comprises:
arranging an adhesive film on the slide;
and respectively arranging the target chip and the bonding pads of the corresponding peripheral elements at preset positions on the adhesive film in a downward mode.
3. The packaging method according to claim 2, wherein the peripheral element comprises a passive element; the step of respectively arranging the target chip and the corresponding pad of the peripheral element at preset positions on the adhesive film in a way that the surface is downward comprises the following steps:
depositing preset metal on the slide glass at the position corresponding to the bonding pad of the passive element;
welding the passive element on the preset metal through a bonding pad;
and arranging the bonding pad of the target chip on the corresponding position of the target chip on the slide glass in a face-down manner.
4. The packaging method according to claim 3, wherein the peripheral element further comprises a High Bandwidth Memory (HBM) device;
after depositing a preset metal on the slide at the position corresponding to the bonding pad of the passive element, the method further comprises the following steps:
and arranging the bonding pads of the HBM device on the corresponding positions of the HBM device on the slide chip in a downward mode.
5. The packaging method according to any one of claims 1 to 4, wherein after the target chip and the corresponding peripheral elements are subjected to plastic packaging on the chip carrier to obtain a plastic package body, and before the target chip and the corresponding peripheral elements in the plastic package body are subjected to wiring interconnection, the method further comprises:
and stripping the plastic package body from the slide glass.
6. The packaging method according to claim 5, wherein the wiring and interconnecting the target chip and its corresponding peripheral elements in the plastic package body comprises:
turning over the plastic package body so that the bonding pads of the target chip and the bonding pads of the peripheral elements face upwards and the plastic package body is exposed;
metal interconnections are made between the target chip and the peripheral components in accordance with the circuit design.
7. The packaging method according to claim 6, wherein after the metal interconnection between the target chip and the peripheral component according to the circuit design, the method further comprises:
and respectively manufacturing bumps on the bonding pad of the target chip and the bonding pad of the peripheral element.
8. The method of claim 5, wherein before the peeling the plastic package body from the carrier sheet, the method further comprises:
and thinning the plastic package body until the upper surface of the target chip is exposed.
9. A method of packaging, comprising:
arranging metal interconnection lines between a target chip and peripheral elements on a chip through a sacrificial layer according to the layout and wiring plan of the target chip and the peripheral elements corresponding to the target chip;
according to the layout and wiring plan, arranging a target chip and corresponding peripheral elements on the sacrificial layer and electrically connecting the target chip and the corresponding peripheral elements with the metal interconnection lines;
and plastically packaging the target chip and the peripheral elements corresponding to the target chip on the slide to obtain a plastic package body.
10. The packaging method according to claim 9, wherein the disposing the target chip and the corresponding peripheral component on the sacrificial layer according to the layout and routing plan, and electrically connecting the target chip and the corresponding peripheral component with the metal interconnection line comprises:
according to the layout and wiring plan, arranging the surface of the salient point on the target chip on the sacrificial layer in a downward mode, and electrically connecting the metal interconnection line; the peripheral element is electrically connected with the metal interconnection line.
11. The packaging method according to claim 10, wherein the peripheral element comprises a High Bandwidth Memory (HBM) device;
the peripheral element is electrically connected to the metal interconnection line, and includes:
and the salient points on the HBM device are electrically connected with the metal interconnection lines respectively.
12. The packaging method according to any one of claims 9 to 11, wherein after the target chip and the corresponding peripheral component are subjected to plastic packaging on the chip carrier to obtain a plastic package body, the method further comprises:
and stripping the plastic package body from the slide glass.
13. The method of packaging of claim 12, wherein after peeling the molded body from the carrier sheet, the method further comprises:
and respectively manufacturing bumps on the bonding pad of the target chip and the bonding pad of the peripheral element.
14. A chip, wherein the chip is packaged by the packaging method according to any one of claims 1 to 13.
CN202011420770.3A 2020-12-07 2020-12-07 Packaging method and chip Pending CN112652573A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011420770.3A CN112652573A (en) 2020-12-07 2020-12-07 Packaging method and chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011420770.3A CN112652573A (en) 2020-12-07 2020-12-07 Packaging method and chip

Publications (1)

Publication Number Publication Date
CN112652573A true CN112652573A (en) 2021-04-13

Family

ID=75350405

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011420770.3A Pending CN112652573A (en) 2020-12-07 2020-12-07 Packaging method and chip

Country Status (1)

Country Link
CN (1) CN112652573A (en)

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11177015A (en) * 1997-12-11 1999-07-02 Canon Inc Semiconductor package and intermediate substrate for mounting the same
CN101836289A (en) * 2007-10-22 2010-09-15 日本电气株式会社 Semiconductor device
CN102097341A (en) * 2009-12-10 2011-06-15 日东电工株式会社 Manufacturing method for semiconductor device
US7977783B1 (en) * 2009-08-27 2011-07-12 Amkor Technology, Inc. Wafer level chip size package having redistribution layers
US20120146216A1 (en) * 2010-12-09 2012-06-14 Nepes Corporation Semiconductor package and fabrication method thereof
CN104851860A (en) * 2015-04-30 2015-08-19 华为技术有限公司 Integrated circuit die and manufacturing method thereof
WO2018084143A1 (en) * 2016-11-02 2018-05-11 株式会社村田製作所 Electronic component package, circuit module, and method for producing electronic component package
CN108231603A (en) * 2017-12-14 2018-06-29 通富微电子股份有限公司 The preparation method and chip packing-body of a kind of chip packing-body
CN109216206A (en) * 2018-08-23 2019-01-15 江苏中科智芯集成科技有限公司 A kind of wafer scale is fanned out to packaging method and encapsulating structure
CN110783284A (en) * 2018-07-27 2020-02-11 台湾积体电路制造股份有限公司 Package body
CN111095544A (en) * 2019-09-06 2020-05-01 深圳市汇顶科技股份有限公司 Integrated device and preparation method thereof
US20200203187A1 (en) * 2017-11-29 2020-06-25 Pep Innovation Pte. Ltd. Chip packaging method and package structure
CN111653494A (en) * 2020-06-16 2020-09-11 中国电子科技集团公司第二十四研究所 Non-contact heating flip-chip welding process method

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11177015A (en) * 1997-12-11 1999-07-02 Canon Inc Semiconductor package and intermediate substrate for mounting the same
CN101836289A (en) * 2007-10-22 2010-09-15 日本电气株式会社 Semiconductor device
US7977783B1 (en) * 2009-08-27 2011-07-12 Amkor Technology, Inc. Wafer level chip size package having redistribution layers
CN102097341A (en) * 2009-12-10 2011-06-15 日东电工株式会社 Manufacturing method for semiconductor device
US20120146216A1 (en) * 2010-12-09 2012-06-14 Nepes Corporation Semiconductor package and fabrication method thereof
CN104851860A (en) * 2015-04-30 2015-08-19 华为技术有限公司 Integrated circuit die and manufacturing method thereof
WO2018084143A1 (en) * 2016-11-02 2018-05-11 株式会社村田製作所 Electronic component package, circuit module, and method for producing electronic component package
US20200203187A1 (en) * 2017-11-29 2020-06-25 Pep Innovation Pte. Ltd. Chip packaging method and package structure
CN108231603A (en) * 2017-12-14 2018-06-29 通富微电子股份有限公司 The preparation method and chip packing-body of a kind of chip packing-body
CN110783284A (en) * 2018-07-27 2020-02-11 台湾积体电路制造股份有限公司 Package body
CN109216206A (en) * 2018-08-23 2019-01-15 江苏中科智芯集成科技有限公司 A kind of wafer scale is fanned out to packaging method and encapsulating structure
CN111095544A (en) * 2019-09-06 2020-05-01 深圳市汇顶科技股份有限公司 Integrated device and preparation method thereof
CN111653494A (en) * 2020-06-16 2020-09-11 中国电子科技集团公司第二十四研究所 Non-contact heating flip-chip welding process method

Similar Documents

Publication Publication Date Title
US8922005B2 (en) Methods and apparatus for package on package devices with reversed stud bump through via interconnections
TWI345276B (en) Dice rearrangement package structure using layout process to form a compliant configuration
US20180233441A1 (en) PoP Device
TWI236721B (en) Leadframe for leadless flip-chip package and method for manufacturing the same
TWI567899B (en) Semiconductor device packages
US20120280404A1 (en) Stack packages having fastening element and halogen-free inter-package connector
US20130300000A1 (en) Microelectronic package with stacked microelectronic elements and method for manufacture thereof
JP2003115560A (en) Semiconductor device, laminated semiconductor device, manufacturing method of semiconductor device, and manufacturing method of laminated semiconductor device
US20210305122A1 (en) Semiconductor package and manufacturing method thereof
US11456268B2 (en) Semiconductor package and manufacturing method thereof
US8222080B2 (en) Fabrication method of package structure
TW200952138A (en) Chip rearrangement package structure and the method thereof
CN104716103A (en) Underfill Pattern with Gap
TW200939407A (en) Multi-chip package structure and the method thereof
TW200411891A (en) High density multi-chip module structure and manufacturing method thereof
CN114050111A (en) Fan-out type packaging method and fan-out type packaging structure
JP2006295183A (en) Multi-package module provided with stacked packages having asymmetrically disposed die and molding
CN114497019A (en) Multi-chip three-dimensional integrated structure and manufacturing method
US20100127374A1 (en) Multi-stack semiconductor package, semiconductor module and electronic signal processing system including thereof
KR100726892B1 (en) Three-dimensional chip stacking package module and preparation method thereof
TWI311806B (en) Cob type ic package for improving bonding of bumps embedded in substrate and method for fabricating the same
US20090146299A1 (en) Semiconductor package and method thereof
KR20150081161A (en) Method for fabricating semiconductor package and semiconductor package using the same
CN107919333B (en) Three-dimensional POP packaging structure and packaging method thereof
CN106409702A (en) Multi-chip stacked package structure and manufacture method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination