WO2018079105A1 - Procédé de fabrication de tranche et tranche - Google Patents

Procédé de fabrication de tranche et tranche Download PDF

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Publication number
WO2018079105A1
WO2018079105A1 PCT/JP2017/032814 JP2017032814W WO2018079105A1 WO 2018079105 A1 WO2018079105 A1 WO 2018079105A1 JP 2017032814 W JP2017032814 W JP 2017032814W WO 2018079105 A1 WO2018079105 A1 WO 2018079105A1
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WO
WIPO (PCT)
Prior art keywords
wafer
resin layer
holding
curing
resin
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Application number
PCT/JP2017/032814
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English (en)
Japanese (ja)
Inventor
田中 利幸
敏 又川
中島 亮
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株式会社Sumco
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Publication of WO2018079105A1 publication Critical patent/WO2018079105A1/fr

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B7/00Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
    • B24B7/20Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
    • B24B7/22Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting

Definitions

  • the present invention relates to a wafer manufacturing method and a wafer.
  • a curable resin is applied to one surface of the wafer, and the curable resin is processed flat and cured to form a resin layer.
  • the flat surface of the resin layer is held and the other surface of the wafer is ground and flattened, and after the resin layer is removed or not removed, the other flat surface is held and one of the wafers is held. Grind and flatten the surface.
  • the technique may be referred to as “resin pasting”. And further flattening which applied such resin pasting grinding is examined (for example, refer to patent documents 1).
  • the other surface of the wavy wafer is sucked and held by holding means. Further, a curable resin is dropped onto the film on the stage, and one surface of the wafer is pressed against the dropped curable resin to form a pre-curing flat surface on the curable resin following the film. Thereafter, the suction holding of the other surface is released to cure the curable resin, and a resin layer having a flat surface after curing is formed.
  • the flat surface after curing of the resin layer after being separated from the film is not sufficiently flattened, and the nanotopography on the wafer surface after mirror polishing cannot be sufficiently reduced.
  • the device may not be properly manufactured.
  • An object of the present invention is to provide a wafer manufacturing method and a wafer that can be planarized without affecting the manufacture of semiconductor devices.
  • the present inventor can sufficiently flatten the flat surface after curing of the resin layer by appropriately setting the viscosity of the curable resin before curing. I got the knowledge.
  • the present invention has been completed based on the above findings.
  • the method for producing a wafer of the present invention includes a resin layer forming step of forming a resin layer on one surface of a wafer cut from a single crystal ingot or a lapped wafer, and the one surface via the resin layer.
  • a second surface grinding step wherein the resin layer forming step includes a holding step of sucking and holding the other surface of the wafer by a holding means, a flat portion of the flat surface forming means, and one surface of the wafer
  • a flat surface forming step in which a curable resin having a viscosity of 1000 mPa ⁇ s or less is sandwiched between and a pre-curing flat surface following the flat portion is formed on the curable resin, and the holding release for releasing the suction holding of the other surface Craft
  • the resin layer forming step includes a holding step of sucking and holding the other surface of the wafer by a holding means, a flat portion of the flat surface forming means, and one surface of the wafer
  • a flat surface forming step in which a curable resin having a viscosity of 1000 mPa ⁇ s or less is sandwiched between and a pre-curing flat surface following the flat portion is formed on the curable resin, and the holding release for releasing the suction holding of the
  • a sufficiently flattened resin layer having a flat surface after curing can be formed.
  • the waviness of the wafer after the first surface grinding step, the resin layer removal step, and the second surface grinding step can be sufficiently reduced on the wafer provided with the resin layer.
  • the nanotopography of the wafer surface after mirror polishing can be made sufficiently small, and a wafer capable of appropriately manufacturing a semiconductor device can be provided.
  • the resin layer forming step forms the resin layer so as to satisfy the following formula (1).
  • V / T ⁇ 10 (1)
  • V Viscosity before curing of the curable resin (mPa ⁇ s)
  • T Thickness ( ⁇ m) of the thickest portion of the curable resin after the holding release step and before the curing step
  • the present invention by appropriately setting the thickness of the curable resin with respect to the viscosity of the curable resin and setting V / T to 10 or less, deformation of the flat surface after curing of the resin layer can be suppressed,
  • the maximum value of nanotopography on the wafer surface after mirror polishing can be made 5 nm or less.
  • the wafer of the present invention is characterized in that the maximum value of nanotopography measured in a plurality of regions of 10 mm ⁇ 10 mm on the surface is 5 nm or less.
  • FIG. 2 is an explanatory diagram of the wafer manufacturing method, showing a state following FIGS. 2A to 2C.
  • FIG. 2 is an explanatory diagram of the wafer manufacturing method, showing a state following FIGS. 2A to 2C.
  • FIG. 2 is an explanatory diagram of the wafer manufacturing method, showing a state following FIGS. 2A to 2C.
  • FIG. 2 is an explanatory diagram of the wafer manufacturing method, showing a state following FIGS. 2A to 2C.
  • FIG. 6 is an explanatory diagram of the action of using a curable resin having a pre-curing viscosity V of 1000 mPa ⁇ s or less, and shows a state following FIGS. 5A to 5C.
  • FIG. 5A to 5C shows a state following FIGS. 5A to 5C.
  • FIGS. 5A to 5C are explanatory diagrams of the action of using a curable resin having a pre-curing viscosity V of 1000 mPa ⁇ s or less, and shows a state following FIGS. 5A to 5C.
  • a single crystal ingot such as silicon, SiC, GaAs, or sapphire is cut with a wire saw to obtain a plurality of wafers ( Step S1: Slicing step).
  • steps S1: Slicing step both surfaces of the wafer are simultaneously planarized by a lapping apparatus (step S2: lapping process) and chamfered (step S3: chamfering process).
  • step S4 a resin layer forming step in which a curable resin R (see FIG. 2B) is applied to one surface W1 of the wafer W to form a resin layer RH (see FIG. 2B).
  • the coating step (step S11), the holding step (step S12), and the flat surface forming step (step S13). ), A holding release process (step S14), a curing process (step S15), and a separation process (step S16).
  • the curable resin R is applied onto the flat plate 11 as a flat surface forming unit having the flat portion 11A that has been highly flattened.
  • the curable resin R one having a viscosity V before curing (hereinafter simply referred to as “viscosity before curing”) of 1000 mPa ⁇ s or less is used as the curable resin R.
  • the viscosity V before curing is preferably 100 mPa ⁇ s or more.
  • the holding means 12 sucks and holds the other surface W2 of the wafer W with the holding surface 121, as indicated by a solid line in FIG. 2B. At this time, the swell W21 on the other surface W2 of the wafer W is corrected following the holding surface 121, and the swell W11 on the one surface W1 is also reduced.
  • the holding means 12 is lowered, and the curable resin R is sandwiched between the flat portion 11A and one surface W1 of the wafer W, as shown by a two-dot chain line in FIG. By pressing the curable resin R, a pre-curing flat surface R1 that follows the flat portion 11A is formed on the curable resin R.
  • the suction holding of the other surface W2 of the wafer W by the holding unit 12 is released.
  • the curable resin R is cured to form a resin layer RH in which the surface opposite to the surface in contact with the one surface W1 becomes the flat surface RH1 after curing.
  • the flat portion 11A is separated from the resin layer RH.
  • FIGS. 5A to 5C the operation of using the curable resin R having a pre-curing viscosity V of 1000 mPa ⁇ s or less will be described with reference to FIGS. 5A to 5C in which the shapes of the wafer W and the curable resin R are exaggerated and simplified.
  • the holding process is performed on the wafer W as shown in FIG. 5A
  • the waviness W21 of the other surface W2 is corrected following the holding surface 121 as shown in FIG.
  • the swell W11 of the surface W1 is reduced to a swell W111 indicated by a solid line.
  • a pre-curing flat surface R1 that follows the flat portion 11A is formed in the curable resin R.
  • the deformation of the wafer contact surface R2 is difficult to be absorbed by the curable resin R, so that the compression elastic force F1 and the tensile elastic force F2 remain.
  • the cured flat surface RH1 of the resin layer RH is caused by the remaining elastic forces F1 and F2 as shown in FIG. 6A. It will be deformed and its flatness will be reduced.
  • the pre-curing viscosity V is set to 1000 mPa ⁇ s or less, the deformation of the wafer contact surface R2 is easily absorbed by the curable resin R, and the compression elastic force F1 and the tensile elastic force F2 hardly remain.
  • the separation step is performed after the formation of the resin layer RH, as shown in FIG. 6B, the deformation of the flat surface RH1 after the curing of the resin layer RH is suppressed, and the sufficiently flattened flat surface RH1 is flattened.
  • the resin layer RH can be formed.
  • the resin layer RH is preferably formed so as to satisfy the following formula (1).
  • the viscosity V before curing is 1000 mPa ⁇ s or less.
  • the curable resin R is too thin with respect to the pre-curing viscosity V, so that the wafer contact surface R2 is deformed by the holding release process.
  • the elastic forces F1 and F2 may remain in the curable resin R, although the viscosity V before curing is sufficiently smaller than the case where the viscosity V is greater than 1000 mPa ⁇ s.
  • the flatness of the flat surface RH1 after curing of the resin layer RH after the separation step is very small, but the nanotopography on the surface of the wafer W after mirror polishing described later may not be 5 nm or less.
  • the thickness of the curable resin R is appropriate with respect to the pre-curing viscosity V. Even if it is deformed, this deformation can be sufficiently absorbed by the curable resin R, and residual compression elastic force F1 and tensile elastic force F2 can be suppressed. As a result, the flatness of the flat surface RH1 after curing of the resin layer RH after the separation step can be sufficiently maintained, and the nanotopography of the surface of the wafer W after mirror polishing can be reduced to 5 nm or less.
  • the other surface W2 is sucked and held by the holding surface 121 so that the one surface W1 of the wafer W faces upward, and the curable resin is set on the one surface W1.
  • the resin is dripped and the wafer W is rotated to spin the curable resin over the entire surface W1.
  • the spin coating method is used to place the screen plate on one surface W1, and the curable resin is placed on the screen plate and applied with a squeegee.
  • a method in which the highly flattened flat plate 11 is pressed against the curable resin after applying the curable resin by a screen printing method, an electric spray deposition method, or the like by spraying the entire surface of the one surface W1 can be applied.
  • the curable resin is preferably a curable resin such as a photosensitive resin in terms of ease of peeling after processing.
  • the photosensitive resin is preferable in that it is not subjected to heat stress.
  • a UV curable resin is used as the curable resin.
  • Other specific curable resin materials include adhesives (such as wax).
  • the other surface W2 is surface ground using a surface grinding device 20 as shown in FIG. 2C.
  • a surface grinding device 20 As shown in FIG. 2C, the wafer W is placed on the highly flattened holding surface 211 of the vacuum chuck table 21 with the flat surface RH1 after curing facing downward, the vacuum chuck table 21 sucks and holds the wafer W.
  • the surface plate 23 provided with the grindstone 22 on the lower surface is moved above the wafer W.
  • the vacuum chuck table 21 is rotated, and as shown by a two-dot chain line in FIG. 2C, the grindstone 22 and the other surface W2 are brought into contact with each other.
  • Surface grinding When the machining allowance is equal to or greater than the machining allowance minimum value P, the surface grinding is finished.
  • the other surface W2 becomes a flat surface from which the undulation is sufficiently removed.
  • the resin layer RH formed on one surface W1 of the wafer W is peeled off from the wafer W as shown in FIG. 3A.
  • the resin layer RH may be chemically removed using a solvent.
  • one surface W1 is surface ground using the same surface grinding device 20 as in the first surface grinding step.
  • the vacuum chuck table 21 sucks and holds the wafer W, as shown by a solid line in FIG. 3B.
  • the surface plate 23 moved above the wafer W is lowered while being rotated, and the vacuum chuck table 21 is rotated, so that one surface W1 is surface ground as indicated by a two-dot chain line in FIG. 3B.
  • the machining allowance is equal to or greater than the machining allowance minimum value P, the surface grinding is finished, so that one surface W1 becomes a flat surface from which the undulation is sufficiently removed.
  • etching is performed in order to remove a work-affected layer that occurs during chamfering or resin pasting grinding and remains on the wafer W (step S8: etching process).
  • mirror polishing including a primary polishing step (step S9) for polishing both surfaces of the wafer W using a double-side polishing device and a final polishing step (step S10) for polishing both surfaces of the wafer W using a single-side polishing device.
  • a process is performed and the manufacturing method of a wafer is complete
  • Resin-grinding is performed under conditions satisfying the above formula (1), and the wafer W obtained after this mirror polishing step has a characteristic that the maximum value of nanotopography measured in a plurality of regions of 10 mm ⁇ 10 mm on the surface is 5 nm or less. Have.
  • the resin pasting and grinding step may be performed under the above conditions without performing the lapping step. Even in such a case, the wafer W having the above-described characteristics can be obtained. Further, the removal of the resin layer RH may be performed by grinding in the second surface grinding process as the resin layer removing process instead of peeling off.
  • the thickness A of the thickest portion of the curable resin (hereinafter simply referred to as “resin thickness”) T is 70 ⁇ m after the holding release step and before the curing step using the resin A.
  • the coating process, the holding process, and the flat surface forming process were performed.
  • the resin A was cured by UV irradiation in the curing step to form a resin layer, and a separation step was performed.
  • the value of V / T was 5, as shown in FIG. 7, satisfying the above formula (1).
  • the resins A to C were applied to other wafers in the combinations as shown in FIG. 7 to form a resin layer having the resin thickness shown in FIG.
  • the 1st surface grinding process, the resin layer removal process, and the 2nd surface grinding process were performed with respect to each wafer provided with the resin layer.
  • surface grinding was performed using a grinding machine (DFG8000 series) manufactured by DISCO Corporation with a machining allowance of 20 ⁇ m. Thereafter, an etching process, a mirror polishing process, and a cleaning process were performed.
  • a double-side polishing device was used as the primary polishing step, and polishing was performed in a total of 5 ⁇ m to 20 ⁇ m on both sides.
  • a single-side polishing device was used as the final polishing step to polish less than 1 ⁇ m on only one side.
  • One sample was prepared for each condition.
  • FIG. 7 shows a maximum value of nanotopography, a nanotopography map, and a binarized image in each wafer. Further, the case where a white area exists in the binarized image is described as “with pattern”, and the case where it does not exist is described as “without pattern”.
  • the maximum value of nanotopography was almost the same between Resin A and Resin B having a pre-curing viscosity V of 1000 mPa ⁇ s or less.
  • the maximum value of nanotopography in the resin C having a pre-curing viscosity V larger than 1000 mPa ⁇ s was larger than those in the resin A and the resin B. Also for the binarized image, it was confirmed that the white area of the resin C was larger than the resin A and the resin B.
  • the nanotopography on the wafer surface after mirror polishing can be made sufficiently small by forming the resin layer using a curable resin having a viscosity V before curing of 1000 mPa ⁇ s or less.
  • the above-described flatness measuring device Wafersight 2 was used, and the surface after mirror polishing was measured in the above range. Each measurement was performed in a range passing through the center of the wafer. The measurement results are shown in FIG. As shown in FIG. 8, it was found that the shape of the nanotopography and the flat surface after curing were very similar. From this, it was found that the uneven shape of the flat surface after curing was transferred to the wafer as waviness.
  • the maximum value of nanotopography was 5 nm or less when V / T was 10 or less. From the above, the maximum value of nanotopography after mirror polishing is as high as 5 nm or less by forming a resin layer under conditions where the viscosity V before curing is 1000 mPa ⁇ s or less and V / T is 10 or less. It was confirmed that a quality wafer could be obtained.

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  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Grinding Of Cylindrical And Plane Surfaces (AREA)

Abstract

L'invention concerne un procédé de formation de couche de résine pour former une couche de résine (RH) sur une surface (W1) d'une tranche (W) comprenant : une étape de maintien pour maintenir, par aspiration, l'autre surface (W2) de la tranche (W) par un moyen de maintien; une étape de formation de surface plate pour prendre en sandwich une résine durcissable ayant une viscosité non supérieure à 1000 mPa·s entre la partie plate d'une plaque plate et une surface (W1) de la tranche (W) de manière à former une surface plate pré-durcie se conformant à la partie plate sur la résine durcissable; une étape de libération de maintien pour libérer le support, par aspiration, de l'autre surface (W2); une étape de durcissement pour former la couche de résine (RH) par durcissement de la résine durcissable; et une étape de séparation pour séparer la partie plate de la couche de résine (RH).
PCT/JP2017/032814 2016-10-31 2017-09-12 Procédé de fabrication de tranche et tranche WO2018079105A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016-212774 2016-10-31
JP2016212774A JP2018074018A (ja) 2016-10-31 2016-10-31 ウェーハの製造方法およびウェーハ

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WO2018079105A1 true WO2018079105A1 (fr) 2018-05-03

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DE102018221922A1 (de) 2018-12-17 2020-06-18 Siltronic Ag Verfahren zur Herstellung von Halbleiterscheiben mittels einer Drahtsäge, Drahtsäge und Halbleiterscheibe aus einkristallinem Silizium
JP7349784B2 (ja) * 2018-12-26 2023-09-25 東京エレクトロン株式会社 基板処理システム、および基板処理方法
JP6844733B1 (ja) * 2020-05-21 2021-03-17 信越半導体株式会社 基板ウェーハの製造方法、及び基板ウェーハ

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11111653A (ja) * 1997-10-07 1999-04-23 Toshiba Ceramics Co Ltd 半導体ウェーハの製造方法
JP2002134581A (ja) * 2000-10-25 2002-05-10 Speedfam Co Ltd ナノトポグラフィ評価用基準ウェーハとその製造方法及び該ウェーハを用いたウェーハ評価方法
JP2010155298A (ja) * 2008-12-26 2010-07-15 Disco Abrasive Syst Ltd 樹脂被覆方法および樹脂被覆装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11111653A (ja) * 1997-10-07 1999-04-23 Toshiba Ceramics Co Ltd 半導体ウェーハの製造方法
JP2002134581A (ja) * 2000-10-25 2002-05-10 Speedfam Co Ltd ナノトポグラフィ評価用基準ウェーハとその製造方法及び該ウェーハを用いたウェーハ評価方法
JP2010155298A (ja) * 2008-12-26 2010-07-15 Disco Abrasive Syst Ltd 樹脂被覆方法および樹脂被覆装置

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JP2018074018A (ja) 2018-05-10

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