WO2018072448A1 - 一种频移键控调制信号的解调方法及系统 - Google Patents

一种频移键控调制信号的解调方法及系统 Download PDF

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WO2018072448A1
WO2018072448A1 PCT/CN2017/086836 CN2017086836W WO2018072448A1 WO 2018072448 A1 WO2018072448 A1 WO 2018072448A1 CN 2017086836 W CN2017086836 W CN 2017086836W WO 2018072448 A1 WO2018072448 A1 WO 2018072448A1
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data
frequency
bit
address code
clock
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PCT/CN2017/086836
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English (en)
French (fr)
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韩路
赵辉
张毅
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国民技术股份有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/14—Demodulator circuits; Receiver circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/14—Demodulator circuits; Receiver circuits
    • H04L27/142—Compensating direct current components occurring during the demodulation and which are caused by mistuning

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  • the present invention relates to the field of frequency shift keying modulation and demodulation, and in particular to a method and system for demodulating a frequency shift keying modulated signal.
  • the re-banding filter can be used to filter out side lobes other than the main lobe without affecting the transmission of information, it will damage the constant envelope characteristics of the modulated signal.
  • Non-constant envelope signals require high linearity and can only be amplified with amplifiers that are less power efficient but have better linearity.
  • the FSK modulation and demodulation method can be improved to obtain the GFSK modulation and demodulation method (Gaussian frequency shift keying), which can realize the continuity of the phase at the intersection of the code primitives. In this way, the signal energy can be concentrated on the main lobe, which is a kind of Efficient modulation and demodulation.
  • the traditional scheme requires good reception performance in a Gaussian white noise channel while having low complexity, and the direct phase discrimination method is usually used to implement the demodulation function.
  • the direct phase discrimination method is a demodulation method that utilizes the phase of a signal without using the amplitude of the signal. After the received signal is subjected to orthogonal down-conversion, the phase of the signal is solved, and then the scoring operation is performed to recover the baseband signal after passing through the Gaussian filter.
  • the existing frequency shift keying demodulation method is shown in FIG. 1, and the method has the following defects:
  • Frame synchronization is generated by an external circuit.
  • the implementation process is very complicated and requires external circuit support.
  • its frame synchronization algorithm will cause a high retransmission rate.
  • the frequency compensation circuit is in the form of no feedback, and the compensation real-time performance is poor, which affects the bit error rate
  • the timing compensation algorithm is complicated to implement. At the same time, since the bit information is extracted from the zero-crossing point of the baseband signal, the noise is greatly affected when the signal-to-noise ratio is relatively low.
  • the invention provides a frequency demodulation modulation signal demodulation method and system, and aims to solve the problem that in short-distance wireless communication application field, the transmission power is low, and at the same time, it is compatible with various data transmission rates and modulation indexes, and is not suitable for correction. Under the premise of wrong coding and bit error rate, it is difficult to improve the sensitivity of the receiver.
  • a method for demodulating a frequency shift keying modulated signal comprising:
  • the zero-intermediate I/Q data is changed into phase data, and then subjected to differential subtraction and decision operation to generate a bit code stream;
  • the invention solves the problem that the short-distance wireless communication frequency shift keying demodulation technology realizes difficulty, relies on an external frame synchronization circuit, and has a high error rate at the same time, and proposes a simple and more accurate frequency shift keying.
  • the demodulation method adopts internal self-synchronization code generation, configurable frame synchronization code generation, and frequency offset detection and compensation technology to be fed back, instead of the traditional frequency shift keying demodulation technology, so that the demodulation system can reach Higher sensitivity, lower bit error rate, and greatly reduced complexity.
  • the present invention can also be improved as follows.
  • the received intermediate frequency can be consistent with the intermediate frequency generated by the numerically controlled oscillator, and the received data is zero-intermediated for subsequent demodulation, and the conventional demodulation method is used, and no frequency compensation is performed in the process. It is compensated before the data decision. Since the received data is not zero-frequency intermediate, the error will be accumulated to the decision position, so the sensitivity will decrease and the bit error rate will increase.
  • bit stream data generated in the S2 includes a J bit preamble, a K bit address code, and I bit load data.
  • S31 accumulating the received bit stream data for J times of preamble data, and obtaining an average value of the accumulated values as a reference value;
  • the traditional technology first introduces the concept of reference value and directly compares the received data with a preset address code. Actually, the process of comparison may be affected by factors such as system gain adjustment or DC cancellation, which may result in receiving. The address code and the preset address code are not equal in area. Secondly, the concept of threshold is not configured in the conventional technology. Only when the address code of the K bit and the pre-set address code of the K bit are completely matched, the frame synchronization is successful. Actually, it is also affected by factors such as system gain adjustment or DC cancellation in the comparison process. The comparison process is not completely reliable. Only a certain number of address codes need to be successfully matched, and the frame synchronization can be confirmed.
  • an internal self-generated clock is used to ensure the consistency of the decoded data and the clock, and the crystal frequency of the crystal is obtained by recovering the frequency shift keying modulation inside the clock, and feeding back to the decoding end to decode the input data, thereby improving decoding. accuracy.
  • the invention also proposes a demodulation system for frequency shift keying modulated signals, the system comprising:
  • the processing module is configured to process data sent by the external radio frequency system to obtain I/Q data of two intermediate frequency frequencies; and down-convert the I/Q data after the DC cancellation processing by the numerical control oscillator, and frequency offset compensation, Making the I/Q signal reach zero intermediate frequency;
  • the conversion module is configured to limit the out-of-band noise of the zero-intermediate I/Q data by low-pass filtering, and transform into phase data after performing time phase conversion, and generate a bit stream after differential subtraction and decision operation;
  • An output module configured to compare the generated bit code stream with the address code, and output a frame synchronization pulse when the number of comparison result errors is less than a preset maximum number
  • the synchronization module is configured to output a frequency offset code after the generated bit stream is subjected to frequency offset calculation, and after demodulation, output a final demodulation result bit code stream, and simultaneously perform clock synchronization processing.
  • the invention solves the problem that the existing short-distance wireless communication frequency shift keying demodulation system realizes difficulty, relies on an external frame synchronization circuit, and has a high error rate at the same time, and proposes a simple and more accurate frequency shift keying demodulation.
  • the system uses internal self-synchronization code generation, configurable frame synchronization code generation, and frequency offset detection and compensation technology to be fed back, instead of the traditional frequency shift keying demodulation technology, the demodulation system can achieve higher Sensitivity, lower bit error rate, and greatly reduced complexity.
  • processing module includes:
  • a Gaussian modulation module configured to perform Gaussian modulation on the received I/Q data to obtain data A of the M length bit
  • a decoding comparison module configured to decode data A to obtain data B, and perform subtraction operation on data B and data A to obtain a frequency offset control word and send it to a numerically controlled oscillator;
  • a frequency control module for adjusting the output frequency of the numerically controlled oscillator according to the frequency control word.
  • the received intermediate frequency can be consistent with the intermediate frequency generated by the numerically controlled oscillator, and the received data is zero-intermediated for subsequent demodulation, and the conventional demodulation method is used, and no frequency compensation is performed in the process. It is compensated before the data judgment, because the reception cannot be guaranteed.
  • the data is zero-intermediate, the error will be accumulated to the position of the decision, so the sensitivity will decrease and the bit error rate will increase.
  • bit stream data generated in the conversion module includes a J bit preamble, a K bit address code, and I bit load data.
  • the output module includes:
  • a reference value calculation module configured to accumulate the received bit stream data by J times of preamble data, and obtain an average value of the accumulated values as a reference value
  • a data comparison module configured to compare the address code data in the received bit stream data with a reference value, if the address code data is greater than the reference value, the address code to be compared is 1; if the address code data is less than the reference value, The address code to be compared is 0;
  • the counting and accumulating module is configured to compare the address code data in the bit stream data with the reference value and generate the to-be-referenced address code, and compare the to-be-compared address code with a preset address code. Then the counter is incremented by 1. If not equal, the counter keeps the current value unchanged;
  • the pulse generation module is configured to: after the number of comparisons is K times, if the value of K minus the configuration threshold is less than the counter value, the synchronization is completed and a frame synchronization pulse is issued, and if the value of K minus the configuration threshold is greater than the counter value, then Resend the process.
  • the traditional technology first introduces the concept of reference value and directly compares the received data with a preset address code. Actually, the process of comparison may be affected by factors such as system gain adjustment or DC cancellation, which may result in receiving. The address code and the preset address code are not equal in area. Secondly, the concept of threshold is not configured in the conventional technology. Only when the address code of the K bit and the pre-set address code of the K bit are completely matched, the frame synchronization is successful. Actually, it is also affected by factors such as system gain adjustment or DC cancellation in the comparison process. The comparison process is not completely reliable. Only a certain number of address codes need to be successfully matched, and the frame synchronization can be confirmed.
  • the synchronization module includes:
  • a decoding module configured to decode the received frequency offset code to obtain 1 bit load data
  • the clock self-recovery module is configured to automatically recover the clock frequency according to the demodulated signal and the sampling frequency, and compare the clock frequency with the load data to perform clock cycle adjustment. When the clock frequency leads the load data, the clock cycle increases; When the clock frequency lags behind the load data, the clock period is self-reduced, and finally the recovered clock signal is obtained;
  • An encoding module configured to encode, according to the recovered clock signal, load data obtained after decoding to obtain encoded data
  • the comparison module is configured to compare the encoded data with the externally input demodulated data to obtain a crystal frequency.
  • the clock synchronization module adopts an internal self-generated clock to ensure the consistency of the decoded data and the clock, and the frequency of the crystal is obtained by recovering the internal frequency shift keying modulation of the clock, and feeding back to the decoding end for decoding the input data. Improve the decoding accuracy.
  • 1 is a schematic diagram showing the principle of frequency shift keying modulation in the prior art
  • FIG. 2 is a flowchart of a method for demodulating a frequency shift keying modulated signal according to an embodiment of the present invention
  • FIG. 4 is a flowchart of obtaining a frame synchronization pulse according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of clock synchronization processing according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a principle of a frequency demodulation modulated signal demodulation system according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a schematic diagram of a down conversion processing module according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a principle of a clock synchronization module according to an embodiment of the present invention.
  • this embodiment provides a method for demodulating a frequency shift keying modulated signal, where the method includes:
  • SP1 processing data sent by the external radio frequency system, and obtaining I/Q data of two intermediate frequency frequencies
  • the I/Q data after the DC cancellation processing is down-converted by the numerically controlled oscillator and the frequency offset compensation, so that the I/Q signal reaches zero intermediate frequency;
  • the zero-intermediate I/Q data is limited to out-of-band noise by low-pass filtering, and is transformed into phase data after time phase conversion;
  • the phase data is limited by the low-pass filtering to limit the out-of-band noise, and after the differential subtraction and the decision operation, the bit stream is generated, and the bit stream data includes the J bit preamble, the K bit address code, and the I bit load data;
  • the final demodulation result bit code stream is output, and clock synchronization processing is simultaneously performed.
  • the present embodiment provides a simple and more accurate frequency shift keying solution for the existing short-range wireless communication frequency shift keying demodulation technology, which is difficult to implement, relies on an external frame synchronization circuit, and has a high bit error rate.
  • the modulation method adopts internal self-synchronization code generation, configurable frame synchronization code generation, and frequency offset detection compensation technology to be fed back, instead of the traditional frequency shift keying demodulation technology, so that the demodulation system can achieve higher Sensitivity, lower bit error rate, and greatly reduced complexity.
  • the frequency ⁇ RF of the input data I/Q and the sine-cosine waveform frequency ⁇ generated by the digital oscillator should be equal to achieve zero-IF.
  • the ideal frequency ⁇ RF of the input data I/Q and the sine cosine waveform frequency ⁇ generated by the numerically controlled oscillator are all known conditions, but the ideal frequency ⁇ RF of the input data I/Q is affected by the frequency error of the transmission channel and the transmission system, possibly Greater than or less than the ideal frequency ⁇ RF . This will result in an increase in the bit error rate of the entire demodulation system.
  • the present embodiment proposes a method for performing frequency offset compensation processing on the I/Q data after DC cancellation processing, as shown in FIG.
  • the specific implementation process of the method is as follows:
  • SP32 decoding data A to obtain data B, and subtracting data B and data A to obtain a frequency offset control word and transmitting it to a numerically controlled oscillator;
  • SP33 adjust the output frequency of the numerical control oscillator according to the frequency control word.
  • ⁇ RF can be guaranteed to be equal to ⁇ in real time, that is, the received intermediate frequency is consistent with the intermediate frequency generated by the numerically controlled oscillator in the receiving system, and the received data is zero-intermediated for subsequent demodulation.
  • frequency compensation is not performed at this position, but compensation is performed before the data decision. Since ⁇ RF is not guaranteed to be equal to ⁇ , the error is accumulated to the position of the decision, so the sensitivity will decrease, and the bit error rate will be lowered. Will rise.
  • the process of obtaining a frame synchronization pulse in the SP6 is:
  • SP61 accumulating the received bit stream data for J times of preamble data, and obtaining an average value of the accumulated values as a reference value
  • the SP62 compares the address code data in the received bit stream data with a reference value. If the address code data is greater than the reference value, the to-be-compared address code is 1. If the address code data is smaller than the reference value, the address code to be compared is compared. Is 0;
  • the SP63 compares the address code data in the bit stream data with the reference value and generates the to-be-compared address code, and compares the to-be-compared address code with the preset address code. If they are equal, the counter is incremented by one. If not equal, the counter keeps the current value unchanged;
  • the demodulation system can ensure that the address code is locked with a high probability, and a synchronization pulse is generated to reduce the number of retransmissions.
  • the concept of the reference value is not introduced first, and the received data is directly compared with the preset address code.
  • the process of the comparison may be affected by factors such as system gain adjustment or DC cancellation, which may result in reception.
  • the address code and the preset address code are not equal in area.
  • the concept of threshold is not configured in the conventional technology. Only when the address code of the K bit and the pre-set address code of the K bit are completely matched, the frame synchronization is successful. Actually, it is also affected by factors such as system gain adjustment or DC cancellation in the comparison process.
  • the comparison process is not completely reliable. Only a certain number of address codes need to be successfully matched, and the frame synchronization can be confirmed.
  • the frequency offset code outputted in the SP8 is demodulated and outputs a final demodulation result bit code stream and simultaneously performs clock synchronization processing:
  • SP82 automatically recovers the clock frequency according to the demodulation signal and the sampling frequency, and compares the clock frequency with the load data to adjust the clock period.
  • the clock period increases automatically; when the clock frequency lags behind the load In the case of data, the clock period is self-reduced, and finally the recovered clock signal is obtained;
  • SP83 according to the recovered clock signal, encoding the load data obtained after decoding to obtain encoded data
  • an internal self-generated clock is used to ensure the consistency of the decoded data and the clock, and the crystal frequency of the crystal is obtained by recovering the frequency shift keying modulation inside the clock, and feeding back to the decoding end to decode the input data, thereby improving decoding. accuracy.
  • this embodiment provides a demodulation system for frequency shift keying modulated signals, and the system includes:
  • the original data processing module is configured to process data sent by the external radio frequency system to obtain I/Q data of two intermediate frequency frequencies;
  • a DC cancellation module for performing DC cancellation processing on I/Q data to remove DC offset
  • the down conversion processing module is configured to perform down-conversion processing and frequency offset compensation on the I/Q data after the DC cancellation processing by the numerical control oscillator, so that the I/Q signal reaches zero intermediate frequency;
  • a data conversion module configured to limit zero-frequency I/Q data by using a pre-demodulation filter to limit out-of-band noise, and perform phase phase conversion to become phase data
  • the code stream generating module is configured to limit the out-of-band noise by passing the phase data through the demodulation filter, and generate a bit code stream after the differential subtraction and the decision operation; the bit stream data includes a J bit preamble and a K bit address code. And I bit load data.
  • a pulse output module configured to compare the generated bit code stream with the address code, and output a frame synchronization pulse when the number of comparison result errors is less than a preset maximum number
  • a frequency offset calculation module configured to output a frequency offset code after the generated bit code stream is subjected to frequency offset calculation
  • the clock synchronization module after demodulating the output frequency offset code, outputs a final demodulation result bit code stream and simultaneously performs clock synchronization processing.
  • the system is difficult to realize the existing short-range wireless communication frequency shift keying demodulation system, relying on external frame synchronization circuit and high bit error rate.
  • a simple and more accurate frequency shift keying demodulation is proposed.
  • the system uses internal self-synchronization code generation, configurable frame synchronization code generation, and frequency offset detection and compensation technology to be fed back, instead of the traditional frequency shift keying demodulation technology, the demodulation system can achieve higher Sensitivity, lower bit error rate, and greatly reduced complexity.
  • the frequency ⁇ RF of the input data I/Q and the sine-cosine waveform frequency ⁇ generated by the digital oscillator should be equal to achieve zero-IF.
  • the ideal frequency ⁇ RF of the input data I/Q and the sine cosine waveform frequency ⁇ generated by the numerically controlled oscillator are all known conditions, but the ideal frequency ⁇ RF of the input data I/Q is affected by the frequency error of the transmission channel and the transmission system, possibly Greater than or less than the ideal frequency ⁇ RF . This will result in an increase in the bit error rate of the entire demodulation system.
  • the present embodiment proposes a specific implementation manner of performing frequency offset compensation processing on the I/Q data after DC cancellation processing in the down conversion processing module, such as shown in FIG. 7, the down conversion processing module includes:
  • a Gaussian modulation module configured to perform Gaussian modulation on the received I/Q data to obtain data A of the M length bit
  • a decoding comparison module configured to decode data A to obtain data B, and perform subtraction operation on data B and data A to obtain a frequency offset control word and send it to a numerically controlled oscillator;
  • a frequency control module for adjusting the output frequency of the numerically controlled oscillator according to the frequency control word.
  • the received intermediate frequency can be consistent with the intermediate frequency generated by the numerically controlled oscillator, and the received data is zero-intermediated for subsequent demodulation, and the conventional demodulation method is used, and no frequency compensation is performed in the process. It is compensated before the data decision. Since the received data is not zero-frequency intermediate, the error will be accumulated to the decision position, so the sensitivity will decrease and the bit error rate will increase.
  • the pulse output module comprises:
  • a reference value calculation module configured to accumulate the received bit stream data by J times of preamble data, and obtain an average value of the accumulated values as a reference value
  • a data comparison module configured to compare the address code data in the received bit stream data with a reference value, if the address code data is greater than the reference value, the address code to be compared is 1; if the address code data is less than the reference value, The address code to be compared is 0;
  • the counting and accumulating module is configured to compare the address code data in the bit stream data with the reference value and generate the to-be-referenced address code, and then perform the address code to be compared with the preset address code. Compare, if they are equal, the counter is incremented by 1. If they are not equal, the counter keeps the current value unchanged;
  • the pulse generation module is configured to: after the number of comparisons is K times, if the value of K minus the configuration threshold is less than the counter value, the synchronization is completed and a frame synchronization pulse is issued, and if the value of K minus the configuration threshold is greater than the counter value, then Resend the process.
  • the traditional technology first introduces the concept of reference value and directly compares the received data with a preset address code. Actually, the process of comparison may be affected by factors such as system gain adjustment or DC cancellation, which may result in receiving. The address code and the preset address code are not equal in area. Secondly, the concept of threshold is not configured in the conventional technology. Only when the address code of the K bit and the pre-set address code of the K bit are completely matched, the frame synchronization is successful. Actually, it is also affected by factors such as system gain adjustment or DC cancellation in the comparison process. The comparison process is not completely reliable. Only a certain number of address codes need to be successfully matched, and the frame synchronization can be confirmed.
  • the clock synchronization module includes:
  • a decoding module configured to decode the received frequency offset code to obtain 1 bit load data
  • the clock self-recovery module is configured to automatically recover the clock frequency according to the demodulated signal and the sampling frequency, and compare the clock frequency with the load data to perform clock cycle adjustment. When the clock frequency leads the load data, the clock cycle increases; When the clock frequency lags behind the load data, the clock period is self-reduced, and finally the recovered clock signal is obtained;
  • An encoding module configured to encode, according to the recovered clock signal, load data obtained after decoding to obtain encoded data
  • the comparison module is configured to compare the encoded data with the externally input demodulated data to obtain a crystal frequency.
  • the clock synchronization module adopts an internal self-generated clock to ensure the consistency of the decoded data and the clock, and the frequency of the crystal is obtained by recovering the internal frequency shift keying modulation of the clock, and feeding back to the decoding end for decoding the input data. Improve the decoding accuracy.

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Abstract

一种频移键控调制信号的解调方法及系统，涉及频移键控调制解调领域。对外部射频系统发送的数据进行处理获得两路中频频率的I/Q数据并去除直流偏移；然后通过数控振荡器进行零中频化处理；将零中频化的I/Q数据通过低通滤波限制带外噪声，并进行时间相位转化后变为相位数据；将相位数据通过低通滤波限制带外噪声，并经过差分减法及判决运算后生成bit码流；将生成的bit码流与地址码进行比对，当比对结果错误数量小于预设的最大数量时，输出帧同步脉冲；将生成bit码流经过频率偏移计算后，输出频率偏移码；输出的频率偏移码经过解调后，输出最终解调结果bit码流，并同时进行时钟同步处理。本发明适用于频移键控调制解调。

Description

一种频移键控调制信号的解调方法及系统 技术领域
本发明涉及频移键控调制解调领域，具体地，涉及一种频移键控调制信号的解调方法及系统。
背景技术
不同的调制解调技术具有不同的能量利用效率，以适应不同的应用环境。短距离无线通信由于通信距离短，要求低成本，低复杂度，低功耗，所以一般会采用简单而有效的调制解调方式，包括ASK(幅移键控)，PSK(相移键控)，FSK(频移键控)等等。上述常规的调制解调技术在数据改变瞬间，载波相位会出现突变，造成调制信号的频谱在主瓣之外存在较大的旁瓣，形成对相邻信道的干扰。虽然采用再带滤波器可以滤除主瓣之外的旁瓣而不影响信息的传输，但是会损坏调制信号的恒包络特性。非恒包络的信号对线性度要求很高，只能使用功率效率较低但线性度较好的放大器进行放大。对FSK调制解调方式进行改进可以得到GFSK调制解调方式(高斯频移键控)，它能够实现相位在码原交替处的连续，采用该方式可以使信号能量集中于主瓣，是一种高效的调制解调方式。
传统的方案要求在具有低复杂度的同时，在高斯白噪声信道中具有良好的接收性能，通常采用直接鉴相方式实现解调功能。直接鉴相法是一种利用信号的相位，而不利用信号的幅度的解调方式。接收到的信号经过正交下变频之后，求解信号的相位，之后再进行查分运算，恢复出经过高斯滤波器后的基带信号。
目前现有的频移键控解调方式如图1所示，该方法具有以下缺陷：
1、帧同步由外部电路产生，实现过程非常复杂，需要有外部电路的支撑，同时其帧同步算法会导致重发率较高的问题；
2、频率补偿电路为无反馈形式，补偿实时性差，影响误码率；
3、时序补偿算法实现复杂，同时由于是从基带信号的过零点提取位信息，在信噪比比较低的情况下，受噪声影响较大。
发明内容
本发明提供一种频移键控调制信号的解调方法及系统，目的在于解决在短距离无线通信应用领域，在发射功率较低、同时在兼容多种数据传输速率和调制指数、不适用纠错编码及误码率的前提下，提高接收机的灵敏度难度大的问题。
本发明解决上述技术问题的技术方案如下：
一种频移键控调制信号的解调方法，所述方法包括：
S1、对外部射频系统发送的数据进行处理，获得两路中频频率的I/Q数据，将直流消除处理后的I/Q数据通过数控振荡器进行下变频处理以及频率偏移补偿，使得I/Q数据达到零中频化；
S2、将零中频化的I/Q数据变为相位数据后经过差分减法及判决运算后生成bit码流；
S3、将生成的bit码流与地址码进行比对，当比对结果错误数量小于预设的最大数量时，输出帧同步脉冲；
S4、将生成的bit码流经过频率偏移计算后，输出频率偏移码，再经过解调后输出最终解调结果bit码流，并同时进行时钟同步处理。
本发明针对现有短距离无线通信频移键控解调技术实现难度大、依赖外部帧同步电路、同时误码率较高的问题，提出一种简单的、更准确频移键控 的解调方法，该方法采用内部自同步码生成、可配置的帧同步码生成、及待反馈的频率偏移侦测补偿技术，代替传统频移键控解调技术，使解调系统能够达到更高的灵敏度、更低的误码率，以及使其实现复杂度大大降低。
在上述技术方案的基础上，本发明还可以做如下改进。
进一步，所述S1中将直流消除处理后的I/Q数据进行频率偏移补偿处理的过程为：
S11、对接收到的I/Q数据进行高斯调制，获得M长度bit的数据A；
S12、对数据A进行解码获得数据B，并将数据B与数据A进行减法运算获得频率偏移控制字并发送至数控振荡器；
S13、根据频率控制字调节数控振荡器输出频率。
通过以上处理过程可以使接收到的中频频率和数控振荡器产生的中频一致，保证接收数据零中频化，用于后续解调，而采用传统解调方式，没有在该过程中进行频率补偿，而是在数据判决前进行补偿，由于不能保证接收到的数据零中频化，会将误差累积到判决的位置，这样灵敏度将下降，误码率也会上升。
进一步，所述S2中生成的bit码流数据中包括J bit前导、K bit地址码和I bit负载数据。
进一步，所述S3中获得帧同步脉冲的过程为：
S31、将接收到的bit码流数据累加J次前导数据，求取累加值的平均值作为基准值；
S32、将接收到的bit码流数据中的地址码数据与基准值相比较，如果地址码数据大于基准值，则待对比地址码为1，如果地址码数据小于基准值，则待对比地址码为0；
S33、在每完成一次bit码流数据中的地址码数据与基准值的比较并生成待对比地址码后，将待对比地址码与预先设定的地址码进行比较，如果相 等，则计数器加1，如果不相等，则计数器保持当前数值不变；
S34、当比较的次数为K次后，如果K减去配置阈值的数值小于计数器数值，则同步完成并发出帧同步脉冲，如果K减去配置阈值的数值大于计数器数值，则进入重发流程。
传统技术首先是没有引入基准值概念，直接把接收到的数据和预先设定的地址码进行比对，实际在比对的过程由于受系统增益调整或直流消除等因素影响，可能导致接收到的地址码和预先设定的地址码大面积不相等，其次传统技术中也没有配置阈值的概念，只有K bit的地址码和K bit的预先设定的地址码完全匹配后，才表示帧同步成功，实际同样受比对过程中系统增益调整或直流消除等因素影响，比对过程并不是完全可靠，只需要一定数量地址码匹配成功，即可认定帧同步完成。
进一步，所述S4中输出的频率偏移码经过解调后，输出最终解调结果bit码流、并同时进行时钟同步处理的过程为：
S41、对接收到的频率偏移码进行解码，获得1bit负载数据；
S42、根据解调信号以及采样频率自动恢复出时钟频率，并将时钟频率与负载数据进行比较后进行时钟周期调整，当时钟频率超前于负载数据时，时钟周期自增加；当时钟频率落后于负载数据时，时钟周期自减少，最终获得恢复的时钟信号；
S43、根据恢复的时钟信号，将解码后获得的负载数据进行编码，获得编码数据；
S44、将编码数据与外部输入的解调数据进行比较，进而获得晶振频率，并将所述晶振频率作为解码解调数据的基准点。
上述方法中采用内部自生成时钟，保证解码后的数据与时钟的一致性，并且通过恢复时钟内部进行频移键控调制，求出晶体的晶振频率，反馈到解码端进行输入数据解码，提高解码准确性。
本发明还提出了一种频移键控调制信号的解调系统，所述系统包括：
处理模块，用于对外部射频系统发送的数据进行处理，获得两路中频频率的I/Q数据；将直流消除处理后的I/Q数据通过数控振荡器进行下变频处理以及频率偏移补偿，使得I/Q信号达到零中频化；
转化模块，用于将零中频化的I/Q数据通过低通滤波限制带外噪声，并进行时间相位转化后变为相位数据，并经过差分减法及判决运算后生成bit码流；
输出模块，用于将生成的bit码流与地址码进行比对，当比对结果错误数量小于预设的最大数量时，输出帧同步脉冲；
同步模块，用于将生成bit码流经过频率偏移计算后，输出频率偏移码，并经过解调后输出最终解调结果bit码流，并同时进行时钟同步处理。
本发明针对现有短距离无线通信频移键控解调系统实现难度大、依赖外部帧同步电路、同时误码率较高的问题，提出一种简单的、更准确频移键控的解调系统，该系统采用内部自同步码生成、可配置的帧同步码生成、及待反馈的频率偏移侦测补偿技术，代替传统频移键控解调技术，使解调系统能够达到更高的灵敏度、更低的误码率，以及使其实现复杂度大大降低。
进一步，所述处理模块包括：
高斯调制模块，用于对接收到的I/Q数据进行高斯调制，获得M长度bit的数据A；
解码比较模块，用于对数据A进行解码获得数据B，并将数据B与数据A进行减法运算获得频率偏移控制字并发送至数控振荡器；
频率控制模块，用于根据频率控制字调节数控振荡器输出频率。
通过以上处理过程可以使接收到的中频频率和数控振荡器产生的中频一致，保证接收数据零中频化，用于后续解调，而采用传统解调方式，没有在该过程中进行频率补偿，而是在数据判决前进行补偿，由于不能保证接收 到的数据零中频化，会将误差累积到判决的位置，这样灵敏度将下降，误码率也会上升。
进一步，所述转化模块中生成的bit码流数据中包括J bit前导、K bit地址码和I bit负载数据。
进一步，所述输出模块包括：
基准值计算模块，用于将接收到的bit码流数据累加J次前导数据，求取累加值的平均值作为基准值；
数据比较模块，用于将接收到的bit码流数据中的地址码数据与基准值相比较，如果地址码数据大于基准值，则待对比地址码为1，如果地址码数据小于基准值，则待对比地址码为0；
计数累加模块，用于在每完成一次bit码流数据中的地址码数据与基准值的比较并生成待对比地址码后，将待对比地址码与预先设定的地址码进行比较，如果相等，则计数器加1，如果不相等，则计数器保持当前数值不变；
脉冲生成模块，用于当比较的次数为K次后，如果K减去配置阈值的数值小于计数器数值，则同步完成并发出帧同步脉冲，如果K减去配置阈值的数值大于计数器数值，则进入重发流程。
传统技术首先是没有引入基准值概念，直接把接收到的数据和预先设定的地址码进行比对，实际在比对的过程由于受系统增益调整或直流消除等因素影响，可能导致接收到的地址码和预先设定的地址码大面积不相等，其次传统技术中也没有配置阈值的概念，只有K bit的地址码和K bit的预先设定的地址码完全匹配后，才表示帧同步成功，实际同样受比对过程中受系统增益调整或直流消除等因素影响，比对过程并不是完全可靠，只需要一定数量地址码匹配成功，即可认定帧同步完成。
进一步，所述同步模块包括：
解码模块，用于对接收到的频率偏移码进行解码，获得1bit负载数据；
时钟自恢复模块，用于根据解调信号以及采样频率自动恢复出时钟频率，并将时钟频率与负载数据进行比较后进行时钟周期调整，当时钟频率超前于负载数据时，时钟周期自增加；当时钟频率落后于负载数据时，时钟周期自减少，最终获得恢复的时钟信号；
编码模块，用于根据恢复的时钟信号，将解码后获得的负载数据进行编码，获得编码数据；
比较模块，用于将编码数据与外部输入的解调数据进行比较，进而获得晶振频率。
所述时钟同步模块中采用内部自生成时钟，保证解码后的数据与时钟的一致性，并且通过恢复时钟内部进行频移键控调制，求出晶体的晶振频率，反馈到解码端进行输入数据解码，提高解码准确性。
附图说明
图1为现有技术中频移键控调制的原理示意图；
图2为本发明实施例所述的频移键控调制信号的解调方法的流程图；
图3为本发明实施例所述的频率偏移补偿的流程图；
图4为本发明实施例所述的获得帧同步脉冲的流程图；
图5为本发明实施例所述的时钟同步处理的流程图；
图6为本发明实施例所述的频移键控调制信号的解调系统的原理示意图；
图7为本发明实施例所述的下变频处理模块的原理示意图；
图8为本发明实施例所述的时钟同步模块的原理示意图。
具体实施方式
以下结合附图对本发明的原理和特征进行描述，所举实例只用于解释本 发明，并非用于限定本发明的范围。
实施例1
如图2所示，本实施例提出一种频移键控调制信号的解调方法，所述方法包括：
SP1、对外部射频系统发送的数据进行处理，获得两路中频频率的I/Q数据；
SP2、对I/Q数据进行直流消除处理，去除直流偏移；
SP3、将直流消除处理后的I/Q数据通过数控振荡器进行下变频处理以及频率偏移补偿，使得I/Q信号达到零中频化；
SP4、将零中频化的I/Q数据通过低通滤波限制带外噪声，并进行时间相位转化后变为相位数据；
SP5、将相位数据通过低通滤波限制带外噪声，并经过差分减法及判决运算后生成bit码流，所述bit码流数据中包括J bit前导、K bit地址码和I bit负载数据；
SP6、将生成的bit码流与地址码进行比对，当比对结果错误数量小于预设的最大数量时，输出帧同步脉冲；
SP7、将生成的bit码流经过频率偏移计算后，输出频率偏移码；
SP8、输出的频率偏移码经过解调后，输出最终解调结果bit码流，并同时进行时钟同步处理。
本实施例针对现有短距离无线通信频移键控解调技术实现难度大，依赖外部帧同步电路，同时误码率较高的问题，提出一种简单的、更准确频移键控的解调方法，该方法采用内部自同步码生成、可配置的帧同步码生成、及待反馈的频率偏移侦测补偿技术，代替传统频移键控解调技术，使解调系统能够达到更高的灵敏度、更低的误码率，以及使其实现复杂度大大降低。
出于零点中频化输入I/Q数据的目的，其输入数据I/Q的频率ωRF和数 控振荡器产生的正余弦波形频率ω应该相等，才能达到零中频化的目的。输入数据I/Q的理想频率ωRF和数控振荡器产生的正余弦波形频率ω均为已知条件，但是输入数据I/Q的理想频率ωRF受传输信道和发射系统频率误差的影响，可能大于或小于理想频率ωRF。这将导致整个解调系统的误码率上升，为了解决该问题，本实施例提出了中将直流消除处理后的I/Q数据进行频率偏移补偿处理的方法，如图3所示，所述方法具体实现过程为：
SP31、对接收到的I/Q数据进行高斯调制，获得M长度bit的数据A；
SP32、对数据A进行解码获得数据B，并将数据B与数据A进行减法运算获得频率偏移控制字并发送至数控振荡器；
SP33、根据频率控制字调节数控振荡器输出频率。
经过上述过程，可以实时保证ωRF等于ω，即接收到的中频频率和接收系统内数控振荡器产生的中频一致，保证接收数据零中频化，用于后续解调。而采用传统解调方式，没有在该位置进行频率补偿，而是在数据判决前进行补偿，由于不能保证ωRF等于ω，则会将误差积累到判决的位置，这样灵敏度将下降，误码率将上升。
优选的，如图4所示，所述SP6中获得帧同步脉冲的过程为：
SP61、将接收到的bit码流数据累加J次前导数据，求取累加值的平均值作为基准值；
SP62、将接收到的bit码流数据中的地址码数据与基准值相比较，如果地址码数据大于基准值，则待对比地址码为1，如果地址码数据小于基准值，则待对比地址码为0；
SP63、在每完成一次bit码流数据中的地址码数据与基准值的比较并生成待对比地址码后，将待对比地址码与预先设定的地址码进行比较，如果相等，则计数器加1，如果不相等，则计数器保持当前数值不变；
SP64、当比较的次数为K次后，如果K减去配置阈值的数值小于计数器 数值，则同步完成并发出帧同步脉冲，如果K减去配置阈值的数值大于计数器数值，则进入重发流程。
通过以上过程可以保证解调系统大概率锁定地址码，产生同步脉冲，减少重发次数。
传统技术中首先没有引入基准值概念，直接把接收到的数据和预先设定的地址码进行比对，实际在比对的过程由于受系统增益调整或直流消除等因素影响，可能导致接收到的地址码和预先设定的地址码大面积不相等，其次传统技术中也没有配置阈值的概念，只有K bit的地址码和K bit的预先设定的地址码完全匹配后，才表示帧同步成功，实际同样受比对过程中受系统增益调整或直流消除等因素影响，比对过程并不是完全可靠，只需要一定数量地址码匹配成功，即可认定帧同步完成。
优选的，如图5所示，所述SP8中输出的频率偏移码经过解调后输出最终解调结果bit码流并同时进行时钟同步处理的过程为：
SP81、对接收到的频率偏移码进行解码，获得1bit负载数据；
SP82、根据解调信号以及采样频率自动恢复出时钟频率，并将时钟频率与负载数据进行比较后进行时钟周期调整，当时钟频率超前于负载数据时，时钟周期自增加；当时钟频率落后于负载数据时，时钟周期自减少，最终获得恢复的时钟信号；
SP83、根据恢复的时钟信号，将解码后获得的负载数据进行编码，获得编码数据；
SP84、将编码数据与外部输入的解调数据进行比较，进而获得晶振频率，并将所述晶振频率作为解码解调数据的基准点。
上述方法中采用内部自生成时钟，保证解码后的数据与时钟的一致性，并且通过恢复时钟内部进行频移键控调制，求出晶体的晶振频率，反馈到解码端进行输入数据解码，提高解码准确性。
实施例2
如图6所示，本实施例提出了一种频移键控调制信号的解调系统，所述系统包括：
原始数据处理模块，用于对外部射频系统发送的数据进行处理，获得两路中频频率的I/Q数据；
直流消除模块，用于对I/Q数据进行直流消除处理，去除直流偏移；
下变频处理模块，用于将直流消除处理后的I/Q数据通过数控振荡器进行下变频处理以及频率偏移补偿，使得I/Q信号达到零中频化；
数据转化模块，用于将零中频化的I/Q数据通过预解调滤波器限制带外噪声，并进行时间相位转化后变为相位数据；
码流生成模块，用于将相位数据通过后解调滤波器限制带外噪声，并经过差分减法及判决运算后生成bit码流；所述bit码流数据中包括J bit前导、K bit地址码和I bit负载数据。
脉冲输出模块，用于将生成的bit码流与地址码进行比对，当比对结果错误数量小于预设的最大数量时，输出帧同步脉冲；
频率偏移计算模块，用于将生成bit码流经过频率偏移计算后，输出频率偏移码；
时钟同步模块，用于输出的频率偏移码经过解调后，输出最终解调结果bit码流，并同时进行时钟同步处理。
该系统针对现有短距离无线通信频移键控解调系统实现难度大，依赖外部帧同步电路，同时误码率较高的问题，提出一种简单的、更准确频移键控的解调系统，该系统采用内部自同步码生成、可配置的帧同步码生成、及待反馈的频率偏移侦测补偿技术，代替传统频移键控解调技术，使解调系统能够达到更高的灵敏度、更低的误码率，以及使其实现复杂度大大降低。
出于零点中频化输入I/Q数据的目的，其输入数据I/Q的频率ωRF和数 控振荡器产生的正余弦波形频率ω应该相等，才能达到零中频化的目的。输入数据I/Q的理想频率ωRF和数控振荡器产生的正余弦波形频率ω均为已知条件，但是输入数据I/Q的理想频率ωRF受传输信道和发射系统频率误差的影响，可能大于或小于理想频率ωRF。这将导致整个解调系统的误码率上升，为了解决该问题，本实施例提出了下变频处理模块中将直流消除处理后的I/Q数据进行频率偏移补偿处理的具体实现方式，如图7所示，所述下变频处理模块包括：
高斯调制模块，用于对接收到的I/Q数据进行高斯调制，获得M长度bit的数据A；
解码比较模块，用于对数据A进行解码获得数据B，并将数据B与数据A进行减法运算获得频率偏移控制字并发送至数控振荡器；
频率控制模块，用于根据频率控制字调节数控振荡器输出频率。
通过以上处理过程可以使接收到的中频频率和数控振荡器产生的中频一致，保证接收数据零中频化，用于后续解调，而采用传统解调方式，没有在该过程中进行频率补偿，而是在数据判决前进行补偿，由于不能保证接收到的数据零中频化，会将误差累积到判决的位置，这样灵敏度将下降，误码率也会上升。
优选的，所述脉冲输出模块包括：
基准值计算模块，用于将接收到的bit码流数据累加J次前导数据，求取累加值的平均值作为基准值；
数据比较模块，用于将接收到的bit码流数据中的地址码数据与基准值相比较，如果地址码数据大于基准值，则待对比地址码为1，如果地址码数据小于基准值，则待对比地址码为0；
计数累加模块，用于在每完成一次bit码流数据中的地址码数据与基准值的比较并生成待对比地址码后，将待对比地址码与预先设定的地址码进行 比较，如果相等，则计数器加1，如果不相等，则计数器保持当前数值不变；
脉冲生成模块，用于当比较的次数为K次后，如果K减去配置阈值的数值小于计数器数值，则同步完成并发出帧同步脉冲，如果K减去配置阈值的数值大于计数器数值，则进入重发流程。
传统技术首先是没有引入基准值概念，直接把接收到的数据和预先设定的地址码进行比对，实际在比对的过程由于受系统增益调整或直流消除等因素影响，可能导致接收到的地址码和预先设定的地址码大面积不相等，其次传统技术中也没有配置阈值的概念，只有K bit的地址码和K bit的预先设定的地址码完全匹配后，才表示帧同步成功，实际同样受比对过程中受系统增益调整或直流消除等因素影响，比对过程并不是完全可靠，只需要一定数量地址码匹配成功，即可认定帧同步完成。
优选的，如图8所示，所述时钟同步模块包括：
解码模块，用于对接收到的频率偏移码进行解码，获得1bit负载数据；
时钟自恢复模块，用于根据解调信号以及采样频率自动恢复出时钟频率，并将时钟频率与负载数据进行比较后进行时钟周期调整，当时钟频率超前于负载数据时，时钟周期自增加；当时钟频率落后于负载数据时，时钟周期自减少，最终获得恢复的时钟信号；
编码模块，用于根据恢复的时钟信号，将解码后获得的负载数据进行编码，获得编码数据；
比较模块，用于将编码数据与外部输入的解调数据进行比较，进而获得晶振频率。
所述时钟同步模块中采用内部自生成时钟，保证解码后的数据与时钟的一致性，并且通过恢复时钟内部进行频移键控调制，求出晶体的晶振频率，反馈到解码端进行输入数据解码，提高解码准确性。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明 的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种频移键控调制信号的解调方法，其特征在于，所述方法包括：
    S1、对外部射频系统发送的数据进行处理，获得两路中频频率的I/Q数据，将直流消除处理后的I/Q数据通过数控振荡器进行下变频处理以及频率偏移补偿，使得I/Q数据达到零中频化；
    S2、将零中频化的I/Q数据变为相位数据后经过差分减法及判决运算后生成bit码流；
    S3、将生成的bit码流与地址码进行比对，当比对结果错误数量小于预设的最大数量时，输出帧同步脉冲；
    S4、将生成bit码流经过频率偏移计算后，输出频率偏移码，再经过解调后输出最终解调结果bit码流，并同时进行时钟同步处理。
  2. 根据权利要求1所述的一种频移键控调制信号的解调方法，其特征在于，所述S1中将直流消除处理后的I/Q数据进行频率偏移补偿处理的过程为：
    S11、对接收到的I/Q数据进行高斯调制，获得M长度bit的数据A；
    S12、对数据A进行解码获得数据B，并将数据B与数据A进行减法运算获得频率偏移控制字并发送至数控振荡器；
    S13、根据频率控制字调节数控振荡器的输出频率。
  3. 根据权利要求1或2所述的一种频移键控调制信号的解调方法，其特征在于，所述S2中生成的bit码流数据中包括J bit前导、K bit地址码和I bit负载数据。
  4. 根据权利要求3所述的一种频移键控调制信号的解调方法，其特征在于，所述S3中获得帧同步脉冲的过程为：
    S31、将接收到的bit码流数据累加J次前导数据，求取累加值的平均值作为基准值；
    S32、将接收到的bit码流数据中的地址码数据与基准值相比较，如果地址码数据大于基准值，则待对比地址码为1，如果地址码数据小于基准值，则待对比地址码为0；
    S33、在每完成一次bit码流数据中的地址码数据与基准值的比较并生成待对比地址码后，将待对比地址码与预先设定的地址码进行比较，如果相等，则计数器加1，如果不相等，则计数器保持当前数值不变；
    S34、当比较的次数为K次后，如果K减去配置阈值的数值小于计数器数值，则同步完成并发出帧同步脉冲，如果K减去配置阈值的数值大于计数器数值，则进入重发流程。
  5. 根据权利要求4所述的一种频移键控调制信号的解调方法，其特征在于，所述S4中输出的频率偏移码经过解调后输出最终解调结果bit码流，并同时进行时钟同步处理的过程为：
    S41、对接收到的频率偏移码进行解码，获得1bit负载数据；
    S42、根据解调信号以及采样频率自动恢复出时钟频率，并将时钟频率与负载数据进行比较后进行时钟周期调整，当时钟频率超前于负载数据时，时钟周期自增加；当时钟频率落后于负载数据时，时钟周期自减少，最终获得恢复的时钟信号；
    S43、根据恢复的时钟信号，将解码后获得的负载数据进行编码，获得编码数据；
    S44、将编码数据与外部输入的解调数据进行比较，进而获得晶振频率， 并将所述晶振频率作为解码解调数据的基准点。
  6. 一种频移键控调制信号的解调系统，其特征在于，所述系统包括：
    处理模块，用于对外部射频系统发送的数据进行处理，获得两路中频频率的I/Q数据；将直流消除处理后的I/Q数据通过数控振荡器进行下变频处理以及频率偏移补偿，使得I/Q信号达到零中频化；
    转化模块，用于将零中频化的I/Q数据通过低通滤波限制带外噪声，并进行时间相位转化后变为相位数据，并经过差分减法及判决运算后生成bit码流；
    输出模块，用于将生成的bit码流与地址码进行比对，当比对结果错误数量小于预设的最大数量时，输出帧同步脉冲；
    同步模块，用于将生成bit码流经过频率偏移计算后，输出频率偏移码，并经过解调后输出最终解调结果bit码流，并同时进行时钟同步处理。
  7. 根据权利要求6所述的一种频移键控调制信号的解调系统，其特征在于，所述处理模块包括：
    高斯调制模块，用于对接收到的I/Q数据进行高斯调制，获得M长度bit的数据A；
    解码比较模块，用于对数据A进行解码获得数据B，并将数据B与数据A进行减法运算获得频率偏移控制字；
    频率控制模块，用于根据频率控制字调节数控振荡器输出频率。
  8. 根据权利要求6或7所述的一种频移键控调制信号的解调系统，其特征在于，所述转化模块中生成的bit码流数据中包括J bit前导、K bit地址码和I bit负载数据。
  9. 根据权利要求8所述的一种频移键控调制信号的解调系统，其特征在于，所述输出模块包括：
    基准值计算模块，用于将接收到的bit码流数据累加J次前导数据，求取累加值的平均值作为基准值；
    数据比较模块，用于将接收到的bit码流数据中的地址码数据与基准值相比较，如果地址码数据大于基准值，则待对比地址码为1，如果地址码数据小于基准值，则待对比地址码为0；
    计数累加模块，用于在每完成一次bit码流数据中的地址码数据与基准值的比较并生成待对比地址码后，将待对比地址码与预先设定的地址码进行比较，如果相等，则计数器加1，如果不相等，则计数器保持当前数值不变；
    脉冲生成模块，用于当比较的次数为K次后，如果K减去配置阈值的数值小于计数器数值，则同步完成并发出帧同步脉冲，如果K减去配置阈值的数值大于计数器数值，则进入重发流程。
  10. 根据权利要求9所述的一种频移键控调制信号的解调系统，其特征在于，所述同步模块包括：
    解码模块，用于对接收到的频率偏移码进行解码，获得1bit负载数据；
    时钟自恢复模块，用于根据解调信号以及采样频率自动恢复出时钟频率，并将时钟频率与负载数据进行比较后进行时钟周期调整，当时钟频率超前于负载数据时，时钟周期自增加；当时钟频率落后于负载数据时，时钟周期自减少，最终获得恢复的时钟信号；
    编码模块，用于根据恢复时钟信号，将解码后获得的负载数据进行编码，获得编码数据；
    比较模块，用于将编码数据与外部输入的解调数据进行比较，进而获得 晶振频率。
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