WO2018072066A1 - 脉冲神经电路 - Google Patents

脉冲神经电路 Download PDF

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WO2018072066A1
WO2018072066A1 PCT/CN2016/102302 CN2016102302W WO2018072066A1 WO 2018072066 A1 WO2018072066 A1 WO 2018072066A1 CN 2016102302 W CN2016102302 W CN 2016102302W WO 2018072066 A1 WO2018072066 A1 WO 2018072066A1
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nmos device
transconductance amplifier
drain
gate
operational transconductance
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PCT/CN2016/102302
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English (en)
French (fr)
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张金勇
刘晨光
孙宏伟
王磊
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中国科学院深圳先进技术研究院
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Priority to PCT/CN2016/102302 priority Critical patent/WO2018072066A1/zh
Publication of WO2018072066A1 publication Critical patent/WO2018072066A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

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  • the invention relates to the field of artificial neural network technology, and in particular to a pulse neural circuit.
  • the so-called piecewise linearized Izhikevich model refers to the use of a segmentation description instead of the squared term in the Izhikevich model.
  • the expression is:
  • ⁇ represents the membrane potential
  • u represents the membrane recovery potential
  • I represents the input current
  • k 1 , k 2 , k 3 , a, b are constants
  • v th is the membrane potential threshold, and when the membrane potential exceeds the membrane potential threshold, then ⁇ And u are reassigned
  • c and d are constants, and different c and d values can be selected to obtain different modes of neural pulse mode.
  • the main implementation schemes of the impulse neural circuit of the Izhikevich model are as follows: (1) The squared property of the saturation region of the MOS tube is used to simulate the expression of the Izhikevich model. See Jayawan H B Wijekoon, Piotr Dudek. Compact silicon neuron circuit with spiking and bursting behavior. Neural Netw [J]. Neural Networks, 2008, 21(2-3): 524-34. (2) The expression of the Izhikevich model is simulated by the tau-cell structure in the form of a full current signal. See Van Schaik A, Jin C T, McEwan A L, et al. A log-domain implementation of the Izhikevich neuron model [C]. ISCAS.
  • the problem with the above implementation scheme is that, as in the above scheme (1), the MOS transistor operating in the saturation region consumes a large power supply voltage, so that the power consumption is large, and it is difficult to constitute a large-scale neural network; in addition, the MOS transistor saturation region can The squared term appears, but the expression implemented by the circuit formed under this scheme is still quite different from the expression of the Izhikevich model.
  • the circuit composed of the full current form in the scheme (2) converts all the variables in the Izhikevich model into current, but satisfies the relationship in the mathematical expression after the conversion, but the actual nerve pulse is caused by the injection of the ion current.
  • the changing membrane potential that is, the Izhikevich model
  • the scheme (3) adopts the combination of CCII and diode to realize the piecewise linearized Izhikevich model, which realizes the theory simple, but because of the diode, the circuit is difficult to integrate; at the same time, to ensure the normal operation of the CCII circuit, dual power supply is used, and the power supply mode is adopted. Complex and high supply voltage.
  • Embodiments of the present invention provide a pulse neural circuit for simplifying circuit implementation, improving circuit integration, and better simulating a piecewise linearized Izhikevich model under low voltage and low power consumption conditions, the pulse neural circuit including a pulse Generating a circuit and a membrane potential re-emphasis circuit;
  • a pulse generating circuit for calculating a transconductance amplifier, a current absolute value circuit connected to the operational transconductance amplifier, a current mirror, a first capacitor Cv for simulating a membrane potential, and a second capacitor Cu for simulating a membrane recovery potential, Constructed to simulate neural pulse oscillations;
  • a membrane potential re-emphasis circuit connected to the pulse generating circuit, the voltage comparator implemented by the transconductance amplifier, the switching circuit, configured to be used for the membrane potential re-evaluation.
  • the pulse neural circuit of the embodiment of the present invention is based on a piecewise linearized Izhikevich model, and uses a combination of a simple transimpedance amplifier, a current absolute value circuit, and a current mirror to obtain a plurality of neural pulse modes, which are compared with the existing circuit.
  • the implementation is simpler, and the absolute value circuit can be used to indirectly realize the absolute value calculation of the voltage.
  • the diode is removed compared with the existing scheme, so that the circuit is easier to integrate; the combination of voltage and current can better simulate the actual medium ion.
  • the relationship between current and membrane potential, relative to the existing scheme circuit to achieve function and mode The expressions in the type are more similar; and can achieve very low power design under low voltage operation, meeting the large-scale design requirements of neural circuits.
  • FIG. 1 is a view showing a specific example of a pulse neural circuit in an embodiment of the present invention
  • FIG. 2 is a specific example diagram of a structure of an OTA circuit according to an embodiment of the present invention.
  • FIG. 3 is a diagram showing another specific example of the structure of an OTA circuit according to an embodiment of the present invention.
  • FIG. 4 is a diagram showing a specific example of a current absolute value circuit according to an embodiment of the present invention.
  • FIG. 5 is a view showing a specific example of a current mirror according to an embodiment of the present invention.
  • the embodiment of the invention provides a pulse neural circuit based on segmentation.
  • the linearized Izhikevich model based on the piecewise linearization expression derived from the evolution of the Izhikevich model, uses a combination of simple modules such as an operational transconductance amplifier, a current absolute value circuit, and a current mirror to obtain a circuit with multiple neural pulse modes.
  • the circuit is easy to integrate and can achieve very low power design under low voltage operation, meeting the large-scale design requirements of neural circuits.
  • the embodiment of the present invention implements a pulsed neural circuit of a piecewise linearized Izhikevich model by combining a pulse generating circuit and a membrane potential reassignment circuit.
  • a pulse generating circuit for calculating a transconductance amplifier, a current absolute value circuit connected to the operational transconductance amplifier, a current mirror, a first capacitor Cv for simulating a membrane potential, and a second capacitor Cu for simulating a membrane recovery potential, Constructed for simulating neural pulse oscillation;
  • a membrane potential reassignment circuit coupled to a pulse generating circuit, a voltage comparator implemented by operating a transconductance amplifier, the switching circuit configured to be used for a membrane potential reassignment.
  • the specific implementation of the pulse neural circuit of the embodiment of the present invention will be described below with reference to the example of FIG.
  • the specific circuit structure shown in FIG. 1 is only one specific example of the pulse neural circuit in the embodiment of the present invention.
  • some or all of the structural units in the circuit can be completely deformed.
  • the same function can be realized by increasing or decreasing the transistor.
  • a specific structural redesign of the current absolute value circuit, the current mirror, the voltage comparator or the switching circuit is performed, and the implementation principle of the holding circuit is the same.
  • the pulse neural circuit may include a pulse generating circuit and a membrane potential re-emphasis circuit
  • the pulse generating circuit includes: a first operational transconductance amplifier OTA1, a second operational transconductance amplifier OTA2, and a third operational transconductance amplifier OTA3;
  • the first operational transconductance amplifier OTA1 positive voltage input terminal is connected to the second operational transconductance amplifier OTA2 positive voltage input terminal and the first capacitor C v positive terminal; the first operational transconductance amplifier OTA1 negative voltage input terminal is connected to the first voltage k 1 '
  • the first operational transconductance amplifier OTA1 output terminal is connected to the current absolute value circuit input terminal; the second operational transconductance amplifier OTA2 positive voltage input terminal is connected to the current mirror first input terminal; the second operational transconductance amplifier OTA2 negative voltage input terminal and output The terminal is shorted; the second operational transconductance amplifier OTA2 output is connected to the third operational transconductance amplifier OTA3 positive voltage input terminal and the second capacitor C u positive terminal; the third operational transconductance amplifier OTA3 negative voltage input terminal is connected to the second voltage k 3 '; The third operational transconductance amplifier OTA3 output is connected to the second input end of the current mirror; the first capacitor C v positive input is connected to the input current I, the negative pole
  • the membrane potential reassignment circuit includes: a fourth operational transconductance amplifier OTA4 as a voltage comparator, as a first PMOS device PMOS1 and a first NMOS device NMOS1 of the switching circuit;
  • the fourth operational transconductance amplifier OTA4 positive voltage input terminal is connected to the first capacitor C v positive pole and the first NMOS device NMOS1 drain; the fourth operational transconductance amplifier OTA4 negative voltage input terminal is connected to the third voltage V th ;
  • the positive current output terminal of the lead amplifier OTA4 is connected to the gate of the first NMOS device NMOS1; the negative terminal of the fourth operational transconductance amplifier OTA4 is connected to the gate of the first PMOS device PMOS1; the source of the first PMOS device PMOS1 is connected to the fourth voltage d;
  • the first PMOS device PMOS1 drain is connected to the second capacitor Cu positive; the first NMOS device NMOS1 source is connected to the fifth voltage c.
  • the input current of the second input of the current mirror is labeled I 2
  • the input current of the first input of the current mirror is labeled I 3
  • the current flowing through the first capacitor Cv and the second capacitor Cu can be expressed as:
  • v and u are voltages across the first capacitor C v and the second capacitor C u
  • ⁇ represents the membrane potential
  • u represents the membrane recovery potential
  • g m1 denotes a transconductance corresponding to the first operational transconductance amplifier OTA1
  • g m2 denotes a transconductance corresponding to the second operational transconductance amplifier OTA2
  • g m3 denotes a transconductance corresponding to the third operational transconductance amplifier OTA3.
  • k 4 and k 5 are constants. Comparing (5), (6) and (1), it can be seen that the pulse generation circuit can obtain the neural pulse oscillation in the piecewise linearized Izhikevich model more accurately.
  • the fourth operational transconductance amplifier OTA4 is a voltage comparator, and the first PMOS device PMOS1 and the first NMOS device NMOS1 are switching circuits.
  • v rises v is greater than the third voltage v th and reaches vdd due to the limitation of the voltage comparator and the switching speed, wherein the third voltage v th is a membrane potential threshold, which causes the first NMOS device NMOS1 to be turned on.
  • v is set to the fifth voltage c; and when the appropriate first PMOS device PMOS1 size is selected, since its on-time is short, u is not completely set to the fourth voltage d, but is controlled by the fourth voltage d Part of the charge is transferred to the second capacitor C u , thereby approximately realizing the re-estimation of the membrane potential, that is, the function performed by the equation (2).
  • the first operational transconductance amplifier OTA1, the second operational transconductance amplifier OTA2, the third operational transconductance amplifier OTA3, and the fourth operational transconductance amplifier OTA4 can be implemented in various ways.
  • 2 is a diagram showing a specific example of the structure of an OTA circuit according to an embodiment of the present invention. As shown in FIG. 2, the OTA circuit in this example adopts a structure composed of five MOS tubes, in which:
  • the second NMOS device NMOS2 source is connected to the third NMOS device NMOS3 source, and is grounded;
  • the second NMOS device NMOS2 gate is connected to the third NMOS device NMOS3 gate, and is short-circuited with the second NMOS device NMOS2 drain;
  • the second NMOS The drain of the NMOS2 of the device is connected to the drain of the PMOS2 of the second PMOS device, and serves as a negative current output terminal;
  • the drain of the third NMOS device NMOS3 is connected to the drain of the third PMOS device PMOS3 and serves as a positive current output terminal;
  • the second PMOS device PMOS2 gate is used as a positive voltage input terminal; the second PMOS device PMOS2 source is connected to the third PMOS device PMOS3 source and the fourth PMOS device PMOS4 drain;
  • the third PMOS device PMOS3 gate serves as a negative voltage input terminal
  • FIG. 3 is a diagram showing another specific example of the structure of an OTA circuit according to an embodiment of the present invention.
  • the OTA circuit in this example adopts a structure composed of five MOS tubes, in which:
  • the twelfth NMOS device NMOS12 source is connected to the thirteenth NMOS device NMOS13 source and the fourteenth NMOS device NMOS14 drain; the twelfth NMOS device NMOS12 gate is used as a positive voltage input terminal; the twelfth NMOS device NMOS12 is connected to the drain a seventh PMOS device PMOS7 drain, and as a negative current output;
  • the thirteenth NMOS device NMOS13 gate serves as a negative voltage input terminal; the thirteenth NMOS device NMOS13 drain is connected to the eighth PMOS device PMOS8 drain, and serves as a positive current output terminal;
  • the fourteenth NMOS device NMOS14 source is grounded; the fourteenth NMOS device NMOS14 gate is connected to the sixth voltage v b ;
  • the seventh PMOS device PMOS7 drain is shorted to the gate; the seventh PMOS device PMOS7 gate is connected to the eighth PMOS device PMOS8 gate; the seventh PMOS device PMOS7 source is connected to the eighth PMOS device PMOS8 source, and the input voltage is connected Vdd.
  • the first operational transconductance amplifier OTA1, the second operational transconductance amplifier OTA2, and the third operational transconductance amplifier OTA3 are in a non-inverting single-ended output mode;
  • the operational transconductance amplifier OTA4 uses a two-terminal output.
  • the current absolute value circuit can also be implemented in various ways.
  • 4 is a diagram showing a specific example of a current absolute value circuit according to an embodiment of the present invention. As shown in FIG. 4, the current absolute value circuit in this example adopts the following structure:
  • the drain of the fourth NMOS device NMOS4 is connected to the output terminal of the constant current source; the gate of the fourth NMOS device NMOS4 is connected to the gate of the fifth NMOS device NMOS5; the source of the fourth NMOS device NMOS4 is connected to the drain of the eighth NMOS device NMOS8;
  • the current source current is labeled as I B ;
  • the fifth NMOS device NMOS5 source is connected to the sixth NMOS device NMOS6 drain, and serves as the current absolute value circuit input terminal, the input current is labeled I i in FIG. 4; the fifth NMOS device NMOS5 drain is connected to the fifth PMOS device PMOS5 drain And a seventh NMOS device NMOS7 drain;
  • the drain of the sixth NMOS device NMOS6 is shorted to the gate; the gate of the sixth NMOS device NMOS6 is connected to the gate of the seventh NMOS device NMOS7; the source of the sixth NMOS device NMOS6 is connected to the source of the seventh NMOS device NMOS7, and is grounded;
  • the eighth NMOS device NMOS8 drain is shorted to the gate; the eighth NMOS device NMOS8 gate is connected to the ninth NMOS device NMOS9 gate; the eighth NMOS device NMOS8 source is connected to the ninth NMOS device NMOS9 source, and is grounded;
  • the drain of the ninth NMOS device NMOS9 is connected to the drain of the sixth PMOS device PMOS6, and serves as the output terminal of the current absolute value circuit.
  • the output current in FIG. 4 is labeled as I o ;
  • the sixth PMOS device PMOS6 gate is connected to the fifth PMOS device PMOS5 gate;
  • the sixth PMOS device PMOS6 source is connected to the fifth PMOS device PMOS5 source and the constant current source input terminal, and is connected to the input voltage vdd;
  • the fifth PMOS device PMOS5 is shorted to the drain of the gate.
  • the current absolute value circuit can obtain a positive output current regardless of whether the input current is positive or negative.
  • FIG. 5 is a schematic diagram of a specific example of a current mirror according to an embodiment of the present invention. As shown in FIG. 5, in this example, the current mirror adopts a basic current mirror structure, and is composed of an NMOS transistor, wherein:
  • the tenth NMOS device NMOS10 source is connected to the eleventh NMOS device NMOS11 source, and is grounded; the tenth NMOS device NMOS10 gate is connected to the eleventh NMOS device NMOS11 gate; the tenth NMOS device NMOS10 drain is shorted to the gate, And as the first input end of the current mirror, the current input to the first input end of the current mirror in FIG. 5 is labeled I i ;
  • the drain of the eleventh NMOS device NMOS11 serves as the second input of the current mirror, and the current of the second input terminal of the input current mirror in FIG. 5 is labeled I o .
  • the pulsed neural circuit operates in a subthreshold region, which can greatly reduce power consumption and power supply voltage.
  • the pulse neural circuit of the embodiment of the present invention has the following advantages:
  • a pulsed neural circuit based on the piecewise linearized Izhikevich model is realized by a simple circuit module combination, and the structure is simple.
  • pulse neural circuit works in the sub-threshold area, the power supply voltage and operating current is very low, greatly reducing power consumption, more suitable for the application in the construction of large-scale neural networks.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

Abstract

一种脉冲神经电路，该脉冲神经电路包括：脉冲产生电路和膜电位重赋值电路；脉冲产生电路，通过运算跨导放大器，与运算跨导放大器连接的电流绝对值电路、电流镜、用于模拟膜电位的第一电容Cv和用于模拟膜恢复电位的第二电容Cu，被构造为用于模拟神经脉冲振荡；与脉冲产生电路连接的膜电位重赋值电路，通过运算跨导放大器实现的电压比较器，开关电路，被构造为用于膜电位重赋值。该脉冲神经电路可以使电路实现更简单，提高电路集成度，并在低电压低功耗条件下更好的模拟分段线性化Izhikevich模型。

Description

脉冲神经电路 技术领域
本发明涉及人工神经网络技术领域，尤其涉及脉冲神经电路。
背景技术
在人工神经网络领域，脉冲神经网络的模拟与实现在近年来引起了人们的广泛关注。针对生理上神经脉冲的主要特征，人们提出了许多不同的模型来进行拟合，如I&F模型、Izhikevich模型和H-H模型等等，而Izhikevich模型由于能更高效、更简单地实现精确的神经脉冲的模拟，成为了最常用的模型之一。在神经系统的实现方面，VLSI可利用电子元件和电路来模拟神经行为，成为了计算神经科学的一种主要实现方式。这其中，模拟集成电路由于具有更高效、更低功耗等优势，成为了脉冲神经电路设计的主流。为更好地实现Izhikevich模型的脉冲神经电路设计，人们提出了一种分段线性化的Izhikevich模型，分段线性的改进可以使Izhikevich模型的实现电路更加简单、准确。
所谓分段线性化的Izhikevich模型，是指采用分段描述来替代Izhikevich模型中的平方项，其表达式为：
Figure PCTCN2016102302-appb-000001
当ν≥vth时，
Figure PCTCN2016102302-appb-000002
其中，ν表示膜电位，u表示膜恢复电位，I表示输入电流，k1、k2、k3、a、b为常数；vth为膜电位阈值，当膜电位超过膜电位阈值，则ν和u被重新赋值；c、d为常数，选择不同的c、d值可得到不同模式的神经脉冲模式。
目前Izhikevich模型的脉冲神经电路主要实现方案有：(1)采用MOS管饱和区的平方特性来模拟Izhikevich模型的表达式。参见文献Jayawan H B Wijekoon,Piotr Dudek.Compact silicon neuron circuit with spiking and bursting behavior.Neural Netw[J].Neural Networks,2008,21(2-3):524-34。(2)采用tau-cell结构以全电流信号的方式模拟Izhikevich模型的表达式。参见文献Van Schaik A,Jin C T,McEwan A L,et al.A log-domain implementation of the Izhikevich neuron model[C].ISCAS.2010:4253-4256。(3) 采用CCII和二极管组合的方式实现分段线性化的Izhikevich模型。参见文献Sharifipoor O,Ahmadi A.An analog implementation of biologically plausible neurons using CCII building blocks[J].Neural Networks the Official Journal of the International Neural Network Society,2012,36C(8):129-135。
上述实现方案的问题在于：如上述方案(1)采用饱和区工作的MOS管会消耗较大的电源电压，使得功耗较大，很难构成大规模神经网络；此外，MOS管饱和区尽管能够出现平方项，但该方案下构成的电路所实现的表达式与Izhikevich模型的表达式仍有很大差别。方案(2)中全电流形式构成的电路是将Izhikevich模型中的变量全部转换为电流，只是满足了转换后的数学表达式中的关系，然而实际的神经脉冲是由离子电流的注入而引起的变化的膜电位，也即Izhikevich模型所要模拟的是电压与电流之间的转化关系；此外该电路中用到了很多的偏置电流，会增加电路实现的难度。方案(3)采用CCII和二极管组合的方式实现分段线性化的Izhikevich模型，实现理论简单，但由于采用了二极管，该电路难以集成；同时，为保证CCII电路正常工作采用双电源供电，供电方式复杂且电源电压较高。
发明内容
本发明实施例提供一种脉冲神经电路，用以使电路实现更简单，提高电路集成度，并在低电压低功耗条件下更好的模拟分段线性化Izhikevich模型，该脉冲神经电路包括脉冲产生电路和膜电位重赋值电路；
脉冲产生电路，通过运算跨导放大器，与运算跨导放大器连接的电流绝对值电路、电流镜、用于模拟膜电位的第一电容Cv和用于模拟膜恢复电位的第二电容Cu，被构造为用于模拟神经脉冲振荡；
与脉冲产生电路连接的膜电位重赋值电路，通过运算跨导放大器实现的电压比较器，开关电路，被构造为用于膜电位重赋值。
本发明实施例的脉冲神经电路基于分段线性化Izhikevich模型，采用运算跨导放大器、电流绝对值电路和电流镜等简单电路模块的组合，得到多种神经脉冲模式，相对于现有方案电路的实现更简单，且采用电流绝对值电路可以间接实现电压的绝对值运算，相对于现有方案去掉了二极管，使得电路更易集成；采用电压与电流相结合的方式，可以更好的模拟实际中离子电流与膜电位之间的关系，相对于现有方案电路实现功能与模 型中的表达式更相近；并且可以实现低电压工作下的甚低功耗设计，满足神经电路大规模的设计需求。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1为本发明实施例中脉冲神经电路的具体实例图；
图2为本发明实施例中OTA电路结构的一个具体实例图；
图3为本发明实施例中OTA电路结构的另一具体实例图；
图4为本发明实施例中电流绝对值电路的一个具体实例图；
图5为本发明实施例中电流镜的一个具体实例图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚明白，下面结合附图对本发明实施例做进一步详细说明。在此，本发明的示意性实施例及其说明用于解释本发明，但并不作为对本发明的限定。
为了使电路实现更简单，提高电路集成度，并在低电压低功耗条件下更好的模拟分段线性化Izhikevich模型，本发明实施例提供一种脉冲神经电路，该脉冲神经电路基于分段线性化Izhikevich模型，根据由Izhikevich模型演变得到的分段线性化表达式，采用运算跨导放大器、电流绝对值电路和电流镜等简单模块的组合，得到了具有多种神经脉冲方式的电路，该电路容易集成，可以实现低电压工作下的甚低功耗设计，满足神经电路大规模的设计需求。
具体实施时，本发明实施例采用脉冲产生电路与膜电位重赋值电路相结合的方式实现分段线性化Izhikevich模型的脉冲神经电路。脉冲产生电路，通过运算跨导放大器，与运算跨导放大器连接的电流绝对值电路、电流镜、用于模拟膜电位的第一电容Cv和用于模拟膜恢复电位的第二电容Cu，被构造为用于模拟神经脉冲振荡；与脉冲产生电路连接的膜电位重赋值电路，通过运算跨导放大器实现的电压比较器，开关电路，被构造为用于膜电位重赋值。
下面结合图1的示例说明本发明实施例的脉冲神经电路的具体实施。当然，本领域技术人员容易理解，图1所示的具体电路结构仅为实现本发明实施例脉冲神经电路的一个具体实例，在具体实施时完全可以将电路中的部分或全部结构单元进行变形，例如可以通过增加或增少晶体管来实现相同的功能，进一步的，比如对于电流绝对值电路、电流镜、电压比较器或开关电路进行具体结构上的重新设计，而保持电路的实现原理相同。
如图1所示，在本例中该脉冲神经电路可以包括脉冲产生电路和膜电位重赋值电路；
脉冲产生电路包括：第一运算跨导放大器OTA1，第二运算跨导放大器OTA2，第三运算跨导放大器OTA3；
第一运算跨导放大器OTA1正电压输入端连接第二运算跨导放大器OTA2正电压输入端和第一电容Cv正极；第一运算跨导放大器OTA1负电压输入端接入第一电压k1'；第一运算跨导放大器OTA1输出端连接电流绝对值电路输入端；第二运算跨导放大器OTA2正电压输入端连接电流镜第一输入端；第二运算跨导放大器OTA2负电压输入端与输出端短接；第二运算跨导放大器OTA2输出端连接第三运算跨导放大器OTA3正电压输入端和第二电容Cu正极；第三运算跨导放大器OTA3负电压输入端接入第二电压k3'；第三运算跨导放大器OTA3输出端连接电流镜第二输入端；第一电容Cv正极接入输入电流I，负极接地；第二电容Cu负极接地；电流绝对值电路输出端连接第一电容Cv正极；
膜电位重赋值电路包括：作为电压比较器的第四运算跨导放大器OTA4，作为开关电路的第一PMOS器件PMOS1和第一NMOS器件NMOS1；
第四运算跨导放大器OTA4正电压输入端连接第一电容Cv正极和第一NMOS器件NMOS1漏极；第四运算跨导放大器OTA4负电压输入端接入第三电压Vth；第四运算跨导放大器OTA4正电流输出端连接第一NMOS器件NMOS1栅极；第四运算跨导放大器OTA4负电流输出端连接第一PMOS器件PMOS1栅极；第一PMOS器件PMOS1源极接入第四电压d；第一PMOS器件PMOS1漏极连接第二电容Cu正极；第一NMOS器件NMOS1源极接入第五电压c。
在图1中，电流镜第二输入端的输入电流标记为I2，电流镜第一输入端的输入电流标记为I3，由电流绝对值电路输出端信号线提供至第二电容Cu正极的电流标记为I1。
由图1可知，流经第一电容Cv和第二电容Cu的电流可分别表示为：
Figure PCTCN2016102302-appb-000003
Figure PCTCN2016102302-appb-000004
其中v、u分别为第一电容Cv和第二电容Cu两端电压，ν表示膜电位，u表示膜恢复电位。gm1表示第一运算跨导放大器OTA1对应的跨导，gm2表示第二运算跨导放大器OTA2对应的跨导，gm3表示第三运算跨导放大器OTA3对应的跨导。对(3)式和(4)式进行简化可得到：
Figure PCTCN2016102302-appb-000005
Figure PCTCN2016102302-appb-000006
k4、k5为常数。对比(5)式、(6)式与(1)式可看出，脉冲产生电路可以较为精确的得到分段线性化Izhikevich模型中的神经脉冲振荡。
在膜电位重赋值电路中，第四运算跨导放大器OTA4为电压比较器，第一PMOS器件PMOS1和第一NMOS器件NMOS1为开关电路。当v上升时，由于电压比较器和开关速度的限制，v会大于第三电压vth并达到vdd，其中第三电压vth为膜电位阈值，此时会使得第一NMOS器件NMOS1导通，v置为第五电压c；而当选择合适的第一PMOS器件PMOS1尺寸时，由于其导通时间很短，u不会完全置为第四电压d，而会使得受第四电压d控制的部分电荷转移到第二电容Cu上，从而近似的实现了膜电位的重赋值，即式(2)所完成的功能。
在本发明实施例中，第一运算跨导放大器OTA1，第二运算跨导放大器OTA2，第三运算跨导放大器OTA3，第四运算跨导放大器OTA4可以有多种实现方式。图2为本发明实施例中OTA电路结构的一个具体实例图，如图2所示，本例中OTA电路采用由五个MOS管构成的结构，在该结构中：
第二NMOS器件NMOS2源极连接第三NMOS器件NMOS3源极，并接地；第二NMOS器件NMOS2栅极连接第三NMOS器件NMOS3栅极，并与第二NMOS器件NMOS2漏极短接；第二NMOS器件NMOS2漏极连接第二PMOS器件PMOS2漏极，并作为负电流输出端；
第三NMOS器件NMOS3漏极连接第三PMOS器件PMOS3漏极，并作为正电流输出端；
第二PMOS器件PMOS2栅极作为正电压输入端；第二PMOS器件PMOS2源极连接第三PMOS器件PMOS3源极和第四PMOS器件PMOS4漏极；
第三PMOS器件PMOS3栅极作为负电压输入端；
第四PMOS器件PMOS4栅极接入第六电压vb；第四PMOS器件PMOS4源极接入输入电压vdd。
又如，采用输入管为NMOS的OTA，依然可以实现电路功能。图3为本发明实施例中OTA电路结构的另一具体实例图，如图3所示，本例中OTA电路采用由五个MOS管构成的结构，在该结构中：
第十二NMOS器件NMOS12源极连接第十三NMOS器件NMOS13源极和第十四NMOS器件NMOS14漏极；第十二NMOS器件NMOS12栅极作为正电压输入端；第十二NMOS器件NMOS12漏极连接第七PMOS器件PMOS7漏极，并作为负电流输出端；
第十三NMOS器件NMOS13栅极作为负电压输入端；第十三NMOS器件NMOS13漏极连接第八PMOS器件PMOS8漏极，并作为正电流输出端；
第十四NMOS器件NMOS14源极接地；第十四NMOS器件NMOS14栅极接第六电压vb；
第七PMOS器件PMOS7漏极与栅极短接；第七PMOS器件PMOS7栅极连接第八PMOS器件PMOS8栅极；第七PMOS器件PMOS7源极连接第八PMOS器件PMOS8源极，并接入输入电压vdd。
在具体的实例中，例如在图2或图3所示实例中，第一运算跨导放大器OTA1、第二运算跨导放大器OTA2和第三运算跨导放大器OTA3采用同相单端输出方式；第四运算跨导放大器OTA4采用双端输出方式。
实施时电流绝对值电路也可以有多种实现方式。图4为本发明实施例中电流绝对值电路的一个具体实例图，如图4所示，本例中电流绝对值电路采用如下结构：
第四NMOS器件NMOS4漏极连接恒流源输出端；第四NMOS器件NMOS4栅极连接第五NMOS器件NMOS5栅极；第四NMOS器件NMOS4源极连接第八NMOS器件NMOS8漏极；图4中恒流源电流标记为IB；
第五NMOS器件NMOS5源极连接第六NMOS器件NMOS6漏极，并作为电流绝对值电路输入端，图4中输入电流标记为Ii；第五NMOS器件NMOS5漏极连接第五PMOS器件PMOS5漏极和第七NMOS器件NMOS7漏极；
第六NMOS器件NMOS6漏极与栅极短接；第六NMOS器件NMOS6栅极连接第七NMOS器件NMOS7栅极；第六NMOS器件NMOS6源极连接第七NMOS器件NMOS7源极，并接地；
第八NMOS器件NMOS8漏极与栅极短接；第八NMOS器件NMOS8栅极连接第九NMOS器件NMOS9栅极；第八NMOS器件NMOS8源极连接第九NMOS器件NMOS9源极，并接地；
第九NMOS器件NMOS9漏极连接第六PMOS器件PMOS6漏极，并作为电流绝对值电路输出端，图4中输出电流标记为Io；
第六PMOS器件PMOS6栅极连接第五PMOS器件PMOS5栅极；第六PMOS器件PMOS6源极连接第五PMOS器件PMOS5源极和恒流源输入端，并接入输入电压vdd；
第五PMOS器件PMOS5栅极与漏极短接。
不论输入电流为正为负，电流绝对值电路均可得到正向的输出电流。
实施时电流镜也可以有多种实现方式，例如采用基本电流镜结构，或是采用威尔逊电流镜结构，又或是采用级联电流镜结构均可。图5为本发明实施例中电流镜的一个具体实例图，如图5所示，本例中电流镜采用基本电流镜结构，由NMOS管构成，其中：
第十NMOS器件NMOS10源极连接第十一NMOS器件NMOS11源极，并接地；第十NMOS器件NMOS10栅极连接第十一NMOS器件NMOS11栅极；第十NMOS器件NMOS10漏极与栅极短接，并作为电流镜第一输入端，图5中输入电流镜第一输入端的电流标记为Ii；
第十一NMOS器件NMOS11漏极作为电流镜第二输入端，图5中输入电流镜第二输入端的电流标记为Io。
实施例中脉冲神经电路工作在亚阈值区域，可以使功耗和电源电压大大降低。
综上所述，本发明实施例的脉冲神经电路具备如下优点：
1、结构方面：本发明实施例采用简单电路模块组合的方式，实现了一种基于分段线性化Izhikevich模型的脉冲神经电路，结构简单。
2、功耗方面：脉冲神经电路工作在亚阈区，电源电压和工作电流很低，大大降低了功耗，更适合在构建大规模神经网络中应用。
3、精确性方面：简单模块的组合使得电路实现的函数功能与分段线性化Izhikevich模型的函数表达式更加相似，模拟的神经脉冲更加精确。
4、集成方面：采用电流绝对值电路可以间接实现电压绝对值的运算，相对于现有技术去掉了二极管，且在单电源下即可正常工作，使得电路更易集成。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种脉冲神经电路，其特征在于，包括脉冲产生电路和膜电位重赋值电路；
    脉冲产生电路，通过运算跨导放大器，与运算跨导放大器连接的电流绝对值电路、电流镜、用于模拟膜电位的第一电容Cv和用于模拟膜恢复电位的第二电容Cu，被构造为用于模拟神经脉冲振荡；
    与脉冲产生电路连接的膜电位重赋值电路，通过运算跨导放大器实现的电压比较器，开关电路，被构造为用于膜电位重赋值。
  2. 如权利要求1所述的脉冲神经电路，其特征在于，脉冲产生电路包括：第一运算跨导放大器OTA1，第二运算跨导放大器OTA2，第三运算跨导放大器OTA3；
    第一运算跨导放大器OTA1正电压输入端连接第二运算跨导放大器OTA2正电压输入端和第一电容Cv正极；第一运算跨导放大器OTA1负电压输入端接入第一电压k1'；第一运算跨导放大器OTA1输出端连接电流绝对值电路输入端；第二运算跨导放大器OTA2正电压输入端连接电流镜第一输入端；第二运算跨导放大器OTA2负电压输入端与输出端短接；第二运算跨导放大器OTA2输出端连接第三运算跨导放大器OTA3正电压输入端和第二电容Cu正极；第三运算跨导放大器OTA3负电压输入端接入第二电压k3'；第三运算跨导放大器OTA3输出端连接电流镜第二输入端；第一电容Cv正极接入输入电流I，负极接地；第二电容Cu负极接地；电流绝对值电路输出端连接第一电容Cv正极；
    膜电位重赋值电路包括：第四运算跨导放大器OTA4，第一PMOS器件PMOS1，第一NMOS器件NMOS1；
    第四运算跨导放大器OTA4正电压输入端连接第一电容Cv正极和第一NMOS器件NMOS1漏极；第四运算跨导放大器OTA4负电压输入端接入第三电压vth；第四运算跨导放大器OTA4正电流输出端连接第一NMOS器件NMOS1栅极；第四运算跨导放大器OTA4负电流输出端连接第一PMOS器件PMOS1栅极；第一PMOS器件PMOS1源极接入第四电压d；第一PMOS器件PMOS1漏极连接第二电容Cu正极；第一NMOS器件NMOS1源极接入第五电压c。
  3. 如权利要求2所述的脉冲神经电路，其特征在于，第一运算跨导放大器OTA1，第二运算跨导放大器OTA2，第三运算跨导放大器OTA3，第四运算跨导放大器OTA4采用由五个MOS管构成的结构，在该结构中：
    第二NMOS器件NMOS2源极连接第三NMOS器件NMOS3源极，并接地；第二NMOS器件NMOS2栅极连接第三NMOS器件NMOS3栅极，并与第二NMOS器件NMOS2漏极短接；第二NMOS器件NMOS2漏极连接第二PMOS器件PMOS2漏极，并作为负电流输出端；
    第三NMOS器件NMOS3漏极连接第三PMOS器件PMOS3漏极，并作为正电流输出端；
    第二PMOS器件PMOS2栅极作为正电压输入端；第二PMOS器件PMOS2源极连接第三PMOS器件PMOS3源极和第四PMOS器件PMOS4漏极；
    第三PMOS器件PMOS3栅极作为负电压输入端；
    第四PMOS器件PMOS4栅极接入第六电压vb；第四PMOS器件PMOS4源极接入输入电压vdd。
  4. 如权利要求2所述的脉冲神经电路，其特征在于，第一运算跨导放大器OTA1，第二运算跨导放大器OTA2，第三运算跨导放大器OTA3，第四运算跨导放大器OTA4采用由五个MOS管构成的结构，在该结构中：
    第十二NMOS器件NMOS12源极连接第十三NMOS器件NMOS13源极和第十四NMOS器件NMOS14漏极；第十二NMOS器件NMOS12栅极作为正电压输入端；第十二NMOS器件NMOS12漏极连接第七PMOS器件PMOS7漏极，并作为负电流输出端；
    第十三NMOS器件NMOS13栅极作为负电压输入端；第十三NMOS器件NMOS13漏极连接第八PMOS器件PMOS8漏极，并作为正电流输出端；
    第十四NMOS器件NMOS14源极接地；第十四NMOS器件NMOS14栅极接第六电压vb；
    第七PMOS器件PMOS7漏极与栅极短接；第七PMOS器件PMOS7栅极连接第八PMOS器件PMOS8栅极；第七PMOS器件PMOS7源极连接第八PMOS器件PMOS8源极，并接入输入电压vdd。
  5. 如权利要求2所述的脉冲神经电路，其特征在于，第一运算跨导放大器OTA1、第二运算跨导放大器OTA2和第三运算跨导放大器OTA3采用同相单端输出方式；第四运算跨导放大器OTA4采用双端输出方式。
  6. 如权利要求1所述的脉冲神经电路，其特征在于，电流绝对值电路采用如下结构：
    第四NMOS器件NMOS4漏极连接恒流源输出端；第四NMOS器件NMOS4栅极连接第五NMOS器件NMOS5栅极；第四NMOS器件NMOS4源极连接第八NMOS器件NMOS8漏极；
    第五NMOS器件NMOS5源极连接第六NMOS器件NMOS6漏极，并作为电流绝对值电路输入端；第五NMOS器件NMOS5漏极连接第五PMOS器件PMOS5漏极和第七NMOS器件NMOS7漏极；
    第六NMOS器件NMOS6漏极与栅极短接；第六NMOS器件NMOS6栅极连接第七NMOS器件NMOS7栅极；第六NMOS器件NMOS6源极连接第七NMOS器件NMOS7源极，并接地；
    第八NMOS器件NMOS8漏极与栅极短接；第八NMOS器件NMOS8栅极连接第九NMOS器件NMOS9栅极；第八NMOS器件NMOS8源极连接第九NMOS器件NMOS9源极，并接地；
    第九NMOS器件NMOS9漏极连接第六PMOS器件PMOS6漏极，并作为电流绝对值电路输出端；
    第六PMOS器件PMOS6栅极连接第五PMOS器件PMOS5栅极；第六PMOS器件PMOS6源极连接第五PMOS器件PMOS5源极和恒流源输入端，并接入输入电压vdd；
    第五PMOS器件PMOS5栅极与漏极短接。
  7. 如权利要求1所述的脉冲神经电路，其特征在于，电流镜采用由NMOS管构成，并采用如下结构：
    第十NMOS器件NMOS10源极连接第十一NMOS器件NMOS11源极，并接地；第十NMOS器件NMOS10栅极连接第十一NMOS器件NMOS11栅极；第十NMOS器件NMOS10漏极与栅极短接，并作为电流镜第一输入端；
    第十一NMOS器件NMOS11漏极作为电流镜第二输入端。
  8. 如权利要求1所述的脉冲神经电路，其特征在于，电流镜采用威尔逊电流镜结构。
  9. 如权利要求1所述的脉冲神经电路，其特征在于，电流镜采用级联电流镜结构。
  10. 如权利要求1所述的脉冲神经电路，其特征在于，所述脉冲神经电路工作在亚阈值区域。
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