WO2018058625A1 - 一种检测报文反压的方法及装置 - Google Patents

一种检测报文反压的方法及装置 Download PDF

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Publication number
WO2018058625A1
WO2018058625A1 PCT/CN2016/101304 CN2016101304W WO2018058625A1 WO 2018058625 A1 WO2018058625 A1 WO 2018058625A1 CN 2016101304 W CN2016101304 W CN 2016101304W WO 2018058625 A1 WO2018058625 A1 WO 2018058625A1
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WIPO (PCT)
Prior art keywords
packet
duration
buffer
message
threshold
Prior art date
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PCT/CN2016/101304
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English (en)
French (fr)
Inventor
张斌
陈立钢
陈加怀
许利霞
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2016/101304 priority Critical patent/WO2018058625A1/zh
Priority to EP16898144.7A priority patent/EP3328009B1/en
Priority to EP20157554.5A priority patent/EP3754918A1/en
Priority to ES16898144T priority patent/ES2796609T3/es
Priority to JP2017554451A priority patent/JP6660400B2/ja
Priority to PCT/CN2016/106134 priority patent/WO2018058764A1/zh
Priority to CN201680006002.9A priority patent/CN108432193B/zh
Publication of WO2018058625A1 publication Critical patent/WO2018058625A1/zh
Priority to US16/250,168 priority patent/US10599549B2/en
Priority to US16/653,326 priority patent/US11550694B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3485—Performance evaluation by tracing or monitoring for I/O devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3041—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is an input/output interface
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G06F13/4269—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using a handshaking protocol, e.g. Centronics connection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the present invention relates to the field of computer technologies, and in particular, to a method and apparatus for detecting a back pressure of a message.
  • PCIe Peripheral Component Interconnect Express
  • devices with PCIe ports can transmit packets through the PCIe port.
  • a central processing unit CPU
  • CPU central processing unit
  • UP uplink port
  • DP downstream port
  • EP end point
  • the CPU sends a packet to the EP
  • the CPU first sends the packet to the UP of the PCIe switch.
  • the UP of the PCIe switch sends the packet to the DP connected to the EP, and then the DP sends the packet to the EP.
  • the packets to be sent at the PCIe port are backlogged, that is, the packet is back pressured. If the packet is not detected in time, the device that sends the packet will be sent. An instruction timeout occurred and eventually caused the device to hang and not work properly.
  • An existing packet backpressure detection method is: all the to-be-sent packets at the PCIe port are stored in the cache unit, and a timer is set for each packet stored in the cache unit, and the packet is recorded in the cache. The storage duration of the unit is determined. When the timer set for any packet times out, it is determined that the PCIe port sends a packet backpressure, and sends an error packet to the error processing unit that the packet is reversed on the PCIe port.
  • a device may include multiple PCIe ports, and a large number of packets to be sent are usually stored in the cache unit at each PCIe port.
  • the backpressure detection method in the prior art causes a large number of timer resources to be applied.
  • the error handling unit receives a large number of error handling reports, causing the internal bandwidth of the device to be excessively occupied, resulting in wasted resources in the device.
  • the present invention provides a method and a device for detecting a packet back pressure, which are used to solve the problem of excessive overhead of detecting a packet backpressure scheme in the prior art.
  • the present application provides a method for detecting packet backpressure, which is applied to a device having a PCIe port.
  • the device may be a CPU with a PCIe port device, a PCIe switch, or an End Point (EP).
  • the PCIe port is a PCIe port of the CPU, such as a root complex (RC).
  • the device stores the packet that needs to be sent in the buffer.
  • the packet stored in the buffer is in the buffer. It is removed from the buffer after being sent via the PCIe port, and the buffer stores at most one message at any time.
  • the buffer may be a separate storage device, such as a random access memory (RAM), a flash disk, or a storage area divided from the storage device.
  • RAM random access memory
  • the storage time of each packet stored in the device record buffer is accumulated, and the storage duration of each packet is accumulated to obtain the accumulated duration of the buffer storage message. When the accumulated duration reaches the first threshold, it is determined.
  • the packet is back pressured on the PCIe port.
  • the function of storing the length of each message stored in the above recording buffer may be implemented by a hardware module having a timing function in the device, or may be implemented by an application executing by the CPU of the device.
  • the device determines the backpressure of the packet on the PCIe port
  • the packet is back-pressured in one direction for one PCIe port, and only one packet is stored in the buffer at any time, compared with the existing one.
  • the scheme for timing each packet to be sent on the PCIe port can greatly reduce the system overhead.
  • the device when the PCIe port is back pressured due to a link failure, the device only generates a packet backpressure error for the link fault, which avoids the occurrence of an error storm and improves system stability.
  • the device stores the recorded buffer under the set conditions.
  • the cumulative duration of the text is reduced.
  • the manner of reducing includes clearing the accumulated duration, or subtracting the storage duration of a sent message from the accumulated duration.
  • the implementation of the method can prevent the device from determining that the PCIe port sends a packet back pressure due to the accumulation of the storage time of the normal packet that is not a backpressure packet, and improves the accuracy of detecting the back pressure of the packet.
  • the device resets the accumulated duration of the buffer storage message to 0 under a preset condition.
  • the implementation of the method can prevent the device from determining that the PCIe port sends a packet back pressure due to the accumulation of the storage time of the normal packet that is not a backpressure packet, and improves the accuracy of detecting the back pressure of the packet.
  • the device sets a zeroing timer and performs timing. When the time recorded by the clearing timer reaches the second threshold, the accumulated duration of the buffer storage message is reset to 0. .
  • the zeroing timer can be implemented by the processor of the device executing application instructions or by a hardware module as a timer in the device. The implementation of the method can prevent the device from determining that the PCIe port sends a packet back pressure due to the accumulation of the storage time of the normal packet that is not a backpressure packet, and improves the accuracy of detecting the back pressure of the packet.
  • the device records the number of packets stored in the buffer, and resets the accumulated duration of the buffer storage message to 0 when the number of records reaches the third threshold.
  • the counting function can be implemented by the processor of the device executing application instructions or by a hardware module as a counter in the device.
  • the implementation of the method can prevent the device from determining that the PCIe port sends a packet back pressure due to the accumulation of the storage time of the normal packet that is not a backpressure packet, and improves the accuracy of detecting the back pressure of the packet.
  • the storage duration of each packet in the buffer sequentially recorded by the device forms a queue of lengths.
  • the length of the queue reaches the fourth threshold, the first record is deleted from the duration queue.
  • the storage duration, and the storage duration of the first record deleted from the duration queue is subtracted from the accumulated duration.
  • the accumulated duration is the sum of the set length of the buffer recently cached (the set number is the fourth threshold) in the buffer, and the peak of the packet storage duration is not Divided into two statistical units, ensuring that the peak value of the message storage duration is always detected, improving the sensitivity of the message back pressure detection.
  • the storage duration of each packet in the buffer recorded by the device is formed into a duration queue, and the device accumulates all the durations in the duration queue to obtain a window duration; when the duration of the queue reaches the length
  • the storage duration of the first record is deleted from the duration queue, and the storage duration of the first record deleted from the duration queue is subtracted from the window duration.
  • the device is changed to the sixth threshold, the packet is back pressured on the PCIe port. Since the duration of the window is not reset to 0, the peak value of the packet storage duration is always detected, which improves the sensitivity of the packet back pressure detection.
  • the device determines that the PCIe port generates a packet backpressure after the stored storage time of the packet in the buffer reaches a fifth threshold, where the fifth threshold is less than the first threshold. In this implementation manner, if the storage duration of any packet is greater than the fifth threshold, the device determines that the packet is back pressured, and then the packet is buffered in the buffer for a long time but has not caused the accumulated duration to exceed the first time. At the threshold, it is determined as soon as possible that the message back pressure occurs, and the sensitivity of the device to detect the back pressure of the message is improved.
  • the device when the to-be-sent packet in the packet sending queue in the first direction of the PCIe port becomes the current packet to be sent by the PCIe port, the device And storing the packet to be sent in the first direction in a buffer; the first direction is an uplink direction or a downlink direction of the PCIe port.
  • the device performs the The packet to be sent is stored in the second buffer, the second direction is opposite to the first direction, and the packet stored in the second buffer is sent from the second buffer after being sent via the PCIe port.
  • the second buffer stores at most one message at any time; the device records the storage duration of each message stored in the second buffer, and stores the second buffer of the record.
  • the storage duration of each packet is accumulated to obtain a second accumulated duration of the second buffer storage message; when the second accumulated duration reaches the first threshold, the device determines the PCIe port A message back pressure occurred.
  • the device can detect the back pressure of the packet to be sent in the uplink and downlink directions of the same port of the PCIe switch, and improve the sensitivity and pertinence of the packet back pressure detection.
  • the device further includes: a second PCIe port; the device is further configured to: each of the to-be-sent packets in the packet sending queue of the second PCIe port becomes the second PCIe port
  • the packet that needs to be sent in the second PCIe port is stored in the third buffer, and the packet stored in the third buffer is in the second buffer.
  • the PCIe port After the PCIe port is sent, it is removed from the third buffer, and the third buffer stores at most one message at any time; records the storage duration of each packet stored in the third buffer, and records the record length.
  • the storage duration of each packet stored in the third buffer is accumulated to obtain a third cumulative duration of the third buffer storage message; when the third accumulated duration reaches the first threshold, the location is determined.
  • the second PCIe port generates a packet backpressure. In this implementation manner, the device can detect the back pressure of packets generated at multiple PCIe ports, thereby improving the efficiency of packet back pressure detection.
  • the present application provides an apparatus for detecting a back pressure of a message, the apparatus being for performing the method of any of the foregoing first aspect or any optional implementation of the first aspect.
  • the apparatus comprises means for performing the method of any of the above-described first aspect or any alternative implementation of the first aspect.
  • the present application provides an apparatus for detecting a back pressure of a message, the apparatus being used to perform the method in the foregoing first aspect or any optional implementation of the first aspect.
  • the device includes: a bus, and a PCIe port, a memory, and a processor respectively connected to the bus; wherein the PCIe port is used to send a message; and the memory is used to store a packet of the PCIe port. a transmit queue; the processor is operative to perform the method of any of the foregoing first aspect or any alternative implementation of the first aspect.
  • the present application provides a computer readable medium for storing a computer program, the computer program comprising instructions for performing the method of the first aspect or any alternative implementation of the first aspect.
  • the present application may further combine to provide more implementations.
  • Figure 1 is a schematic diagram of a PCIe system
  • FIG. 2 is a schematic diagram of a method for detecting a packet back pressure in the prior art
  • FIG. 3 is a schematic diagram of a PCIe system according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a detailed structure of the device 10 according to an embodiment of the present application.
  • FIG. 9 to FIG. 11 are schematic diagrams of a PCIe switch according to an embodiment of the present application.
  • FIG. 13 is a schematic diagram of an apparatus 800 for detecting packet backpressure according to an embodiment of the present disclosure.
  • the PCIe switch includes multiple DPs, and each DP buffer unit can buffer multiple packets (for example, 128 packets). If a timer is set for each packet in each DP, PCIe A large number of timers need to be set in the switch, which will greatly increase the system overhead. In addition, once the link between the DP and the EP fails, the timer corresponding to a large number of other packets in the buffer unit will time out after the timer corresponding to a packet in the buffer unit of the DP expires. The error processing unit 402 A large number of error reports indicating packet backpressure on the same PCIe port will be received, and even an error reporting storm will be formed.
  • the error handling unit 402 will be more difficult to resolve the packet back pressure, resulting in excessive internal bandwidth of the device, resulting in resources in the device. The waste is affected, and the error processing unit 402 affects the normal processing of the packet back pressure at the PCIe port.
  • the embodiments of the present application provide a method and apparatus for detecting packet back pressure.
  • the technical solutions of the present application are described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific features of the embodiments and the embodiments of the present application are the detailed description of the technical solutions of the present application, and are not limited to the technical solutions of the present application. In the case of no conflict, the technical features in the embodiments of the present application and the embodiments may be combined with each other.
  • FIG. 3 is a schematic diagram of a PCIe system in the embodiment of the present application.
  • the device 10 includes a PCIe port 11, and the device 20 includes a PCIe port 21, and the device 10 and the device 20 perform a packet through a link between the PCIe port 11 and the PCIe port 21. transmission.
  • the device 10 detects the back pressure of the packet generated at the PCIe port 11 as an example.
  • 4 is a detailed structural diagram of the device 10, in which the buffer unit 12 is configured to store the to-be-sent packet of the PCIe port 11, and each to-be-sent packet in the packet transmission queue of the PCIe port 11 becomes the PCIe port 11.
  • the device 10 stores the packet that needs to be sent in the buffer 13.
  • the packet stored in the buffer 13 is removed from the buffer after being sent via the PCIe port 11.
  • the buffer is arbitrary. Store at most one message at a time.
  • the packet sending queue of the PCIe port 11 is ⁇ message 1, packet 2, message 3, ... ⁇ , where the packet 1 is the packet of the queue head in the packet sending queue, that is, the packet at the PCIe port.
  • the message that needs to be sent in the message sending queue is stored in the buffer 13.
  • the buffer 13 removes the stored message 1 and stores the message 1
  • the subsequent message transmission queue ⁇ message 2, message 3, ... ⁇ currently needs to send the message 2, and so on, the buffer 13 is used to store the PCIe port at any time. a message.
  • the buffer 13 can store other messages only after the stored message is sent from the PCIe port 11.
  • Buffer 13 can be a separate register or other storage device, such as random access RAM, Flash disk, and buffer 13 can also be a storage area divided from registers or other storage devices.
  • the processor 14 is responsible for detecting the packet back pressure occurring at the PCIe port 11. Specifically, the processor 14 is configured to: record the storage duration of each packet stored in the buffer, and perform the storage duration of each packet recorded. The accumulated time length of the buffer storage message is obtained. When the accumulated duration reaches the first threshold, it is determined that the packet back pressure occurs on the PCIe port 11.
  • the processor 14 can be a processing device or a collection of multiple processing devices.
  • the processor 14 can be an Application-Specific Integrated Circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention.
  • the processor 14 is a general purpose processor, such as a central processing unit CPU, which implements the above by reading application instructions in the memory of the device 10 for storing executable instructions and executing the application instructions.
  • the device 10 determines that the packet back pressure is generated on the PCIe port 11, and only records the storage duration of the packet stored in the buffer 13 at any time, and the packet stored in the buffer 13
  • the number of words is not more than 1, which can greatly reduce the system overhead compared to the prior art scheme of timing each packet to be sent simultaneously for the PCIe port.
  • the device 10 only generates a packet backpressure error for the link failure, thereby avoiding the occurrence of an error storm and improving system stability.
  • the processor 14 is further configured to: reduce the accumulated duration of the stored message in the buffered buffer 13 under the set condition, and avoid accumulation of the storage time of the normal message that is not a backpressure message.
  • the first threshold is reached, so that the processor 14 determines the situation in which the PCIe port sends a packet back pressure, and improves the accuracy of detecting the back pressure of the packet.
  • the processor 14 reduces the accumulated duration of the stored buffer 13 in the recorded buffer under the set condition as: the processor 14 stores the buffer 13 in a preset condition. The duration is reset to 0.
  • the processor 14 resets the accumulated duration of the buffer 13 stored message to 0 under a preset condition: setting a clear timer, and timing, when the clear timer records When the time reaches the second threshold, the accumulated duration of the message stored in the buffer 13 is reset to zero.
  • an implementation manner of the processor 14 resetting the accumulated duration of the buffer 13 stored message to 0 under the preset condition is: recording the number of the packets stored in the buffer 13 and recording the When the number reaches the third threshold, the accumulated duration of the buffer 13 stored message is reset to zero.
  • an implementation manner in which the processor 14 reduces the accumulated duration of the stored buffers 13 in the recorded buffers under the set conditions is: the storage duration of each packet in the buffers 13 sequentially recorded. a queue, when the length of the queue of the duration reaches a fourth threshold, deleting the storage duration of the first record from the duration queue, and subtracting the storage duration of the first record deleted from the duration queue from the accumulation duration .
  • the duration queue is similar to a fixed length window.
  • the window moves, so that the accumulation duration is the set number of the buffer 13 recently cached (the set number of The message whose value is the fourth threshold) stores the sum of the durations in the buffer.
  • the peak value of the message storage duration will not be divided into two segments. In the statistical unit, the peak value of the packet storage duration is always detected, which improves the sensitivity of the packet back pressure detection.
  • the processor 14 is further configured to: when the storage duration of any of the recorded packets in the buffer 13 reaches a fifth threshold, the device determines that the packet back pressure occurs on the PCIe port 11, and the fifth threshold is smaller than the first threshold. Threshold. In this implementation manner, when a packet is stored in the buffer 13 for a long time but has not caused the accumulated duration to exceed the first threshold, it can be determined that the packet backpressure occurs on the PCIe port 11 as soon as possible, thereby improving the detection packet. The sensitivity of the pressure.
  • the device 10 may be a CPU, and the PCIe port 11 is a PCIe port of the CPU, such as a root port (RP) of a root complex (Root Complex, RC) of the CPU, and a device connected to the CPU.
  • 20 can be a switch or an EP.
  • the device 10 may also be a PCIe switch.
  • the PCIe port 11 is the UP or DP of the PCIe switch.
  • the PCIe port 11 is UP
  • the device 20 is the CPU or the DP of another switch.
  • the PCIe port 11 is the DP
  • the device 20 is The UP of the EP or another switch may be a CPU when the PCIe port 11 as the DP is a non-transparent (NT) port.
  • NT non-transparent
  • the device 10 may also be an EP, and the device 20 may be a CPU or a switch to which the EP is connected; or the device 10 is an EP that is a root complex (RC) of the extended PCIe structure, and the PCIe port 11 is the extended The port of the RC, the device 20 is a switch, another EP or a CPU.
  • RC root complex
  • the following takes the device 10 as a PCIe switch as an example to describe the method for detecting the back pressure of the packet provided by the embodiment of the present application.
  • FIG. 5 is a schematic diagram of a PCIe switch SW500 according to an embodiment of the present disclosure.
  • the SW 500 includes an UP 510 for connecting to a CPU and a DP 520 for connecting to an EP.
  • the SW 500 may include one or more DPs, and the DP 520 is a SW 500.
  • the DP 520 has one or more packets to be sent to the EP.
  • the packets form a message sending queue.
  • the DP 520 sends packets according to the order of the packets in the sending queue.
  • the packets to be sent are stored in the packet.
  • the buffer 522 stores the packet in the packet sending queue, that is, the packet to be sent, and the buffer 522 stores at least one packet at any time.
  • the buffer unit 521 is configured to store the packet in the sending queue. In the second and subsequent messages.
  • buffer 522 is stored After the stored message is sent to the EP via the DP 520, the previously stored message to be sent in the buffer unit 521 becomes the current message to be sent at the DP 520, and is moved from the buffer unit 521 to the buffer 522.
  • the SW500 further includes a processor 530, configured to: record the storage duration of each packet stored in the buffer 522, and accumulate the storage duration of each of the recorded packets, and obtain the cumulative duration of the buffer 522 to store the packet. When the accumulated duration reaches the first threshold, it is determined that the DP520 has a packet back pressure.
  • processor 530 is referenced to processor 14.
  • FIG. 5 is only an example of detecting a packet backpressure scheme when the device 10 is a PCIe switch, and the scope of protection of the present application cannot be limited by FIG. 5.
  • the DP520 when the DP520 is an NT port, the DP520 can be connected to another CPU.
  • the buffer 522 is configured to store a message that the DP 520 needs to send in the message sending queue to be sent by the UP 510.
  • the processor 530 determines, according to the accumulated length of the message stored in the buffer 522, the DP 520 sends the message to the UP 510. Whether to send a message back pressure in the direction.
  • the method for detecting the back pressure of the packet is also suitable for detecting whether the UP510 sends a packet backpressure to the DP520, and is suitable for detecting whether the UP510 sends a packet back to the CPU in the direction in which the packet is sent.
  • the embodiment of the present application provides a method for detecting a packet backpressure occurring on a first port in a PCIe switch, where the first port may be an uplink port and a downlink port of the PCIe switch. Any port.
  • the method for detecting a back pressure of a message includes the following steps:
  • Step 601 When each packet to be sent in the packet sending queue of the first port becomes the packet to be sent by the first port, the PCIe switch stores the packet that needs to be sent in the buffer, where The message stored in the buffer is removed from the buffer after being sent via the first port, and the buffer stores at most one message at any time.
  • the current packet to be sent by the first port refers to the first packet that should be sent out of all the packets that have not been sent by the first port.
  • the buffer stores at most one message at any one time, and stores the next message only after the stored message is sent through the first port.
  • the implementation of the buffer refers to buffer 13.
  • the first port can send packets in the upstream direction, it can also send packets in the downstream direction.
  • the buffer is used to store the message that the first port needs to send in one of the directions.
  • the uplink direction of the first port refers to the direction in which the first port sends packets to the CPU
  • the downlink direction of the first port indicates that the first port sends packets to the downlink port of the PCIe switch.
  • the uplink direction of the first port refers to the direction in which the first port sends packets to the uplink port of the PCIe switch
  • the downlink direction of the first port refers to the first port to the endpoint device EP. The direction in which the message is sent.
  • Step 602 The PCIe switch records the storage duration of each packet stored in the buffer, and accumulates the storage duration of each packet, and obtains the accumulated duration of the buffer storage packet.
  • the cumulative duration is 0; t 1 after the time t 0, the packet 1 into the buffer, and time t 2 after t 1 from the first
  • the target end for example, EP
  • the recorded message 1 is stored in the buffer for t 2 -t 1
  • the accumulated time of the buffer storage message is t 2 -t 1 .
  • the length t is t 3 t 2 time after the packet 2 enters the buffer zone, and the time t 3 after t. 4 transmitted from the first port to the destination end
  • the recorded message is stored in the buffer 2 4 - t 3
  • the accumulated duration of the buffer storage message is (t 2 -t 1 )+(t 4 -t 3 ).
  • the storage time of each packet stored in the PCIe switch recording buffer may be implemented by a processor of the PCIe switch, and the processor may be a general-purpose processor, such as a CPU, and the function of timing the packets stored in the buffer may be
  • the implementation of the application instruction by the processor can also be implemented by the processor as a hardware module of the timer.
  • the processor can also be an integrated circuit such as an ASIC, and the function of timing the message stored in the buffer can be implemented by a part of the circuit structure in the integrated circuit of the processor.
  • Step 603 When the accumulated duration of the record reaches the first threshold, the PCIe switch determines that the packet is back pressured on the first port.
  • the specific data of the first threshold may be determined by the degree of message backlog that the device can tolerate, and may be set to an empirical value, such as 60s.
  • the first threshold may be a default setting in the PCIe switch, or may be set by the user.
  • the processor of the PCIe switch includes a configuration unit, where the configuration unit is configured to receive configuration data of the user, and determine, according to the configuration data.
  • the first threshold When the accumulated duration of the record reaches the first threshold, it indicates that the packet sent on the first port is too slow.
  • the processor determines that the first port has a message back pressure.
  • the packet is back-pressured in one direction for one PCIe port, and only one packet is stored in the buffer at any time, compared to the prior art for PCIe.
  • the scheme of timing each packet to be sent on the port can greatly reduce the system overhead.
  • the PCIe switch when the PCIe port is backpressured due to a link failure, the PCIe switch generates only one packet backpressure error for the link fault, which avoids the occurrence of an error storm and improves system stability.
  • it since it is determined whether the packet back pressure occurs according to the accumulated duration of the buffer storage message, it can be avoided that the storage duration of each packet does not exceed the set threshold, but the accumulated value of the storage duration of the plurality of packets is too large.
  • the method for detecting packet back pressure further includes the following steps:
  • Step 604 The PCIe switch reduces the accumulated duration of the recorded buffer storage message under the set conditions.
  • the PCIe switch resets the accumulated duration of the buffer 13 stored message to 0 under preset conditions.
  • the PCIe switch sets the clear timer and counts it. When the time recorded by the clear timer reaches the second threshold, the accumulated duration of the buffer storage message is reset to zero.
  • the clear timer resets the accumulated duration to 0 and restarts from 0. Or, after the reset timer resets the accumulated duration to 0, the timer continues to be counted based on the second threshold of the record. When the second threshold is increased, the accumulated duration is reset to 0.
  • the above clear timer can be implemented by a processor of the PCIe switch.
  • the clear timer can be implemented by the processor executing the application instruction, or can be called by the processor as the hardware of the timer. Module implementation.
  • the processor is an integrated circuit such as an ASIC, the clear timer can be implemented by a part of the circuit structure in the integrated circuit of the processor.
  • the PCIe switch starts counting from the first packet in the buffer cache. Once the count reaches 1024, the PCIe switch stores the accumulated duration of the buffer in the buffer to be 0.
  • the number of each packet stored in the PCIe switch record buffer can be implemented by the processor of the PCIe switch.
  • the counting function can be implemented by the processor executing application instructions, or The processor calls the hardware module implementation as a counter.
  • the processor is an integrated circuit such as an ASIC, the counting function can be realized by a part of the circuit structure in the integrated circuit of the processor.
  • the PCIe switch can store the message in the buffer for a long time (ie, the second threshold), or after storing a sufficient number of packets (ie, the third threshold) in the buffer. Clearing the accumulated duration of the buffered packets to ensure that the accumulation of the normal length of the packets that are not the backpressure packets reaches the first threshold, so that the PCIe switch determines that the first port sends the packets back pressure. Improve the accuracy of detecting the back pressure of the message.
  • the PCIe switch sequentially records the storage duration of the packet in the buffer, and the recorded duration forms a duration queue according to the sequence of the records.
  • the duration of the queue leader in the duration queue is the storage duration of the first record in the queue.
  • the buffer first stores message 1, the storage duration is ⁇ t 1 ; then the message 2 is stored, the storage duration is ⁇ t 2 ; then the message 3 is stored, and the storage duration is ⁇ t 3 , then the duration queue is ( ⁇ t 1 , ⁇ t 2 , ⁇ t 3 ), wherein ⁇ t 1 of the head of the queue in the duration queue is the first recorded duration of all storage durations included in the duration queue.
  • the peak value of the packet storage duration is divided into two statistical units is as follows: assuming that the third threshold is 300, the message counter starts from the message with sequence number 1 and reports to the message with sequence number 300. The accumulated duration determined by the text timer is cleared. Since the sum of the storage durations of the packets of sequence numbers 1 to 300 does not exceed the first threshold, no packet backpressure is detected. Similarly, when the message counter detects the message with the sequence number 600, the accumulated time length determined by the message timer is cleared again. The sum of the storage durations of the packets of the sequence numbers 301 to 600 does not exceed the first threshold. Therefore, no packet back pressure is detected.
  • the fourth threshold is set to a value smaller than the third threshold.
  • the third threshold is 1024
  • the fourth threshold is 300.
  • the method for detecting a packet back pressure further includes the following steps:
  • the PCIe switch can determine whether a packet back pressure occurs according to the accumulated duration of the packet buffering time, and the packet back pressure is determined as long as the storage duration of any packet is greater than the fifth threshold.
  • the fifth threshold is smaller than the first threshold. For example, the first threshold is 60 s and the fifth threshold is 5 s.
  • the foregoing second threshold to the sixth threshold may be default settings, or may be set by a user.
  • the processor of the PCIe switch includes a configuration unit, and the configuration unit is configured to receive The configuration data of the user determines the second threshold to the sixth threshold according to the configuration data.
  • the processor 530 is configured to reduce the accumulated duration and the second accumulated duration under the set conditions.
  • the processor 530 reduces the first accumulated duration and the second accumulated duration by using the foregoing manners 1, 2, or a combination of the two.
  • the PCIe switch can detect the back pressure of the packets generated on different ports of the PCIe switch by using the same processor.
  • the buffer 522 is configured to store the packet to be sent in the packet sending queue of the DP 520 to the EP 301
  • the third buffer 552 is configured to store the DP 550 in the packet sending queue in the direction of the EP 302.
  • the third buffer unit 551 is configured to store the second and subsequent messages in the message sending queue sent by the DP 550 to the EP 302.
  • the processor 530 is configured to record the storage duration of each packet in the buffer 522, and accumulate the storage duration of the record, obtain the accumulated duration of the packet in the buffer 522, and determine when the accumulated duration reaches the first threshold.
  • the processor 530 is further configured to reduce the first accumulated duration under the set conditions and decrease the second accumulated duration under the set conditions.
  • the processor 530 reduces the first accumulated duration and the second accumulated duration by using the foregoing manners 1, 2, or a combination of the two.
  • the processor 530 For the implementation of the processor 530 to detect the packet directional direction of the packet sent by the DP 520 to the EP 301 and the packet directional direction of the DP 550 to the EP 302, refer to the implementation of steps 601 to 605, which is not repeated here.
  • the PCIe switch can separately access the PCIe through different processors.
  • the packet back pressure detected on different ports of the switch is detected.
  • the buffer 522 is configured to store a packet to be sent in the packet sending queue sent by the DP520 to the EP301
  • the third buffer 552 is configured to store a packet sending queue sent by the DP550 to the EP302.
  • the processor 530 is configured to record the storage duration of each packet in the buffer 522, and accumulate the storage duration of the record, obtain the accumulated duration of the packet stored in the buffer 522, and determine when the accumulated duration reaches the first threshold.
  • the DP520 has a message back pressure.
  • the processor 540 is configured to record the storage duration of each packet in the third buffer 552, and accumulate the storage duration of the record to obtain a fourth accumulated duration of the packet stored in the third buffer 552, where the fourth accumulation is performed. When the duration reaches the first threshold, it is determined that the DP550 has a message back pressure.
  • the processor 530 is further configured to reduce the first accumulated duration under the set conditions
  • the processor 540 is further configured to decrease the second accumulated duration under the set conditions.
  • the processor 530 and the processor 540 reduce the first accumulated duration and the second accumulated duration by using the foregoing modes 1, 2, or a combination of the two.
  • the processor 530 detects the back pressure of the packet sent by the DP 520 to the EP 301, and the processor 540 detects the back pressure of the packet sent by the DP 550 to the EP 302. Referring to the implementation manners of steps 601 to 605, Repeat.
  • the method for detecting the back pressure of the packet corresponding to the foregoing FIG. 6 to FIG. 11 is also applicable to detecting whether a packet back pressure occurs at the PCIe port of the CPU or the EP.
  • the embodiment of the present application is not repeated here.
  • FIG. 12 is a schematic diagram of an apparatus 700 for detecting a packet back pressure according to an embodiment of the present disclosure.
  • the apparatus 700 is applied to a device having a PCIe port, where the apparatus 700 includes:
  • the buffering module 701 is configured to: when each packet to be sent in the packet sending queue of the PCIe port becomes the current packet to be sent by the PCIe port, store the packet to be sent in the buffer, where the buffer The stored message is removed from the buffer after being sent via the PCIe port, and the buffer stores at most one message at any time;
  • the timing module 702 is configured to record the storage duration of each packet stored in the buffer, and accumulate the storage duration of each recorded packet to obtain a cumulative duration of the buffer storage message.
  • the determining module 703 is configured to determine that a packet back pressure occurs on the PCIe port when the accumulated duration reaches the first threshold.
  • the apparatus 700 further includes:
  • the timing clearing module 704 is configured to reset the accumulated duration determined by the timing module to 0 under a preset condition.
  • timing clearing module 704 is specifically configured to:
  • the number of messages stored in the buffer is recorded, and the accumulated duration determined by the timing module is reset to 0 when the number reaches the third threshold.
  • the timing control module 705 is configured to delete the storage time of the first record from the duration queue when the length of the long queue reaches the fourth threshold, and subtract the first record deleted from the duration queue from the accumulated duration determined by the timing module. The storage time.
  • each module included in the foregoing apparatus 700 reference may be made to the implementation of the steps in the foregoing steps 601 to 605. It should be noted that the apparatus 700 is not limited to the application in the PCIe switch, and may be applied to the CPU or the EP.
  • FIG. 13 is a schematic diagram of a device 800 for detecting packet backpressure according to an embodiment of the present disclosure.
  • the device 800 includes: a bus 801, and a PCIe port 802, a memory 803, and a processor 804 respectively connected to the bus 801;
  • the PCIe port 802 is configured to send a packet.
  • the memory 803 is configured to store a message sending queue of the PCIe port.
  • the processor 804 is configured to: when each packet to be sent in the packet sending queue of the PCIe port 802 is a packet that needs to be sent by the PCIe port 802, the packet to be sent is stored in the buffer, where The packet stored in the buffer is removed from the buffer after being sent via the PCIe port 802.
  • the buffer stores at most one message at any time; the storage duration of each message stored in the recording buffer, and each report of the record
  • the storage duration of the text is accumulated to obtain the accumulated duration of the buffer storage message; when the accumulated duration reaches the first threshold, it is determined that the packet back pressure occurs on the PCIe port 802.
  • the memory 803 is further configured to store an instruction
  • the processor 804 is configured to execute instructions stored by the memory 803 to implement the functions of the processor 804.
  • the processor 804 is further configured to reset the accumulated duration to 0 under a preset condition.
  • the processor 804 is configured to reset the accumulated duration to 0 under a preset condition, including:
  • the processor 804 is configured to reset the accumulated duration to 0 under a preset condition, including:
  • the number of messages stored in the buffer is recorded, and the accumulated duration is reset to 0 when the number reaches the third threshold.
  • the storage duration of each packet sequentially recorded by the processor 804 forms a queue of durations, and the processor 804 is further configured to:
  • the storage time of the first record is deleted from the duration queue, and the storage duration of the first record deleted from the duration queue is subtracted from the accumulated duration.
  • the processor 804 is further configured to:
  • the fifth threshold When the storage duration of any of the recorded packets in the buffer reaches the fifth threshold, it is determined that the packet is back pressured on the PCIe port, and the fifth threshold is smaller than the first threshold.
  • the device further includes a second PCIe port 805;
  • the processor 804 is further configured to: each pending in the message sending queue of the second PCIe port 805
  • the packet to be sent in the second PCIe port 805 is stored in the third buffer, and the packet stored in the third buffer is in the first buffer.
  • the PCIe port 805 After the PCIe port 805 is sent, it is removed from the third buffer, and the third buffer stores at most one packet at any time; records the storage duration of each packet stored in the third buffer, and records the third buffer of the packet.
  • the storage duration of each stored message is accumulated to obtain a third accumulated duration of the third buffer storage message. When the third accumulated duration reaches the first threshold, it is determined that the second PCIe port 805 generates a packet backpressure.
  • the device 800 For the implementation of the components of the device 800, refer to the implementation of the steps in the foregoing steps 601 to 605. It should be noted that the device 800 is not limited to a PCIe switch, and may also be a CPU or an EP.
  • the embodiment of the present application provides a server, where the server includes a device 10 capable of implementing the foregoing method for detecting a packet back pressure.
  • the embodiment of the present application provides a storage controller, where the storage controller includes a device 10 capable of implementing the foregoing method for detecting a packet back pressure.
  • the embodiment of the present application further provides a computer readable medium for storing a computer program, where the computer program includes a method for performing a detection packet back pressure corresponding to any one of FIG. 6 to FIG. 11 and any optional method of the method.
  • the instructions for the steps in the implementation are not limited to any one of FIG. 6 to FIG. 11 and any optional method of the method.
  • embodiments of the present application can be provided as a method, system, or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.

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Abstract

一种检测报文反压的方法及装置，用于解决现有技术中检测报文反压方案开销过大的问题。该方法应用于具有高速外围部件互连PCIe端口的设备，该方法包括：在该PCIe端口的报文发送队列中的每个待发送报文成为该PCIe端口的当前需要发送的报文时，该设备将该需要发送的报文存储在缓冲区中，其中，该缓冲区存储的报文在经由该PCIe端口发送后从该缓冲区移除，该缓冲区在任意时刻至多存储一个报文；该设备记录该缓冲区存储的每个报文的存储时长，并对记录的该每个报文的存储时长进行累加，得到该缓冲区存储报文的累计时长；当该累计时长达到第一阈值时，该设备确定该PCIe端口发生报文反压。

Description

一种检测报文反压的方法及装置 技术领域
本发明涉及计算机技术领域，特别涉及一种检测报文反压的方法及装置。
背景技术
高速外围部件互连(Peripheral Component Interconnect express，PCIe)系统中，具有PCIe端口的设备之间可以通过PCIe端口进行报文传输。例如，中央处理器(Central Processing Unit，CPU)通过PCIe端口连接PCIe交换机的上行端口(Upstream Port，UP)，PCIe交换机的下行端口(Downstream Port，DP)连接端点设备(Endpoint，EP)。CPU向EP发送报文时，CPU先将报文发送至PCIe交换机的UP，然后，PCIe交换机的UP将报文发送至与该EP连接的DP，然后该DP将报文发送至EP。
在两个PCIe端口之间的链路出现异常时，PCIe端口处的待发送报文出现积压，即发生报文反压，如果不能及时检测到报文反压，将导致发送该报文的设备发生指令超时，并最终导致该装置挂起(hang)，无法正常工作。
现有的一种报文反压检测方法为：PCIe端口处的所有待发送报文均存储在缓存单元中，针对缓存单元中存储的每个报文分别设置计时器，记录该报文在缓存单元中的存储时长，当针对任一报文设置的计时器超时时，确定该PCIe端口发送报文反压，并向错误处理单元发送该PCIe端口出现报文反压的错误报文。
但是，一个设备可能会包括多个PCIe端口，且每个PCIe端口处的缓存单元中通常存储有大量的待发送报文，现有技术中的报文反压检测方法会导致申请大量计时器资源，并且错误处理单元会收到大量的错误处理报告，导致设备内部带宽被过多占用，造成设备内的资源浪费。
发明内容
本申请提供一种检测报文反压的方法及装置，用于解决现有技术中检测报文反压方案开销过大的问题。
第一方面，本申请提供一种检测报文反压的方法，该方法应用于具有PCIe端口的设备中。该设备可以为具有PCIe端口设备的CPU、PCIe交换机或端点设备(End Point，EP)，在该设备为CPU时，该PCIe端口为CPU的PCIe端口，如运行根复合体(Root Complex，RC)的CPU的根端口(Root Port，RP)；在设备为PCIe交换机时，该PCIe端口为PCIe交换机的上行端口以及下行端口中的任一端口；在设备为EP时，该PCIe端口为该EP与PCIe系统中其他设备连接的PCIe端口。在PCIe端口的报文发送队列中的每个待发送报文成为PCIe端口的当前需要发送的报文时，设备将该当前需要发送的报文存储在缓冲区中，缓冲区存储的报文在经由PCIe端口发送后从该缓冲区移除，缓冲区在任意时刻至多存储一个报文。该缓冲区可以为一独立的存储器件，如随机存储器(Random-Access Memory，RAM)、闪存(Flash disk)，也可以为从存储器件中划分出的一个存储区域。设备记录缓冲区存储的每个报文的存储时长，并对记录的每个报文的存储时长进行累加，得到缓冲区存储报文的累计时长；当该累计时长达到第一阈值时，确定该PCIe端口发生报文反压。上述记录缓冲区存储的每个报文的存储时长的功能可以由设备中的具有计时功能的硬件模块实现，也可以由设备的CPU执行应用程序实现。
上述设备确定PCIe端口发生报文反压的方案中，针对一个PCIe端口在一个方向上的报文反压，在任一时刻只对一个报文在缓冲区中存储时长进行计时，相比于现有技术中同时针对PCIe端口的每一个待发送报文进行计时的方案，能够大幅降低系统开销。而且，在PCIe端口因链路故障发生报文反压时，设备针对该链路故障只产生一次报文反压错误，避免了错误风暴的发生，提高系统稳定性。再者，由于根据缓冲区存储报文的累计时长确定是否发生报文反压，能够避免每个报文的存储时长均未超出设定阈值，但多个报文的存储时长的累加值过大导致发送报文的设备无法正常工作。
在一种可选的实现方式中，设备在设定的条件下将记录的缓冲区存储报 文的累计时长减小，减小的方式包括对累计时长进行清零，或者，从累计时长中减去已发送的一报文的存储时长。本实现方式能够避免因过多并非反压报文的正常报文的存储时长的累积达到第一阈值使设备确定PCIe端口发送报文反压的情形，提高检测报文反压的准确度。
在一种可选的实现方式中，设备在预设条件下将缓冲区存储报文的累计时长重置为0。本实现方式能够避免因过多并非反压报文的正常报文的存储时长的累积达到第一阈值使设备确定PCIe端口发送报文反压的情形，提高检测报文反压的准确度。
在一种可选的实现方式中，设备机设置清零计时器，并进行计时，当该清零计时器记录的时间达到第二阈值时，将缓冲区存储报文的累计时长重置为0。该清零计时器可以由设备的处理器执行应用程序指令实现，也可以设备中作为计时器的硬件模块实现。本实现方式能够避免因过多并非反压报文的正常报文的存储时长的累积达到第一阈值使设备确定PCIe端口发送报文反压的情形，提高检测报文反压的准确度。
在一种可选的实现方式中，设备记录通过缓冲区存储过的报文的数量，并当记录的数量达到第三阈值时将缓冲区存储报文的累计时长重置为0。该计数功能可以由设备的处理器执行应用程序指令实现，也可以由设备中作为计数器的硬件模块实现。本实现方式能够避免因过多并非反压报文的正常报文的存储时长的累积达到第一阈值使设备确定PCIe端口发送报文反压的情形，提高检测报文反压的准确度。
在一种可选的实现方式中，设备依次记录的缓冲区中每个报文的存储时长形成时长队列，当该时长队列的长度达到第四阈值时，从所述时长队列中删除最先记录的存储时长，并从累加时长中减去从该时长队列中被删除的该最先记录的存储时长。本实现方式中，该累加时长为缓冲区最近缓存的设定数量(该设定数量的值为第四阈值)的报文在缓冲区中存储时长的和，报文存储时长的峰值不会被划分到分割在两个统计单位内，保证报文存储时长的峰值始终被检测到，提高报文反压检测的灵敏度。
在一种可选的实现方式中，设备依次记录的缓冲区中每个报文的存储时长形成时长队列，设备对该时长队列中所有时长进行累加，获得窗口时长；当该时长队列的长度达到第四阈值时，从所述时长队列中删除最先记录的存储时长，并从窗口时长中减去从该时长队列中被删除的该最先记录的存储时长。设备换机在该窗口时长达到第六阈值时，确定PCIe端口发生报文反压。由于该窗口时长不会被重置为0，保证报文存储时长的峰值始终被检测到，提高报文反压检测的灵敏度。
在一种可选的实现方式中，设备在记录的任一报文在该缓冲区中的存储时长达到第五阈值后确定PCIe端口发生报文反压，该第五阈值小于该第一阈值。本实现方式中，只要有任一报文的存储时长大于第五阈值，设备即确定发生报文反压，进而在有报文在缓冲区缓存了过长时间但尚未导致该累计时长超过第一阈值时，尽快地确定发生了报文反压，提高设备器检测报文反压的灵敏度。
在一种可选的实现方式中，在所述PCIe端口的第一方向上的报文发送队列中的每个待发送报文成为所述PCIe端口的当前需要发送的报文时，所述设备将所述第一方向上的所述需要发送的报文存储在缓冲区中；所述第一方向为所述PCIe端口的上行方向或下行方向。在所述PCIe端口的第二方向上的报文发送队列中的每个待发送报文成为所述PCIe端口的当前需要发送的报文时，所述设备将所述第二方向上的所述需要发送的报文存储在第二缓冲区中，所述第二方向与所述第一方向相反，所述第二缓冲区存储的报文在经由所述PCIe端口发送后从所述第二缓冲区移除，所述第二缓冲区在任意时刻至多存储一个报文；所述设备记录所述第二缓冲区存储的每个报文的存储时长，并对记录的所述第二缓冲区存储的每个报文的存储时长进行累加，得到所述第二缓冲区存储报文的第二累计时长；当所述第二累计时长达到所述第一阈值时，所述设备确定所述PCIe端口发生报文反压。本实现方式中，设备能够对PCIe交换机同一端口的上下行两个方向上待发送报文所发生的报文反压进行检测，提高报文反压检测的灵敏度和针对性。
在一种可选的实现方式中，设备还包括第二PCIe端口；设备还用于：在所述第二PCIe端口的报文发送队列中的每个待发送报文成为所述第二PCIe端口的当前需要发送的报文时，将所述第二PCIe端口中所述需要发送的报文存储在第三缓冲区中，其中，所述第三缓冲区存储的报文在经由所述第二PCIe端口发送后从所述第三缓冲区移除，所述第三缓冲区在任意时刻至多存储一个报文；记录所述第三缓冲区存储的每个报文的存储时长，并对记录的所述第三缓冲区存储的每个报文的存储时长进行累加，得到所述第三缓冲区存储报文的第三累计时长；当所述第三累计时长达到所述第一阈值时确定所述第二PCIe端口发生报文反压。本实现方式中，设备能够对多个PCIe端口处发生的报文反压进行检测，提高报文反压检测的效率。
第二方面，本申请提供一种检测报文反压的装置，该装置用于执行上述第一方面或第一方面的任意可选的实现方式中的方法。具体的，该设备包括用于执行上述第一方面或第一方面的任意可选的实现方式中的方法的模块。
第三方面，本申请提供一种检测报文反压的设备，该设备用于执行上述第一方面或第一方面的任意可选的实现方式中的方法。具体的，该设备包括：总线，以及分别与所述总线相连的PCIe端口、存储器、处理器；其中，所述PCIe端口用于发送报文；所述存储器用于存储所述PCIe端口的报文发送队列；所述处理器用于执行上述第一方面或第一方面的任意可选的实现方式中的方法。
第四方面，本申请提供了一种计算机可读介质，用于存储计算机程序，该计算机程序包括用于执行第一方面或第一方面的任意可选的实现方式中的方法的指令。
本申请在上述各方面提供的实现方式的基础上，还可以进行进一步组合以提供更多实现方式。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中 所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为PCIe系统的示意图；
图2为现有技术中检测报文反压方法的示意图；
图3为本申请实施例提供的一种PCIe系统的示意图；
图4为本申请实施例提供的设备10的详细结构的示意图；
图5为本申请实施例提供的PCIe交换机的结构示意图；
图6为本申请实施例提供的检测报文反压方法的流程示意图；
图7为本申请实施例提供的检测报文反压方法的进一步细化流程示意图；
图8为报文的存储时长与报文序号的关系图；
图9至图11分别为本申请实施例提供的PCIe交换机的示意图；
图12为本申请实施例提供的检测报文反压的装置700的示意图；
图13为本申请实施例提供的检测报文反压的设备800的示意图。
具体实施方式
为了便于理解本申请实施例提供的方案，下面首先介绍PCIe系统以及现有技术中检测报文反压的方法。
图1为PCIe系统的一种可能实现方式的示意图，其中，RP110为CPU100的PCIe端口，SW200为PCIe交换机(Switch，SW)，UP210为SW200的上行端口，DP221～223为SW200的下行端口，EP301～303为端点设备。其中，CPU100可以是多个CPU的集合。
UP210用于从CPU100的RP110接收CPU100发送至EP的报文，并将该报文发送至与EP连接的DP，例如，UP210在接收CPU100发送至EP301的报文后，将报文发送至与EP301相连接的DP221，经由DP221将报文发送至EP301。
在DP与EP之间的链路发生异常时，CPU发送至EP的报文在DP处积 压，发生报文反压，如果不及时发现报文反压，将导致CPU中报文处理缓慢或停滞，甚至导致CPU中出现严重的指令超时，并最终导致CPU挂起，无法正常工作。
图2所示为现有技术中的一种检测报文的方法，在该方法中，PCIe交换机的DP处待发送的报文均存储在缓存单元中，针对缓存单元中存储的每个报文分别设置一个计时器401，用于记录该报文在缓存单元中的存储时长，在该报文从PCIe端口发送后，该计时器对该报文的存储时长的计时终止。如果计时器401超时，表明该报文在缓存单元中的存储时长过长，换言之，该报文未能在超时时长内从该PCIe端口发送出去，表明该PCIe端口发生报文反压，计时器401将向错误处理单元402上报该PCIe端口发生反压的错误报告。
但是，PCIe交换机包括多个DP，而每个DP的缓存单元中能够缓存多条报文(例如，128条报文)，如果为每个DP中的每个报文设置一计时器，则PCIe交换机中需设置大量的计时器，这将会极大地增加系统开销。不仅如此，一旦DP与EP间链路发生故障，在DP的缓存单元中的一个报文对应的的计时器超时后，缓存单元中大量其他报文对应的计时器将陆续超时，错误处理单元402将接收大量表明同一PCIe端口发生报文反压的错误报告，甚至形成错误报告风暴，增大错误处理单元402解决报文反压的难度，导致设备内部带宽被过多占用，造成设备内的资源浪费，影响错误处理单元402对PCIe端口处报文反压的正常处理。
为了解决现有技术中存在的上述问题，本申请实施例提供一种检测报文反压的方法及装置。下面通过附图以及具体实施例对本申请技术方案做详细的说明，应当理解本申请实施例以及实施例中的具体特征是对本申请技术方案的详细的说明，而不是对本申请技术方案的限定，在不冲突的情况下，本申请实施例以及实施例中的技术特征可以相互组合。
图3所示为本申请实施例中PCIe系统的示意图，设备10包括PCIe端口11，设备20包括PCIe端口21，设备10与设备20通过PCIe端口11与PCIe端口21之间的链路进行报文传输。
下面以设备10检测PCIe端口11处发生的报文反压为例进行说明。图4为设备10的详细结构示意图，其中，缓存单元12用于存储PCIe端口11的待发送报文，而在PCIe端口11的报文发送队列中的每个待发送报文成为PCIe端口11的当前需要发送的报文时，设备10将该当前需要发送的报文存储在缓冲区13中，缓冲区13存储的报文在经由PCIe端口11发送后从该缓冲区移除，缓冲区在任意时刻至多存储一个报文。例如，PCIe端口11的报文发送队列为{报文1，报文2，报文3，…}，其中，报文1为报文发送队列中队首的报文，即在该PCIe端口的报文发送队列中当前需要发送的报文，将报文1存储在缓冲区13中，在报文1通过PCIe端口11发送后，缓冲区13移除存储的报文1，并存储报文1发送后的报文发送队列{报文2，报文3，…}中当前需要发送的报文2，依此类推，缓冲区13在任意时刻用于存储PCIe端口的报文发送队列中当前需要发送的一个报文。缓冲区13只有在存储的报文从PCIe端口11发送后，才能存储其他报文。缓冲区13可以为一独立的寄存器或其他存储设备，如随机存储器RAM、Flash disk，缓冲区13也可以为从寄存器或其他存储设备中划分出的一个存储区域。
处理器14负责检测PCIe端口11处发生的报文反压，具体的，处理器14用于：记录缓冲区存储的每个报文的存储时长，并对记录的每个报文的存储时长进行累加，得到缓冲区存储报文的累计时长；当该累计时长达到第一阈值时，确定PCIe端口11发生报文反压。
该处理器14可以为一个处理器件，也可以为多个处理器件的集合。该处理器14可以为特定应用集成电路(Application-Specific Integrated Circuit，ASIC)，或一个或多个用于控制本发明方案程序执行的集成电路。或者，处理器14为一通用处理器，如中央处理器CPU，该CPU通过读取设备10的用于存储可执行指令的存储器中的应用程序指令，并执行该应用程序指令，来实现上述由处理器14所实现的功能。
上述设备10确定PCIe端口11发生报文反压的方案中，由于在任意时刻只对缓冲区13中存储的报文的存储时长进行计时，且缓冲区13中存储的报 文数不大于1，相比于现有技术中同时针对PCIe端口的每一个待发送报文进行计时的方案，能够大幅降低系统开销。而且，在PCIe端口因链路故障发生报文反压时，设备10针对该链路故障只产生一次报文反压错误，避免了错误风暴的发生，提高系统稳定性。再者，由于根据缓冲区存储报文的累计时长确定是否发生报文反压，能够避免每个报文的存储时长均未超出设定阈值，但多个报文的存储时长的累加值过大导致设备无法正常工作。
可选的，处理器14还用于：在设定的条件下将记录的缓冲区13存储报文的累计时长减小，避免因过多并非反压报文的正常报文的存储时长的累积达到第一阈值使处理器14确定PCIe端口发送报文反压的情形，提高检测报文反压的准确度。
可选的，处理器14在设定的条件下将记录的缓冲区13存储报文的累计时长减小的一种实现为：处理器14在预设条件下将缓冲区13存储报文的累计时长重置为0。
可选的，处理器14在预设条件下将缓冲区13存储报文的累计时长重置为0的一种实现方式为：设置清零计时器，并进行计时，当该清零计时器记录的时间达到第二阈值时，将缓冲区13存储报文的累计时长重置为0。
可选的，处理器14在预设条件下将缓冲区13存储报文的累计时长重置为0的一种实现方式为：记录通过缓冲区13存储过的报文的数量，并当记录的数量达到第三阈值时将缓冲区13存储报文的累计时长重置为0。
可选的，处理器14在设定的条件下将记录的缓冲区13存储报文的累计时长减小的一种实现方式为：依次记录的缓冲区13中每个报文的存储时长形成时长队列，当该时长队列的长度达到第四阈值时，从所述时长队列中删除最先记录的存储时长，并从累加时长中减去从该时长队列中被删除的该最先记录的存储时长。在本实现方式中，上述时长队列类似一个固定长度的窗口，在缓冲区13存储新的报文时，该窗口移动，使得累加时长为缓冲区13最近缓存的设定数量(该设定数量的值为第四阈值)的报文在缓冲区中存储时长的和。通过该固定长度的窗口，报文存储时长的峰值不会被划分到分割在两 个统计单位内，保证报文存储时长的峰值始终被检测到，提高报文反压检测的灵敏度。
可选的，处理器14还用于：当记录的任一报文在缓冲区13中的存储时长达到第五阈值时，设备确定PCIe端口11发生报文反压，该第五阈值小于第一阈值。在本实现方式中，在有报文在缓冲区13存储了过长时间但尚未导致该累计时长超过第一阈值时，能够尽快地确定PCIe端口11发生了报文反压，提高检测报文反压的灵敏度。
本申请实施例中，设备10可以为CPU，PCIe端口11为该CPU的PCIe端口，如CPU的根复合体(Root Complex，RC)的根端口(Root Port，RP)，与该CPU连接的设备20可以为交换机或EP。设备10也可以是PCIe交换机，PCIe端口11为该PCIe交换机的UP或DP，在PCIe端口11为UP时，设备20为CPU或另一交换机的DP；在PCIe端口11为DP时，设备20为EP或另一交换机的UP，在作为DP的PCIe端口11为非透明(non-transparant，NT)端口时，该设备20也可以为一CPU。设备10也可以为EP，设备20可以为该EP所连接的CPU或交换机；或者，设备10为一作为扩展PCIe结构的根复合体(Root Complex，RC)的EP，PCIe端口11为该扩展的RC的端口，设备20为交换机、另一EP或CPU。
下面以设备10为PCIe交换机为例，对本申请实施例提供的检测报文反压的方法予以说明。
图5为本申请实施例提供的一种PCIe交换机SW500的示意图，SW500包括用于连接CPU的UP510以及用于连接EP的DP520，SW500可以包括1个或1个以上的DP，DP520为SW500的任一DP。DP520处存在待发往EP的一个或多个报文，这些报文形成一报文发送队列，DP520根据该报文发送队列中报文的排序依次发送报文，这些待发送的报文存储在缓存单元521以及缓冲区522之中。其中，缓冲区522存储该报文发送队列中队首的报文，即当前需发送的报文，缓冲区522在任意时刻至多存储一个报文；缓存单元521用于存储该报文发送队列中排在第二以及之后的报文。当缓冲区522中存 储的报文经由DP520发送至EP后，缓存单元521中原存储的需先发送的报文成为DP520处的当前需发送的报文，将其从缓存单元521中移至缓冲区522。
SW500还包括处理器530，用于：记录缓冲区522存储的每个报文的存储时长，并对记录的所述每个报文的存储时长进行累加，得到缓冲区522存储报文的累计时长；当所述累计时长达到第一阈值时，确定DP520发生报文反压。处理器530的实现方式参照处理器14。
本领域技术人员可以知道，图5所示仅为设备10为PCIe交换机时检测报文反压方案的一个举例，不能以图5限定本申请的保护范围。例如，在DP520为NT端口时，DP520可以连接另一CPU。又例如，缓冲区522用于存储DP520向UP510待发送的报文发送队列中当前需发送的一个报文，处理器530根据缓冲区522存储报文的累计时长确定DP520在向UP510发送报文的方向上是否发送报文反压。同理，该检测报文反压的方法同样适应于检测UP510向DP520发送报文的方向是否发送报文反压，以及适用于检测UP510向CPU发送报文的方向是否发送报文反压。
结合图5提供的PCIe交换机，本申请实施例提供一种对PCIe交换机中的第一端口上发生的报文反压进行检测的方法，该第一端口可以为PCIe交换机的上行端口以及下行端口中的任一端口。参照图6，该检测报文反压的方法包括如下步骤：
步骤601：在第一端口的报文发送队列中的每个待发送报文成为第一端口的当前需要发送的报文时，PCIe交换机将该当前需要发送的报文存储在缓冲区中，其中，该缓冲区存储的报文在经由第一端口发送后从该缓冲区移除，该缓冲区在任意时刻至多存储一个报文。
具体的，第一端口的当前需要发送的报文，指的是第一端口尚未发送的所有报文中，应当第一个发送出去的报文。缓冲区在任一时刻至多存储一个报文，且只有在存储的报文经由第一端口发送后才存储下一个报文。缓冲区的实现方式参照缓冲区13。
由于第一端口可以向上行方向发送报文，也可以向下行方向发送报文， 缓冲区用于存储第一端口在其中一个方向上当前需要发送的报文。其中，在第一端口为上行端口时，第一端口的上行方向指该第一端口向CPU发送报文的方向，第一端口的下行方向指该第一端口向PCIe交换机的下行端口发送报文的方向；在第一端口为下行端口时，第一端口的上行方向指该第一端口向PCIe交换机的上行端口发送报文的方向，第一端口的下行方向指该第一端口向端点设备EP发送报文的方向。
步骤602：PCIe交换机记录缓冲区存储的每个报文的存储时长，并对记录的每个报文的存储时长进行累加，得到缓冲区存储报文的累计时长。
例如，假设t0时刻之前缓冲区没有存储过报文，则该累计时长为0；在t0之后的t1时刻，报文1进入缓冲区，并在t1之后的t2时刻从第一端口发送至目标端(例如EP)，则记录的报文1在缓冲区中的存储时长为t2-t1，缓冲区存储报文的累计时长为t2-t1。在t2之后的t3时刻，报文2进入缓冲区，并在在t3之后的t4时刻从第一端口发送至目标端，则记录的报文2在缓冲区中的存储时长为t4-t3，缓冲区存储报文的累计时长为(t2-t1)+(t4-t3)。
PCIe交换机记录缓冲区存储的每个报文的存储时长，可以由PCIe交换机的处理器实现，该处理器可以为一通用处理器，如CPU，该对缓冲区存储的报文进行计时的功能可以通过处理器执行应用程序指令实现，也可以通过处理器调用作为计时器的硬件模块实现。该处理器还可以为ASIC等集成电路，该对缓冲区存储的报文进行计时的功能可以由处理器的集成电路中的部分电路结构实现。
步骤603：当记录的该累计时长达到第一阈值时，PCIe交换机确定第一端口发生报文反压。
具体的，该第一阈值的具体数据可以由设备能够容忍的报文积压程度所确定，可以设置为一经验值，如60s。该第一阈值可以为PCIe交换机中的默认设定，也可以由用户进行设定，例如，PCIe交换机的处理器包括一配置单元，该配置单元用于接收用户的配置数据，根据该配置数据确定该第一阈值。当记录的该累计时长达到第一阈值时，表明第一端口上发送报文的速度过慢， 处理器确定第一端口发生报文反压。
上述检测报文反压方法中，针对一个PCIe端口在一个方向上的报文反压，在任一时刻只对一个报文在缓冲区中存储时长进行计时，相比于现有技术中同时针对PCIe端口的每一个待发送报文进行计时的方案，能够大幅降低系统开销。而且，在PCIe端口因链路故障发生报文反压时，PCIe交换机针对该链路故障只产生一次报文反压错误，避免了错误风暴的发生，提高系统稳定性。再者，由于根据缓冲区存储报文的累计时长确定是否发生报文反压，能够避免每个报文的存储时长均未超出设定阈值，但多个报文的存储时长的累加值过大导致发送报文的CPU无法正常工作，例如，PCIe交换机包括10个DP，采用图2所示的检测报文反压方法时，虽然每个DP处的每个报文对应的计时器均未超时，但均临近超时时长，由于CPU受到10个DP处报文累计的影响，由于10个DP处的报文在缓存单元中的存储时长均接近超时时长，很有可能导致CPU发生指令超时。
可选的，参照图7，本申请实施例中，检测报文反压的方法还包括如下步骤：
步骤604：PCIe交换机在设定的条件下将记录的缓冲区存储报文的累计时长减小。
步骤604可以包括多种实现方式，包括但不限于：
方式1，PCIe交换机在预设条件下将缓冲区13存储报文的累计时长重置为0。
该方式1同样可以具有多种实现方式，包括：
清零方式1，PCIe交换机设置清零计时器，并进行计时，当该清零计时器记录的时间达到第二阈值时，将缓冲区存储报文的累计时长重置为0。
例如，设置第二阈值为600s，清零计时器从0s开始计时，一旦计时达到600s，处理器将确定的该累计时长重置为0。
该清零计时器在将累计时长重置为0后，从0开始重新计时。或者，清零计时器在将累计时长重置为0后，基于记录的第二阈值继续计时，每当计 时增加第二阈值时将累计时长重置为0。
上述清零计时器可以由PCIe交换机的处理器实现，该处理器为一通用处理器时，该清零计时器可以通过处理器执行应用程序指令实现，也可以通过处理器调用作为计时器的硬件模块实现。该处理器为ASIC等集成电路时，该清零计时器可以由处理器的集成电路中的部分电路结构实现。
清零方式2，PCIe交换机记录通过缓冲区存储过的报文的数量，并当记录的数量达到第三阈值时将缓冲区存储报文的累计时长重置为0。
例如，设置第三阈值为1024，PCIe交换机从缓冲区缓存第一个报文开始计数，一旦该计数达到1024，PCIe交换机将缓冲区存储报文的该累计时长为0。
在将累计时长重置为0后，PCIe交换机对将累计时长重置为0后通过缓冲区存储过的报文从0开始重新计数。或者，PCIe交换机基于记录的第三阈值，对通过缓冲区存储过的报文的数量继续计数，每当计数增加第三阈值时将累计时长重置为0。
PCIe交换机记录缓冲区存储的每个报文的数量，可以由PCIe交换机的处理器实现，在该处理器为一通用处理器时，该计数功能可以通过处理器执行应用程序指令实现，也可以通过处理器调用作为计数器的硬件模块实现。该处理器为ASIC等集成电路时，该计数的功能可以由处理器的集成电路中的部分电路结构实现。
上述清零方式1以及清零方式2可以只选择其中一个实施，也可以二者同时实施。在二者同时实施时，一旦清零计时器的计时达到第二阈值或对通过缓冲区存储的报文的计数达到第三阈值，PCIe交换机均将报文计时器确定的该累计时长重置为0。在一种可选的实现方式中，在清零计时器的计时达到第二阈值时，PCIe交换机还要将清零计时器的计时以及对通过缓冲区存储的报文的计数均重置为0；以及，在对通过缓冲区存储的报文的计数达到第三阈值时，PCIe交换机还要将清零计时器的计时以及对通过缓冲区存储的报文的计数均重置为0。在另一种可选的实现方式中，在清零计时器的计时达到第二 阈值时，PCIe交换机将清零计时器的计时重置为0，而不将通过缓冲区存储的报文的计数重置为0；以及，在通过缓冲区存储的报文的计数达到第三阈值时，PCIe交换机将通过缓冲区存储的报文的计数重置为0，而不将清零计时器的计时重置为0。
由于缓冲区中缓存的任一报文的存储时长均大于0，在缓冲区缓存了足够多数量的报文后，或者，在缓冲区进行了足够长时间的报文缓存后，缓冲区存储报文的累计时长肯定能够达到该第一阈值。由本申请未实施例可知，缓冲区进行了过长时间的报文缓存才使得缓冲区存储报文的累计时长达到第一阈值的情形并不是发生了报文反压，同理，缓冲区缓冲区缓存了过多数量的报文才使得缓冲区存储报文的累计时长达到第一阈值的情形也不是发生了报文反压。
上述方式1中，PCIe交换机能够在缓冲区进行了足够长时间(即：第二阈值)的报文存储后，或者，在缓冲区存储过足够多数量(即：第三阈值)的报文后，将缓冲区存储报文的累计时长清零，能够避免因过多并非反压报文的正常报文的存储时长的累积达到第一阈值使PCIe交换机确定第一端口发送报文反压的情形，提高检测报文反压的准确度。
方式2，PCIe交换机依次记录的缓冲区中每个报文的存储时长形成时长队列，当该时长队列的长度达到第四阈值时，从所述时长队列中删除最先记录的存储时长，并从累加时长中减去从该时长队列中被删除的该最先记录的存储时长。
具体的，PCIe交换机依次记录报文在缓冲区中的存储时长，所记录的时长依据记录的先后顺序形成时长队列，其中时长队列中队首的时长为该时长队列中最先记录的存储时长。例如，缓冲区首先存储报文1，存储时长为Δt1；然后存储报文2，存储时长为Δt2；然后存储报文3，存储时长为Δt3，则该时长队列为(Δt1，Δt2，Δt3)，其中，该时长队列中队首的Δt1为时长队列包括的所有存储时长中最先记录的时长。假设第四阈值为4，缓冲区在将报文3发送出去之后存储报文4时，报文计时器会记录报文4的存储时长Δt4，此时， 时长队列的长度达到4，报文计时器将从该时长队列中删除最先记录的存储时长Δt1，形成新的时长队列(Δt2，Δt3，Δt4)，对应的，报文计时器记录的缓冲区存储报文的累计时长由(Δt1+Δt2+Δt3)变更为(Δt2+Δt3+Δt4)。
参照图8所示的报文存储时长与报文序号的关系图，上述时长队列类似一个固定长度的窗口，在缓冲区缓存新的报文时，该窗口移动，使得累加时长为缓冲区最近缓存的设定数量(该设定数量的值为第四阈值)的报文在缓冲区中存储时长的和。通过该固定长度的窗口，报文存储时长的峰值不会被划分到分割在两个统计单位内，保证报文存储时长的峰值始终被检测到，提高报文反压检测的灵敏度。
报文存储时长的峰值被划分到分割在两个统计单位内的示例为：假设第三阈值为300，报文计数器从序号为1的报文开始计时，到序号为300的报文时对报文计时器确定的累计时长进行清零，由于序号1至300的报文的存储时长之和并未超过第一阈值，因此并未检测到报文反压。同理，报文计数器在检测到序号为600的报文时再次对报文计时器确定的累计时长进行清零，由于序号301至600的报文的存储时长之和并未超过第一阈值，因此并未检测到报文反压。但是，由于报文存储时长的峰值出现在序号300的报文附近，实际上序号151至序号450的报文存储时长之和已经大于第一阈值，已经发生了报文反压，但由于将报文存储时长的峰值分割在两个统计单位内，导致未能检测到报文反压。
上述方式1与方式2可以只实施其中一个，也可以同时实施，在二者同时实时时，第四阈值设置为小于第三阈值的数值，例如，第三阈值为1024，第四阈值为300。
可替换的，在方式2中，PCIe交换机对该时长队列中所有时长进行累加，获得窗口时长，在该时长队列的长度达到第四阈值时，从所述时长队列中删除最先记录的存储时长，并从窗口时长中减去从该时长队列中被删除的该最先记录的存储时长。PCIe交换机在该窗口时长达到第六阈值时，确定第一端口发生报文反压。由于该窗口时长不会被重置为0，保证报文存储时长的峰值 始终被检测到，提高报文反压检测的灵敏度。
可选的，本申请实施例中，检测报文反压的方法还包括如下步骤：
步骤605：当记录的任一报文在缓冲区13中的存储时长达到第五阈值时，PCIe交换机确定第一端口发生报文反压，该第五阈值小于第一阈值。
具体的，PCIe交换机不仅能够根据报文缓存时间的累计时长确定是否发生报文反压，而且只要有任一报文的存储时长大于第五阈值，即确定发生报文反压，进而在有报文在缓冲区缓存了过长时间但尚未导致该累计时长超过第一阈值时，尽快地确定发生了报文反压，提高检测报文反压的灵敏度。其中，第五阈值小于第一阈值，例如，第一阈值为60s，第五阈值为5s。
可选的，本申请实施例中，PCIe交换机在确定发生报文反压后时，生成报文反压错误，并根据报文反压错误对报文反压进行处理，PCIe交换机处理报文反压的方式请参照现有技术中各种处理报文反压的方式，如断开发生报文反压的链路，发送消息信号中断(Message Signal Interrupt，MSI)到CPU，等等。另外，PCIe交换机生成的报文反压错误报告中还可以包括导致该累计时间达到第一阈值的报文的报文头信息。
可选的，本申请实施例中，上述第二阈值至第六阈值可以为默认设定，也可以由用户进行设定，具体的，PCIe交换机的处理器包括配置单元，该配置单元用于接收用户的配置数据，根据该配置数据确定上述第二阈值至第六阈值。
可选的，本申请实施例中，PCIe交换机能够通过同一处理器实现对PCIe交换机的同一端口(UP或DP)上下行两个方向上的报文反压进行检测。
如图9所示，缓冲区522用于存储DP520发往EP方向上报文发送队列中当前需发送的报文，第二缓冲区524用于存储DP520发往UP510方向的报文发送队列中当前需发送的报文，第二缓存单元523用于存储DP520发往UP510的报文发送队列中排在第二以及之后的报文。处理器530用于记录缓冲区522中每个报文的存储时长，并对记录的该存储时长进行累加，获得缓冲区522中存储报文的累计时长，并在该累计时长达到第一阈值时确定DP520 发生报文反压；处理器530还用于记录第二缓冲区524中每个报文的存储时长，并对记录的该存储时长进行累加，获得第二缓冲区524中存储报文的第二累计时长，并在该第二累计时长达到第一阈值时确定DP520发生报文反压。
在一种可选实现方式中，处理器530用于在设定的条件下将该累计时长以及该第二累计时长减小。其中，处理器530采用前述方式1、方式2或二者的结合将第一累计时长以及第二累计时长减小。
上述处理器530检测DP520向UP510发送报文方向以及向EP发送报文方向的报文反压的实现请参照步骤601至步骤605的实现，在此不予重复。
可选的，本申请实施例中，PCIe交换机能够通过同一处理器实现对PCIe交换机的不同端口上发生的报文反压进行检测。
如图10所示，缓冲区522用于存储DP520发往EP301的方向上报文发送队列中当前需发送的报文，第三缓冲区552用于存储DP550发往EP302方向上报文发送队列中当前需发送的报文，第三缓存单元551用于存储DP550发往EP302的报文发送队列中排在第二以及之后的报文。处理器530用于记录缓冲区522中每个报文的存储时长，并对记录的存储时长进行累加，获得缓冲区522中存在报文的累计时长，并在该累计时长达到第一阈值时确定DP520发生报文反压；处理器530还用于记录第三缓冲区552中每个报文的存储时长，并对记录的存储时长进行累加，获得第三缓冲区552中存储报文的第三累计时长，并在该第三累计时长达到第一阈值时确定DP550发生报文反压。
在一种可选实现方式中，处理器530还用于在设定的条件下将第一累计时长减小，以及在设定的条件下第二累计时长减小。其中，处理器530采用前述方式1、方式2或二者的结合将第一累计时长以及第二累计时长减小。
上述处理器530检测DP520向EP301发送报文方向以及DP550向EP302发送报文方向的报文反压的实现请参照步骤601至步骤605的实现，在此不予重复。
可选的，本申请实施例中，PCIe交换机能够通过不同的处理器分别对PCIe 交换机的不同端口上发生的报文反压进行检测。
如图11所示，缓冲区522用于存储DP520发往EP301方向上的报文发送队列中当前需发送的报文，第三缓冲区552用于存储DP550发往EP302方向上的报文发送队列中当前需发送的报文。处理器530用于记录缓冲区522中每个报文的存储时长，并对记录的存储时长进行累加，获得缓冲区522中存储报文的累计时长，并在该累计时长达到第一阈值时确定DP520发生报文反压。处理器540用于记录第三缓冲区552中每个报文的存储时长，并对记录的存储时长进行累加，获得第三缓冲区552中存储报文的第四累计时长，在该第四累计时长达到第一阈值时确定DP550发生报文反压。
在一种可选实现方式中，处理器530还用于在设定的条件下将第一累计时长减小，处理器540还用于在设定的条件下第二累计时长减小。其中，处理器530以及处理器540采用前述方式1、方式2或二者的结合分别将第一累计时长以及第二累计时长减小。
上述处理器530检测DP520向EP301发送报文方向的报文反压，以及处理器540检测DP550发往EP302方向的报文反压的实现方式请参照步骤601至步骤605的实现方式，在此不予重复。
需要说明的是，上述图6至图11所对应的检测报文反压的方法同样适用于检测CPU或EP的PCIe端口处是否发生报文反压，本申请实施例在此不再重复。
图12为本申请实施例提供的检测报文反压的装置700的示意图，装置700应用于具有PCIe端口的设备，装置700包括：
缓存模块701，用于在PCIe端口的报文发送队列中的每个待发送报文成为PCIe端口的当前需要发送的报文时，将需要发送的报文存储在缓冲区中，其中，缓冲区存储的报文在经由PCIe端口发送后从缓冲区移除，缓冲区在任意时刻至多存储一个报文；
计时模块702，用于记录缓冲区存储的每个报文的存储时长，并对记录的每个报文的存储时长进行累加，得到缓冲区存储报文的累计时长；
确定模块703，用于当累计时长达到第一阈值时确定PCIe端口发生报文反压。
可选的，本申请实施例中，装置700还包括：
计时清零模块704，用于在预设条件下将计时模块确定的累计时长重置为0。
可选的，本申请实施例中，计时清零模块704具体用于：
设置清零计时器，并进行计时，当清零计时器记录的时间达到第二阈值时，将计时模块确定的累计时长重置为0。
可选的，本申请实施例中，计时清零模块704具体用于：
记录通过缓冲区存储过的报文的数量，并当数量达到第三阈值时将计时模块确定的累计时长重置为0。
可选的，本申请实施例中，计时模块702依次记录的每个报文的存储时长形成时长队列，装置700还包括：
计时控制模块705，用于当时长队列的长度达到第四阈值时从时长队列中删除最先记录的存储时长，并从计时模块确定的累加时长中减去从时长队列中被删除的最先记录的存储时长。
可选的，本申请实施例中，确定模块703还用于：
当计时模块记录的任一报文在缓冲区中的存储时长达到第五阈值时，确定PCIe端口发生报文反压，第五阈值小于第一阈值。
上述装置700包括的各模块的实现方式可以参照前述步骤601至步骤605中各步骤的实现方式，需要说明的是，装置700不限于应用在PCIe交换机中，也可以应用在CPU或EP中。
图13为本申请实施例提供的检测报文反压的设备800的示意图，设备800包括：总线801，以及分别与总线801相连的PCIe端口802、存储器803、处理器804；
其中，PCIe端口802用于发送报文；
存储器803用于存储PCIe端口的报文发送队列；
处理器804用于：在PCIe端口802的报文发送队列中的每个待发送报文成为PCIe端口802的当前需要发送的报文时，将需要发送的报文存储在缓冲区中，其中，缓冲区存储的报文在经由PCIe端口802发送后从缓冲区移除，缓冲区在任意时刻至多存储一个报文；记录缓冲区存储的每个报文的存储时长，并对记录的每个报文的存储时长进行累加，得到缓冲区存储报文的累计时长；当累计时长达到第一阈值时确定PCIe端口802发生报文反压。
可选的，本申请实施例中，存储器803还用于存储指令；
处理器804用于执行存储器803存储的指令，以实现处理器804的功能。
可选的，本申请实施例中，处理器804还用于：在预设条件下将累计时长重置为0。
可选的，本申请实施例中，处理器804用于：在预设条件下将累计时长重置为0，包括：
设置清零计时器，并进行计时，当清零计时器记录的时间达到第二阈值时，将累计时长重置为0。
可选的，本申请实施例中，处理器804用于：在预设条件下将累计时长重置为0，包括：
记录通过缓冲区存储过的报文的数量，并当数量达到第三阈值时将累计时长重置为0。
可选的，本申请实施例中，处理器804依次记录的每个报文的存储时长形成时长队列，处理器804还用于：
当时长队列的长度达到第四阈值时从时长队列中删除最先记录的存储时长，并从累加时长中减去从时长队列中被删除的最先记录的存储时长。
可选的，本申请实施例中，处理器804还用于：
当记录的任一报文在缓冲区中的存储时长达到第五阈值时，确定PCIe端口发生报文反压，第五阈值小于第一阈值。
可选的，本申请实施例中，设备还包括第二PCIe端口805；
处理器804还用于：在第二PCIe端口805的报文发送队列中的每个待发 送报文成为第二PCIe端口的当前需要发送的报文时，将第二PCIe端口805中需要发送的报文存储在第三缓冲区中，其中，第三缓冲区存储的报文在经由第二PCIe端口805发送后从第三缓冲区移除，第三缓冲区在任意时刻至多存储一个报文；记录第三缓冲区存储的每个报文的存储时长，并对记录的第三缓冲区存储的每个报文的存储时长进行累加，得到第三缓冲区存储报文的第三累计时长；当第三累计时长达到第一阈值时确定第二PCIe端口805发生报文反压。
上述设备800的各部件的实现方式可以参照前述步骤601至步骤605中各步骤的实现方式，需要说明的是，设备800不限于为PCIe交换机中，也可以为CPU或EP。
本申请实施例提供一种服务器，该服务器包括能够实现前述检测报文反压方法的设备10。
本申请实施例提供一种存储控制器，该存储控制器包括能够实现前述检测报文反压方法的设备10。
本申请实施例还提供一种计算机可读介质，用于存储计算机程序，该计算机程序包括用于执行图6至图11中任一图所对应检测报文反压方法以及该方法的任意可选的实现方式中的步骤的指令。
本申请实施例在上述各方面提供的实现方式的基础上，还可以进行进一步组合以提供更多实现方式。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程 和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (14)

  1. 一种检测报文反压的方法，其特征在于，所述方法应用于具有高速外围部件互连PCIe端口的设备，所述方法包括：
    在所述PCIe端口的报文发送队列中的每个待发送报文成为所述PCIe端口的当前需要发送的报文时，所述设备将所述需要发送的报文存储在缓冲区中，其中，所述缓冲区存储的报文在经由所述PCIe端口发送后从所述缓冲区移除，所述缓冲区在任意时刻至多存储一个报文；
    所述设备记录所述缓冲区存储的每个报文的存储时长，并对记录的所述每个报文的存储时长进行累加，得到所述缓冲区存储报文的累计时长；
    当所述累计时长达到第一阈值时，所述设备确定所述PCIe端口发生报文反压。
  2. 根据权利要求1所述的方法，其特征在于，还包括：
    所述设备在预设条件下将所述累计时长重置为0。
  3. 根据权利要求2所述的方法，其特征在于，所述设备在预设条件下将所述累计时长重置为0，包括：
    所述设备设置清零计时器，并进行计时，当所述清零计时器记录的时间达到第二阈值时，将所述累计时长重置为0。
  4. 根据权利要求2所述的方法，其特征在于，所述设备在预设条件下将所述累计时长重置为0，包括：
    所述设备记录通过所述缓冲区存储过的报文的数量，并当所述数量达到第三阈值时将所述累计时长重置为0。
  5. 根据权利要求1至4任一项所述的方法，其特征在于，所述设备依次记录的所述每个报文的存储时长形成时长队列，所述方法还包括：
    当所述时长队列的长度达到第四阈值时，所述设备从所述时长队列中删除最先记录的存储时长，并从所述累加时长中减去从所述时长队列中被删除的所述最先记录的存储时长。
  6. 根据权利要求1至5任一项所述的方法，其特征在于，还包括：
    当记录的任一报文在所述缓冲区中的存储时长达到第五阈值时，所述设备确定所述PCIe端口发生报文反压，所述第五阈值小于所述第一阈值。
  7. 根据权利要求1至6任一项所述的方法，其特征在于，所述在所述PCIe端口的报文发送队列中的每个待发送报文成为所述PCIe端口的当前需要发送的报文时，所述设备将所述需要发送的报文存储在缓冲区中，包括：
    在所述PCIe端口的第一方向上的报文发送队列中的每个待发送报文成为所述PCIe端口的当前需要发送的报文时，所述设备将所述第一方向上的所述需要发送的报文存储在缓冲区中；所述第一方向为所述PCIe端口的上行方向或下行方向；
    所述方法还包括：
    在所述PCIe端口的第二方向上的报文发送队列中的每个待发送报文成为所述PCIe端口的当前需要发送的报文时，所述设备将所述第二方向上的所述需要发送的报文存储在第二缓冲区中，所述第二方向与所述第一方向相反，所述第二缓冲区存储的报文在经由所述PCIe端口发送后从所述第二缓冲区移除，所述第二缓冲区在任意时刻至多存储一个报文；
    所述设备记录所述第二缓冲区存储的每个报文的存储时长，并对记录的所述第二缓冲区存储的每个报文的存储时长进行累加，得到所述第二缓冲区存储报文的第二累计时长；
    当所述第二累计时长达到所述第一阈值时，所述设备确定所述PCIe端口发生报文反压。
  8. 一种检测报文反压的装置，其特征在于，所述装置应用于具有PCIe端口的设备，所述装置包括：
    缓存模块，用于在所述PCIe端口的报文发送队列中的每个待发送报文成为所述PCIe端口的当前需要发送的报文时，将所述需要发送的报文存储在缓冲区中，其中，所述缓冲区存储的报文在经由所述PCIe端口发送后从所述缓冲区移除，所述缓冲区在任意时刻至多存储一个报文；
    计时模块，用于记录所述缓冲区存储的每个报文的存储时长，并对记录的所述每个报文的存储时长进行累加，得到所述缓冲区存储报文的累计时长；
    确定模块，用于当所述累计时长达到第一阈值时确定所述PCIe端口发生报文反压。
  9. 根据权利要求8所述的装置，其特征在于，还包括：
    计时清零模块，用于在预设条件下将所述计时模块确定的所述累计时长重置为0。
  10. 根据权利要求8所述的装置，其特征在于，所述计时清零模块具体用于：
    设置清零计时器，并进行计时，当所述清零计时器记录的时间达到第二阈值时，将所述计时模块确定的所述累计时长重置为0。
  11. 根据权利要求9所述的装置，其特征在于，所述计时清零模块具体用于：
    记录通过所述缓冲区存储过的报文的数量，并当所述数量达到第三阈值时将所述计时模块确定的所述累计时长重置为0。
  12. 根据权利要求8至11任一项所述的装置，其特征在于，所述计时模块依次记录的所述每个报文的存储时长形成时长队列，所述装置还包括：
    计时控制模块，用于当所述时长队列的长度达到第四阈值时从所述时长队列中删除最先记录的存储时长，并从所述计时模块确定的所述累加时长中减去从所述时长队列中被删除的所述最先记录的存储时长。
  13. 根据权利要求8至12任一项所述的装置，其特征在于，所述确定模块还用于：
    当所述计时模块记录的任一报文在所述缓冲区中的存储时长达到第五阈值时，确定所述PCIe端口发生报文反压，所述第五阈值小于所述第一阈值。
  14. 一种检测报文反压的设备，其特征在于，包括处理器、存储器、PCIe端口、总线，所述处理器、存储器和PCIe端口之间通过总线连接并完成相互间的通信，所述存储器中用于存储计算机执行指令，所述设备运行时，所述 处理器执行所述存储器中的计算机执行指令以利用所述设备中的硬件资源执行权利要求1至7中任一所述的方法。
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