WO2018043888A1 - Film type semiconductor sealing member, semiconductor package manufactured using same, and manufacturing method therefor - Google Patents

Film type semiconductor sealing member, semiconductor package manufactured using same, and manufacturing method therefor Download PDF

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Publication number
WO2018043888A1
WO2018043888A1 PCT/KR2017/006526 KR2017006526W WO2018043888A1 WO 2018043888 A1 WO2018043888 A1 WO 2018043888A1 KR 2017006526 W KR2017006526 W KR 2017006526W WO 2018043888 A1 WO2018043888 A1 WO 2018043888A1
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WIPO (PCT)
Prior art keywords
layer
semiconductor
sealing member
type semiconductor
epoxy resin
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PCT/KR2017/006526
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French (fr)
Korean (ko)
Inventor
권기혁
이윤만
Original Assignee
삼성에스디아이 주식회사
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Priority to CN201780051248.2A priority Critical patent/CN109643693B/en
Publication of WO2018043888A1 publication Critical patent/WO2018043888A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a film type semiconductor sealing member, a semiconductor package manufactured using the same, and a method of manufacturing the same. More specifically, a film-type semiconductor sealing member that can be applied to a large area, generates less warpage, and has excellent narrow gap filling characteristics, suitable for wafer level packaging or panel level packaging process, It relates to a manufactured semiconductor package and a method of manufacturing the same.
  • the method of sealing a semiconductor element with an epoxy resin composition is commercially performed for the purpose of protecting a semiconductor element from external environments, such as moisture or a mechanical shock.
  • packaging is performed in units of semiconductor chips, but packaging is performed in a wafer state or a panel state which is not cut recently.
  • a process for cutting into semiconductor chips was developed.
  • the former method is referred to as chip scale packaging (CSP) and the latter process is called wafer level packaging (WLP) and panel level packaging (PLP).
  • Wafer-level packaging has advantages in that the process is simpler than the chip scale packaging process, and the package thickness is reduced, thereby reducing the semiconductor mounting space.
  • wafer level packaging or panel level packaging there is a problem in that warpage due to the difference in thermal expansion rate between the wafer or the panel and the encapsulant is large because the film forming area is larger than that of the chip scale packaging for sealing individual chips. If warping occurs, it will affect the yield and wafer handling of subsequent processes.
  • a liquid type epoxy resin or a silicone resin is mainly used as a sealing material for wafer level packaging and panel level packaging.
  • a liquid type composition has a low inorganic filler content and a resin also uses a liquid single molecule. There is a problem that the reliability of the semiconductor package after sealing is weak.
  • An object of the present invention is to provide a semiconductor sealing member for films which is less in warp, can achieve excellent reliability, and is suitable for wafer level packaging or panel level packaging processes.
  • Another object of the present invention is to provide a semiconductor sealing member for films having excellent fluidity and excellent narrow gap filling properties.
  • Still another object of the present invention is to provide a method for manufacturing a semiconductor package using the semiconductor sealing member for film.
  • Still another object of the present invention is to provide a semiconductor package sealed with the semiconductor sealing member for film.
  • the invention is a first layer of glass fabric; A second layer formed on the first layer and including a first epoxy resin and a first inorganic filler; A third layer formed under the first layer and comprising a second epoxy resin and a second inorganic filler, wherein the thickness of the third layer is thicker than the thickness of the second layer. to provide. At this time, the thickness of the third layer is preferably at least two times the thickness of the second layer.
  • the first inorganic filler may have a maximum particle diameter of less than 1/2 of the pore area of the glass fabric, the maximum particle diameter of the second inorganic filler may be less than 1/2 of the thickness of the third layer.
  • the maximum particle diameter of the first inorganic filler and the second inorganic filler may be the same or different from each other.
  • the third layer may include two or more kinds of inorganic fillers having different maximum particle diameters, wherein the third layer includes a first region in which inorganic fillers having a large maximum particle diameter are distributed and an inorganic having a small maximum particle diameter. It may consist of a second region in which fillers are distributed.
  • the present invention provides a method of manufacturing a semiconductor package comprising the step of sealing the semiconductor device using the film-type semiconductor sealing member according to the present invention.
  • the sealing may be performed by a compression molding method or a lamination method.
  • the method of manufacturing a semiconductor package comprises the steps of preparing a carrier member having a temporary fixing member attached to one surface; Arranging a plurality of semiconductor chips on the temporary fixing member; Forming a sealing layer on the semiconductor chip using the film type semiconductor sealing member; Separating the sealing layer and the temporary fixing member; Forming a substrate including a redistribution layer on the plurality of semiconductor chips; Forming an external connection terminal under the substrate; And forming a separate semiconductor package through a dicing process.
  • the present invention provides a semiconductor package sealed using the film-type semiconductor sealing member according to the present invention.
  • the semiconductor package may include a flip chip type semiconductor chip, a wire bonding type semiconductor chip, or a combination thereof.
  • the semiconductor package may include at least two or more heterogeneous semiconductor chips.
  • the semiconductor package a substrate comprising a redistribution layer; At least one semiconductor chip disposed on the redistribution layer; A sealing layer formed to seal the semiconductor chip using the film-type semiconductor sealing member according to the present invention; And an external connection terminal formed under the substrate.
  • the semiconductor sealing member according to the present invention can be usefully applied to wafer level packaging and panel level packaging formed into a film and applied to a large area.
  • the semiconductor sealing member according to the present invention has excellent rigidity including a glass fabric, when manufacturing a semiconductor package using the same, excellent reliability can be realized.
  • the semiconductor sealing member according to the present invention has excellent fluidity in the lower portion of the glass fabric and includes a thick resin layer, it has excellent narrow gap peeling characteristics and can minimize damage to the wire during molding.
  • FIG. 1 is a view showing an embodiment of a semiconductor sealing member according to the present invention.
  • FIG. 2 is a view showing another embodiment of a semiconductor sealing member according to the present invention.
  • FIG. 3 is a view illustrating an embodiment of a semiconductor package according to the present invention.
  • FIG. 4 is a view showing another embodiment of a semiconductor package according to the present invention.
  • FIG. 5 is a view showing another embodiment of a semiconductor package according to the present invention.
  • Positional relationships such as 'top', 'top', 'bottom', and 'bottom' are described based on the drawings and do not represent absolute positional relationships. That is, the positions of the 'top' and 'bottom' or 'top' and 'bottom' may be changed depending on the position to be observed.
  • the semiconductor sealing member according to the present invention includes a first layer 10 made of glass fabric, a second layer 20 formed on top of the first layer, and the first layer.
  • the third layer 30 is formed at the bottom of the.
  • the glass fabric is a fabric formed by weaving the glass fibers 12, and the material of the glass fibers constituting the glass fabric is not particularly limited.
  • the glass fabric may be formed of E glass, C glass, A glass, S glass, D glass, NE glass, T glass, H glass, and the like, of which E glass or S glass is particularly preferable.
  • the thickness of the glass fabric is specifically 10 ⁇ m to 50 ⁇ m, more specifically 15 ⁇ m to 35 ⁇ m, for example 15 ⁇ m, 16 ⁇ m, 17 ⁇ m, 18 ⁇ m, 19 ⁇ m, 20 ⁇ m, 21 ⁇ m, 22 ⁇ m, 23 ⁇ m, 24 ⁇ m, 25 ⁇ m, 26 ⁇ m, 27 ⁇ m, 28 ⁇ m, 29 ⁇ m, 30 ⁇ m, 31 ⁇ m, 32 ⁇ m, 33 ⁇ m, 34 ⁇ m, 35 ⁇ m. In the above range, the production of a film-type semiconductor sealing member is easy.
  • the second layer 20 is formed on top of the first layer 10 made of glass fabric, the first epoxy resin composition comprising a first epoxy resin 24 and the first inorganic filler 22 Is formed by.
  • the first epoxy resin 24 an epoxy resin including two or more epoxy groups may be used, and is not particularly limited.
  • the first epoxy resin 24 is an epoxy resin obtained by epoxidizing a condensate of phenol or alkyl phenols with hydroxybenzaldehyde, a phenol novolak type epoxy resin, a cresol novolak type epoxy resin, and a polyfunctional type.
  • Epoxy resin, naphthol novolac type epoxy resin, novolak type epoxy resin of bisphenol A / bisphenol F / bisphenol AD, glycidyl ether of bisphenol A / bisphenol F / bisphenol AD, bishydroxy biphenyl epoxy resin, dicyclo Pentadiene type epoxy resin etc. are mentioned.
  • the epoxy resin may be a cresol novolac type epoxy resin, a polyfunctional epoxy resin, a phenol aralkyl type epoxy resin, a biphenyl type epoxy resin, or the like.
  • first inorganic filler 22 general inorganic fillers used in a semiconductor sealing material may be used without limitation, and are not particularly limited.
  • silica, calcium carbonate, magnesium carbonate, alumina, ceria, magnesia, clay, talc, calcium silicate, titanium oxide, antimony oxide, glass fiber, etc. may be used as the first inorganic filler. have. These may be used alone or in combination. Among these, silica is particularly preferable.
  • the first inorganic filler is preferably a maximum particle size of less than 1/2 of the pore area of the glass fabric, more specifically 1/3 or less of the pore area of the glass fabric. This is because when the maximum particle diameter of the first inorganic filler exceeds 1/2 of the pore area of the glass fabric, the voids of the glass fabric are blocked by the first inorganic filler, which may result in poor fluidity during molding.
  • the first inorganic filler has a maximum particle diameter of specifically 0.5 ⁇ m to 20 ⁇ m, more specifically 1 ⁇ m to 10 ⁇ m, for example 1 ⁇ m, 2 ⁇ m, 3 ⁇ m, 4 ⁇ m, 5 ⁇ m, 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, 9 ⁇ m, 10 ⁇ m.
  • the second layer 20 is specifically 5 wt% to 99 wt%, more specifically 5 wt% to 80 wt%, even more specifically 15 wt% to 70 wt% of the first epoxy resin 24
  • the first The inorganic filler 22 is specifically 1% to 95% by weight, more specifically 1% to 85% by weight, even more specifically 5% to 70% by weight, for example 10% to 50% by weight, 10 wt%, 15 wt%, 20 wt%, 25 wt%, 30 wt%, 35 wt%, 40 wt%, 45 wt%, and 50 wt%.
  • fluidity and mechanical properties of the semiconductor sealing member can be properly secured.
  • the thickness of the second layer 20 is specifically 5 ⁇ m to 40 ⁇ m, more specifically 10 ⁇ m to 30 ⁇ m, for example, 10 ⁇ m, 11 ⁇ m, 12 ⁇ m, 13 ⁇ m, 14 ⁇ m, 15 ⁇ m, 16 Micrometer, 17 ⁇ m, 18 ⁇ m, 19 ⁇ m, 20 ⁇ m, 21 ⁇ m, 22 ⁇ m, 23 ⁇ m, 24 ⁇ m, 25 ⁇ m, 26 ⁇ m, 27 ⁇ m, 28 ⁇ m, 29 ⁇ m, 30 ⁇ m.
  • the third layer 30 is formed on the lower portion of the first layer 10 made of glass fabric, the second epoxy resin composition comprising a second epoxy resin 34 and the second inorganic filler 32 Is formed by.
  • the second epoxy resin 34 an epoxy resin including two or more epoxy groups may be used, and is not particularly limited.
  • the second epoxy resin 34 is an epoxy resin obtained by epoxidizing a condensate of phenol or alkyl phenols with hydroxybenzaldehyde, a phenol novolak type epoxy resin, a cresol novolak type epoxy resin, and a polyfunctional type.
  • Epoxy resin, naphthol novolac type epoxy resin, novolak type epoxy resin of bisphenol A / bisphenol F / bisphenol AD, glycidyl ether of bisphenol A / bisphenol F / bisphenol AD, bishydroxy biphenyl epoxy resin, dicyclo Pentadiene type epoxy resin etc. are mentioned.
  • the epoxy resin may be a cresol novolac type epoxy resin, a polyfunctional epoxy resin, a phenol aralkyl type epoxy resin, a biphenyl type epoxy resin, or the like.
  • the second epoxy resin 34 may be the same as or different from the first epoxy resin 24.
  • the second epoxy resin 34 may include two or more different resins.
  • the epoxy resins may be present in different regions.
  • the third layer may include the same epoxy resin as the first epoxy resin forming the second layer and an epoxy resin different from the first epoxy resin, and in this case, the same epoxy as the first epoxy resin.
  • the resin may be disposed at the top of the third layer, that is, in the region proximate the glass fabric, and an epoxy resin different from the first epoxy resin may be disposed at the bottom of the third layer.
  • the second inorganic filler 32 may be used without limitation, general inorganic fillers used in the semiconductor sealing material, it is not particularly limited.
  • silica, calcium carbonate, magnesium carbonate, alumina, ceria, magnesia, clay, talc, calcium silicate, titanium oxide, antimony oxide, glass fiber, etc. may be used as the first inorganic filler. have. These may be used alone or in combination. Among these, silica is particularly preferable.
  • the maximum particle diameter of the second inorganic filler 32 may be specifically 1/2 or less, more specifically 1/3 or less of the thickness of the third layer 30. If the maximum particle diameter of the second inorganic filler exceeds 1/2 of the thickness of the third layer, moldability and fillability may be degraded.
  • the second inorganic filler has a maximum particle diameter of 0.5 ⁇ m to 60 ⁇ m, more specifically 1 ⁇ m to 30 ⁇ m, for example, 1 ⁇ m, 2 ⁇ m, 3 ⁇ m, 4 ⁇ m, 5 ⁇ m, 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, 9 ⁇ m, 10 ⁇ m, 11 ⁇ m, 12 ⁇ m, 13 ⁇ m, 14 ⁇ m, 15 ⁇ m, 16 ⁇ m, 17 ⁇ m, 18 ⁇ m, 19 ⁇ m, 20 ⁇ m, 21 ⁇ m, 22 ⁇ m, 23 ⁇ m , 24 ⁇ m, 25 ⁇ m, 26 ⁇ m, 27 ⁇ m, 28 ⁇ m, 29 ⁇ m, 30 ⁇ m.
  • the maximum particle diameter of the first inorganic filler and the second inorganic filler may be the same or different from each other.
  • the third layer 30 is specifically 5 wt% to 99 wt%, more specifically 5 wt% to 80 wt%, and more specifically 15 wt% to 70 wt% of the second epoxy resin 34.
  • the second The inorganic filler 32 is specifically 1% to 95% by weight, more specifically 1% to 85% by weight, even more specifically 5% to 70% by weight, for example 10% to 50% by weight, 10 wt%, 15 wt%, 20 wt%, 25 wt%, 30 wt%, 35 wt%, 40 wt%, 45 wt%, and 50 wt%. There is an effect excellent in moldability in the above range.
  • the third layer 30 is formed thicker than the second layer 20.
  • the thickness of the third layer 30 may be two times or more, more specifically, two to five times the thickness of the second layer 20.
  • the third layer 30 has a thickness of 10 ⁇ m to 425 ⁇ m, more specifically 20 ⁇ m to 425 ⁇ m, even more specifically 40 ⁇ m to 210 ⁇ m, for example, 50 ⁇ m to 150 ⁇ m, 50 ⁇ m. , 55 ⁇ m, 60 ⁇ m, 65 ⁇ m, 70 ⁇ m, 75 ⁇ m, 80 ⁇ m, 85 ⁇ m, 90 ⁇ m, 95 ⁇ m, 100 ⁇ m, 105 ⁇ m, 110 ⁇ m, 115 ⁇ m, 120 ⁇ m, 125 ⁇ m, 130 ⁇ m, 135 Micrometer, 140 micrometer, 145 micrometer, 150 micrometer.
  • the thickness of the third layer satisfies the above range, excellent fluidity and package filling property can be ensured.
  • the third layer 30 may include one type of inorganic filler having the same maximum particle diameter, and as shown in FIG. 2, two or more types of inorganic fillers having different maximum particle diameters may be used. It may also include.
  • the third layer When the third layer includes two or more kinds of inorganic fillers having different sizes, the third layer is formed of a first region 30a in which inorganic fillers having a large maximum particle size are distributed and an inorganic filler having a small maximum particle diameter is distributed. It may be divided into two regions 30b. In FIG. 2, the inorganic fillers having the largest particle diameters are shown below the third layer. However, the present invention is not limited thereto. It may be located at the bottom of the third floor.
  • the epoxy resins forming the matrix of the first region 30a and the second region 30b may be the same or different from each other.
  • the first region 30a may include the same epoxy resin as the first epoxy resin of the second layer
  • the second region 30b may include an epoxy resin different from the first epoxy resin.
  • the first epoxy resin composition and the second epoxy resin composition forming the second layer 20 and the third layer 30 include a curing agent, a curing accelerator, a coupling agent, and a release agent in addition to the epoxy resin and the inorganic filler. And colorants.
  • curing agents generally used in semiconductor sealing members may be used without limitation.
  • the curing agent is specifically 1% to 40% by weight, more specifically 3% to 35% by weight, for example, 3% by weight, 4% by weight, 5% by weight relative to the total weight of the epoxy resin composition included , 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18 Wt%, 19 wt%, 20 wt%, 21 wt%, 22 wt%, 23 wt%, 24 wt%, 25 wt%, 26 wt%, 27 wt%, 28 wt%, 29 wt%, 30 wt% , 31%, 32%, 33%, 34%, 35% by weight.
  • the curing accelerator is for promoting the reaction between the epoxy resin and the curing agent, for example, tertiary amines, organometallic compounds, organophosphorus compounds, imidazole, boron compounds and the like can be used.
  • Tertiary amines include benzyldimethylamine, triethanolamine, triethylenediamine, diethylaminoethanol, tri (dimethylaminomethyl) phenol, 2-2- (dimethylaminomethyl) phenol, 2,4,6-tris (diaminomethyl ) Phenol and tri-2-ethylhexyl acid salt and the like can be used.
  • the amount of the curing accelerator may be specifically about 0.01% to 2% by weight, more specifically about 0.02% to 1.5% by weight, more specifically about 0.05% to 1% by weight, based on the total weight of the epoxy resin composition. For example, it may be 0.05%, 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1% by weight. In the above range, there is an advantage that the curing of the epoxy resin composition is promoted and the degree of curing is also good.
  • the coupling agent is for improving the interfacial strength by reacting between the epoxy resin and the inorganic filler.
  • the coupling agent may be a silane coupling agent.
  • the said silane coupling agent may react between an epoxy resin and an inorganic filler, and what is necessary is just to improve the interface strength of an epoxy resin and an inorganic filler,
  • the kind is not specifically limited.
  • Specific examples of the silane coupling agent include epoxysilane, aminosilane, ureidosilane, mercaptosilane, and the like.
  • the coupling agents may be used alone or in combination.
  • the coupling agent is specifically about 0.01% to 5% by weight, more specifically about 0.05% to 3% by weight, even more specifically about 0.1% to 2% by weight relative to the total weight of the epoxy resin composition, for example , 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1%, 1.1%, 1.2%, 1.3 It may be included in the content of wt%, 1.4 wt%, 1.5 wt%, 1.6 wt%, 1.7 wt%, 1.8 wt%, 1.9 wt%, 2 wt%. In the above range, the strength of the cured epoxy resin composition is improved.
  • the release agent may be used at least one selected from the group consisting of paraffin wax, ester wax, higher fatty acid, higher fatty acid metal salt, natural fatty acid and natural fatty acid metal salt.
  • the release agent is specifically 0.1% to 1% by weight, for example 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, 0.8% by weight of the epoxy resin composition %, 0.9% by weight, may be included in 1% by weight.
  • the colorant is for laser marking of the semiconductor device sealant, and colorants well known in the art may be used, and are not particularly limited.
  • the colorant may include one or more of carbon black, titanium black, titanium nitride, copper hydroxide phosphate, iron oxide, and mica.
  • the colorant is specifically about 0.01% to 5% by weight, more specifically about 0.05% to 3% by weight, and even more specifically about 0.1% to 2% by weight relative to the total weight of the epoxy resin composition, for example, 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1%, 1.1%, 1.2%, 1.3% It may be included in the content of%, 1.4% by weight, 1.5% by weight, 1.6% by weight, 1.7% by weight, 1.8% by weight, 1.9% by weight, 2% by weight.
  • the epoxy resin composition of the present invention may be selected from the group consisting of stress relieving agents such as modified silicone oil, silicone powder, and silicone resin within the scope of not impairing the object of the present invention; Antioxidants such as Tetrakis [methylene-3- (3,5-di-tertbutyl-4-hydroxyphenyl) propionate] methane; And the like may be further added as necessary.
  • the semiconductor sealing member according to the present invention for example, after placing the glass fabric on the first release film, coating the first epoxy resin composition on the glass fabric, dried to form a first film
  • it may be prepared by a method of laminating the first film and the second film.
  • the lamination may be performed by using an adhesive member such as an adhesive or an adhesive, or may be performed by laminating the first film and the second film by applying pressure or temperature.
  • the semiconductor sealing member of the present invention manufactured by the above method has a film form, it can be usefully used in a large area process such as wafer level packaging or panel level packaging.
  • the semiconductor sealing member according to the present invention includes a glass fabric, it is possible to manufacture a semiconductor package having high rigidity and high reliability.
  • the semiconductor sealing member according to the present invention forms a thick third layer formed under the glass fabric, thereby exhibiting excellent fluidity, formability, step embedding and filling properties in sealing molding.
  • the method of manufacturing a semiconductor package according to the present invention is characterized by including the step of sealing the semiconductor device using the film-type semiconductor sealing member according to the present invention.
  • the sealing may be performed by semiconductor sealing methods generally used in the art, for example, a compression molding method or a lamination method.
  • the semiconductor package manufacturing method may be performed by a method for forming a redistribution layer after wafer level packaging or panel level packaging.
  • the semiconductor package may be manufactured by the following method.
  • a temporary fixing member such as an adhesive tape or a thermal release tape is attached to one surface of a carrier member such as a carrier wafer or a carrier panel to prepare a carrier member having a temporary fixing member attached to one surface.
  • the film-type semiconductor sealing member of the present invention is disposed on the semiconductor chip, and then molded by a method such as compression or lamination to form a sealing layer.
  • the molding temperature may vary depending on the type of sealing member, but may be generally performed at about 120 ° C. to 170 ° C.
  • a pre-baking process may be performed before forming the sealing layer, wherein the prebaking temperature is about 100 ° C. to 150 ° C., More specifically, 110 °C to 130 °C, for example 110 °C, 111 °C, 112 °C, 113 °C, 114 °C, 115 °C, 116 °C, 117 °C, 118 °C, 119 °C, 120 °C, 121 °C, 122 °C , 123 ° C, 124 ° C, 125 ° C, 126 ° C, 127 ° C, 128 ° C, 129 ° C, 130 ° C.
  • the sealing layer and the temporary fixing member are separated.
  • the separation may be performed by, for example, a method of raising a temperature to generate bubbles in the adhesive tape, but is not limited thereto.
  • a substrate including a redistribution layer is formed on the semiconductor chip.
  • the substrate including the redistribution layer may be formed by alternately stacking a dielectric layer and a metal layer on a semiconductor chip.
  • the dielectric layer may be made of, for example, photosensitive polyimide
  • the metal layer may be made of, for example, copper.
  • dielectric layers and metal layers of various materials used in the art may be used without limitation.
  • the redistribution layer may be formed of, for example, a photoresist such as polybenzoazole, and the like, but is not limited thereto.
  • Various redistribution layer forming materials used in the art may be used without limitation.
  • an external connection terminal such as a solder ball is formed at the bottom of the substrate, and an individual semiconductor package is formed through a dicing process.
  • 3 to 5 illustrate embodiments of a semiconductor package according to the present invention.
  • the semiconductor package according to the present invention is characterized by being sealed using the film-type semiconductor sealing member according to the present invention.
  • the semiconductor package according to the present invention the substrate 300, at least one semiconductor chip (200a, 200b), the sealing layer 100 and the external connection terminal 400 formed of a film-type semiconductor sealing member according to the present invention ).
  • the substrate 300 supports the semiconductor chips 200a and 200b and provides electrical signals to the semiconductor chips 200a and 200b, and semiconductor mounting substrates generally used in the art may be used without limitation. have.
  • the substrate 300 may be a circuit board, a lead frame substrate, or a substrate including a redistribution layer.
  • the circuit board may be made of an insulating material, for example, a flat plate to which a heat-curable film such as an epoxy resin or a polyimide is attached, or a heat-resistant organic film such as a liquid crystal polyester film or a polyamide film.
  • a circuit pattern is formed on the circuit board, and the circuit pattern includes a power line for supplying power, a ground line, a signal line for signal transmission, and the like.
  • Each of the wires may be separated from each other by an interlayer insulating layer.
  • the circuit board may be a printed circuit board (PCB) in which a circuit pattern is formed by a printing process.
  • PCB printed circuit board
  • the lead frame substrate may be made of a metal material such as nickel, iron, copper, nickel alloy, iron alloy, copper alloy, or the like.
  • the lead frame substrate may include a semiconductor chip mounting part for mounting a semiconductor chip and a connection terminal part electrically connected to an electrode part of the semiconductor chip.
  • the lead frame substrate is not limited thereto, and leads of various structures and materials known in the art may be used. Frame substrates can be used without limitation.
  • the substrate including the redistribution layer may include a redistribution layer (Re-Distribution Layer, RDL) in the outermost layer of the laminate in which the dielectric layer 310 and the metal layer 320 are alternately stacked.
  • RDL redistribution Layer
  • 330 is a formed substrate.
  • the dielectric layer 310 may be made of, for example, photosensitive polyimide
  • the metal layer 320 may be made of, for example, copper.
  • dielectric layers and metal layers of various materials used in the art may be used without limitation.
  • the redistribution layer may be formed of, for example, a photoresist such as polybenzoazole, and the like, but is not limited thereto.
  • Various redistribution layer forming materials used in the art may be used without limitation.
  • At least one semiconductor chip 200a or 200b is mounted on the substrate 300.
  • the number of semiconductor chips mounted on a substrate is not particularly limited. For example, as illustrated in FIG. 3 or 4, two or more semiconductor chips may be mounted on one substrate, and as illustrated in FIG. 5. As described above, one semiconductor chip may be mounted on one substrate.
  • the semiconductor chip mounting method is not particularly limited, and semiconductor chip mounting techniques known in the art may be used without limitation.
  • the semiconductor chip may be a flip chip type semiconductor chip 200b, a wire bonding type semiconductor chip 200a, or a combination thereof.
  • a bump is formed on a bottom surface of the semiconductor chip, and the bump is used to fuse the semiconductor chip to the circuit board.
  • the wire bonding method electrically connects the electrode portion of the semiconductor chip to the substrate with a metal wire. This is how you do it.
  • the semiconductor package according to the present invention may be configured to include two or more semiconductor chips of the same kind as shown in FIG. 3, or may be configured to include heterogeneous semiconductor chips as shown in FIG. 4. .
  • the sealing layer 100 is to protect the semiconductor chips (200a, 200b) from the external environment, it is formed using the film-type semiconductor sealing member according to the present invention. Since the said film type semiconductor sealing member was mentioned above, the detailed description is abbreviate
  • connection terminal 400 for electrically connecting the substrate 300 and an external power source.
  • the connection terminal may be any of various connection terminals well known in the art, for example, a lead, a ball grid array, and the like, without limitation.
  • the semiconductor package according to the present invention as shown in Figure 3, a substrate including a redistribution layer, at least one semiconductor chip disposed on the redistribution layer, is formed to encapsulate the semiconductor chip A sealing layer and an external connection terminal formed under the substrate, wherein the sealing layer is formed by a film-like sealing member according to the present invention.

Abstract

The present invention relates to a film type semiconductor sealing member, a semiconductor package manufactured using the same, and a manufacturing method therefor, the member comprising: a first layer made of a glass woven fabric; a second layer formed on the first layer and including a first epoxy resin and a first inorganic filler; and a third layer formed under the first layer and including a second epoxy resin and a second inorganic filler, wherein the third layer is thicker than the second layer.

Description

필름형 반도체 밀봉 부재, 이를 이용하여 제조된 반도체 패키지 및 그 제조방법Film type semiconductor sealing member, semiconductor package manufactured using same, and method for manufacturing same
본 발명은 필름형 반도체 밀봉 부재, 이를 이용하여 제조된 반도체 패키지 및 그 제조방법에 관한 것이다. 보다 상세하게는 대면적 적용이 가능하고, 휨 발생이 적으며, 내로우 갭 필링(Narrow Gap Pilling) 특성이 우수하여, 웨이퍼 레벨 패키징 또는 패널 레벨 패키징 공정에 적합한 필름형 반도체 밀봉 부재, 이를 이용하여 제조된 반도체 패키지 및 그 제조방법에 관한 것이다.The present invention relates to a film type semiconductor sealing member, a semiconductor package manufactured using the same, and a method of manufacturing the same. More specifically, a film-type semiconductor sealing member that can be applied to a large area, generates less warpage, and has excellent narrow gap filling characteristics, suitable for wafer level packaging or panel level packaging process, It relates to a manufactured semiconductor package and a method of manufacturing the same.
반도체 소자를 수분이나 기계적 충격 등의 외부 환경으로부터 보호하기 위한 목적으로 에폭시 수지 조성물로 반도체 소자를 밀봉하는 방법이 상업적으로 행해지고 있다. 종래에는 반도체 소자 밀봉 시에 웨이퍼를 절단(Dicing)하여 반도체 칩(chip)을 제조한 후, 반도체 칩 단위로 패키징이 이루어졌으나, 최근에 절단되지 않은 웨이퍼 상태 또는 이보다 큰 패널 상태에서 패키징을 수행한 다음, 반도체 칩으로 절단(dicing)하는 공정이 개발되었다. 일반적으로, 전자의 방법을 칩 스케일 패키징(Chip Scale Package, CSP), 후자의 공정을 웨이퍼 레벨 패키징(Wafer Level Packaging, WLP) 및 패널 레벨 패키징(Panel Level Packaging, PLP)이라고 한다. The method of sealing a semiconductor element with an epoxy resin composition is commercially performed for the purpose of protecting a semiconductor element from external environments, such as moisture or a mechanical shock. Conventionally, after manufacturing a semiconductor chip by dicing a wafer at the time of sealing a semiconductor device, packaging is performed in units of semiconductor chips, but packaging is performed in a wafer state or a panel state which is not cut recently. Next, a process for cutting into semiconductor chips was developed. In general, the former method is referred to as chip scale packaging (CSP) and the latter process is called wafer level packaging (WLP) and panel level packaging (PLP).
웨이퍼 레벨 패키징은 칩 스케일 패키징 공정에 비해 공정이 단순하고, 패키지 두께가 얇아 반도체 실장 공간을 감소시킬 수 있다는 장점이 있다. 그러나 웨이퍼 레벨 패키징이나 패널 레벨 패키징의 경우, 개개의 칩을 밀봉하는 칩 스케일 패키징에 비해 제막 면적이 넓기 때문에 웨이퍼 또는 패널과 봉지재의 열 팽창율 차이로 인한 휨(Warpage)이 크게 발생한다는 문제점이 있다. 휨이 발생할 경우, 후속 공정의 수율 및 웨이퍼 핸들링에 영향을 미치게 된다. 또한, 현재 웨이퍼 레벨 패키징이나 패널 레벨 패키징의 밀봉재로는 주로 액상 타입의 에폭시 수지 또는 실리콘 수지가 사용되고 있으나, 액상 타입의 조성물의 경우 무기 충전물의 함량이 낮고, 수지도 액상의 단분자를 사용하기 때문에 밀봉 후 반도체 패키지의 신뢰성이 취약하다는 문제점이 있다. Wafer-level packaging has advantages in that the process is simpler than the chip scale packaging process, and the package thickness is reduced, thereby reducing the semiconductor mounting space. However, in the case of wafer level packaging or panel level packaging, there is a problem in that warpage due to the difference in thermal expansion rate between the wafer or the panel and the encapsulant is large because the film forming area is larger than that of the chip scale packaging for sealing individual chips. If warping occurs, it will affect the yield and wafer handling of subsequent processes. In addition, a liquid type epoxy resin or a silicone resin is mainly used as a sealing material for wafer level packaging and panel level packaging. However, a liquid type composition has a low inorganic filler content and a resin also uses a liquid single molecule. There is a problem that the reliability of the semiconductor package after sealing is weak.
따라서, 웨이퍼 레벨 패키징 또는 패널 레벨 패키징 적용 시에도 휨 발생이 적고, 우수한 신뢰성을 구현할 수 있는 반도체 밀봉 부재의 개발이 요구되고 있다.Therefore, there is a demand for the development of a semiconductor sealing member that is less likely to generate warpage and realizes excellent reliability even in wafer level packaging or panel level packaging applications.
본 발명의 목적은 휨 발생이 적고, 우수한 신뢰성을 구현할 수 있으며, 웨이퍼 레벨 패키징 또는 패널 레벨 패키징 공정에 적합한 필름용 반도체 밀봉 부재를 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor sealing member for films which is less in warp, can achieve excellent reliability, and is suitable for wafer level packaging or panel level packaging processes.
본 발명의 다른 목적은 유동성이 우수하여 내로우 갭 필링(Narrow Gap Pilling) 특성이 우수한 필름용 반도체 밀봉 부재를 제공하는 것이다.Another object of the present invention is to provide a semiconductor sealing member for films having excellent fluidity and excellent narrow gap filling properties.
본 발명의 또 다른 목적은 상기 필름용 반도체 밀봉 부재를 이용한 반도체 패키지 제조 방법을 제공하는 것이다.Still another object of the present invention is to provide a method for manufacturing a semiconductor package using the semiconductor sealing member for film.
본 발명의 또 다른 목적은 상기 필름용 반도체 밀봉 부재로 밀봉된 반도체 패키지를 제공하는 것이다.Still another object of the present invention is to provide a semiconductor package sealed with the semiconductor sealing member for film.
일 측면에서, 본 발명은 유리 직물로 이루어진 제1층; 상기 제1층의 상부에 형성되고, 제1에폭시 수지 및 제1무기 충전제를 포함하는 제2층; 상기 제1층의 하부에 형성되고, 제2에폭시 수지 및 제2무기 충전제를 포함하는 제3층을 포함하며, 상기 제3층의 두께가 상기 제2층의 두께보다 두꺼운 필름형 반도체 밀봉 부재를 제공한다. 이때, 상기 제3층의 두께는 상기 제2층의 두께의 2배 이상인 것이 바람직하다.In one aspect, the invention is a first layer of glass fabric; A second layer formed on the first layer and including a first epoxy resin and a first inorganic filler; A third layer formed under the first layer and comprising a second epoxy resin and a second inorganic filler, wherein the thickness of the third layer is thicker than the thickness of the second layer. to provide. At this time, the thickness of the third layer is preferably at least two times the thickness of the second layer.
한편, 상기 제1무기충전제는 최대 입경이 상기 유리 직물의 공극 면적의 1/2 이하일 수 있으며, 상기 제2무기 충전제의 최대 입경은 상기 제3층의 두께의 1/2 이하일 수 있다. 상기 제1무기 충전제와 제2무기 충전제의 최대 입경은 서로 동일하거나 상이할 수 있다. On the other hand, the first inorganic filler may have a maximum particle diameter of less than 1/2 of the pore area of the glass fabric, the maximum particle diameter of the second inorganic filler may be less than 1/2 of the thickness of the third layer. The maximum particle diameter of the first inorganic filler and the second inorganic filler may be the same or different from each other.
일 구체예에서, 상기 제3층은 최대 입경이 상이한 2종 이상의 무기 충전제를 포함할 수 있으며, 이때, 상기 제3층은 최대 입경이 큰 무기 충전제들이 분포한 제1영역 및 최대 입경이 작은 무기 충전제들이 분포한 제2영역으로 이루어질 수 있다. In one embodiment, the third layer may include two or more kinds of inorganic fillers having different maximum particle diameters, wherein the third layer includes a first region in which inorganic fillers having a large maximum particle diameter are distributed and an inorganic having a small maximum particle diameter. It may consist of a second region in which fillers are distributed.
다른 측면에서, 본 발명은 상기 본 발명에 따른 필름형 반도체 밀봉 부재를 이용하여 반도체 소자를 밀봉하는 단계를 포함하는 반도체 패키지 제조 방법을 제공한다. In another aspect, the present invention provides a method of manufacturing a semiconductor package comprising the step of sealing the semiconductor device using the film-type semiconductor sealing member according to the present invention.
상기 밀봉은 컴프레션 몰딩(Compression Molding)법, 또는 라미네이션(Lamination)법에 의해 수행될 수 있다.The sealing may be performed by a compression molding method or a lamination method.
일 구체예에서, 상기 반도체 패키지 제조 방법은, 일면에 임시 고정 부재가 부착된 캐리어 부재를 준비하는 단계; 상기 임시 고정 부재 상에 다수의 반도체 칩을 배열하는 단계; 상기 필름형 반도체 밀봉 부재를 이용하여 상기 반도체 칩 상에 밀봉층을 형성하는 단계; 상기 밀봉층과 임시 고정 부재를 분리하는 단계; 상기 다수의 반도체 칩 상에 재배선층을 포함하는 기판을 형성하는 단계; 상기 기판의 하부에 외부 접속 단자를 형성하는 단계; 및 다이싱 공정을 통해 개별 반도체 패키지를 형성하는 단계를 포함하는 것일 수 있다. In one embodiment, the method of manufacturing a semiconductor package comprises the steps of preparing a carrier member having a temporary fixing member attached to one surface; Arranging a plurality of semiconductor chips on the temporary fixing member; Forming a sealing layer on the semiconductor chip using the film type semiconductor sealing member; Separating the sealing layer and the temporary fixing member; Forming a substrate including a redistribution layer on the plurality of semiconductor chips; Forming an external connection terminal under the substrate; And forming a separate semiconductor package through a dicing process.
또 다른 측면에서, 본 발명은 상기 본 발명에 따른 필름형 반도체 밀봉 부재를 이용하여 밀봉된 반도체 패키지를 제공한다. 이때, 상기 반도체 패키지는 플립 칩 방식의 반도체 칩, 와이어 본딩 방식의 반도체 칩 또는 이들의 조합을 포함할 수 있다. 또한, 상기 반도체 패키지는 적어도 2개 이상의 이종의 반도체 칩들을 포함할 수 있다.In another aspect, the present invention provides a semiconductor package sealed using the film-type semiconductor sealing member according to the present invention. In this case, the semiconductor package may include a flip chip type semiconductor chip, a wire bonding type semiconductor chip, or a combination thereof. In addition, the semiconductor package may include at least two or more heterogeneous semiconductor chips.
일 구체예에서, 상기 반도체 패키지는, 재배선층을 포함하는 기판; 상기 재배선층 상부에 배치되는 적어도 하나 이상의 반도체 칩; 상기 본 발명에 따른 필름형 반도체 밀봉 부재를 이용하여 상기 반도체 칩을 봉지하도록 형성되는 밀봉층; 및 상기 기판의 하부에 형성되는 외부 접속 단자를 포함한다.In one embodiment, the semiconductor package, a substrate comprising a redistribution layer; At least one semiconductor chip disposed on the redistribution layer; A sealing layer formed to seal the semiconductor chip using the film-type semiconductor sealing member according to the present invention; And an external connection terminal formed under the substrate.
본 발명에 따른 반도체 밀봉 부재는 필름형으로 형성되어 대면적으로 적용되는 웨이퍼 레벨 패키징 및 패널 레벨 패키징에 유용하게 적용될 수 있다. The semiconductor sealing member according to the present invention can be usefully applied to wafer level packaging and panel level packaging formed into a film and applied to a large area.
본 발명에 따른 반도체 밀봉 부재는 유리 직물을 포함하여 우수한 강성을 가지므로, 이를 이용하여 반도체 패키지를 제조할 경우, 우수한 신뢰성을 구현할 수 있다.Since the semiconductor sealing member according to the present invention has excellent rigidity including a glass fabric, when manufacturing a semiconductor package using the same, excellent reliability can be realized.
본 발명에 따른 반도체 밀봉 부재는 유리 직물의 하부에 유동성이 우수하고, 두꺼운 수지층을 포함하기 때문에, 내로우 갭 필링 특성이 우수하고, 몰딩 시에 와이어의 손상을 최소화할 수 있다.Since the semiconductor sealing member according to the present invention has excellent fluidity in the lower portion of the glass fabric and includes a thick resin layer, it has excellent narrow gap peeling characteristics and can minimize damage to the wire during molding.
도 1은 본 발명에 따른 반도체 밀봉 부재의 일 실시예를 도시한 도면이다. 1 is a view showing an embodiment of a semiconductor sealing member according to the present invention.
도 2는 본 발명에 따른 반도체 밀봉 부재의 다른 실시예를 도시한 도면이다.2 is a view showing another embodiment of a semiconductor sealing member according to the present invention.
도 3은 본 발명에 따른 반도체 패키지의 일 실시예를 도시한 도면이다.3 is a view illustrating an embodiment of a semiconductor package according to the present invention.
도 4는 본 발명에 따른 반도체 패키지의 다른 실시예를 도시한 도면이다. 4 is a view showing another embodiment of a semiconductor package according to the present invention.
도 5는 본 발명에 따른 반도체 패키지의 또 다른 실시예를 도시한 도면이다.5 is a view showing another embodiment of a semiconductor package according to the present invention.
이하, 첨부된 도면을 참조하여 본 발명을 보다 구체적으로 설명한다. 다만, 하기 도면은 본 발명에 대한 이해를 돕기 위해 제공되는 것일 뿐, 본 발명이 하기 도면에 의해 한정되는 것은 아니다. Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail. However, the following drawings are provided only to assist in understanding the present invention, and the present invention is not limited by the following drawings.
또한, 도면에 개시된 형상, 크기, 비율, 각도, 개수 등은 예시적인 것이므로 본 발명이 도시된 사항에 한정되는 것은 아니다. 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성 요소를 지칭한다. 또한, 본 발명을 설명함에 있어서, 관련된 공지 기술에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그 상세한 설명은 생략한다. In addition, the shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings are exemplary, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.
본 명세서에서 '포함한다', '갖는다', '이루어진다' 등이 사용되는 경우 '~만'이 사용되지 않는 이상 다른 부분이 추가될 수 있다. 구성 요소를 단수로 표현한 경우에 특별히 명시적인 기재 사항이 없는 한 복수를 포함하는 경우를 포함한다.In the present specification, when 'comprises', 'haves', 'consists of', etc., other parts may be added unless 'only' is used. In the case where the component is expressed in the singular, the plural includes the plural unless specifically stated otherwise.
구성 요소를 해석함에 있어서, 별도의 명시적 기재가 없더라도 오차 범위를 포함하는 것으로 해석한다.In interpreting a component, it is interpreted to include an error range even if there is no separate description.
~상에', '~상부에', '~하부에', '~옆에' 등으로 두 부분의 위치 관계가 설명되는 경우, '바로' 또는 '직접'이 사용되지 않는 이상 두 부분 사이에 하나 이상의 다른 부분이 위치할 수 있다.If the positional relationship between the two parts is described as 'on', 'upper', 'upper', 'next to', etc., between the two parts unless 'direct' or 'direct' is used One or more other parts may be located.
'상부', '상면', '하부', '하면' 등과 같은 위치 관계는 도면을 기준으로 기재된 것일 뿐, 절대적인 위치 관계를 나타내는 것은 아니다. 즉, 관찰하는 위치에 따라, '상부'와 '하부' 또는 '상면'과 '하면'의 위치가 서로 변경될 수 있다. Positional relationships such as 'top', 'top', 'bottom', and 'bottom' are described based on the drawings and do not represent absolute positional relationships. That is, the positions of the 'top' and 'bottom' or 'top' and 'bottom' may be changed depending on the position to be observed.
반도체 밀봉 부재Semiconductor sealing member
먼저, 본 발명에 따른 반도체 밀봉 부재에 대해 설명한다. First, the semiconductor sealing member which concerns on this invention is demonstrated.
도 1 및 도 2에는 본 발명에 따른 반도체 밀봉 부재의 실시예들이 도시되어 있다. 도 1 및 도 2에 도시된 바와 같이, 본 발명에 따른 반도체 밀봉 부재는 유리 직물로 이루어진 제1층(10), 상기 제1층의 상부에 형성되는 제2층(20) 및 상기 제1층의 하부에 형성되는 제3층(30)을 포함한다. 1 and 2 illustrate embodiments of a semiconductor sealing member according to the present invention. 1 and 2, the semiconductor sealing member according to the present invention includes a first layer 10 made of glass fabric, a second layer 20 formed on top of the first layer, and the first layer. The third layer 30 is formed at the bottom of the.
상기 유리 직물은 유리 섬유(12)들이 직조되어 형성되는 직물로, 상기 유리 직물을 구성하는 유리 섬유의 재질은 특별히 제한되지 않는다. 예를 들면, 상기 유리 직물은 E유리, C유리, A유리, S유리, D유리, NE유리, T유리, H유리 등으로 형성될 수 있으며, 이들 중에서도 E유리 또는 S유리가 특히 바람직하다. The glass fabric is a fabric formed by weaving the glass fibers 12, and the material of the glass fibers constituting the glass fabric is not particularly limited. For example, the glass fabric may be formed of E glass, C glass, A glass, S glass, D glass, NE glass, T glass, H glass, and the like, of which E glass or S glass is particularly preferable.
상기 유리 직물의 두께는 구체적으로 10㎛ 내지 50㎛, 보다 구체적으로 15㎛ 내지 35㎛, 예를 들면 15㎛, 16㎛, 17㎛, 18㎛, 19㎛, 20㎛, 21㎛, 22㎛, 23㎛, 24㎛, 25㎛, 26㎛, 27㎛, 28㎛, 29㎛, 30㎛, 31㎛, 32㎛, 33㎛, 34㎛, 35㎛ 일 수 있다. 상기 범위에서, 필름형 반도체 밀봉 부재의 제작이 용이하다. The thickness of the glass fabric is specifically 10 μm to 50 μm, more specifically 15 μm to 35 μm, for example 15 μm, 16 μm, 17 μm, 18 μm, 19 μm, 20 μm, 21 μm, 22 μm, 23 μm, 24 μm, 25 μm, 26 μm, 27 μm, 28 μm, 29 μm, 30 μm, 31 μm, 32 μm, 33 μm, 34 μm, 35 μm. In the above range, the production of a film-type semiconductor sealing member is easy.
다음으로, 상기 제2층(20)은 유리 직물로 이루어진 제1층(10)의 상부에 형성되며, 제1에폭시 수지(24)와 제1무기 충전제(22)를 포함하는 제1에폭시 수지 조성물에 의해 형성된다. Next, the second layer 20 is formed on top of the first layer 10 made of glass fabric, the first epoxy resin composition comprising a first epoxy resin 24 and the first inorganic filler 22 Is formed by.
상기 제1에폭시 수지(24)로는 2개 이상의 에폭시기를 포함하는 에폭시 수지가 사용될 수 있으며, 특별히 제한되지 않는다. 예를 들면, 상기 제1에폭시 수지(24)는, 페놀 또는 알킬 페놀류와 히드록시벤즈알데히드와의 축합물을 에폭시화함으로써 얻어지는 에폭시 수지, 페놀노볼락형 에폭시 수지, 크레졸노볼락형 에폭시 수지, 다관능형 에폭시 수지, 나프톨노볼락형 에폭시 수지, 비스페놀Ａ/비스페놀F/비스페놀AD의 노볼락형 에폭시 수지, 비스페놀Ａ/비스페놀F/비스페놀AD의 글리시딜에테르, 비스히드록시비페닐계 에폭시 수지, 디시클로펜타디엔계 에폭시 수지 등을 들 수 있다. 구체적으로, 상기 에폭시 수지는 크레졸노볼락형 에폭시 수지, 다관능형 에폭시 수지, 페놀아랄킬형 에폭시 수지, 바이페닐형 에폭시 수지 등일 수 있다. As the first epoxy resin 24, an epoxy resin including two or more epoxy groups may be used, and is not particularly limited. For example, the first epoxy resin 24 is an epoxy resin obtained by epoxidizing a condensate of phenol or alkyl phenols with hydroxybenzaldehyde, a phenol novolak type epoxy resin, a cresol novolak type epoxy resin, and a polyfunctional type. Epoxy resin, naphthol novolac type epoxy resin, novolak type epoxy resin of bisphenol A / bisphenol F / bisphenol AD, glycidyl ether of bisphenol A / bisphenol F / bisphenol AD, bishydroxy biphenyl epoxy resin, dicyclo Pentadiene type epoxy resin etc. are mentioned. Specifically, the epoxy resin may be a cresol novolac type epoxy resin, a polyfunctional epoxy resin, a phenol aralkyl type epoxy resin, a biphenyl type epoxy resin, or the like.
한편, 상기 제1무기충전제(22)로는 반도체 밀봉재에 사용되는 일반적인 무기 충전제들이 제한 없이 사용될 수 있으며, 특별히 한정되지 않는다. 예를 들면, 상기 제1무기충전제로는 실리카, 탄산칼슘, 탄산마그네슘, 알루미나, 세리아, 마그네시아, 클레이(clay), 탈크(talc), 규산칼슘, 산화티탄, 산화안티몬, 유리섬유 등이 사용될 수 있다. 이들은 단독 또는 혼합하여 사용될 수 있다. 이 중에서도 실리카가 특히 바람직하다. Meanwhile, as the first inorganic filler 22, general inorganic fillers used in a semiconductor sealing material may be used without limitation, and are not particularly limited. For example, silica, calcium carbonate, magnesium carbonate, alumina, ceria, magnesia, clay, talc, calcium silicate, titanium oxide, antimony oxide, glass fiber, etc. may be used as the first inorganic filler. have. These may be used alone or in combination. Among these, silica is particularly preferable.
한편, 상기 제1무기충전제는 최대 입경이 구체적으로 상기 유리 직물의 공극 면적의 1/2 이하, 보다 구체적으로 유리 직물의 공극 면적의 1/3 이하인 것이 바람직하다. 제1무기 충전제의 최대 입경이 유리 직물의 공극 면적의 1/2를 초과하는 경우에, 제1무기 충전제에 의해 유리 직물의 공극이 막혀 성형 시 유동성이 떨어질 수 있기 때문이다. On the other hand, the first inorganic filler is preferably a maximum particle size of less than 1/2 of the pore area of the glass fabric, more specifically 1/3 or less of the pore area of the glass fabric. This is because when the maximum particle diameter of the first inorganic filler exceeds 1/2 of the pore area of the glass fabric, the voids of the glass fabric are blocked by the first inorganic filler, which may result in poor fluidity during molding.
구체적으로, 상기 제1무기 충전제는 최대 입경이 구체적으로 0.5㎛ 내지 20㎛, 보다 구체적으로 1㎛ 내지 10㎛, 예를 들면 1㎛, 2㎛, 3㎛, 4㎛, 5㎛, 6㎛, 7㎛, 8㎛, 9㎛, 10㎛일 수 있다. Specifically, the first inorganic filler has a maximum particle diameter of specifically 0.5 μm to 20 μm, more specifically 1 μm to 10 μm, for example 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm.
한편, 상기 제2층(20)은 제1에폭시 수지(24)를 구체적으로 5중량% 내지 99중량%, 보다 구체적으로 5중량% 내지 80중량%, 보다 더 구체적으로 15중량% 내지 70중량%, 예를 들면 25중량% 내지 60중량%, 25중량%, 30중량%, 35중량%, 40중량%, 45중량%, 50중량%, 55중량%, 60중량%로 포함하고, 상기 제1무기 충전제(22)를 구체적으로 1중량% 내지 95중량%, 보다 구체적으로 1중량% 내지 85중량%, 보다 더 구체적으로 5중량% 내지 70중량%, 예를 들면 10중량% 내지 50중량%, 10중량%, 15중량%, 20중량%, 25중량%, 30중량%, 35중량%, 40중량%, 45중량%, 50중량%로 포함할 수 있다. 상기 범위에서 반도체 밀봉 부재의 유동성 및 기계적 물성을 적절하게 확보할 수 있다. On the other hand, the second layer 20 is specifically 5 wt% to 99 wt%, more specifically 5 wt% to 80 wt%, even more specifically 15 wt% to 70 wt% of the first epoxy resin 24 For example, 25 wt% to 60 wt%, 25 wt%, 30 wt%, 35 wt%, 40 wt%, 45 wt%, 50 wt%, 55 wt%, 60 wt%, and the first The inorganic filler 22 is specifically 1% to 95% by weight, more specifically 1% to 85% by weight, even more specifically 5% to 70% by weight, for example 10% to 50% by weight, 10 wt%, 15 wt%, 20 wt%, 25 wt%, 30 wt%, 35 wt%, 40 wt%, 45 wt%, and 50 wt%. Within this range, fluidity and mechanical properties of the semiconductor sealing member can be properly secured.
상기 제2층(20)은 그 두께가 구체적으로 5㎛ 내지 40㎛, 보다 구체적으로 10㎛ 내지 30㎛, 예를 들면 10㎛, 11㎛, 12㎛, 13㎛, 14㎛, 15㎛, 16㎛, 17㎛, 18㎛, 19㎛, 20㎛, 21㎛, 22㎛, 23㎛, 24㎛, 25㎛, 26㎛, 27㎛, 28㎛, 29㎛, 30㎛일 수 있다. The thickness of the second layer 20 is specifically 5 μm to 40 μm, more specifically 10 μm to 30 μm, for example, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 Micrometer, 17 μm, 18 μm, 19 μm, 20 μm, 21 μm, 22 μm, 23 μm, 24 μm, 25 μm, 26 μm, 27 μm, 28 μm, 29 μm, 30 μm.
다음으로, 상기 제3층(30)은 유리 직물로 이루어진 제1층(10)의 하부에 형성되며, 제2에폭시 수지(34)와 제2무기 충전제(32)를 포함하는 제2에폭시 수지 조성물에 의해 형성된다. Next, the third layer 30 is formed on the lower portion of the first layer 10 made of glass fabric, the second epoxy resin composition comprising a second epoxy resin 34 and the second inorganic filler 32 Is formed by.
상기 제2에폭시 수지(34)로는 2개 이상의 에폭시기를 포함하는 에폭시 수지가 사용될 수 있으며, 특별히 제한되지 않는다. 예를 들면, 상기 제2에폭시 수지(34)는, 페놀 또는 알킬 페놀류와 히드록시벤즈알데히드와의 축합물을 에폭시화함으로써 얻어지는 에폭시 수지, 페놀노볼락형 에폭시 수지, 크레졸노볼락형 에폭시 수지, 다관능형 에폭시 수지, 나프톨노볼락형 에폭시 수지, 비스페놀Ａ/비스페놀F/비스페놀AD의 노볼락형 에폭시 수지, 비스페놀Ａ/비스페놀F/비스페놀AD의 글리시딜에테르, 비스히드록시비페닐계 에폭시 수지, 디시클로펜타디엔계 에폭시 수지 등을 들 수 있다. 구체적으로, 상기 에폭시 수지는 크레졸노볼락형 에폭시 수지, 다관능형 에폭시 수지, 페놀아랄킬형 에폭시 수지, 바이페닐형 에폭시 수지 등일 수 있다. As the second epoxy resin 34, an epoxy resin including two or more epoxy groups may be used, and is not particularly limited. For example, the second epoxy resin 34 is an epoxy resin obtained by epoxidizing a condensate of phenol or alkyl phenols with hydroxybenzaldehyde, a phenol novolak type epoxy resin, a cresol novolak type epoxy resin, and a polyfunctional type. Epoxy resin, naphthol novolac type epoxy resin, novolak type epoxy resin of bisphenol A / bisphenol F / bisphenol AD, glycidyl ether of bisphenol A / bisphenol F / bisphenol AD, bishydroxy biphenyl epoxy resin, dicyclo Pentadiene type epoxy resin etc. are mentioned. Specifically, the epoxy resin may be a cresol novolac type epoxy resin, a polyfunctional epoxy resin, a phenol aralkyl type epoxy resin, a biphenyl type epoxy resin, or the like.
상기 제2에폭시 수지(34)는 상기 제1에폭시 수지(24)와 동일하거나 상이할 수 있다. The second epoxy resin 34 may be the same as or different from the first epoxy resin 24.
또한, 상기 제2에폭시 수지(34)는 상이한 2종 이상의 수지를 포함할 수 있다. 제2에폭시 수지(34)가 2종 이상의 에폭시 수지를 포함할 경우, 상기 에폭시 수지는 서로 다른 영역에 존재할 수 있다. 예를 들면, 상기 제3층은 상기 제2층을 형성하는 제1에폭시 수지와 동일한 에폭시 수지와 상기 제1에폭시 수지와 상이한 에폭시 수지를 포함할 수 있으며, 이 경우, 제1에폭시 수지와 동일한 에폭시 수지가 제3층의 상부, 즉, 유리 직물에 근접한 영역에 배치되고, 상기 제1에폭시 수지와 상이한 에폭시 수지는 제3층의 하부에 배치될 수 있다. In addition, the second epoxy resin 34 may include two or more different resins. When the second epoxy resin 34 includes two or more epoxy resins, the epoxy resins may be present in different regions. For example, the third layer may include the same epoxy resin as the first epoxy resin forming the second layer and an epoxy resin different from the first epoxy resin, and in this case, the same epoxy as the first epoxy resin. The resin may be disposed at the top of the third layer, that is, in the region proximate the glass fabric, and an epoxy resin different from the first epoxy resin may be disposed at the bottom of the third layer.
한편, 상기 제2무기충전제(32)는 반도체 밀봉재에 사용되는 일반적인 무기 충전제들이 제한 없이 사용될 수 있으며, 특별히 한정되지 않는다. 예를 들면, 상기 제1무기충전제로는 실리카, 탄산칼슘, 탄산마그네슘, 알루미나, 세리아, 마그네시아, 클레이(clay), 탈크(talc), 규산칼슘, 산화티탄, 산화안티몬, 유리섬유 등이 사용될 수 있다. 이들은 단독 또는 혼합하여 사용될 수 있다. 이 중에서도 실리카가 특히 바람직하다.  On the other hand, the second inorganic filler 32 may be used without limitation, general inorganic fillers used in the semiconductor sealing material, it is not particularly limited. For example, silica, calcium carbonate, magnesium carbonate, alumina, ceria, magnesia, clay, talc, calcium silicate, titanium oxide, antimony oxide, glass fiber, etc. may be used as the first inorganic filler. have. These may be used alone or in combination. Among these, silica is particularly preferable.
한편, 상기 제2무기충전제(32)의 최대 입경은 구체적으로 상기 제3층(30)의 두께의 1/2 이하, 보다 구체적으로 1/3 이하일 수 있다. 제2무기 충전제의 최대 입경이 제3층의 두께의 1/2를 초과할 경우, 성형성 및 충진성이 저하될 수 있다. On the other hand, the maximum particle diameter of the second inorganic filler 32 may be specifically 1/2 or less, more specifically 1/3 or less of the thickness of the third layer 30. If the maximum particle diameter of the second inorganic filler exceeds 1/2 of the thickness of the third layer, moldability and fillability may be degraded.
구체적으로, 상기 제2무기 충전제는 최대 입경이 구체적으로 0.5㎛ 내지 60㎛, 보다 구체적으로 1㎛ 내지 30㎛, 예를 들면 1㎛, 2㎛, 3㎛, 4㎛, 5㎛, 6㎛, 7㎛, 8㎛, 9㎛, 10㎛, 11㎛, 12㎛, 13㎛, 14㎛, 15㎛, 16㎛, 17㎛, 18㎛, 19㎛, 20㎛, 21㎛, 22㎛, 23㎛, 24㎛, 25㎛, 26㎛, 27㎛, 28㎛, 29㎛, 30㎛일 수 있다. Specifically, the second inorganic filler has a maximum particle diameter of 0.5 μm to 60 μm, more specifically 1 μm to 30 μm, for example, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm, 20 μm, 21 μm, 22 μm, 23 μm , 24 μm, 25 μm, 26 μm, 27 μm, 28 μm, 29 μm, 30 μm.
한편, 상기 제1무기 충전제와 제2무기 충전제의 최대 입경은 서로 동일하거나 상이할 수 있다. On the other hand, the maximum particle diameter of the first inorganic filler and the second inorganic filler may be the same or different from each other.
또한, 상기 제3층(30)은 제2에폭시 수지(34)를 구체적으로 5중량% 내지 99중량%, 보다 구체적으로 5중량% 내지 80중량%, 보다 더 구체적으로 15중량% 내지 70중량%, 예를 들면 25중량% 내지 60중량%, 25중량%, 30중량%, 35중량%, 40중량%, 45중량%, 50중량%, 55중량%, 60중량%로 포함하고, 상기 제2무기 충전제(32)를 구체적으로 1중량% 내지 95중량%, 보다 구체적으로 1중량% 내지 85중량%, 보다 더 구체적으로 5중량% 내지 70중량%, 예를 들면 10중량% 내지 50중량%, 10중량%, 15중량%, 20중량%, 25중량%, 30중량%, 35중량%, 40중량%, 45중량%, 50중량%로 포함할 수 있다. 상기 범위에서 성형성이 우수한 효과가 있다. In addition, the third layer 30 is specifically 5 wt% to 99 wt%, more specifically 5 wt% to 80 wt%, and more specifically 15 wt% to 70 wt% of the second epoxy resin 34. For example, 25 wt% to 60 wt%, 25 wt%, 30 wt%, 35 wt%, 40 wt%, 45 wt%, 50 wt%, 55 wt%, 60 wt%, and the second The inorganic filler 32 is specifically 1% to 95% by weight, more specifically 1% to 85% by weight, even more specifically 5% to 70% by weight, for example 10% to 50% by weight, 10 wt%, 15 wt%, 20 wt%, 25 wt%, 30 wt%, 35 wt%, 40 wt%, 45 wt%, and 50 wt%. There is an effect excellent in moldability in the above range.
한편, 본 발명에 있어서, 상기 제3층(30)은 그 두께가 상기 제2층(20)에 비해 두껍게 형성된다. 구체적으로 상기 제3층(30)의 두께가 제2층(20)의 두께의 2배 이상, 보다 구체적으로 2배 내지 5배일 수 있다. 본 발명과 같이 유리 직물의 하부에 형성되는 층을 두껍게 형성할 경우, 성형 시에 반도체 칩의 손상을 최소화할 수 있으며, 밀봉 부재의 유동성이 향상되어 내로우 갭 필링 특성이 향상된다. On the other hand, in the present invention, the third layer 30 is formed thicker than the second layer 20. Specifically, the thickness of the third layer 30 may be two times or more, more specifically, two to five times the thickness of the second layer 20. When the thick layer formed on the lower portion of the glass fabric as in the present invention, it is possible to minimize the damage of the semiconductor chip during the molding, the fluidity of the sealing member is improved to improve the narrow gap filling characteristics.
구체적으로, 상기 제3층(30)은 그 두께가 10㎛ 내지 425㎛, 보다 구체적으로 20㎛ 내지 425㎛, 보다 더 구체적으로 40㎛ 내지 210㎛, 예를 들면 50㎛ 내지 150㎛, 50㎛, 55㎛, 60㎛, 65㎛, 70㎛, 75㎛, 80㎛, 85㎛, 90㎛, 95㎛, 100㎛, 105㎛, 110㎛, 115㎛, 120㎛, 125㎛, 130㎛, 135㎛, 140㎛, 145㎛, 150㎛일 수 있다. 제3층의 두께가 상기 범위를 만족할 경우, 우수한 유동성 및 패키지 충전성을 확보할 수 있다. Specifically, the third layer 30 has a thickness of 10 μm to 425 μm, more specifically 20 μm to 425 μm, even more specifically 40 μm to 210 μm, for example, 50 μm to 150 μm, 50 μm. , 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm, 100 μm, 105 μm, 110 μm, 115 μm, 120 μm, 125 μm, 130 μm, 135 Micrometer, 140 micrometer, 145 micrometer, 150 micrometer. When the thickness of the third layer satisfies the above range, excellent fluidity and package filling property can be ensured.
한편, 상기 제3층(30)은 도 1에 도시된 바와 같이, 최대 입경이 동일한 1종의 무기 충전제를 포함할 수도 있고, 도 2에 도시된 바와 같이, 최대 입경이 상이한 2종 이상의 무기 충전제를 포함할 수도 있다. Meanwhile, as shown in FIG. 1, the third layer 30 may include one type of inorganic filler having the same maximum particle diameter, and as shown in FIG. 2, two or more types of inorganic fillers having different maximum particle diameters may be used. It may also include.
상기 제3층이 크기가 상이한 2종 이상의 무기 충전제를 포함할 경우에, 상기 제3층은 최대 입경이 큰 무기 충전제들이 분포하는 제1영역(30a) 및 최대 입경이 작은 무기 충전제들이 분포한 제2영역(30b)으로 구분될 수 있다. 도 2에는 최대 입경이 큰 무기 충전제들이 제3층의 하부에 위치하는 것으로 도시되어 있으나, 이에 한정되는 것은 아니며, 크기가 큰 무기 충전제들이 제3층의 상부에 위치하고, 크기가 작은 무기 충전제들이 제3층의 하부에 위치할 수도 있다. When the third layer includes two or more kinds of inorganic fillers having different sizes, the third layer is formed of a first region 30a in which inorganic fillers having a large maximum particle size are distributed and an inorganic filler having a small maximum particle diameter is distributed. It may be divided into two regions 30b. In FIG. 2, the inorganic fillers having the largest particle diameters are shown below the third layer. However, the present invention is not limited thereto. It may be located at the bottom of the third floor.
한편, 상기 제1영역(30a) 및 제2영역(30b)의 매트릭스가 되는 에폭시 수지는 서로 동일하거나 상이할 수 있다. 예를 들면, 상기 제1영역(30a)에는 제2층의 제1에폭시 수지와 동일한 에폭시 수지가 포함되고, 상기 제2영역(30b)에는 제1에폭시 수지와 상이한 에폭시 수지가 포함될 수 있다. Meanwhile, the epoxy resins forming the matrix of the first region 30a and the second region 30b may be the same or different from each other. For example, the first region 30a may include the same epoxy resin as the first epoxy resin of the second layer, and the second region 30b may include an epoxy resin different from the first epoxy resin.
한편, 상기 제2층(20) 및 제3층(30)을 형성하는 제1에폭시 수지 조성물 및 제2에폭시 수지 조성물은, 상기한 에폭시 수지 및 무기 충전제 이외에, 경화제, 경화촉진제, 커플링제, 이형제 및 착색제 등을 더 포함할 수 있다. On the other hand, the first epoxy resin composition and the second epoxy resin composition forming the second layer 20 and the third layer 30 include a curing agent, a curing accelerator, a coupling agent, and a release agent in addition to the epoxy resin and the inorganic filler. And colorants.
이때, 상기 경화제로는 반도체 밀봉 부재에 일반적으로 사용되는 경화제들이 제한 없이 사용될 수 있으며, 예를 들면, 페놀아랄킬형 페놀수지,　페놀노볼락형 페놀수지, 자일록(xylok)형 페놀수지, 크레졸 노볼락형 페놀수지, 나프톨형 페놀수지, 테르펜형 페놀수지, 다관능형 페놀수지, 디시클로펜타디엔계 페놀수지, 비스페놀 A와 레졸로부터 합성된 노볼락형　페놀수지, 트리스(하이드록시페닐)메탄, 디하이드록시바이페닐을 포함하는 다가 페놀 화합물, 무수 말레인산　및　무수　프탈산을 포함하는 산무수물, 메타페닐렌디아민, 디아미노디페닐메탄, 디아미노디페닐설폰　등의 방향족 아민　등이 사용될 수 있으나, 이에 한정되는 것은 아니다. In this case, as the curing agent, curing agents generally used in semiconductor sealing members may be used without limitation. For example, phenol aralkyl type phenol resins, phenol novolac type phenol resins, xylok type phenol resins, cresol furnaces Volacic Phenolic Resin, Naphthol Phenolic Resin, Terpene Phenolic Resin, Multifunctional Phenolic Resin, Dicyclopentadiene Phenolic Resin, Novolac-type Phenolic Resin Synthesized from Bisphenol A and Resol, Tris (hydroxyphenyl) methane, Di Polyhydric phenol compounds containing hydroxybiphenyl, acid anhydrides containing maleic anhydride and phthalic anhydride, aromatic amines such as metaphenylenediamine, diaminodiphenylmethane, diaminodiphenylsulfone, and the like, may be used. It doesn't happen.
상기 경화제는 포함되는 에폭시 수지 조성물의 총 중량에 대하여, 구체적으로 1중량% 내지 40중량%, 보다 구체적으로 3중량% 내지 35중량%, 예를 들면, 3중량%, 4중량%, 5중량%, 6중량%, 7중량%, 8중량%, 9중량%, 10중량%, 11중량%, 12중량%, 13중량%, 14중량%, 15중량%, 16중량%, 17중량%, 18중량%, 19중량%, 20중량%, 21중량%, 22중량%, 23중량%, 24중량%, 25중량%, 26중량%, 27중량%, 28중량%, 29중량%, 30중량%, 31중량%, 32중량%, 33중량%, 34중량%, 35중량%로 포함될 수 있다. The curing agent is specifically 1% to 40% by weight, more specifically 3% to 35% by weight, for example, 3% by weight, 4% by weight, 5% by weight relative to the total weight of the epoxy resin composition included , 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18 Wt%, 19 wt%, 20 wt%, 21 wt%, 22 wt%, 23 wt%, 24 wt%, 25 wt%, 26 wt%, 27 wt%, 28 wt%, 29 wt%, 30 wt% , 31%, 32%, 33%, 34%, 35% by weight.
상기 경화 촉진제는 에폭시 수지와 경화제의 반응을 촉진하기 위한 것으로, 예를 들면, 3급 아민, 유기금속화합물, 유기인화합물, 이미다졸, 및 붕소화합물 등이 사용 가능하다. 3급 아민에는 벤질디메틸아민, 트리에탄올아민, 트리에틸렌디아민, 디에틸아미노에탄올, 트리(디메틸아미노메틸)페놀, 2-2-(디메틸아미노메틸)페놀, 2,4,6-트리스(디아미노메틸)페놀과 트리-2-에틸헥실산염 등이 사용될 수 있다. 경화 촉진제의 사용량은 에폭시 수지 조성물 총 중량에 대하여 구체적으로　0.01중량% 내지 2중량% 정도일 수 있으며, 보다 구체적으로 0.02중량% 내지 1.5중량% 정도, 보다 더 구체적으로 0.05중량% 내지 1중량% 정도, 예를 들면 0.05중량%, 0.1중량%, 0.2중량%, 0.3중량%, 0.4중량%, 0.5중량%, 0.6중량%, 0.7중량%, 0.8중량%, 0.9중량%, 1중량%일 수 있다.　상기의 범위에서 에폭시 수지 조성물의 경화를 촉진하고 또한, 경화도도 좋은 장점이 있다.The curing accelerator is for promoting the reaction between the epoxy resin and the curing agent, for example, tertiary amines, organometallic compounds, organophosphorus compounds, imidazole, boron compounds and the like can be used. Tertiary amines include benzyldimethylamine, triethanolamine, triethylenediamine, diethylaminoethanol, tri (dimethylaminomethyl) phenol, 2-2- (dimethylaminomethyl) phenol, 2,4,6-tris (diaminomethyl ) Phenol and tri-2-ethylhexyl acid salt and the like can be used. The amount of the curing accelerator may be specifically about 0.01% to 2% by weight, more specifically about 0.02% to 1.5% by weight, more specifically about 0.05% to 1% by weight, based on the total weight of the epoxy resin composition. For example, it may be 0.05%, 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1% by weight. In the above range, there is an advantage that the curing of the epoxy resin composition is promoted and the degree of curing is also good.
상기 커플링제는 에폭시 수지와 무기 충전제 사이에서 반응하여 계면 강도를 향상시키기 위한 것으로, 예를 들면, 실란 커플링제일 수 있다. 상기 실란 커플링제는 에폭시 수지와 무기 충전제 사이에서 반응하여, 에폭시 수지와 무기 충전제의 계면 강도를 향상시키는 것이면 되고, 그 종류가 특별히 한정되지 않는다. 상기 실란 커플링제의 구체적인 예로는 에폭시실란, 아미노실란, 우레이도실란, 머캅토실란 등을 들 수 있다. 상기 커플링제는 단독으로 사용할 수 있으며 병용해서 사용할 수도 있다.The coupling agent is for improving the interfacial strength by reacting between the epoxy resin and the inorganic filler. For example, the coupling agent may be a silane coupling agent. The said silane coupling agent may react between an epoxy resin and an inorganic filler, and what is necessary is just to improve the interface strength of an epoxy resin and an inorganic filler, The kind is not specifically limited. Specific examples of the silane coupling agent include epoxysilane, aminosilane, ureidosilane, mercaptosilane, and the like. The coupling agents may be used alone or in combination.
상기 커플링제는 에폭시 수지 조성물 총 중량에 대해 구체적으로 0.01중량% 내지 5중량% 정도, 보다 구체적으로 0.05중량% 내지 3중량% 정도, 보다 더 구체적으로 0.1중량% 내지 2 중량% 정도, 예를 들면, 0.1중량%, 0.2중량%, 0.3중량%, 0.4중량%, 0.5중량%, 0.6중량%, 0.7중량%, 0.8중량%, 0.9중량%, 1중량%, 1.1중량%, 1.2중량%, 1.3중량%, 1.4중량%, 1.5중량%, 1.6중량%, 1.7중량%, 1.8중량%, 1.9중량%, 2중량%의 함량으로 포함될 수 있다. 상기 범위에서 에폭시 수지 조성물 경화물의 강도가 향상된다.The coupling agent is specifically about 0.01% to 5% by weight, more specifically about 0.05% to 3% by weight, even more specifically about 0.1% to 2% by weight relative to the total weight of the epoxy resin composition, for example , 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1%, 1.1%, 1.2%, 1.3 It may be included in the content of wt%, 1.4 wt%, 1.5 wt%, 1.6 wt%, 1.7 wt%, 1.8 wt%, 1.9 wt%, 2 wt%. In the above range, the strength of the cured epoxy resin composition is improved.
상기 이형제로는 파라핀계 왁스, 에스테르계 왁스, 고급 지방산, 고급 지방산 금속염, 천연 지방산 및 천연 지방산 금속염으로 이루어진 군으로부터 선택되는 1종 이상을 사용할 수 있다. The release agent may be used at least one selected from the group consisting of paraffin wax, ester wax, higher fatty acid, higher fatty acid metal salt, natural fatty acid and natural fatty acid metal salt.
상기 이형제는 에폭시수지 조성물 중 구체적으로 0.1중량% 내지 1중량%, 예를 들면 0.1중량%, 0.2중량%, 0.3중량%, 0.4중량%, 0.5중량%, 0.6중량%, 0.7중량%, 0.8중량%, 0.9중량%, 1중량%로 포함될 수 있다.The release agent is specifically 0.1% to 1% by weight, for example 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, 0.8% by weight of the epoxy resin composition %, 0.9% by weight, may be included in 1% by weight.
상기 착색제는 반도체 소자 밀봉재의 레이저 마킹을 위한 것으로, 당해 기술 분야에 잘 알려져 있는 착색제들이 사용될 수 있으며, 특별히 제한되지 않는다. 예를 들면, 상기 착색제는 카본 블랙, 티탄블랙, 티탄 질화물, 인산수산화구리(dicopper hydroxide phosphate), 철산화물, 운모 중 하나 이상을 포함할 수 있다. The colorant is for laser marking of the semiconductor device sealant, and colorants well known in the art may be used, and are not particularly limited. For example, the colorant may include one or more of carbon black, titanium black, titanium nitride, copper hydroxide phosphate, iron oxide, and mica.
상기 착색제는 에폭시 수지 조성물 총 중량에 대해 구체적으로 0.01중량% 내지 5중량% 정도, 보다 구체적으로 0.05중량% 내지 3중량% 정도, 보다 더 구체적으로 0.1중량% 내지 2중량% 정도, 예를 들면, 0.1중량%, 0.2중량%, 0.3중량%, 0.4중량%, 0.5중량%, 0.6중량%, 0.7중량%, 0.8중량%, 0.9중량%, 1중량%, 1.1중량%, 1.2중량%, 1.3중량%, 1.4중량%, 1.5중량%, 1.6중량%, 1.7중량%, 1.8중량%, 1.9중량%, 2중량%의 함량으로 포함될 수 있다. The colorant is specifically about 0.01% to 5% by weight, more specifically about 0.05% to 3% by weight, and even more specifically about 0.1% to 2% by weight relative to the total weight of the epoxy resin composition, for example, 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1%, 1.1%, 1.2%, 1.3% It may be included in the content of%, 1.4% by weight, 1.5% by weight, 1.6% by weight, 1.7% by weight, 1.8% by weight, 1.9% by weight, 2% by weight.
이외에도, 본 발명의 에폭시 수지 조성물은　본 발명의 목적을 해하지 않는 범위에서 변성 실리콘 오일, 실리콘 파우더, 및 실리콘 레진 등의 응력완화제; Tetrakis[methylene-3-(3,5-di-tertbutyl-4-hydroxyphenyl)propionate]methane 등의 산화방지제; 등을　필요에 따라 추가로 함유할 수 있다.In addition, the epoxy resin composition of the present invention may be selected from the group consisting of stress relieving agents such as modified silicone oil, silicone powder, and silicone resin within the scope of not impairing the object of the present invention; Antioxidants such as Tetrakis [methylene-3- (3,5-di-tertbutyl-4-hydroxyphenyl) propionate] methane; And the like may be further added as necessary.
상기와 같은 본 발명에 따른 반도체 밀봉 부재는, 예를 들면, 제1이형 필름 상에 유리 직물을 배치한 후 상기 유리 직물 상에 제1에폭시 수지 조성물을 코팅하고, 건조시켜 제1필름을 형성하고, 제2이형 필름 상에 제2에폭시 수지 조성물을 코팅하고, 건조시켜 제2필름을 형성한 후, 상기 제1필름과 제2필름을 합지하는 방법으로 제조될 수 있다. 이때, 상기 합지는, 예를 들면, 접착제나 점착제와 같은 접착 부재를 이용하여 수행될 수도 있고, 압력이나 온도를 가해 제1필름과 제2필름을 라미네이션하는 방법으로 수행될 수도 있다. The semiconductor sealing member according to the present invention as described above, for example, after placing the glass fabric on the first release film, coating the first epoxy resin composition on the glass fabric, dried to form a first film After coating the second epoxy resin composition on the second release film and drying to form a second film, it may be prepared by a method of laminating the first film and the second film. In this case, the lamination may be performed by using an adhesive member such as an adhesive or an adhesive, or may be performed by laminating the first film and the second film by applying pressure or temperature.
상기와 같은 방법을 통해 제조된 본 발명의 반도체 밀봉 부재는 필름 형태를 가지기 때문에 웨이퍼 레벨 패키징 또는 패널 레벨 패키징과 같은 대면적 공정에 유용하게 사용될 수 있다. Since the semiconductor sealing member of the present invention manufactured by the above method has a film form, it can be usefully used in a large area process such as wafer level packaging or panel level packaging.
또한, 본 발명에 따른 반도체 밀봉 부재는 유리 직물을 포함하기 때문에 높은 강성을 가져 신뢰성이 높은 반도체 패키지를 제조할 수 있다.In addition, since the semiconductor sealing member according to the present invention includes a glass fabric, it is possible to manufacture a semiconductor package having high rigidity and high reliability.
또한, 본 발명에 따른 반도체 밀봉 부재는 유리 직물의 하부에 형성되는 제3층을 두껍게 형성함으로써, 밀봉 성형 시에 우수한 유동성, 성형성, 단차 매립성 및 충진성을 나타낸다. Further, the semiconductor sealing member according to the present invention forms a thick third layer formed under the glass fabric, thereby exhibiting excellent fluidity, formability, step embedding and filling properties in sealing molding.
반도체 패키지 제조방법Semiconductor Package Manufacturing Method
다음으로, 본 발명에 따른 반도체 패키지 제조방법에 대해 설명한다. Next, a method of manufacturing a semiconductor package according to the present invention will be described.
본 발명에 따른 반도체 패키지 제조 방법은 상기한 본 발명에 따른 필름형 반도체 밀봉 부재를 이용하여 반도체 소자를 밀봉하는 단계를 포함하는 것을 그 특징으로 한다. The method of manufacturing a semiconductor package according to the present invention is characterized by including the step of sealing the semiconductor device using the film-type semiconductor sealing member according to the present invention.
이때, 상기 밀봉은, 당해 기술 분야에서 일반적으로 사용되는 반도체 밀봉 방법들, 예를 들면, 컴프레션 몰딩(Compression Molding)법, 또는 라미네이션(Lamination)법 등에 의해 수행될 수 있다. In this case, the sealing may be performed by semiconductor sealing methods generally used in the art, for example, a compression molding method or a lamination method.
일 구체예에서, 상기 반도체 패키지 제조 방법은, 웨이퍼 레벨 패키징 또는 패널 레벨 패키징 후 재배선층을 형성하는 방법에 의해 이루어질 수 있다. 구체적으로, 다음과 같은 방법을 통해 반도체 패키지를 제조할 수 있다.In one embodiment, the semiconductor package manufacturing method may be performed by a method for forming a redistribution layer after wafer level packaging or panel level packaging. Specifically, the semiconductor package may be manufactured by the following method.
먼저, 캐리어 웨이퍼 또는 캐리어 패널와 같은 캐리어 부재의 일면에 점착 테이프(Adhesive Tape) 또는 열 이형 테이프(Thermal release Tape)와 같은 임시 고정 부재를 부착하여, 일면에 임시 고정 부재가 부착된 캐리어 부재를 준비한다.First, a temporary fixing member such as an adhesive tape or a thermal release tape is attached to one surface of a carrier member such as a carrier wafer or a carrier panel to prepare a carrier member having a temporary fixing member attached to one surface. .
그런 다음, 픽-앤드-플레이스(pick-and-place)와 같은 공정을 이용하여, 상기 임시 고정 부재 상에 다수의 반도체 칩을 재배열(Reconfiguration)시킨다. Then, using a process such as pick-and-place, a plurality of semiconductor chips are rearranged on the temporary fixing member.
반도체칩들의 재배열이 완료되면, 상기한 본 발명의 필름형 반도체 밀봉 부재를 상기 반도체 칩 상에 배치한 후, 컴프레션 또는 라미네이션 등의 방법으로 성형하여 밀봉층을 형성한다. 이때, 상기 성형 온도는 밀봉 부재의 종류에 따라 달라질 수 있으나, 대체로 120℃ 내지 170℃ 정도에서 수행될 수 있다. When the rearrangement of the semiconductor chips is completed, the film-type semiconductor sealing member of the present invention is disposed on the semiconductor chip, and then molded by a method such as compression or lamination to form a sealing layer. In this case, the molding temperature may vary depending on the type of sealing member, but may be generally performed at about 120 ° C. to 170 ° C.
한편, 반도체 칩이 밀봉층 성형 공정에서 이동하는 것을 방지하기 위해, 상기 밀봉층 형성 전에 프리 베이킹(pre-baking) 공정을 실시할 수 있으며, 이때, 상기 프리 베이킹 온도는 100℃ ~ 150℃ 정도, 보다 구체적으로 110℃ ~ 130℃, 예를 들면 110℃, 111℃, 112℃, 113℃, 114℃, 115℃, 116℃, 117℃, 118℃, 119℃, 120℃, 121℃, 122℃, 123℃, 124℃, 125℃, 126℃, 127℃, 128℃, 129℃, 130℃일 수 있다.Meanwhile, in order to prevent the semiconductor chip from moving in the sealing layer forming process, a pre-baking process may be performed before forming the sealing layer, wherein the prebaking temperature is about 100 ° C. to 150 ° C., More specifically, 110 ℃ to 130 ℃, for example 110 ℃, 111 ℃, 112 ℃, 113 ℃, 114 ℃, 115 ℃, 116 ℃, 117 ℃, 118 ℃, 119 ℃, 120 ℃, 121 ℃, 122 ℃ , 123 ° C, 124 ° C, 125 ° C, 126 ° C, 127 ° C, 128 ° C, 129 ° C, 130 ° C.
상기와 같은 방법으로 밀봉층이 형성된 후에, 밀봉층과 임시 고정 부재를 분리한다. 상기 분리는, 예를 들면, 온도를 상승시켜 점착 테이프에 기포가 발생하도록 하는 방법 등에 의해 이루어질 수 있으나, 이에 한정되는 것은 아니다.After the sealing layer is formed in the above manner, the sealing layer and the temporary fixing member are separated. The separation may be performed by, for example, a method of raising a temperature to generate bubbles in the adhesive tape, but is not limited thereto.
다음으로, 상기 반도체 칩 상에 재배선층(Re-Distribution Layer, RDL)을 포함하는 기판을 형성한다. 상기 재배선층을 포함하는 기판은 반도체칩 상에 유전체층과 금속층을 교대로 적층함으로써 형성될 수 있다. 이때, 상기 유전체층은 예를 들면 감광성 폴리이미드 등으로 이루어질 수 있고, 상기 금속층은 예를 들면, 구리 등으로 이루어질 수 있으나. 이에 한정되는 것은 아니며, 당해 기술 분야에서 사용되는 다양한 재질의 유전체층 및 금속층들이 제한 없이 사용될 수 있다. 또한, 상기 재배선층은, 예를 들면, 폴리벤조아졸과 같은 포토레지스트 등으로 이루어질 수 있으나 이에 한정되는 것은 아니며, 당해 기술 분야에서 사용되는 다양한 재배선층 형성 물질들이 제한 없이 사용될 수 있다. Next, a substrate including a redistribution layer (RDL) is formed on the semiconductor chip. The substrate including the redistribution layer may be formed by alternately stacking a dielectric layer and a metal layer on a semiconductor chip. In this case, the dielectric layer may be made of, for example, photosensitive polyimide, and the metal layer may be made of, for example, copper. Without being limited thereto, dielectric layers and metal layers of various materials used in the art may be used without limitation. In addition, the redistribution layer may be formed of, for example, a photoresist such as polybenzoazole, and the like, but is not limited thereto. Various redistribution layer forming materials used in the art may be used without limitation.
그런 다음, 상기 기판의 하부에 솔더볼과 같은 외부 접속 단자를 형성하고, 다이싱 공정을 통해 개별 반도체 패키지를 형성한다. Then, an external connection terminal such as a solder ball is formed at the bottom of the substrate, and an individual semiconductor package is formed through a dicing process.
반도체 패키지Semiconductor package
다음으로, 본 발명에 따른 반도체 패키지에 대해 설명한다. 도 3 내지 도 5에는 본 발명에 따른 반도체 패키지의 실시예들이 도시되어 있다. Next, a semiconductor package according to the present invention will be described. 3 to 5 illustrate embodiments of a semiconductor package according to the present invention.
도 3 내지 도 5에 도시된 바와 같이, 본 발명에 따른 반도체 패키지는 상기 본 발명에 따른 필름형 반도체 밀봉 부재를 이용하여 밀봉된 것을 그 특징으로 한다. 3 to 5, the semiconductor package according to the present invention is characterized by being sealed using the film-type semiconductor sealing member according to the present invention.
구체적으로, 본 발명에 따른 반도체 패키지는, 기판(300), 적어도 하나 이상의 반도체 칩(200a, 200b)과, 본 발명에 따른 필름형 반도체 밀봉 부재로 형성된 밀봉층(100) 및 외부 접속 단자(400)를 포함한다. Specifically, the semiconductor package according to the present invention, the substrate 300, at least one semiconductor chip (200a, 200b), the sealing layer 100 and the external connection terminal 400 formed of a film-type semiconductor sealing member according to the present invention ).
상기 기판(300)은 반도체 칩(200a, 200b)를 지지하고, 반도체 칩(200a, 200b)에 전기 신호를 부여하기 위한 것으로, 당해 기술 분야에서 일반적으로 사용되는 반도체 실장용 기판들이 제한 없이 사용될 수 있다. 예를 들면, 상기 기판(300)은 회로 기판, 리드 프레임 기판 또는 재배선층(redistribution layer)을 포함하는 기판일 수 있다. The substrate 300 supports the semiconductor chips 200a and 200b and provides electrical signals to the semiconductor chips 200a and 200b, and semiconductor mounting substrates generally used in the art may be used without limitation. have. For example, the substrate 300 may be a circuit board, a lead frame substrate, or a substrate including a redistribution layer.
상기 회로 기판은 절연성을 갖는 물질, 예를 들면 에폭시 수지나 폴리이미드와 같은 열 경화성 필름, 액정 폴리에스테르 필름이나 폴리아미드 필름과 같은 내열성 유기 필름이 부착된 평판으로 이루어질 수 있다. 상기 회로 기판에는 회로 패턴이 형성되며, 상기 회로 패턴은 전원 공급을 위한 전원 배선과 접지 배선 및 신호 전송을 위한 신호 배선 등을 포함한다. 상기 각 배선들은 층간 절연막에 의해 서로 구분되어 배치될 수 있다. 구체적으로, 상기 회로 기판은 회로 패턴이 인쇄 공정에 의해 형성된 인쇄회로기판(Printed Circuit Board, PCB)일 수 있다.The circuit board may be made of an insulating material, for example, a flat plate to which a heat-curable film such as an epoxy resin or a polyimide is attached, or a heat-resistant organic film such as a liquid crystal polyester film or a polyamide film. A circuit pattern is formed on the circuit board, and the circuit pattern includes a power line for supplying power, a ground line, a signal line for signal transmission, and the like. Each of the wires may be separated from each other by an interlayer insulating layer. Specifically, the circuit board may be a printed circuit board (PCB) in which a circuit pattern is formed by a printing process.
상기 리드 프레임 기판은 니켈, 철, 구리, 니켈 합금, 철 합금, 동 합금 등과 같은 금속 재질로 이루어질 수 있다. 상기 리드 프레임 기판은, 반도체 칩을 탑재하기 위한 반도체 칩 탑재부와 반도체 칩의 전극부와 전기적으로 연결된 접속 단자부를 포함할 수 있으나, 이에 한정되는 것은 아니며, 당해 기술 분야에 알려진 다양한 구조 및 재질의 리드 프레임 기판이 제한 없이 사용될 수 있다.The lead frame substrate may be made of a metal material such as nickel, iron, copper, nickel alloy, iron alloy, copper alloy, or the like. The lead frame substrate may include a semiconductor chip mounting part for mounting a semiconductor chip and a connection terminal part electrically connected to an electrode part of the semiconductor chip. However, the lead frame substrate is not limited thereto, and leads of various structures and materials known in the art may be used. Frame substrates can be used without limitation.
상기 재배선층을 포함하는 기판은, 도 3 및 도 5에 도시된 바와 같이, 유전체층(310)과 금속층(320)이 교대로 적층된 적층체의 최외층에 재배선층(Re-Distribution Layer, RDL)(330)이 형성된 기판이다. 상기 유전체층(310)은 예를 들면 감광성 폴리이미드 등으로 이루어질 수 있고, 상기 금속층(320)은 예를 들면, 구리 등으로 이루어질 수 있으나. 이에 한정되는 것은 아니며, 당해 기술 분야에서 사용되는 다양한 재질의 유전체층 및 금속층들이 제한 없이 사용될 수 있다. 또한, 상기 재배선층은, 예를 들면, 폴리벤조아졸과 같은 포토레지스트 등으로 이루어질 수 있으나 이에 한정되는 것은 아니며, 당해 기술 분야에서 사용되는 다양한 재배선층 형성 물질들이 제한 없이 사용될 수 있다. 3 and 5, the substrate including the redistribution layer may include a redistribution layer (Re-Distribution Layer, RDL) in the outermost layer of the laminate in which the dielectric layer 310 and the metal layer 320 are alternately stacked. 330 is a formed substrate. The dielectric layer 310 may be made of, for example, photosensitive polyimide, and the metal layer 320 may be made of, for example, copper. Without being limited thereto, dielectric layers and metal layers of various materials used in the art may be used without limitation. In addition, the redistribution layer may be formed of, for example, a photoresist such as polybenzoazole, and the like, but is not limited thereto. Various redistribution layer forming materials used in the art may be used without limitation.
상기 기판(300) 상에는 적어도 하나 이상의 반도체 칩(200a, 200b)이 실장된다. 기판 상에 실장되는 반도체 칩의 개수는 특별히 한정되지 않으며, 예를 들면, 도 3 또는 도 4에 도시된 바와 같이, 하나의 기판에 2개 이상의 반도체 칩이 실장될 수도 있고, 도 5에 도시된 바와 같이, 하나의 기판에 하나의 반도체 칩이 실장될 수도 있다. At least one semiconductor chip 200a or 200b is mounted on the substrate 300. The number of semiconductor chips mounted on a substrate is not particularly limited. For example, as illustrated in FIG. 3 or 4, two or more semiconductor chips may be mounted on one substrate, and as illustrated in FIG. 5. As described above, one semiconductor chip may be mounted on one substrate.
상기 반도체 칩 실장 방법은, 특별히 한정되지 않으며, 당해 기술 분야에 알려진 반도체 칩 실장 기술이 제한 없이 사용될 수 있다. 예를 들면, 상기 반도체 칩은 플립 칩(flip chip) 방식 반도체칩(200b) 또는 와이어 본딩(wire bonding) 방식의 반도체 칩(200a) 또는 이들의 조합일 수 있다. The semiconductor chip mounting method is not particularly limited, and semiconductor chip mounting techniques known in the art may be used without limitation. For example, the semiconductor chip may be a flip chip type semiconductor chip 200b, a wire bonding type semiconductor chip 200a, or a combination thereof.
플립 칩 방식은 반도체 칩의 아랫면에 범프(bump)를 형성하고, 상기 범프를 이용하여 반도체 칩를 회로 기판에 융착시키는 방식이며, 와이어 본딩 방식은 반도체 칩의 전극부와 기판을 금속 와이어로 전기적으로 연결시키는 방법이다. In the flip chip method, a bump is formed on a bottom surface of the semiconductor chip, and the bump is used to fuse the semiconductor chip to the circuit board. The wire bonding method electrically connects the electrode portion of the semiconductor chip to the substrate with a metal wire. This is how you do it.
한편, 본 발명에 따른 반도체 패키지는 도 3에 도시된 바와 같이, 동종의 반도체칩을 2 이상 포함하도록 구성될 수도 있고, 도 4에 도시된 바와 같이, 이종의 반도체 칩을 포함하도록 구성될 수도 있다. Meanwhile, the semiconductor package according to the present invention may be configured to include two or more semiconductor chips of the same kind as shown in FIG. 3, or may be configured to include heterogeneous semiconductor chips as shown in FIG. 4. .
다음으로, 상기 밀봉층(100)은 반도체 칩(200a, 200b)을 외부 환경으로부터 보호하기 위한 것으로, 상기한 본 발명에 따른 필름형 반도체 밀봉 부재를 이용하여 형성된다. 상기 필름형 반도체 밀봉 부재에 대해서는 상술하였으므로, 구체적인 설명은 생략한다.Next, the sealing layer 100 is to protect the semiconductor chips (200a, 200b) from the external environment, it is formed using the film-type semiconductor sealing member according to the present invention. Since the said film type semiconductor sealing member was mentioned above, the detailed description is abbreviate | omitted.
한편, 상기 기판(300)의 하면, 즉, 반도체 칩이 실장된 면의 반대면에는 기판(300)과 외부 전원을 전기적으로 연결하기 위한 외부 접속 단자(400)가 구비된다. 상기 접속 단자는 당해 기술 분야에 잘 알려진 다양한 구조의 접속 단자들, 예를 들면, 리드(lead), 볼 그리드 어레이(Ball Grid Array) 등이 제한 없이 사용될 수 있다. On the other hand, the lower surface of the substrate 300, that is, the opposite surface on which the semiconductor chip is mounted is provided with an external connection terminal 400 for electrically connecting the substrate 300 and an external power source. The connection terminal may be any of various connection terminals well known in the art, for example, a lead, a ball grid array, and the like, without limitation.
일 구체예에 따르면, 본 발명에 따른 반도체 패키지는, 도 3에 도시된 바와 같이, 재배선층을 포함하는 기판, 상기 재배선층 상부에 배치되는 적어도 하나 이상의 반도체 칩, 상기 반도체 칩을 봉지하도록 형성되는 밀봉층 및 상기 기판의 하부에 형성되는 외부 접속 단자를 포함하며, 이때, 상기 밀봉층은 본 발명에 따른 필름형 밀봉 부재에 의해 형성된다.According to one embodiment, the semiconductor package according to the present invention, as shown in Figure 3, a substrate including a redistribution layer, at least one semiconductor chip disposed on the redistribution layer, is formed to encapsulate the semiconductor chip A sealing layer and an external connection terminal formed under the substrate, wherein the sealing layer is formed by a film-like sealing member according to the present invention.
(부호의 설명)(Explanation of the sign)
10, 110: 제1층10, 110: first floor
20, 120 : 제2층20, 120: second layer
30, 130 : 제3층30, 130: 3rd floor
100 : 밀봉층100: sealing layer
200a, 200b : 반도체칩200a, 200b: semiconductor chip
300 : 기판300: substrate
400 : 외부 접속단자400: External connection terminal

Claims (14)

  1. 유리 직물로 이루어진 제1층;A first layer of glass fabric;
    상기 제1층의 상부에 형성되고, 제1에폭시 수지 및 제1무기 충전제를 포함하는 제2층;A second layer formed on the first layer and including a first epoxy resin and a first inorganic filler;
    상기 제1층의 하부에 형성되고, 제2에폭시 수지 및 제2무기 충전제를 포함하는 제3층을 포함하며,A third layer formed under the first layer, the third layer comprising a second epoxy resin and a second inorganic filler;
    상기 제3층의 두께가 상기 제2층의 두께보다 두꺼운 필름형 반도체 밀봉 부재.The film type semiconductor sealing member in which the thickness of the third layer is thicker than the thickness of the second layer.
  2. 제1항에 있어서,The method of claim 1,
    상기 제3층의 두께는 상기 제2층의 두께의 2배 이상인 필름형 반도체 밀봉 부재.The thickness of a said 3rd layer is a film type semiconductor sealing member which is 2 times or more of the thickness of a said 2nd layer.
  3. 제1항에 있어서,The method of claim 1,
    상기 제1무기충전제는 최대 입경이 상기 유리 직물의 공극 면적의 1/2 이하인 필름형 반도체 밀봉 부재.The first inorganic filler is a film-type semiconductor sealing member having a maximum particle diameter of 1/2 or less of the pore area of the glass fabric.
  4. 제1항에 있어서,The method of claim 1,
    상기 제2무기 충전제의 최대 입경은 상기 제3층의 두께의 1/2 이하인 필름형 반도체 밀봉 부재.The maximum particle diameter of the said 2nd inorganic filler is a film type semiconductor sealing member which is 1/2 or less of the thickness of a said 3rd layer.
  5. 제1항에 있어서, The method of claim 1,
    제1무기 충전제와 제2무기 충전제의 최대 입경은 서로 동일하거나 상이한 필름형 반도체 밀봉 부재.A film type semiconductor sealing member in which the maximum particle diameter of the first inorganic filler and the second inorganic filler is the same or different from each other.
  6. 제1항에 있어서,The method of claim 1,
    상기 제3층은 최대 입경이 상이한 2종의 무기 충전제를 포함하는 것인 필름형 반도체 밀봉 부재.The said 3rd layer is a film type semiconductor sealing member which contains 2 types of inorganic fillers from which a maximum particle diameter differs.
  7. 제6항에 있어서,The method of claim 6,
    상기 제3층은 최대 입경이 큰 무기 충전제들이 분포한 제1영역 및 최대 입경이 작은 무기 충전제들이 분포한 제2영역으로 이루어지는 것인 필름형 반도체 밀봉 부재. And the third layer comprises a first region in which inorganic fillers having a largest particle size are distributed and a second region in which inorganic fillers having a small maximum particle size are distributed.
  8. 청구항 1 내지 7 중 어느 한 항의 필름형 반도체 밀봉 부재를 이용하여 반도체 소자를 밀봉하는 단계를 포함하는 반도체 패키지 제조 방법.A semiconductor package manufacturing method comprising the step of sealing a semiconductor element using the film-type semiconductor sealing member of any one of claims 1 to 7.
  9. 제8항에 있어서,The method of claim 8,
    상기 밀봉은 컴프레션 몰딩(Compression Molding)법 또는 라미네이션(Lamination)법에 의해 수행되는 것인 반도체 패키지 제조 방법. Wherein the sealing is performed by a compression molding method or a lamination method.
  10. 제8항에 있어서, The method of claim 8,
    상기 반도체 패키지 제조 방법은,The semiconductor package manufacturing method,
    일면에 임시 고정 부재가 부착된 캐리어 부재를 준비하는 단계;Preparing a carrier member having a temporary fixing member attached to one surface thereof;
    상기 임시 고정 부재 상에 다수의 반도체 칩을 배열하는 단계;Arranging a plurality of semiconductor chips on the temporary fixing member;
    상기 필름형 반도체 밀봉 부재를 이용하여 상기 반도체 칩 상에 밀봉층을 형성하는 단계;Forming a sealing layer on the semiconductor chip using the film type semiconductor sealing member;
    상기 밀봉층과 임시 고정 부재를 분리하는 단계;Separating the sealing layer and the temporary fixing member;
    상기 다수의 반도체 칩 상에 재배선층을 포함하는 기판을 형성하는 단계; Forming a substrate including a redistribution layer on the plurality of semiconductor chips;
    상기 기판의 하부에 외부 접속 단자를 형성하는 단계; 및Forming an external connection terminal under the substrate; And
    다이싱 공정을 통해 개별 반도체 패키지를 형성하는 단계를 포함하는 것인 반도체 패키지 제조방법. A method of manufacturing a semiconductor package comprising the step of forming an individual semiconductor package through a dicing process.
  11. 청구항 1 내지 7 중 어느 한 항의 필름형 반도체 밀봉 부재를 이용하여 밀봉된 반도체 패키지.The semiconductor package sealed using the film type semiconductor sealing member of any one of Claims 1-7.
  12. 제11항에 있어서,The method of claim 11,
    상기 반도체 패키지는 플립 칩 방식의 반도체 칩, 와이어 본딩 방식의 반도체 칩 또는 이들의 조합을 포함하는 것인 반도체 패키지 제조 방법.The semiconductor package manufacturing method of a semiconductor package including a flip chip type semiconductor chip, a wire bonding type semiconductor chip or a combination thereof.
  13. 제11항에 있어서,The method of claim 11,
    상기 반도체 패키지는 적어도 2개 이상의 이종의 반도체 칩들을 포함하는 것인 반도체 패키지.The semiconductor package includes at least two heterogeneous semiconductor chips.
  14. 제11항에 있어서,The method of claim 11,
    상기 반도체 패키지는,The semiconductor package,
    재배선층을 포함하는 기판;A substrate comprising a redistribution layer;
    상기 재배선층 상부에 배치되는 적어도 하나 이상의 반도체 칩;At least one semiconductor chip disposed on the redistribution layer;
    청구항 1 내지 7 중 어느 한 항의 필름형 반도체 밀봉 부재를 이용하여 상기 반도체 칩을 봉지하도록 형성되는 밀봉층; 및A sealing layer formed to seal the semiconductor chip by using the film type semiconductor sealing member of any one of claims 1 to 7; And
    상기 기판의 하부에 형성되는 외부 접속 단자를 포함하는 것인 반도체 패키지.And an external connection terminal formed under the substrate.
PCT/KR2017/006526 2016-08-30 2017-06-21 Film type semiconductor sealing member, semiconductor package manufactured using same, and manufacturing method therefor WO2018043888A1 (en)

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