TW201820556A - Film-type semiconductor encapsulation member, semiconductor package prepared from the same, and method of manufacturing the same - Google Patents

Abstract

Disclosed are a film-type semiconductor encapsulation member, a semiconductor package prepared from the same, and a method of manufacturing the same. The film-type semiconductor encapsulation member includes a first layer including a glass fabric; a second layer formed on the first layer, the second layer including a first epoxy resin and a first inorganic filler; and a third layer formed on a lower surface of the first layer, the third layer including a second epoxy resin and a second inorganic filler, wherein the third layer is thicker than the second layer.

Description

Membrane semiconductor package member, semiconductor package prepared thereby and preparation method thereof

Embodiments relate to a film type semiconductor encapsulation member, a semiconductor package produced thereby, and a method of fabricating the same. More specifically, embodiments relate to a film-type semiconductor encapsulation member that can be used for large-area applications and has low warpage and good slit filling characteristics and is suitable for use in a wafer-level packaging process or a panel-level packaging process. The semiconductor package and its preparation method.

The present application claims the priority of the Korean Patent Application No. 10-2016-0110846, filed on Jan. 30,,,,,,,,,,,,,,,,, in.

A method of encapsulating a semiconductor device with an epoxy resin composition is used on the market to protect the semiconductor device from external environmental influences such as moisture, mechanical shock, and the like. In the encapsulation of a typical semiconductor device, a semiconductor wafer is fabricated by first dicing a wafer and then encapsulating each semiconductor wafer. In recently developed processes, uncut wafers or panels are first packaged and then diced into semiconductor wafers. In general, the former method means chip sourcing packaging (CSP) and the latter method means wafer level packaging (WLP) or panel level packaging (PLP).

Wafer level packaging can be easily fabricated and can be fabricated into thin packages to reduce semiconductor mounting space. However, in wafer level packaging or panel level packaging, the area of the configuration is greater than the area of the wafer size package that encapsulates each wafer. Therefore, warpage may occur due to a thermal expansion coefficient difference between the wafer and the encapsulation material. Warpage affects the yield of subsequent processes and wafer handling procedures. Typically epoxy or tantalum resins are used as encapsulants in wafer level packaging or panel level packaging in aqueous form. The aqueous composition may have a low content of inorganic filler, and as an aqueous unimolecule of the resin, the reliability of the semiconductor package is lowered.

Therefore, there is a need for semiconductor encapsulation materials that can cause low warpage in wafer level packaging or panel level packaging and that exhibit good reliability in wafer level packaging or panel level packaging.

The embodiment relates to a film type semiconductor encapsulating member which can simultaneously reduce warpage and exhibit good reliability, and is suitable for use in a wafer level package or a panel level package.

The embodiment relates to a film type semiconductor encapsulating member having good fluidity and good slit filling characteristics.

Embodiments are directed to a method of fabricating a semiconductor package using a film-type semiconductor encapsulation member.

Embodiments are directed to a semiconductor package encapsulated by a film-type semiconductor encapsulation member.

The film-type semiconductor encapsulating member can implement the embodiment, the film-type semiconductor encapsulating member comprising: a first layer comprising a glass fabric; a second layer formed on the first layer, the second layer comprising the first epoxy a resin and a first inorganic filler; and a third layer formed on a lower surface of the first layer, the third layer comprising a second epoxy resin and a second inorganic filler, wherein the third layer is thicker than the second layer.

In an exemplary embodiment, the thickness of the third layer can be at least twice that of the second layer.

In an exemplary embodiment, the longest diameter of the first inorganic filler may be no more than one-half (one-half) of the pore area of the glass fabric.

In an exemplary embodiment, the longest diameter of the second inorganic filler may be no more than half (one-half) the thickness of the third layer.

In an exemplary embodiment, the maximum diameter of the first inorganic filler may be the same as or different from the maximum diameter of the second inorganic filler.

In an exemplary embodiment, the third layer can include two inorganic fillers having different longest diameters.

In an exemplary embodiment, the third layer may include a first region including an inorganic filler having a first longest diameter, and a second region including an inorganic filler having a second longest diameter. The first longest diameter is greater than the second longest diameter.

The embodiment can be realized by providing a method of manufacturing an encapsulated semiconductor package including a semiconductor device using the film type semiconductor encapsulation member according to the embodiment.

In an exemplary embodiment, the encapsulation may be performed by compression molding or lamination molding.

In an exemplary embodiment, a method of fabricating a semiconductor package includes: preparing a carrier member having a temporary fixing member attached to one surface of a carrier member; arranging a plurality of semiconductor wafers on the temporary fixing member; using the film type semiconductor encapsulation member at Forming an encapsulation layer on the plurality of semiconductor wafers; separating an encapsulation layer from the temporary fixing member; forming a plate including the redistribution layer on the plurality of semiconductor wafers; forming an external terminal on a lower surface of the plate; and cutting through The process forms a separate semiconductor package.

The embodiment can be realized by a semiconductor package encapsulated with a film type semiconductor encapsulation member according to an embodiment.

In an exemplary embodiment, the semiconductor package may include a semiconductor wafer mounted by a flip chip method, a semiconductor wafer mounted by a wire bonding method, or a combination thereof.

In an exemplary embodiment, a semiconductor package can include at least two different semiconductor wafers.

In an exemplary embodiment, the semiconductor package may include: a board including a redistribution layer, at least one semiconductor wafer disposed on the redistribution layer, an encapsulation layer encapsulating the semiconductor wafer with the film type semiconductor encapsulation member, and formed on the board External terminals on the lower surface.

The semiconductor package member according to the embodiment may be formed in a film form and may be used in a large-area process such as a wafer level package or a panel level package.

The semiconductor encapsulation member according to the embodiment may include a glass fabric to exhibit good stiffness, and the semiconductor package fabricated from the semiconductor encapsulation member may have good reliability.

The semiconductor encapsulation member according to the embodiment may include a thick resin layer having good fluidity on the lower surface of the glass fabric, which may exhibit good slit filling characteristics and may reduce damage of wiring in the molding process.

The illustrative embodiments are described more fully hereinafter with reference to the accompanying drawings, but, The embodiments are provided so that this disclosure will be thorough and complete, and the scope of the exemplary embodiments will be fully conveyed by those skilled in the art.

In the drawings, the size of layers and regions may be exaggerated for clarity. The same reference numerals are used throughout the specification to refer to the same elements. In the drawings, parts that are not relevant to the present specification are omitted for the sake of clarity.

It is to be understood that the phrase "comprise" or "an" The presence or addition of steps, operations, components, components, and/or groups thereof. As used herein, the singular " " "

In the explanation of the elements, the error range should be included in the elements, although not specifically stated.

It will also be understood that when a layer or element means "under another layer or substrate", "below another layer or substrate", "on another layer or substrate", "above another layer or substrate" or " When on another layer or next to the substrate, there may be other intermediate layers unless the term "direct" is used. In addition, it should also be understood that when a layer means "between" two layers, the layer may be the only layer between the two layers, or may have one or more intermediate layers.

As used herein, terms such as "upper portion", "upper surface", "lower portion" or "lower surface" are defined with reference to the drawings. Therefore, it should be understood that the term "upper part" or "upper surface" may be used interchangeably with "lower part" or "lower surface" when viewed from different angles, and vice versa. Membrane semiconductor encapsulation member

A film type semiconductor encapsulation member will be described below based on an embodiment.

An example of a film type semiconductor encapsulation member according to an embodiment of the present invention is illustrated in FIGS. 1 and 2. 1 and 2, a film type semiconductor encapsulation member according to an embodiment of the present invention may include: a first layer 10 including a glass fabric; a second layer 20 formed on an upper surface of the first layer 10; Three layers 30 are formed on the lower surface of the first layer 10.

The glass fabric can be formed by weaving the glass fibers 12. The material for the glass fiber 12 is not particularly limited. Examples of the glass fabric may include E glass, C glass, A glass, S glass, D glass, NE glass, T glass, H glass, and the like. In an exemplary embodiment, E glass or S glass can be used.

The glass fabric may have a thickness of from 10 micrometers (μm) to 50 micrometers, such as from 15 micrometers to 35 micrometers. In an exemplary embodiment, the glass fabric may have a thickness of 15 microns, 16 microns, 17 microns, 18 microns, 19 microns, 20 microns, 21 microns, 22 microns, 23 microns, 24 microns, 25 microns, 26 microns, 27 Micron, 28 microns, 29 microns, 30 microns, 31 microns, 32 microns, 33 microns, 34 microns or 35 microns. Within this range, the film type semiconductor encapsulating member can be easily manufactured.

The second layer 20 can be formed on the upper surface of the first layer 10 including the glass fabric. The second layer 20 can be fabricated from a first epoxy composition comprising a first epoxy resin 24 and a first inorganic filler 22.

The first epoxy resin 24 may include any epoxy resin including at least two epoxy groups without limitation. Examples of the first epoxy resin 24 may include an epoxy resin obtained by epoxidizing a phenol or an alkylphenol with a condensation product: hydroxybenzaldehyde, phenol novolac epoxy resin, Cresol novolac epoxy resin, multifunctional epoxy resin, naphthol novolac epoxy resin, bisphenol A/bisphenol F/bisphenol AD phenolic ring Bisphenol A/bisphenol F/bisphenol AD novolac epoxy resin, bisphenol A/bisphenol F/bisphenol AD glycidyl ether, bishydroxybiphenyl epoxy resin (bishydroxybiphenyl epoxy resin), dicyclopentadiene epoxy resin, and the like. In an exemplary embodiment, a cresol novolac epoxy resin, a polyfunctional epoxy resin, a phenol aralkyl epoxy resin, a biphenyl epoxy resin, or the like can be used.

The first inorganic filler 22 may include any inorganic filler commonly used in semiconductor encapsulating materials without limitation. Examples of the first inorganic filler 22 may include cerium oxide, calcium carbonate, magnesium carbonate, aluminum oxide, cerium oxide, magnesium oxide, clay, talc, calcium silicate, titanium oxide, cerium oxide, glass. Fabrics, etc. The compounds can be used singly or in combination. In an exemplary embodiment, cerium oxide can be used.

The longest diameter of the first inorganic filler 22 may be no more than one-half (one-half) of the pore area of the glass fabric, for example, not more than one-third of the pore area of the glass fabric. When the longest diameter of the first inorganic filler 22 is larger than half (one-half) of the pore area of the glass fabric, the pores of the glass fabric may be blocked by the first inorganic filler 22, thereby possibly reducing the semiconductor encapsulation member in the molding process. Flowability.

In an embodiment, the first inorganic filler 22 may have a longest diameter of from 0.5 micrometers to 20 micrometers, such as from 1 micrometer to 10 micrometers. In an exemplary embodiment, the longest diameter of the first inorganic filler 22 can be 1 micron, 2 micron, 3 micron, 4 micron, 5 micron, 6 micron, 7 micron, 8 micron, 9 micron, or 10 micron. The second layer 20 may include 5 wt% to 99 wt% of the first epoxy resin 24, such as 5 wt% to 80 wt%, particularly 15 wt% to 70 wt%, especially 25 wt% to 60 wt%, And comprising from 1 wt% to 95 wt% of the first inorganic filler 22, such as from 1 wt% to 85 wt%, especially from 5 wt% to 70 wt%, especially from 10 wt% to 50 wt%. For example, the second layer 20 may include 25 wt%, 30 wt%, 35 wt%, 40 wt%, 45 wt%, 50 wt%, 55 wt%, or 60 wt% of the first epoxy resin 24, and The first inorganic filler 22 is included in 10 wt%, 15 wt%, 20 wt%, 25 wt%, 30 wt%, 35 wt%, 40 wt%, 45 wt%, 50 wt% or 55 wt%. Within this range, the semiconductor encapsulation member ensures proper fluidity and mechanical properties.

In performing the process, the second layer 20 may have a thickness of from 5 microns to 40 microns, such as from 10 microns to 30 microns. In an exemplary embodiment, the second layer 20 may have a thickness of 10 microns, 11 microns, 12 microns, 13 microns, 14 microns, 15 microns, 16 microns, 17 microns, 18 microns, 19 microns, 20 microns, 21 microns. 22 microns, 23 microns, 24 microns, 25 microns, 26 microns, 27 microns, 28 microns, 29 microns or 30 microns.

The third layer 30 may be formed on the lower surface of the first layer 10 including the glass fabric. The third layer 30 can be fabricated from a second epoxy resin composition comprising a second epoxy resin 34 and a second inorganic filler 32.

The second epoxy resin 34 may include any epoxy resin including at least two epoxy groups without limitation. Examples of the second epoxy resin 34 may include an epoxy resin obtained by epoxidizing a phenol or an alkylphenol with a condensation product: hydroxybenzaldehyde, novolac epoxy resin, cresol novolac epoxy resin, polyfunctional Epoxy resin, naphthol novolac epoxy resin, bisphenol A/bisphenol F/bisphenol AD novolac epoxy resin, bisphenol A/bisphenol F/bisphenol AD glycidyl ether, bishydroxybiphenyl epoxy resin, Dicyclopentadiene epoxy resin and the like. In an exemplary embodiment, a cresol novolac epoxy resin, a polyfunctional epoxy resin, a phenol aralkyl epoxy resin, a biphenyl epoxy resin, or the like can be used.

The second epoxy resin 34 may be the same as or different from the first epoxy resin 24.

The second epoxy resin 34 may also include at least two different resins. When the second epoxy resin 34 includes at least two resins, the respective epoxy resins may be located in different regions. For example, the third layer 30 can include the same epoxy resin as the first epoxy resin 24 of the second layer 20 and an epoxy resin different from the first epoxy resin 24. In this case, the same epoxy resin as the first epoxy resin 24 may be disposed on the upper portion of the third layer 30 closer to the glass fabric, and the epoxy resin different from the first epoxy resin 24 may be disposed on On the lower portion of the third layer 30.

The second inorganic filler 32 may include any inorganic filler commonly used in semiconductor encapsulating materials without limitation. Examples of the second inorganic filler 32 may include cerium oxide, calcium carbonate, magnesium carbonate, aluminum oxide, cerium oxide, magnesium oxide, clay, talc, calcium citrate, titanium oxide, cerium oxide, glass woven fabric, and the like. The compounds can be used singly or in combination. In an exemplary embodiment, cerium oxide can be used.

The longest diameter of the second inorganic filler 32 may be no more than one-half (one-half) the thickness of the third layer 30, for example, not more than one-third the thickness of the third layer 30. When the longest diameter of the second inorganic filler 32 is larger than half (one-half) of the thickness of the third layer 30, the moldability and filling ability of the semiconductor encapsulating member are lowered.

In carrying out the procedure, the second inorganic filler 32 may have a longest diameter of from 0.5 micrometers to 60 micrometers, such as from 1 micrometer to 30 micrometers. In an exemplary embodiment, the second inorganic filler 32 may have a longest diameter of 1 micron, 2 micron, 3 micron, 4 micron, 5 micron, 6 micron, 7 micron, 8 micron, 9 micron, 10 micron, 11 micron, 12 microns, 13 microns, 14 microns, 15 microns, 16 microns, 17 microns, 18 microns, 19 microns, 20 microns, 21 microns, 22 microns, 23 microns, 24 microns, 25 microns, 26 microns, 27 microns, 28 microns , 29 microns or 30 microns.

The maximum diameter of the second inorganic filler 32 may be the same as or different from the maximum diameter of the first inorganic filler 22.

The third layer 30 may include 5 wt% to 99 wt% of the second inorganic filler 34, such as 5 wt% to 80 wt%, particularly 15 wt% to 70 wt%, especially 25 wt% to 60 wt%, and The second inorganic filler 32 is included in an amount of from 1 wt% to 95 wt%, such as from 1 wt% to 85 wt%, particularly from 5 wt% to 70 wt%, especially from 10 wt% to 50 wt%. In an exemplary embodiment, the third layer 30 may include 25 wt%, 30 wt%, 35 wt%, 40 wt%, 45 wt%, 50 wt%, 55 wt%, or 60 wt% of the second epoxy resin. 34, and comprising 10 wt%, 15 wt%, 20 wt%, 25 wt%, 30 wt%, 35 wt%, 40 wt%, 45 wt%, 50 wt% or 55 wt% of the second inorganic filler 32. Within this range, the semiconductor encapsulation member can exhibit good moldability.

The third layer 30 may be thicker than the second layer 20 in the execution of the program. In an exemplary embodiment, the thickness of the third layer 30 can be at least twice, for example, two to five times the thickness of the second layer 20. When the layer disposed on the lower portion of the glass fabric is thick, the semiconductor wafer can be protected from damage during the molding process, and the encapsulation member can have improved fluidity, thereby further improving the slit filling characteristics.

In carrying out the process, the third layer 30 may have a thickness of from about 10 microns to about 425 microns, such as from 20 microns to 425 microns, particularly from 40 microns to 210 microns, especially from 50 microns to 150 microns. In an exemplary embodiment, the third layer 30 can have a thickness of 50 microns, 55 microns, 60 microns, 65 microns, 70 microns, 75 microns, 80 microns, 85 microns, 90 microns, 95 microns, 100 microns, 105 microns. 110 microns, 115 microns, 120 microns, 125 microns, 130 microns, 135 microns, 140 microns, 145 microns or 150 microns. Within this range, the semiconductor encapsulation member ensures good flow and package fill characteristics.

As shown in Figure 1, the third layer 30 can comprise an inorganic filler of the same longest diameter. In another exemplary embodiment, the third layer 30 can have at least two inorganic fillers having different longest diameters.

When the third layer 30 includes at least two inorganic fillers having different longest diameters, the third layer 30 may be divided into: a first region 30a in which the first longest diameter inorganic filler is disposed, and a inorganic having a second longest diameter therein A second region 30b of the packing arrangement. The first longest diameter is greater than the second longest diameter. In FIG. 2, the inorganic filler having the largest diameter is disposed on the lower portion of the third layer 30. However, the embodiment of the present invention is not limited thereto, and the inorganic filler having a larger maximum diameter may be disposed on the upper portion of the third layer 30, and the inorganic filler having a smaller maximum diameter may be disposed under the third layer 30. Partially.

The epoxy resins which can serve as a matrix of the first region 30a and the second region 30b may be the same or different from each other. For example, the first region 30a may include the same epoxy resin as the first epoxy resin 24 of the second layer 20, while the second region 30b may include an epoxy resin different from the first epoxy resin 24. .

In addition to the epoxy resin and the inorganic filler, the first epoxy resin composition in the second layer 20 and the second epoxy resin composition in the third layer 30 may each further include a curing agent and a curing accelerator ( Curing accelerator), a coupling agent, a release agent, a coloring agent, and the like.

In an exemplary embodiment, the curing agent can include any curing agent that is commonly used in semiconductor encapsulating members. Examples of the curing agent may include phenol aralkyl phenol resin, phenol novolac phenol resin, xylitol resin, cresol novolac resin, naphthol phenol resin, terpene phenol resin, polyfunctional phenol resin, dicyclopentadiene a phenol resin, a novolak phenol resin synthesized from bisphenol A and a resol phenol resin, a polyhydric phenol compound including tris(hydroxyphenyl)methane or dihydroxybiphenyl, including an acid anhydride including maleic anhydride or phthalic anhydride For example, an aromatic amine of m-phenylenediamine, diaminodiphenylmethane, diamine diphenyl hydrazine or the like is not limited.

The amount of the curing agent may be from 1 wt% to 40 wt%, for example, from 3 wt% to 35 wt%, based on the total weight of the epoxy resin composition. In an exemplary embodiment, the amount of the curing agent may be 3 wt%, 4 wt%, 5 wt%, 6 wt%, 7 wt%, 8 wt%, 9 wt%, based on the total weight of the epoxy resin composition. 10 wt%, 11 wt%, 12 wt%, 13 wt%, 14 wt%, 15 wt%, 16 wt%, 17 wt%, 18 wt%, 19 wt%, 20 wt%, 21 wt%, 22 Wt%, 23 wt%, 24 wt%, 25 wt%, 26 wt%, 27 wt%, 28 wt%, 29 wt%, 30 wt%, 31 wt%, 32 wt%, 33 wt%, 34 wt% Or 35 wt%.

The curing accelerator accelerates the reaction of the epoxy resin with the curing agent. Examples of the curing accelerator may include a tertiary amine, an organometallic compound, an organophosphorus compound, an imidazole, a boron compound, and the like. Examples of the tertiary amine may include benzyldimethylamine, triethanolamine, triethylenediamine, diethylaminoethanol, and tris(dimethylaminomethyl). ) Tri(dimethylaminomethyl)phenol, 2,2-(dimethylaminomethyl)pheno, 2,4,6-tris(diaminomethyl)phenol (2) 4,6-tris(diaminomethyl)phenol), tri-2-ethylhexanoate, and the like. The amount of the curing accelerator may be from 0.01 wt% to 2 wt%, such as from 0.02 wt% to 1.5 wt%, particularly from 0.05 wt% to 1 wt%, based on the total weight of the epoxy resin composition. In an exemplary embodiment, the amount of the curing accelerator may be 0.05 wt%, 0.1 wt%, 0.2 wt%, 0.3 wt%, 0.4 wt%, 0.5 wt%, 0.6 wt% based on the total weight of the epoxy resin composition. %, 0.7 wt%, 0.8 wt%, 0.9 wt% or 1 wt%. Within this range, the curing reaction of the epoxy resin composition can be accelerated, and the degree of curing can also be improved.

The coupling agent improves the interfacial strength between the epoxy resin and the inorganic filler. For example, the coupling agent can include a decane coupling agent. In order to improve the interface strength of the epoxy resin and the inorganic filler, the decane coupling agent may be any coupling agent which can react between the epoxy resin and the inorganic filler without limitation. Examples of the decane coupling agent may include epoxy decane, amino decane, ureido decane, thiodecane, and the like. The decane coupling agents may be used singly or in combination.

The amount of the coupling agent may be from 0.01 wt% to 5 wt%, such as from 0.05 wt% to 3 wt%, particularly from 0.1 wt% to 2 wt%, based on the total weight of the epoxy resin composition. In an exemplary embodiment, the amount of the coupling agent may be 0.1 wt%, 0.2 wt%, 0.3 wt%, 0.4 wt%, 0.5 wt%, 0.6 wt%, 0.7 wt%, based on the total weight of the epoxy resin composition. , 0.8 wt%, 0.9 wt%, 1 wt%, 1.1 wt%, 1.2 wt%, 1.3 wt%, 1.4 wt%, 1.5 wt%, 1.6 wt%, 1.7 wt%, 1.8 wt%, 1.9 wt% or 2 Wt%. Within this range, the strength of the cured epoxy resin composition can be improved.

The release agent may include at least one selected from the group consisting of paraffin waxes, ester waxes, high fatty acids, metal salts of high fatty acids, natural fatty acids, and metal salts of natural fatty acids.

The amount of the releasing agent may be from 0.1 wt% to 1 wt% based on the total weight of the epoxy resin composition. For example, the amount of the release agent may be 0.1 wt%, 0.2 wt%, 0.3 wt%, 0.4 wt%, 0.5 wt%, 0.6 wt%, 0.7 wt%, 0.8 based on the total weight of the epoxy resin composition. Wt%, 0.9 wt% or 1 wt%.

The colorant can be used for laser marking of the semiconductor device encapsulating member, and any coloring agent known in the art can also be used without particular limitation. Examples of the colorant may include at least one of carbon black, titanium black, titanium nitride, dicopper hydroxide phosphate, iron oxide, and mica.

The amount of the colorant may be from 0.01 wt% to 5 wt%, such as from 0.05 wt% to 3 wt%, particularly from 0.1 wt% to 2 wt%, based on the total weight of the epoxy resin composition. In an exemplary embodiment, the amount of the colorant may be 0.1 wt%, 0.2 wt%, 0.3 wt%, 0.4 wt%, 0.5 wt%, 0.6 wt%, 0.7 wt%, based on the total weight of the epoxy resin composition. , 0.8 wt%, 0.9 wt%, 1 wt%, 1.1 wt%, 1.2 wt%, 1.3 wt%, 1.4 wt%, 1.5 wt%, 1.6 wt%, 1.7 wt%, 1.8 wt%, 1.9 wt% or 2 Wt%.

Further, the epoxy resin composition according to the embodiment may further include a stress relieving agent such as silicon oil, silicon power, ruthenium resin, etc.; an antioxidant such as tetrakitethylene -3-(3,5-di-tert-butyl-4-hydroxyphenyl)propionate]methane (tetrakis[methylene-3-(3,5-di-tertbutyl-4-hydroxyphenyl)propionate]methane).

The film-type semiconductor encapsulation member according to the embodiment can be prepared by disposing a glass fabric on a first release film, then coating a first epoxy resin composition on the glass fabric, and drying the first epoxy resin composition. The first film is formed, the second epoxy resin composition is coated on the second release film, the second epoxy resin composition is dried to form a second film, and the first film and the second film are combined. The combination process can be formed using a joining member (for example, a bonding agent or an adhesive) or by laminating the first film and the second film under pressure and high temperature.

The film type semiconductor encapsulating member prepared by the above method may have a shape of a film. Thus, the semiconductor encapsulation member can be used to fabricate large area semiconductor devices, such as wafer level packages or panel level packages.

The film type semiconductor encapsulation member according to the embodiment may include a glass fabric to have high rigidity of the semiconductor package structure, and may realize fabrication of a high reliability semiconductor package.

The film type semiconductor encapsulation member according to the embodiment may include a thick third layer disposed on a lower portion of the glass fabric to have good fluidity, moldability, step coverage characteristics during package molding ( Step covering property) and fillability. Method of manufacturing a semiconductor package

Hereinafter, a method of fabricating a semiconductor package will be described in accordance with an embodiment of the present invention.

A method of fabricating a semiconductor package in accordance with an embodiment of the present invention may include encapsulating a semiconductor device using the above-described film type semiconductor encapsulation member according to an embodiment of the present invention.

The encapsulation process can be carried out by a semiconductor encapsulation method commonly used in the art. For example, compression molding or lamination can be used.

In an exemplary embodiment, a method of fabricating a semiconductor package can be implemented by performing a wafer level package or a panel level package and then forming a redistribution layer. For example, a semiconductor package can be fabricated by the following process.

A temporary fixing member (for example, an adhesive tape or a heat release tape) may be attached to one surface of a carrier member (for example, a carrier wafer or a carrier sheet) to prepare a surface having a temporary fixing member attached to the carrier member. Carrier member.

The plurality of semiconductor wafers are relocated to the temporary fixing member by a process such as a pick-and-place method.

After the reconfiguration of the plurality of semiconductor wafers is completed, the film-type semiconductor encapsulation member according to an embodiment of the present invention is disposed on a semiconductor wafer, and then an encapsulation layer is formed by a molding process such as compression or lamination. The temperature varies depending on the type of the encapsulating member, and the molding process can be carried out at a temperature of from about 120 ° C to about 170 ° C.

Prior to forming the encapsulation layer, a pre-baking process can be performed to prevent displacement of the semiconductor wafer during the molding process. The pre-bake process can be carried out at a temperature of from about 100 ° C to 150 ° C, for example from about 110 ° C to about 130 ° C.

After the encapsulation layer is formed according to the above process, the encapsulation layer may be separated from the temporary fixation member. The separation process can be carried out by increasing the temperature to form bubbles in the temporary fixing member (for example, an adhesive tape), but is not limited thereto.

Next, a board including a redistribution layer (RDL) is formed on the semiconductor wafer. A board including a redistribution layer can be formed by alternately laminating a dielectric layer and a metal layer on a semiconductor wafer. The dielectric layer may include a photosensitive polyimide or the like, and the metal layer may include copper or the like, but is not limited thereto. Various dielectric layers and metal layers known in the art can be used without limitation. The redistribution layer may include a photoresist, such as polybenzoazole, but is not limited thereto. Various redistribution layers known in the art can be used without limitation.

External terminals (eg, solder balls) may be formed on the lower surface of the board, and then a separate semiconductor package may be fabricated via a dicing process. Semiconductor package

A semiconductor package in accordance with an embodiment of the present invention will be described below. 3 through 5 each illustrate a semiconductor package in accordance with an embodiment of the present invention.

As shown in FIGS. 3 to 5, the above-described film type semiconductor encapsulation member according to an embodiment of the present invention may encapsulate a semiconductor package according to an embodiment of the present invention.

In an exemplary embodiment, a semiconductor package in accordance with an embodiment of the present invention may include a board 300, at least one semiconductor wafer 200a, and/or a semiconductor wafer 200b, an encapsulation layer 100 prepared from a film type semiconductor encapsulation member according to an embodiment. And an external terminal 400.

The board 300 can support the semiconductor wafer 200a and/or the semiconductor wafer 200b and can provide electronic signals to the semiconductor wafer 200a and/or the semiconductor wafer 200b. Any board known in the art of packaging semiconductors can be used without limitation. Examples of the board 300 may include a circuit board, a lead frame board, or a board including a redistribution layer.

The circuit board may include a flat plate having the following attached thereto: an insulating material (for example, epoxy resin), a thermosetting film (for example, polyimide), or a heat resistant organic film (for example, liquid crystal polyester film or polyamide) membrane). The circuit pattern may be formed on the circuit board, and the circuit pattern may include a power supply wiring for supplying power, a ground wiring, and a signal wiring for transmitting signals. These wirings can be separated from each other by an insulating interlayer. For example, the circuit board can be a printed circuit board (PCB) on which a circuit pattern is formed by a printing process.

The lead frame plate can be formed from, for example, the following metals: nickel, iron, copper, nickel alloy, iron alloy, copper alloy, and the like. The lead frame board may include a semiconductor wafer mounting portion on which the semiconductor wafer is mounted, and a terminal portion including an electrode portion electrically connected to the semiconductor wafer, but is not limited thereto. Various lead frame sheets generally known in the art can be used without limitation.

As shown in FIGS. 3 to 5, the board including the redistribution layer may include a redistribution layer (RDL) 330 formed on the outermost layer of the stacked structure in which the dielectric layer 310 and the metal layer 320 are alternately laminated. For example, the dielectric layer 310 may include a photosensitive polyimide, and the metal layer 320 may include copper, but is not limited thereto. Various dielectric layers and metal layers known in the art can be used without limitation. The redistribution layer may include a photoresist, such as polybenzoxazole, but is not limited thereto. Various materials for forming a redistribution layer known in the art can be used without limitation.

At least one semiconductor wafer 200a and/or semiconductor wafer 200b may be mounted on the board 300. The number of semiconductor wafers mounted on the board 300 is not particularly limited. For example, as shown in FIGS. 3 and 4, at least two semiconductor wafers can be mounted on one board, and as shown in FIG. 5, one semiconductor wafer can be mounted on one board.

The method of mounting the semiconductor wafer is not particularly limited, and any method known in the art can be used without limitation. For example, the semiconductor wafer may be a semiconductor wafer 200b mounted by a flip chip method, a semiconductor wafer 200a mounted by a wire bonding method, or a combination thereof.

In the flip chip method, bumps are formed on a lower surface of a semiconductor wafer, and the semiconductor wafer is fused on the circuit board via bumps. In the wire bonding method, the electrode portion of the semiconductor wafer is electrically connected to a plate having a metal wire.

As shown in FIG. 3, a semiconductor package in accordance with an embodiment of the present invention may include at least two semiconductor wafers of the same kind. As shown in FIG. 4, a semiconductor package in accordance with an embodiment of the present invention can include two different semiconductor wafers.

The encapsulation layer 100 may protect the semiconductor wafer 200a and/or the semiconductor wafer 200b from the external environment, and may be formed from the above-described film type semiconductor encapsulation member according to an embodiment of the present invention. In order to avoid repetition, a detailed description thereof will be omitted.

The external terminal 400 may be formed on a lower surface of the board 300, which is an opposite surface of the board 300 on which the semiconductor wafer 200a or the semiconductor wafer 200b is mounted. The external terminal 400 is used for electrical connection of the board 300 to an external power supply. Various external terminals known in the art, such as leads, ball grid arrays, and the like, can be used without limitation.

In an exemplary embodiment, a semiconductor package according to an embodiment of the present invention may include: a board including a redistribution layer, at least one semiconductor wafer disposed on the redistribution layer, an encapsulation layer encapsulating the semiconductor wafer, and an overlayer formed on the board External terminals on the lower surface. The encapsulation layer can be prepared from a film encapsulation layer in accordance with an embodiment of the present invention.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and it is intended to be a part of the invention, and may be modified and modified without departing from the spirit and scope of the invention.

10‧‧‧ first floor

12‧‧‧glass fiber

20‧‧‧ second floor

22‧‧‧First inorganic filler

24‧‧‧First epoxy resin

30‧‧‧ third floor

30a‧‧‧First area

30b‧‧‧Second area

32‧‧‧Second inorganic filler

34‧‧‧Second epoxy resin

100‧‧‧encapsulated layer

200a, 200b‧‧‧ semiconductor wafer

300‧‧‧ boards

310‧‧‧Dielectric layer

320‧‧‧metal layer

330‧‧‧Rewiring layer

400‧‧‧External terminals

To make the features of the present invention more apparent to those skilled in the art, the following detailed description of the embodiments of the invention will be described in detail below. Figure 1 illustrates a film-type semiconductor encapsulation member in accordance with an embodiment. 2 illustrates a film type semiconductor encapsulation member in accordance with another embodiment. FIG. 3 illustrates a semiconductor package in accordance with an embodiment. 4 illustrates a semiconductor package in accordance with another embodiment. FIG. 5 illustrates a semiconductor package in accordance with yet another embodiment.

Claims (14)

A film type semiconductor encapsulating member comprising: a first layer comprising a glass fabric; a second layer formed on the first layer, the second layer comprising a first epoxy resin and a first inorganic filler; Three layers are formed on a lower surface of the first layer, the third layer comprising a second epoxy resin and a second inorganic filler, wherein the third layer is thicker than the second layer. The film-type semiconductor encapsulation member according to claim 1, wherein the third layer is at least twice as thick as the second layer. The film type semiconductor encapsulating member according to claim 1, wherein the first inorganic filler has a longest diameter of not more than half of a pore area of the glass fabric. The film type semiconductor encapsulating member according to claim 1, wherein the second inorganic filler has a longest diameter of not more than half the thickness of the third layer. The film type semiconductor encapsulating member according to claim 1, wherein the longest diameter of the second inorganic filler is the same as or different from the longest diameter of the first inorganic filler. The film type semiconductor encapsulating member according to claim 1, wherein the third layer comprises two inorganic fillers each having a different longest diameter. The film-type semiconductor encapsulation member of claim 6, wherein the third layer comprises a first region and a second region, the first region comprising an inorganic filler having a first longest diameter, and The second region includes an inorganic filler having a second longest diameter, wherein the first longest diameter is greater than the second longest diameter. A method of manufacturing a semiconductor package, comprising encapsulation of a semiconductor device using the film type semiconductor encapsulation member according to any one of claims 1 to 7. The method of manufacturing a semiconductor package according to claim 8, wherein the encapsulation is performed by compression molding or laminate molding. The method of manufacturing a semiconductor package according to claim 8, comprising: preparing a carrier member having a temporary fixing member attached to one surface of the carrier member; on the temporary fixing member Arranging a plurality of semiconductor wafers; forming an encapsulation layer on the plurality of semiconductor wafers using the film type semiconductor encapsulation member; separating the encapsulation layer from the temporary fixing member; forming on the plurality of semiconductor wafers a board including a redistribution layer; an external terminal formed on a lower surface of the board; and a separate semiconductor package formed through a dicing process. A semiconductor package, which is encapsulated by a film type semiconductor encapsulation member according to any one of claims 1 to 7. The semiconductor package of claim 11, comprising a semiconductor wafer mounted by a flip chip method, a semiconductor wafer mounted by a wire bonding method, or a combination thereof. The semiconductor package of claim 11, comprising at least two different semiconductor wafers. The semiconductor package of claim 11, comprising: a board comprising a redistribution layer; at least one semiconductor wafer disposed on the redistribution layer; and an encapsulation layer, as in the first to the first The film-type semiconductor encapsulation member according to any one of the items 7, wherein the semiconductor wafer is encapsulated; and an external terminal is formed on a lower surface of the plate.