TWI695461B - Film-type semiconductor encapsulation member, semiconductor package prepared from the same, and method of manufacturing the same - Google Patents

Film-type semiconductor encapsulation member, semiconductor package prepared from the same, and method of manufacturing the same Download PDF

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TWI695461B
TWI695461B TW106129231A TW106129231A TWI695461B TW I695461 B TWI695461 B TW I695461B TW 106129231 A TW106129231 A TW 106129231A TW 106129231 A TW106129231 A TW 106129231A TW I695461 B TWI695461 B TW I695461B
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layer
semiconductor
film
inorganic filler
epoxy resin
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TW106129231A
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TW201820556A (en
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權冀爀
李允萬
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南韓商三星Ｓｄｉ股份有限公司
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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Abstract

Disclosed are a film-type semiconductor encapsulation member, a semiconductor package prepared from the same, and a method of manufacturing the same. The film-type semiconductor encapsulation member includes a first layer including a glass fabric; a second layer formed on the first layer, the second layer including a first epoxy resin and a first inorganic filler; and a third layer formed on a lower surface of the first layer, the third layer including a second epoxy resin and a second inorganic filler, wherein the third layer is thicker than the second layer.

Description

膜式半導體包封構件、以其製得之半導體封裝 與其製備方法 Film-type semiconductor encapsulation member, and semiconductor package made therefrom And its preparation method

實施例是關於一種膜式半導體包封構件、以其製得之半導體封裝與其製備方法。更具體而言，實施例是關於可用於大面積應用且具有低翹曲與良好窄縫填充特性並適合用於晶圓級封裝製程或面板級封裝製程的膜式半導體包封構件、以其製得之半導體封裝與其製備方法。 The embodiment relates to a film-type semiconductor encapsulating member, a semiconductor package made therefrom, and a preparation method thereof. More specifically, the embodiments relate to a film-type semiconductor encapsulating member that can be used in large-area applications, has low warpage and good narrow-seam filling characteristics, and is suitable for a wafer-level packaging process or a panel-level packaging process, and a manufacturing method thereof The obtained semiconductor package and its preparation method.

本申請案主張2016年8月30日在韓國智慧財產局中申請的韓國專利申請案第10-2016-0110846號的優先權的權益，所述申請案的揭露內容以全文引用的方式併入本文中。 This application claims the priority of Korean Patent Application No. 10-2016-0110846 filed in the Korean Intellectual Property Office on August 30, 2016, and the disclosure content of the application is incorporated herein by reference in its entirety in.

在市面上使用以環氧樹脂組成物包封半導體裝置的方法，以保護半導體裝置免於外部環境影響，例如潮濕、機械衝擊等。在一般半導體裝置的包封中，藉由首先切割晶圓並接著封裝 各半導體晶片而製造半導體晶片。近期已發展的製程中，未經切割的晶圓或面板先被封裝，接著被切割為半導體晶片。一般而言，前者的方法意指晶片尺寸封裝(chip scape packaging，CSP)以及後者的方法意指晶圓級封裝(wafer level packaging，WLP)或面板級封裝(panel level packaging，PLP)。 A method of encapsulating a semiconductor device with an epoxy resin composition on the market is used to protect the semiconductor device from external environmental influences, such as moisture and mechanical impact. In the encapsulation of general semiconductor devices, by cutting the wafer first and then packaging Each semiconductor wafer manufactures a semiconductor wafer. In the recently developed process, uncut wafers or panels are first packaged and then cut into semiconductor chips. Generally speaking, the former method means chip scape packaging (CSP) and the latter method means wafer level packaging (WLP) or panel level packaging (PLP).

晶圓級封裝可易於進行所述製程並可製造薄的封裝以減少半導體安裝空間。然而，在晶圓級封裝或面板級封裝中，配置的面積大於包封各晶片之晶片尺寸封裝的面積。因此，可能因晶圓與包封材料之間的熱膨脹係數差(thermal expansion coefficient difference)而出現翹曲。翹曲會影響後續製程與晶片處理製程(wafer handling procedure)的良率。通常環氧樹脂或矽樹脂以水性形式(aqueous form)作為晶圓級封裝或面板級封裝中的包封材料。水性組成物可具有低含量的無機填料，且作為樹脂的水性單分子(aqueous unimolecule)會降低半導體封裝的可靠性。 Wafer-level packaging can easily perform the process and can produce thin packages to reduce semiconductor installation space. However, in a wafer-level package or a panel-level package, the configuration area is larger than the area of the chip-size package that encapsulates each chip. Therefore, warpage may occur due to the thermal expansion coefficient difference between the wafer and the encapsulating material. Warpage will affect the yield of subsequent processes and wafer handling procedures. Generally, epoxy resin or silicone resin is used as an encapsulating material in wafer-level packaging or panel-level packaging in an aqueous form. The aqueous composition may have a low content of inorganic filler, and the aqueous unimolecule as a resin will reduce the reliability of the semiconductor package.

因此，需要在晶圓級封裝或面板級封裝中可造成低翹曲並可在晶圓級封裝或面板級封裝中展現良好可靠性的半導體包封材料。 Therefore, there is a need for semiconductor encapsulation materials that can cause low warpage in wafer-level packaging or panel-level packaging and can exhibit good reliability in wafer-level packaging or panel-level packaging.

實施例是關於一種膜式半導體包封構件，可同時減少翹曲並展現良好的可靠性，且適合用於晶圓級封裝或面板級封裝。 The embodiment relates to a film-type semiconductor encapsulation member, which can simultaneously reduce warpage and exhibit good reliability, and is suitable for wafer-level packaging or panel-level packaging.

實施例是關於一種具有良好的流動性與良好的窄縫填充 特性之膜式半導體包封構件。 The embodiment is about a kind with good fluidity and good slot filling Characteristic film-type semiconductor encapsulation member.

實施例是關於一種使用膜式半導體包封構件製造半導體封裝的方法。 The embodiment relates to a method of manufacturing a semiconductor package using a film-type semiconductor encapsulation member.

實施例是關於一種以膜式半導體包封構件包封的半導體封裝。 The embodiment relates to a semiconductor package encapsulated with a film-type semiconductor encapsulation member.

膜式半導體包封構件可實現所述實施例，所述膜式半導體包封構件包括：第一層，包括玻璃織物；第二層，形成在第一層上，第二層包括第一環氧樹脂及第一無機填料；以及第三層，形成在第一層的下表面上，第三層包括第二環氧樹脂及第二無機填料，其中第三層比第二層厚。 The embodiment can be realized by a film-type semiconductor encapsulating member, the film-type semiconductor encapsulating member includes: a first layer including a glass fabric; a second layer formed on the first layer, the second layer including a first epoxy A resin and a first inorganic filler; and a third layer formed on the lower surface of the first layer, the third layer includes a second epoxy resin and a second inorganic filler, wherein the third layer is thicker than the second layer.

在例示性實施例中，第三層的厚度可為第二層的至少兩倍。 In an exemplary embodiment, the thickness of the third layer may be at least twice that of the second layer.

在例示性實施例中，第一無機填料的最長直徑可不大於玻璃織物的孔洞區域(pore area)的一半(二分之一)。 In an exemplary embodiment, the longest diameter of the first inorganic filler may be no more than half (one-half) of the pore area of the glass fabric.

在例示性實施例中，第二無機填料的最長直徑可不大於第三層的厚度的一半(二分之一)。 In an exemplary embodiment, the longest diameter of the second inorganic filler may be no more than half (one-half) of the thickness of the third layer.

在例示性實施例中，第一無機填料的最大直徑可與第二無機填料的最大直徑相同或不同。 In an exemplary embodiment, the maximum diameter of the first inorganic filler may be the same as or different from the maximum diameter of the second inorganic filler.

在例示性實施例中，第三層可包括兩種最長直徑各不同的無機填料。 In an exemplary embodiment, the third layer may include two types of inorganic fillers with different longest diameters.

在例示性實施例中，第三層可包括第一區域以及第二區域，第一區域包括具有第一最長直徑的無機填料，以及第二區域 包括具有第二最長直徑的無機填料。第一最長直徑大於第二最長直徑。 In an exemplary embodiment, the third layer may include a first region and a second region, the first region includes an inorganic filler having a first longest diameter, and a second region It includes an inorganic filler with the second longest diameter. The first longest diameter is greater than the second longest diameter.

藉由提供使用根據實施例的膜式半導體包封構件製造包括半導體裝置的包封的半導體封裝的方法，可實現所述實施例。 The embodiment can be realized by providing a method of manufacturing an encapsulated semiconductor package including a semiconductor device using the film-type semiconductor encapsulation member according to the embodiment.

在例示性實施例中，可以壓縮模製(compression molding)或層壓(lamination)模製進行包封。 In an exemplary embodiment, encapsulation may be performed by compression molding or lamination molding.

在例示性實施例中，半導體封裝的製造方法包括：製備具有暫時固定構件貼附至載體構件的一個表面的載體構件；在暫時固定構件上排列多個半導體晶片；使用膜式半導體包封構件在所述多個半導體晶片上形成包封層；自暫時固定構件分離包封層；在所述多個半導體晶片上形成包括重佈線層的板；在板的下表面上形成外部端子；以及經由切割製程形成單獨的半導體封裝。 In an exemplary embodiment, a method of manufacturing a semiconductor package includes: preparing a carrier member having a temporary fixing member attached to one surface of the carrier member; arranging a plurality of semiconductor wafers on the temporary fixing member; and using a film-type semiconductor encapsulation member in Forming an encapsulation layer on the plurality of semiconductor wafers; separating the encapsulation layer from the temporary fixing member; forming a board including a redistribution layer on the plurality of semiconductor wafers; forming external terminals on the lower surface of the board; and via cutting The process forms a separate semiconductor package.

所述實施例可藉由以根據實施例的膜式半導體包封構件包封的半導體封裝而實現。 The embodiment can be realized by a semiconductor package encapsulated with the film-type semiconductor encapsulation member according to the embodiment.

在例示性實施例中，半導體封裝可包括以倒裝晶片(flip chip)方法安裝的半導體晶片、以打線接合(wire bonding)方法安裝的半導體晶片或其組合。 In an exemplary embodiment, the semiconductor package may include a semiconductor chip mounted by a flip chip method, a semiconductor chip mounted by a wire bonding method, or a combination thereof.

在例示性實施例中，半導體封裝可包括至少兩種不同的半導體晶片。 In an exemplary embodiment, the semiconductor package may include at least two different semiconductor wafers.

在例示性實施例中，半導體封裝可包括：包括重佈線層的板、至少一個配置於重佈線層上的半導體晶片、以膜式半導體包封構件包封半導體晶片的包封層以及形成在板的下表面上的外 部端子。 In an exemplary embodiment, the semiconductor package may include: a board including a redistribution layer, at least one semiconductor wafer disposed on the redistribution layer, an encapsulation layer that encapsulates the semiconductor wafer with a film-type semiconductor encapsulation member, and formed on the board Outside on the lower surface 部terminal.

根據實施例的半導體封裝構件可以膜式形成，並可用於大面積製程，例如晶圓級封裝或面板級封裝。 The semiconductor packaging member according to the embodiment may be formed in a film type, and may be used in a large-area manufacturing process, such as wafer-level packaging or panel-level packaging.

根據實施例的半導體包封構件可包括玻璃織物，以展現良好的韌性(stiffness)，且自半導體包封構件製造的半導體封裝可具有良好的可靠性。 The semiconductor encapsulation member according to the embodiment may include a glass fabric to exhibit good stiffness, and the semiconductor package manufactured from the semiconductor encapsulation member may have good reliability.

根據實施例的半導體包封構件可包括在玻璃織物的下表面上具有良好流動性的厚的樹脂層，此可展現良好的窄縫填充特性並可減少模製製程中佈線的損傷。 The semiconductor encapsulating member according to the embodiment may include a thick resin layer having good fluidity on the lower surface of the glass fabric, which may exhibit good narrow-seam filling characteristics and may reduce wiring damage during the molding process.

10:第一層 10: first floor

12:玻璃纖維 12: Fiberglass

20:第二層 20: Second floor

22:第一無機填料 22: The first inorganic filler

24:第一環氧樹脂 24: First epoxy resin

30:第三層 30: third floor

30a:第一區域 30a: first area

30b:第二區域 30b: Second area

32:第二無機填料 32: Second inorganic filler

34:第二環氧樹脂 34: Second epoxy resin

100:包封層 100: encapsulation layer

200a、200b:半導體晶片 200a, 200b: semiconductor wafer

300:板 300: board

310:介電層 310: dielectric layer

320:金屬層 320: metal layer

330:重佈線層 330: Rerouting layer

400:外部端子 400: external terminal

為讓本發明的特徵對此技術領域中具有通常知識者更明顯易懂，下文特舉例示性實施例，並配合所附圖式作詳細說明如下。 In order to make the features of the present invention more obvious and understandable to those who have ordinary knowledge in the technical field, the following specifically exemplifies the exemplary embodiments and makes detailed descriptions in conjunction with the accompanying drawings as follows.

圖1根據一實施例說明膜式半導體包封構件。 FIG. 1 illustrates a film-type semiconductor encapsulation member according to an embodiment.

圖2根據另一實施例說明膜式半導體包封構件。 FIG. 2 illustrates a film-type semiconductor encapsulation member according to another embodiment.

圖3根據實施例說明半導體封裝。 FIG. 3 illustrates a semiconductor package according to an embodiment.

圖4根據另一實施例說明半導體封裝。 FIG. 4 illustrates a semiconductor package according to another embodiment.

圖5根據又另一實施例說明半導體封裝。 FIG. 5 illustrates a semiconductor package according to yet another embodiment.

以下將參考圖式更充分說明例示性實施例，然而可以不同形式實施，且不應解釋為僅限於此述的實施例。較佳的是，提 供該些實施例是為了使此揭露內容將透徹及完整，並將向此技術領域中具有通常知識者充分傳達例示性實施的範圍。 The exemplary embodiments will be described more fully below with reference to the drawings, but may be implemented in different forms and should not be interpreted as being limited to the embodiments described herein. Preferably, mention These embodiments are provided so that the disclosure content will be thorough and complete, and will fully convey the scope of exemplary implementation to those with ordinary knowledge in this technical field.

在圖式中，為了清楚說明，層與區域的尺寸可被誇大。本說明書通篇相同的參考編號指代相同的元件。在圖式中，為了清晰起見，省略與本說明書無關的部分。 In the drawings, the size of layers and regions may be exaggerated for clarity. The same reference numbers refer to the same elements throughout this specification. In the drawings, for clarity, parts not related to this description are omitted.

更應理解，當在本說明書中使用用語「包括」時，是用於指出所述特徵、整體、步驟、操作、元件及/或組件的存在，但不排除一或多個其他特徵、整體、步驟、操作、元件、組件及/或其群組的存在或添加。除非上下文中清楚地另外指明，否則本文所用的單數形式「一」亦含有包含多數形式的意涵。 It should be further understood that when the term "comprising" is used in this specification, it is used to indicate the existence of the described features, wholes, steps, operations, elements and/or components, but does not exclude one or more other features, wholes, The presence or addition of steps, operations, elements, components, and/or groups thereof. Unless the context clearly dictates otherwise, the singular form "a" as used herein also includes a majority form.

在解釋元件中，儘管未特別說明，誤差範圍應包含於元件中。 In the explanation element, although not specifically stated, the error range should be included in the element.

也應理解，當層或元件意指為「在另一層或基板之下」、「低於另一層或基板」、「在另一層或基板之上」、「高於另一層或基板」或「在另一層或基板旁」時，可能有其他中間層，除非是使用「直接」一詞的情況。另外，也應理解，當層意指在兩個層「之間」時，所述層可為所述兩層之間唯一的層，或者亦可有一個或更多個中間層。 It should also be understood that when a layer or element means "under another layer or substrate", "below another layer or substrate", "above another layer or substrate", "above another layer or substrate" or " "On another layer or substrate", there may be other intermediate layers, unless the term "direct" is used. In addition, it should also be understood that when a layer is meant to be "between" two layers, the layer may be the only layer between the two layers, or one or more intervening layers may also be present.

如本文中所使用，例如「上部分」、「上表面」、「下部分」或「下表面」的用語參考附圖而定義。因此，應理解，從不同角度觀看時，用語「上部分」或「上表面」可與「下部分」或「下表面」互換使用，反之亦然。 As used herein, terms such as "upper part", "upper surface", "lower part" or "lower surface" are defined with reference to the drawings. Therefore, it should be understood that the terms "upper part" or "upper surface" can be used interchangeably with "lower part" or "lower surface" when viewed from different angles, and vice versa.

膜式半導體包封構件Film-type semiconductor encapsulation member

以下將根據實施例說明一種膜式半導體包封構件。 Hereinafter, a film-type semiconductor encapsulating member will be described according to embodiments.

圖1與圖2中繪示根據本發明實施例的膜式半導體包封構件的實例。圖1與圖2所示，根據本發明實施例的膜式半導體包封構件可包括：第一層10，包括玻璃織物；第二層20，形成在第一層10的上表面上；以及第三層30，形成在第一層10的下表面上。 Examples of film-type semiconductor encapsulating members according to embodiments of the present invention are shown in FIGS. 1 and 2. As shown in FIGS. 1 and 2, the film-type semiconductor encapsulating member according to an embodiment of the present invention may include: a first layer 10 including glass fabric; a second layer 20 formed on the upper surface of the first layer 10; and Three layers 30 are formed on the lower surface of the first layer 10.

玻璃織物可藉由編織玻璃纖維12而形成。用於玻璃纖維12的材料不受特別限制。玻璃織物的實例可包括E玻璃、C玻璃、A玻璃、S玻璃、D玻璃、NE玻璃、T玻璃、H玻璃等。在例示性實施例中，可使用E玻璃或S玻璃。 The glass fabric can be formed by weaving glass fiber 12. The material used for the glass fiber 12 is not particularly limited. Examples of the glass fabric may include E glass, C glass, A glass, S glass, D glass, NE glass, T glass, H glass, and the like. In an exemplary embodiment, E glass or S glass may be used.

玻璃織物的厚度可為10微米(μm)至50微米，例如15微米至35微米。在例示性實施例中，玻璃織物的厚度可為15微米、16微米、17微米、18微米、19微米、20微米、21微米、22微米、23微米、24微米、25微米、26微米、27微米、28微米、29微米、30微米、31微米、32微米、33微米、34微米或35微米。在此範圍內，膜式半導體包封構件可容易被製造。 The thickness of the glass fabric may be 10 micrometers (μm) to 50 micrometers, for example, 15 micrometers to 35 micrometers. In an exemplary embodiment, the thickness of the glass fabric may be 15 microns, 16 microns, 17 microns, 18 microns, 19 microns, 20 microns, 21 microns, 22 microns, 23 microns, 24 microns, 25 microns, 26 microns, 27 Micron, 28 microns, 29 microns, 30 microns, 31 microns, 32 microns, 33 microns, 34 microns, or 35 microns. Within this range, the film-type semiconductor encapsulation member can be easily manufactured.

第二層20可形成在包括玻璃織物的第一層10的上表面上。第二層20可由包括第一環氧樹脂24與第一無機填料22的第一環氧樹脂組成物製造。 The second layer 20 may be formed on the upper surface of the first layer 10 including the glass fabric. The second layer 20 may be made of a first epoxy resin composition including a first epoxy resin 24 and a first inorganic filler 22.

第一環氧樹脂24可包括任何包括至少兩個環氧基的環氧 樹脂，而不受到限制。第一環氧樹脂24的實例可包括藉由將苯酚或烷基酚與以下的縮合產品環氧化而獲得的環氧樹脂：羥基苯甲醛(hydroxybenzaldehyde)、酚醛環氧樹脂(phenol novolac epoxy resin)、甲酚酚醛環氧樹脂(cresol novolac epoxy resin)、多官能環氧樹脂(multifunctional epoxy resin)、萘酚酚醛環氧樹脂(naphthol novolac epoxy resin)、雙酚A/雙酚F/雙酚AD酚醛環氧樹脂(bisphenol A/bisphenol F/bisphenol AD novolac epoxy resin)、雙酚A/雙酚F/雙酚AD縮水甘油醚(bisphenol A/bisphenol F/bisphenol AD glycidyl ether)、雙羥基聯苯環氧樹脂(bishydroxybiphenyl epoxy resin)、二環戊二烯環氧樹脂(dicyclopentadiene epoxy resin)等。在例示性實施例中，可使用甲酚酚醛環氧樹脂、多官能環氧樹脂、苯酚芳烷基環氧樹脂、聯苯環氧樹脂等。 The first epoxy resin 24 may include any epoxy including at least two epoxy groups Resin without limitation. Examples of the first epoxy resin 24 may include epoxy resins obtained by epoxidizing phenol or alkylphenol with the following condensation products: hydroxybenzaldehyde, phenol novolac epoxy resin, Cresol novolac epoxy resin, multifunctional epoxy resin, naphthol novolac epoxy resin, bisphenol A/bisphenol F/bisphenol AD phenolic ring Bisphenol A/bisphenol F/bisphenol AD novolac epoxy resin, bisphenol A/bisphenol F/bisphenol AD glycidyl ether, dihydroxybiphenyl epoxy resin (bishydroxybiphenyl epoxy resin), dicyclopentadiene epoxy resin (dicyclopentadiene epoxy resin), etc. In an exemplary embodiment, cresol novolac epoxy resin, multifunctional epoxy resin, phenol aralkyl epoxy resin, biphenyl epoxy resin, etc. may be used.

第一無機填料22可包括任何在半導體包封材料中普遍使用的無機填料，而不受到限制。第一無機填料22的實例可包括二氧化矽、碳酸鈣、碳酸鎂、氧化鋁、二氧化鈰、氧化鎂、黏土(clay)、滑石(talc)、矽酸鈣、氧化鈦、氧化銻、玻璃織物等。所述化合物可以單獨或組合的方式使用。在例示性實施例中，可使用二氧化矽。 The first inorganic filler 22 may include any inorganic filler commonly used in semiconductor encapsulating materials without limitation. Examples of the first inorganic filler 22 may include silica, calcium carbonate, magnesium carbonate, alumina, ceria, magnesia, clay, talc, calcium silicate, titanium oxide, antimony oxide, glass Fabric, etc. The compounds can be used alone or in combination. In the exemplary embodiment, silicon dioxide may be used.

第一無機填料22的最長直徑可不大於玻璃織物的孔洞區域的一半(二分之一)，例如不大於玻璃織物的孔洞區域的三分之一。當第一無機填料22的最長直徑大於玻璃織物的孔洞區域的一 半(二分之一)時，玻璃織物的孔洞可能被第一無機填料22阻塞，從而可能在模製製程中降低半導體包封構件的流動性(flowability)。 The longest diameter of the first inorganic filler 22 may not be larger than half (half) of the hole area of the glass fabric, for example, not larger than one third of the hole area of the glass fabric. When the longest diameter of the first inorganic filler 22 is larger than one of the hole areas of the glass fabric At half (one-half), the pores of the glass fabric may be blocked by the first inorganic filler 22, which may reduce the flowability of the semiconductor encapsulation member during the molding process.

在實施例中，第一無機填料22的最長直徑可為0.5微米至20微米，例如1微米至10微米。在例示性實施例中，第一無機填料22的最長直徑可為1微米、2微米、3微米、4微米、5微米、6微米、7微米、8微米、9微米或10微米。第二層20可包括5wt%至99wt%的第一環氧樹脂24，例如5wt%至80wt%，特別是15wt%至70wt%，尤其是25wt%至60wt%，以及包括1wt%至95wt%的第一無機填料22，例如1wt%至85wt%，特別是5wt%至70wt%，尤其是10wt%至50wt%。舉例而言，第二層20可包括25wt%、30wt%、35wt%、40wt%、45wt%、50wt%、55wt%或60wt%的第一環氧樹脂24，以及包括10wt%、15wt%、20wt%、25wt%、30wt%、35wt%、40wt%、45wt%、50wt%或55wt%的第一無機填料22。在此範圍內，半導體包封構件可確保適當的流動性與機械特性。 In an embodiment, the longest diameter of the first inorganic filler 22 may be 0.5 μm to 20 μm, for example, 1 μm to 10 μm. In an exemplary embodiment, the longest diameter of the first inorganic filler 22 may be 1 micrometer, 2 micrometers, 3 micrometers, 4 micrometers, 5 micrometers, 6 micrometers, 7 micrometers, 8 micrometers, 9 micrometers, or 10 micrometers. The second layer 20 may include 5wt% to 99wt% of the first epoxy resin 24, for example, 5wt% to 80wt%, especially 15wt% to 70wt%, especially 25wt% to 60wt%, and including 1wt% to 95wt% The first inorganic filler 22 is, for example, 1 wt% to 85 wt%, especially 5 wt% to 70 wt%, especially 10 wt% to 50 wt%. For example, the second layer 20 may include 25wt%, 30wt%, 35wt%, 40wt%, 45wt%, 50wt%, 55wt%, or 60wt% of the first epoxy resin 24, and include 10wt%, 15wt%, 20wt %, 25wt%, 30wt%, 35wt%, 40wt%, 45wt%, 50wt% or 55wt% of the first inorganic filler 22. Within this range, the semiconductor encapsulation member can ensure proper fluidity and mechanical properties.

在執行程序中，第二層20的厚度可為5微米至40微米，例如10微米至30微米。在例示性實施例中，第二層20的厚度可為10微米、11微米、12微米、13微米、14微米、15微米、16微米、17微米、18微米、19微米、20微米、21微米、22微米、23微米、24微米、25微米、26微米、27微米、28微米、29微米或30微米。 In the execution procedure, the thickness of the second layer 20 may be 5 μm to 40 μm, for example, 10 μm to 30 μm. In an exemplary embodiment, the thickness of the second layer 20 may be 10 microns, 11 microns, 12 microns, 13 microns, 14 microns, 15 microns, 16 microns, 17 microns, 18 microns, 19 microns, 20 microns, 21 microns , 22 microns, 23 microns, 24 microns, 25 microns, 26 microns, 27 microns, 28 microns, 29 microns, or 30 microns.

第三層30可形成在包括玻璃織物的第一層10的下表面上。第三層30可由包括第二環氧樹脂34與第二無機填料32的第二環氧樹脂組成物製造。 The third layer 30 may be formed on the lower surface of the first layer 10 including the glass fabric. The third layer 30 may be made of a second epoxy resin composition including a second epoxy resin 34 and a second inorganic filler 32.

第二環氧樹脂34可包括任何包括至少兩個環氧基的環氧樹脂，而不受到限制。第二環氧樹脂34的實例可包括藉由將苯酚或烷基酚與以下的縮合產品環氧化而獲得的環氧樹脂：羥苯甲醛、酚醛環氧樹脂、甲酚酚醛環氧樹脂、多官能環氧樹脂、萘酚酚醛環氧樹脂、雙酚A/雙酚F/雙酚AD酚醛環氧樹脂、雙酚A/雙酚F/雙酚AD縮水甘油醚、雙羥基聯苯環氧樹脂、二環戊二烯環氧樹脂等。在例示性實施例中，可使用甲酚酚醛環氧樹脂、多官能環氧樹脂、苯酚芳烷基環氧樹脂、聯苯環氧樹脂等。 The second epoxy resin 34 may include any epoxy resin including at least two epoxy groups without limitation. Examples of the second epoxy resin 34 may include epoxy resins obtained by epoxidizing phenol or alkylphenol with the following condensation products: paraben, novolac epoxy resin, cresol novolac epoxy resin, polyfunctional Epoxy resin, naphthol novolac epoxy resin, bisphenol A/bisphenol F/bisphenol AD novolac epoxy resin, bisphenol A/bisphenol F/bisphenol AD glycidyl ether, dihydroxybiphenyl epoxy resin, Dicyclopentadiene epoxy resin, etc. In an exemplary embodiment, cresol novolac epoxy resin, multifunctional epoxy resin, phenol aralkyl epoxy resin, biphenyl epoxy resin, etc. may be used.

第二環氧樹脂34可與第一環氧樹脂24相同或不同。 The second epoxy resin 34 may be the same as or different from the first epoxy resin 24.

第二環氧樹脂34亦可包括至少兩種不同的樹脂。當第二環氧樹脂34包括至少兩種樹脂時，各個環氧樹脂可位在不同的區域中。舉例而言，第三層30可包括與第二層20的第一環氧樹脂24相同的環氧樹脂以及與第一環氧樹脂24不同的環氧樹脂。在此情況下，與第一環氧樹脂24相同的環氧樹脂可配置於較靠近玻璃織物的第三層30的上部分上，且與第一環氧樹脂24不同的環氧樹脂可配置於第三層30的下部分上。 The second epoxy resin 34 may also include at least two different resins. When the second epoxy resin 34 includes at least two resins, each epoxy resin may be located in a different area. For example, the third layer 30 may include the same epoxy resin as the first epoxy resin 24 of the second layer 20 and an epoxy resin different from the first epoxy resin 24. In this case, the same epoxy resin as the first epoxy resin 24 may be disposed on the upper portion of the third layer 30 closer to the glass fabric, and an epoxy resin different from the first epoxy resin 24 may be disposed on On the lower part of the third layer 30.

第二無機填料32可包括任何在半導體包封材料中普遍使用的無機填料，而不受到限制。第二無機填料32的實例可包括二氧化矽、碳酸鈣、碳酸鎂、氧化鋁、二氧化鈰、氧化鎂、粘土、 滑石、矽酸鈣、氧化鈦、氧化銻、玻璃織物等。所述化合物可以單獨或組合的方式使用。在例示性實施例中，可使用二氧化矽。 The second inorganic filler 32 may include any inorganic filler commonly used in semiconductor encapsulating materials without limitation. Examples of the second inorganic filler 32 may include silica, calcium carbonate, magnesium carbonate, alumina, ceria, magnesia, clay, Talc, calcium silicate, titanium oxide, antimony oxide, glass fabric, etc. The compounds can be used alone or in combination. In the exemplary embodiment, silicon dioxide may be used.

第二無機填料32的最長直徑可不大於第三層30的厚度的一半(二分之一)，例如不大於第三層30的厚度的三分之一。當第二無機填料32的最長直徑大於第三層30的厚度的一半(二分之一)時，會降低半導體包封構件的造模性(moldability)與填充性(filling ability)。 The longest diameter of the second inorganic filler 32 may not be greater than half (half) the thickness of the third layer 30, for example, not greater than one third of the thickness of the third layer 30. When the longest diameter of the second inorganic filler 32 is greater than half (half) of the thickness of the third layer 30, the moldability and filling ability of the semiconductor encapsulating member will be reduced.

在執行程序中，第二無機填料32的最長直徑可為0.5微米至60微米，例如1微米至30微米。在例示性實施例中，第二無機填料32的最長直徑可為1微米、2微米、3微米、4微米、5微米、6微米、7微米、8微米、9微米、10微米、11微米、12微米、13微米、14微米、15微米、16微米、17微米、18微米、19微米、20微米、21微米、22微米、23微米、24微米、25微米、26微米、27微米、28微米、29微米或30微米。 In the execution procedure, the longest diameter of the second inorganic filler 32 may be 0.5 μm to 60 μm, for example, 1 μm to 30 μm. In an exemplary embodiment, the longest diameter of the second inorganic filler 32 may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 microns, 13 microns, 14 microns, 15 microns, 16 microns, 17 microns, 18 microns, 19 microns, 20 microns, 21 microns, 22 microns, 23 microns, 24 microns, 25 microns, 26 microns, 27 microns, 28 microns , 29 microns or 30 microns.

第二無機填料32的最大直徑可與第一無機填料22的最大直徑相同或不同。 The maximum diameter of the second inorganic filler 32 may be the same as or different from the maximum diameter of the first inorganic filler 22.

第三層30可包括5wt%至99wt%的第二環氧樹脂34，例如5wt%至80wt%，特別是15wt%至70wt%，尤其是25wt%至60wt%，以及包括1wt%至95wt%的第二無機填料32，例如1wt%至85wt%，特別是5wt%至70wt%，尤其是10wt%至50wt%。在例示性實施例中，第三層30可包括25wt%、30wt%、35wt%、40wt%、45wt%、50wt%、55wt%或60wt%的第二環氧樹脂34， 以及包括10wt%、15wt%、20wt%、25wt%、30wt%、35wt%、40wt%、45wt%、50wt%或55wt%的第二無機填料32。在此範圍內，半導體包封構件可展現良好的造模性。 The third layer 30 may include 5 wt% to 99 wt% of the second epoxy resin 34, for example, 5 wt% to 80 wt%, especially 15 wt% to 70 wt%, especially 25 wt% to 60 wt%, and including 1 wt% to 95 wt% The second inorganic filler 32 is, for example, 1 wt% to 85 wt%, especially 5 wt% to 70 wt%, especially 10 wt% to 50 wt%. In an exemplary embodiment, the third layer 30 may include 25wt%, 30wt%, 35wt%, 40wt%, 45wt%, 50wt%, 55wt%, or 60wt% second epoxy resin 34, And the second inorganic filler 32 including 10wt%, 15wt%, 20wt%, 25wt%, 30wt%, 35wt%, 40wt%, 45wt%, 50wt% or 55wt%. Within this range, the semiconductor encapsulation member can exhibit good moldability.

在執行程序中，第三層30可較第二層20厚。在例示性實施例中，第三層30的厚度可為第二層20的至少兩倍，例如兩倍到五倍。當配置於玻璃織物的下部分上的層是厚的，半導體晶片可在模製製程中免於損傷，且包封構件可具有改善的流動性，從而進一步改善窄縫填充特性。 In the execution procedure, the third layer 30 may be thicker than the second layer 20. In an exemplary embodiment, the thickness of the third layer 30 may be at least twice that of the second layer 20, for example, two to five times. When the layer disposed on the lower portion of the glass fabric is thick, the semiconductor wafer can be protected from damage during the molding process, and the encapsulation member can have improved fluidity, thereby further improving the slot filling characteristics.

在執行程序中，第三層30的厚度可約為10微米至425微米，例如20微米至425微米，特別是40微米至210微米，尤其是50微米至150微米。在例示性實施例中，第三層30的厚度可為50微米、55微米、60微米、65微米、70微米、75微米、80微米、85微米、90微米、95微米、100微米、105微米、110微米、115微米、120微米、125微米、130微米、135微米、140微米、145微米或150微米。在此範圍內，半導體包封構件可確保良好的流動性與封裝填充特性。 In the execution procedure, the thickness of the third layer 30 may be about 10 μm to 425 μm, such as 20 μm to 425 μm, especially 40 μm to 210 μm, especially 50 μm to 150 μm. In an exemplary embodiment, the thickness of the third layer 30 may be 50 microns, 55 microns, 60 microns, 65 microns, 70 microns, 75 microns, 80 microns, 85 microns, 90 microns, 95 microns, 100 microns, 105 microns , 110 microns, 115 microns, 120 microns, 125 microns, 130 microns, 135 microns, 140 microns, 145 microns, or 150 microns. Within this range, the semiconductor encapsulation member can ensure good fluidity and package filling characteristics.

如圖1所示，第三層30可包括最長直徑相同的一種無機填料。在另一例示性實施例中，第三層30可具有最長直徑各不同的至少兩種無機填料。 As shown in FIG. 1, the third layer 30 may include an inorganic filler with the same longest diameter. In another exemplary embodiment, the third layer 30 may have at least two inorganic fillers with different longest diameters.

當第三層30包括最長直徑各不同的至少兩種無機填料時，第三層30可分為：其中有第一最長直徑的無機填料配置的第一區域30a以及其中有第二最長直徑的無機填料配置的第二區域 30b。第一最長直徑大於第二最長直徑。在圖2中，最大直徑較大的無機填料配置於第三層30的下部分上。然而，本發明的實施例不以此為限，且最大直徑較大的無機填料可配置於第三層30的上部分上，而最大直徑較小的無機填料可配置於第三層30的下部分上。 When the third layer 30 includes at least two types of inorganic fillers with different longest diameters, the third layer 30 can be divided into: a first region 30a in which an inorganic filler with a first longest diameter is configured and an inorganic in which a second longest diameter is included Second area of packing configuration 30b. The first longest diameter is greater than the second longest diameter. In FIG. 2, the inorganic filler having a larger maximum diameter is arranged on the lower portion of the third layer 30. However, the embodiments of the present invention are not limited thereto, and the inorganic filler with a larger maximum diameter may be disposed on the upper portion of the third layer 30, and the inorganic filler with a smaller maximum diameter may be disposed below the third layer 30 Partly.

可作為第一區域30a與第二區域30b之基質(matrix)的環氧樹脂可彼此相同或不同。舉例而言，第一區域30a中可包括與第二層20的第一環氧樹脂24相同的環氧樹脂，而第二區域30b中則可包括與第一環氧樹脂24不同的環氧樹脂。 The epoxy resins that can be the matrix of the first region 30a and the second region 30b may be the same or different from each other. For example, the first region 30a may include the same epoxy resin as the first epoxy resin 24 of the second layer 20, and the second region 30b may include an epoxy resin different from the first epoxy resin 24 .

除了環氧樹脂及無機填料，第二層20中的第一環氧樹脂組成物與第三層30中的第二環氧樹脂組成物可各進一步包括固化劑(curing agent)、固化加速劑(curing accelerator)、耦合劑(coupling agent)、脫模劑(release agent)、著色劑(coloring agent)等。 In addition to the epoxy resin and the inorganic filler, the first epoxy resin composition in the second layer 20 and the second epoxy resin composition in the third layer 30 may each further include a curing agent (curing agent) and a curing accelerator ( curing accelerator, coupling agent, release agent, coloring agent, etc.

在例示性實施例中，所述固化劑可包括任何在半導體包封構件中普遍使用的固化劑。固化劑的實例可包括酚芳烷基酚樹脂、苯酚酚醛清漆酚樹脂、木糖酚樹脂、甲酚酚醛酚樹脂、萘酚酚樹脂、萜烯酚樹脂、多官能酚樹脂、二環戊二烯酚樹脂、由雙酚A和甲階酚樹脂合成的酚醛清漆酚樹脂、包括三(羥基苯基)甲烷或二羥基聯苯的多元酚化合物、包括包括馬來酸酐或鄰苯二甲酸酐的酸酐、例如間苯二胺的芳族胺、二氨基二苯甲烷、二胺二苯碸等，而不受到限制。 In an exemplary embodiment, the curing agent may include any curing agent commonly used in semiconductor encapsulation members. Examples of the curing agent may include phenol aralkyl phenol resin, phenol novolac phenol resin, xylose phenol resin, cresol novolac phenol resin, naphthol phenol resin, terpene phenol resin, polyfunctional phenol resin, dicyclopentadiene Phenol resin, novolak phenol resin synthesized from bisphenol A and resol resin, polyphenol compound including tris(hydroxyphenyl)methane or dihydroxybiphenyl, including anhydride including maleic anhydride or phthalic anhydride For example, aromatic amines such as m-phenylenediamine, diaminodiphenylmethane, diamine diphenylbenzene, etc., without limitation.

基於環氧樹脂組成物的總重量，固化劑的量可為1wt%至40wt%，例如3wt%至35wt%。在例示性實施例中，基於環氧樹脂組成物的總重量，固化劑的量可為3wt%、4wt%、5wt%、6wt%、7wt%、8wt%、9wt%、10wt%、11wt%、12wt%、13wt%、14wt%、15wt%、16wt%、17wt%、18wt%、19wt%、20wt%、21wt%、22wt%、23wt%、24wt%、25wt%、26wt%、27wt%、28wt%、29wt%、30wt%、31wt%、32wt%、33wt%、34wt%或35wt%。 Based on the total weight of the epoxy resin composition, the amount of the curing agent may be 1 wt% to 40 wt%, for example, 3 wt% to 35 wt%. In an exemplary embodiment, based on the total weight of the epoxy resin composition, the amount of the curing agent may be 3wt%, 4wt%, 5wt%, 6wt%, 7wt%, 8wt%, 9wt%, 10wt%, 11wt%, 12wt%, 13wt%, 14wt%, 15wt%, 16wt%, 17wt%, 18wt%, 19wt%, 20wt%, 21wt%, 22wt%, 23wt%, 24wt%, 25wt%, 26wt%, 27wt%, 28wt% , 29wt%, 30wt%, 31wt%, 32wt%, 33wt%, 34wt% or 35wt%.

固化加速劑可加速環氧樹脂與固化劑的反應。固化加速劑的實例可包括三級胺(tertiary amine)、有機金屬化合物、有機磷化合物、咪唑(imidazole)、硼化合物等。三級胺的實例可包括苯甲基二甲胺(benzyldimethylamine)、三乙醇胺(triethanolamine)、三伸乙基二胺(triethylenediamine)、二乙基氨基乙醇(diethylaminoethanol)、三(二甲基氨基甲基)苯酚(tri(dimethylaminomethyl)phenol)、2,2-(二甲基氨基甲基)苯酚(2,2-(dimethylaminomethyl)pheno)、2,4,6-三(二氨基甲基)苯酚(2,4,6-tris(diaminomethyl)phenol)、三-2-乙基己酸(tri-2-ethylhexanoate)等。基於環氧樹脂組成物的總重量，固化加速劑的量可為0.01wt%至2wt%，例如0.02wt%至1.5wt%，特別是0.05wt%至1wt%。在例示性實施例中，基於環氧樹脂組成物的總重量，固化加速劑的量可為0.05wt%、0.1wt%、0.2wt%、0.3wt%、0.4wt%、0.5wt%、0.6wt%、0.7wt%、0.8wt%、0.9wt% 或1wt%。在此範圍內，可加速環氧樹脂組成物的固化反應，亦可改善固化程度。 The curing accelerator can accelerate the reaction of the epoxy resin and the curing agent. Examples of the curing accelerator may include tertiary amine, organometallic compound, organophosphorus compound, imidazole, boron compound, and the like. Examples of the tertiary amine may include benzyldimethylamine, triethanolamine, triethylenediamine, diethylaminoethanol, tri(dimethylaminomethyl) )Phenol (tri(dimethylaminomethyl)phenol), 2,2-(dimethylaminomethyl)phenol (2,2-(dimethylaminomethyl)pheno), 2,4,6-tris(diaminomethyl)phenol (2 , 4,6-tris (diaminomethyl) phenol), tri-2-ethylhexanoate (tri-2-ethylhexanoate), etc. Based on the total weight of the epoxy resin composition, the amount of the curing accelerator may be 0.01 wt% to 2 wt%, for example, 0.02 wt% to 1.5 wt%, especially 0.05 wt% to 1 wt%. In an exemplary embodiment, based on the total weight of the epoxy resin composition, the amount of the curing accelerator may be 0.05wt%, 0.1wt%, 0.2wt%, 0.3wt%, 0.4wt%, 0.5wt%, 0.6wt %, 0.7wt%, 0.8wt%, 0.9wt% Or 1wt%. Within this range, the curing reaction of the epoxy resin composition can be accelerated, and the degree of curing can also be improved.

耦合劑可改善環氧樹脂與無機填料之間的界面強度(interfacial strength)。舉例而言，耦合劑可包括矽烷耦合劑。為了改善環氧樹脂與無機填料的介面強度，矽烷耦合劑可為任何可在環氧樹脂與無機填料之間反應的耦合劑，而不受限制。矽烷耦合劑的實例可包括環氧矽烷、氨基矽烷、脲基矽烷、氫硫基矽烷等。所述矽烷耦合劑可以單獨或組合的方式使用。 The coupling agent can improve the interfacial strength between the epoxy resin and the inorganic filler. For example, the coupling agent may include a silane coupling agent. In order to improve the interface strength of the epoxy resin and the inorganic filler, the silane coupling agent can be any coupling agent that can react between the epoxy resin and the inorganic filler without limitation. Examples of the silane coupling agent may include epoxy silane, amino silane, urea silane, hydrogen sulfide silane, and the like. The silane coupling agent may be used alone or in combination.

基於環氧樹脂組成物的總重量，耦合劑的量可為0.01wt%至5wt%，例如0.05wt%至3wt%，特別是0.1wt%至2wt%。在例示性實施例中，基於環氧樹脂組成物的總重量，耦合劑的量可為0.1wt%、0.2wt%、0.3wt%、0.4wt%、0.5wt%、0.6wt%、0.7wt%、0.8wt%、0.9wt%、1wt%、1.1wt%、1.2wt%、1.3wt%、1.4wt%、1.5wt%、1.6wt%、1.7wt%、1.8wt%、1.9wt%或2wt%。在此範圍內，可改善固化後的環氧樹脂組成物的強度。 Based on the total weight of the epoxy resin composition, the amount of the coupling agent may be 0.01 wt% to 5 wt%, for example, 0.05 wt% to 3 wt%, especially 0.1 wt% to 2 wt%. In an exemplary embodiment, based on the total weight of the epoxy resin composition, the amount of the coupling agent may be 0.1wt%, 0.2wt%, 0.3wt%, 0.4wt%, 0.5wt%, 0.6wt%, 0.7wt% , 0.8wt%, 0.9wt%, 1wt%, 1.1wt%, 1.2wt%, 1.3wt%, 1.4wt%, 1.5wt%, 1.6wt%, 1.7wt%, 1.8wt%, 1.9wt% or 2wt% . Within this range, the strength of the cured epoxy resin composition can be improved.

脫模劑可包括從以下組成族群中選出的至少一者：石蠟、酯蠟、高脂肪酸、高脂肪酸的金屬鹽、天然脂肪酸和天然脂肪酸的金屬鹽。 The release agent may include at least one selected from the group consisting of paraffin wax, ester wax, high fatty acid, metal salt of high fatty acid, natural fatty acid, and metal salt of natural fatty acid.

基於環氧樹脂組成物的總重量，脫模劑的量可為0.1wt%至1wt%。舉例而言，基於環氧樹脂組成物的總重量，脫模劑的量可為0.1wt%、0.2wt%、0.3wt%、0.4wt%、0.5wt%、0.6wt%、0.7wt%、0.8wt%、0.9wt%或1wt%。 Based on the total weight of the epoxy resin composition, the amount of the release agent may be 0.1 wt% to 1 wt%. For example, based on the total weight of the epoxy resin composition, the amount of the release agent may be 0.1wt%, 0.2wt%, 0.3wt%, 0.4wt%, 0.5wt%, 0.6wt%, 0.7wt%, 0.8 wt%, 0.9wt% or 1wt%.

著色劑可用於半導體裝置包封構件的雷射標記，且亦可使用此技術領域中已知的任何著色劑而不受特別限制。著色劑的實例可包括以下至少一者：碳黑、鈦黑、氮化鈦、磷酸氫氧化二銅(dicopper hydroxide phosphate)、氧化鐵以及雲母。 The colorant can be used for laser marking of the encapsulating member of the semiconductor device, and any colorant known in this technical field can also be used without particular limitation. Examples of the colorant may include at least one of carbon black, titanium black, titanium nitride, dicopper hydroxide phosphate, iron oxide, and mica.

基於環氧樹脂組成物的總重量，著色劑的量可為0.01wt%至5wt%，例如0.05wt%至3wt%，特別是0.1wt%至2wt%。在例示性實施例中，基於環氧樹脂組成物的總重量，著色劑的量可為0.1wt%、0.2wt%、0.3wt%、0.4wt%、0.5wt%、0.6wt%、0.7wt%、0.8wt%、0.9wt%、1wt%、1.1wt%、1.2wt%、1.3wt%、1.4wt%、1.5wt%、1.6wt%、1.7wt%、1.8wt%、1.9wt%或2wt%。 Based on the total weight of the epoxy resin composition, the amount of the colorant may be 0.01 wt% to 5 wt%, for example, 0.05 wt% to 3 wt%, especially 0.1 wt% to 2 wt%. In an exemplary embodiment, based on the total weight of the epoxy resin composition, the amount of the colorant may be 0.1wt%, 0.2wt%, 0.3wt%, 0.4wt%, 0.5wt%, 0.6wt%, 0.7wt% , 0.8wt%, 0.9wt%, 1wt%, 1.1wt%, 1.2wt%, 1.3wt%, 1.4wt%, 1.5wt%, 1.6wt%, 1.7wt%, 1.8wt%, 1.9wt% or 2wt% .

另外，根據實施例的環氧樹脂組成物可進一步包括應力消除劑(stress relieving agent)，例如矽油(silicon oil)、矽粉末(silicon powder)、矽樹脂等；抗氧化劑，例如四[亞甲基-3-(3,5-二叔丁基-4-羥基苯基)丙酸酯]甲烷(tetrakis[methylene-3-(3,5-di-tertbutyl-4-hydroxyphenyl)propionate]methane)等。 In addition, the epoxy resin composition according to the embodiment may further include a stress relieving agent, such as silicon oil, silicon powder, silicone resin, etc.; an antioxidant, such as tetramethylene -3-(3,5-di-tert-butyl-4-hydroxyphenyl)propionate]methane (tetrakis[methylene-3-(3,5-di-tertbutyl-4-hydroxyphenyl)propionate]methane), etc.

根據實施例的膜式半導體包封構件可使用以下方法製備：配置玻璃織物在第一離型膜上、接著在玻璃織物上塗佈第一環氧樹脂組成物、乾燥第一環氧樹脂組成物以形成第一膜、在第二離型膜上塗佈第二環氧樹脂組成物、乾燥第二環氧樹脂組成物以形成第二膜、以及使第一膜與第二膜組合。組合製程可使用接合構件(例如：接合劑或黏著劑)或藉由在壓力與高溫下層壓第 一膜與第二膜而形成。 The film-type semiconductor encapsulating member according to the embodiment may be prepared using the following method: disposing a glass fabric on the first release film, then coating the first epoxy resin composition on the glass fabric, and drying the first epoxy resin composition To form a first film, apply a second epoxy resin composition on the second release film, dry the second epoxy resin composition to form a second film, and combine the first film with the second film. The combined process can use bonding members (for example: bonding agent or adhesive) or by laminating under pressure and high temperature A film and a second film are formed.

藉由以上方法所製備的膜式半導體包封構件可具有膜的形狀。因此，半導體包封構件可用於製造大面積的半導體裝置，例如晶圓級封裝或面板級封裝。 The film-type semiconductor encapsulating member prepared by the above method may have the shape of a film. Therefore, the semiconductor encapsulation member can be used to manufacture large-area semiconductor devices, such as wafer-level packaging or panel-level packaging.

根據實施例的膜式半導體包封構件可包括玻璃織物以使半導體封裝結構有高韌性(stiffness)，並可實現高可靠性半導體封裝的製造。 The film-type semiconductor encapsulation member according to the embodiment may include a glass fabric to give the semiconductor package structure high stiffness, and may realize the manufacture of a highly reliable semiconductor package.

根據實施例的膜式半導體包封構件可包括在玻璃織物的下部分上配置的厚的第三層，以使其在封裝模製過程中具有良好的流動性、造模性、階梯覆蓋特性(step covering property)以及填充性。 The film-type semiconductor encapsulation member according to the embodiment may include a thick third layer disposed on the lower portion of the glass fabric so that it has good fluidity, moldability, and step coverage characteristics during the package molding process ( step covering property) and filling.

製造半導體封裝的方法Method for manufacturing semiconductor package

下文中，將根據本發明的實施例說明製造半導體封裝的方法。 Hereinafter, a method of manufacturing a semiconductor package will be explained according to an embodiment of the present invention.

根據本發明實施例的半導體封裝的製造方法可包括使用根據本發明實施例的上述膜式半導體包封構件來包封半導體裝置。 The method of manufacturing a semiconductor package according to an embodiment of the present invention may include encapsulating a semiconductor device using the above-described film-type semiconductor encapsulating member according to an embodiment of the present invention.

可藉由此技術領域中普遍使用的半導體包封方法進行包封製程。舉例而言，可使用壓縮模製或層壓。 The encapsulation process can be performed by the semiconductor encapsulation method commonly used in the technical field. For example, compression molding or lamination can be used.

在例示性實施例中，半導體封裝的製造方法可藉由進行晶圓級封裝或面板級封裝並接著形成重佈線層而實施。舉例而 言，半導體封裝可藉由以下製程製造。 In an exemplary embodiment, a method of manufacturing a semiconductor package may be implemented by performing wafer-level packaging or panel-level packaging and then forming a redistribution layer. For example In other words, the semiconductor package can be manufactured by the following process.

暫時固定構件(例如：黏合膠帶或熱釋放膠帶)可貼附至載體構件(例如：載體晶圓或載體板)的一個表面上，從而製備具有暫時固定構件貼附至載體構件的一個表面上的載體構件。 The temporary fixing member (for example: adhesive tape or heat release tape) can be attached to one surface of the carrier member (for example: carrier wafer or carrier plate), thereby preparing the one having the temporary fixing member attached to the one surface of the carrier member Carrier member.

多個半導體晶片藉由例如取放法(pick-and-place method)的製程而重新配置於暫時固定構件上。 A plurality of semiconductor chips are rearranged on the temporary fixing member through a process such as a pick-and-place method.

在完成所述多個半導體晶片的重新配置後，根據本發明實施例的膜式半導體包封構件配置於半導體晶片上，接著藉由模製製程(例如壓縮或層壓)形成包封層。溫度視包封構件的類型而變化，可在約120℃至約170℃的溫度下進行模製製程。 After the rearrangement of the plurality of semiconductor wafers is completed, the film-type semiconductor encapsulation member according to an embodiment of the present invention is disposed on the semiconductor wafer, and then an encapsulation layer is formed by a molding process (such as compression or lamination). The temperature varies depending on the type of encapsulation member, and the molding process may be performed at a temperature of about 120°C to about 170°C.

在形成包封層前，可進行預烤(pre-baking)製程以防止模製製程期間的半導體晶片位移。預烤製程可在約100℃至150℃的溫度下進行，例如約110℃至約130℃。 Before forming the encapsulation layer, a pre-baking process may be performed to prevent displacement of the semiconductor wafer during the molding process. The pre-baking process may be performed at a temperature of about 100°C to 150°C, for example, about 110°C to about 130°C.

在包封層根據上述製程形成後，包封層可自暫時固定構件分離。藉由提高溫度以在暫時固定構件(例如：黏合膠帶)中形成氣泡，可進行分離製程，但不以此為限。 After the encapsulation layer is formed according to the above process, the encapsulation layer can be separated from the temporary fixing member. By increasing the temperature to form bubbles in the temporary fixing member (for example: adhesive tape), the separation process can be performed, but not limited to this.

接著，包括重佈線層(RDL)的板在半導體晶片上形成。藉由交替地在半導體晶片上層壓介電層與金屬層，可形成包括重佈線層的板。介電層可包括感光性聚醯亞胺(photosensitive polyimide)等，且金屬層可包括銅等，但不以此為限。可不受限制地使用此技術領域中已知的各種介電層與金屬層。重佈線層可包括光阻劑(photoresist)，例如聚苯並唑(polybenzoazole)，但 不以此為限。可不受限制地使用此技術領域中已知的各種重佈線層。 Next, a board including a redistribution layer (RDL) is formed on the semiconductor wafer. By alternately laminating a dielectric layer and a metal layer on the semiconductor wafer, a board including a redistribution layer can be formed. The dielectric layer may include photosensitive polyimide, etc., and the metal layer may include copper, etc., but not limited thereto. Various dielectric layers and metal layers known in this technical field can be used without limitation. The redistribution layer may include photoresist, such as polybenzoazole, but Not limited to this. Various redistribution layers known in this technical field can be used without limitation.

外部端子(例如：焊球)可在板的下表面上形成，然後可經由切割(dicing)製程製造單獨的半導體封裝。 External terminals (eg, solder balls) may be formed on the lower surface of the board, and then a separate semiconductor package may be manufactured through a dicing process.

半導體封裝Semiconductor packaging

以下將說明根據本發明實施例的半導體封裝。圖3至圖5各說明根據本發明實施例的半導體封裝。 Hereinafter, a semiconductor package according to an embodiment of the present invention will be described. 3 to 5 each illustrate a semiconductor package according to an embodiment of the present invention.

如圖3至圖5中所示，上述根據本發明實施例的膜式半導體包封構件可包封根據本發明實施例的半導體封裝。 As shown in FIGS. 3 to 5, the above-mentioned film-type semiconductor encapsulation member according to an embodiment of the present invention may encapsulate a semiconductor package according to an embodiment of the present invention.

在例示性實施例中，根據本發明實施例的半導體封裝可包括：板300、至少一個半導體晶片200a及/或半導體晶片200b、自根據實施例的膜式半導體包封構件製備的包封層100以及外部端子400。 In an exemplary embodiment, a semiconductor package according to an embodiment of the present invention may include: a board 300, at least one semiconductor wafer 200a and/or semiconductor wafer 200b, and an encapsulation layer 100 prepared from the film-type semiconductor encapsulation member according to the embodiment和外terminal400。 And the external terminal 400.

板300可支撐半導體晶片200a及/或半導體晶片200b，並可提供電子訊號至半導體晶片200a及/或半導體晶片200b。封裝半導體的技術領域中已知的任何板可不受限制使用。板300的實例可包括電路板、引線框架板(lead frame board)或包括重佈線層的板。 The board 300 may support the semiconductor wafer 200a and/or the semiconductor wafer 200b, and may provide electronic signals to the semiconductor wafer 200a and/or the semiconductor wafer 200b. Any board known in the technical field of packaging semiconductors can be used without limitation. Examples of the board 300 may include a circuit board, a lead frame board or a board including a redistribution layer.

電路板可包括具有以下貼附於其上的平板：絕緣材料(例如：環氧樹脂)、熱固化膜(例如：聚醯亞胺)或耐熱有機膜(例如：液晶聚酯膜或聚醯胺膜)。電路圖案可在電路板上形成，且電 路圖案可包括用於供給電力的電力供給佈線、接地佈線以及用於傳送訊號的訊號佈線。這些佈線可藉由絕緣夾層而彼此分離。舉例而言，電路板可為以印刷製程形成電路圖案於其上的印刷電路板(printed circuit board，PCB)。 The circuit board may include a flat plate having the following attached thereto: an insulating material (for example: epoxy resin), a heat-curable film (for example: polyimide), or a heat-resistant organic film (for example: liquid crystal polyester film or polyamide) membrane). The circuit pattern can be formed on the circuit board, and the The road pattern may include power supply wiring for supplying power, ground wiring, and signal wiring for transmitting signals. These wirings can be separated from each other by an insulating interlayer. For example, the circuit board may be a printed circuit board (PCB) on which circuit patterns are formed by a printing process.

引線框架板可自例如以下金屬形成：鎳、鐵、銅、鎳合金、鐵合金、銅合金等。引線框架板可包括用於安裝半導體晶片於其上的半導體晶片安裝部分，以及包括電性連接至半導體晶片的電極部分的端子部分，但不以此為限。可不受限制地使用此技術領域中普遍已知的各種引線框架板。 The lead frame plate may be formed from, for example, the following metals: nickel, iron, copper, nickel alloy, iron alloy, copper alloy, and the like. The lead frame board may include a semiconductor wafer mounting portion for mounting the semiconductor wafer thereon, and a terminal portion including an electrode portion electrically connected to the semiconductor wafer, but not limited thereto. Various lead frame boards generally known in this technical field can be used without limitation.

如圖3至圖5所示，包括重佈線層的板可包括形成在層疊結構之最外層上的重佈線層(RDL)330，在層疊結構中交替地層疊介電層310與金屬層320。舉例而言，介電層310可包括感光性聚醯亞胺，且金屬層320可包括銅，但不以此為限。可不受限制地使用此技術領域中已知的各種介電層與金屬層。重佈線層可包括光阻劑(photoresist)，例如聚苯並唑，但不以此為限。可不受限制地使用此技術領域中已知的各種用於形成重佈線層的材料。 As shown in FIGS. 3 to 5, the board including the redistribution layer may include a redistribution layer (RDL) 330 formed on the outermost layer of the stacked structure in which the dielectric layer 310 and the metal layer 320 are alternately stacked. For example, the dielectric layer 310 may include photosensitive polyimide, and the metal layer 320 may include copper, but not limited thereto. Various dielectric layers and metal layers known in this technical field can be used without limitation. The redistribution layer may include photoresist, such as polybenzoxazole, but not limited thereto. Various materials for forming a redistribution layer known in this technical field can be used without limitation.

至少一個半導體晶片200a及/或半導體晶片200b可安裝在板300上。安裝在板300上的半導體晶片的數量不受特別限制。舉例而言，如圖3與圖4所示，至少兩個半導體晶片可安裝在一個板上，且如圖5所示，一個半導體晶片可安裝在一個板上。 At least one semiconductor wafer 200 a and/or semiconductor wafer 200 b may be mounted on the board 300. The number of semiconductor wafers mounted on the board 300 is not particularly limited. For example, as shown in FIGS. 3 and 4, at least two semiconductor wafers can be mounted on one board, and as shown in FIG. 5, one semiconductor wafer can be mounted on one board.

安裝半導體晶片的方法不受特別限制，且可不受限制地 使用此技術領域中已知的任何方法。舉例而言，半導體晶片可為以倒裝晶片(flip chip)方法安裝的半導體晶片200b、以打線接合(wire bonding)方法安裝的半導體晶片200a或其組合。 The method of mounting the semiconductor wafer is not particularly limited, and may be unrestricted Any method known in this technical field is used. For example, the semiconductor wafer may be a semiconductor wafer 200b mounted by a flip chip method, a semiconductor wafer 200a mounted by a wire bonding method, or a combination thereof.

在倒裝晶片方法中，凸塊在半導體晶片的下表面上形成，且半導體晶片經由凸塊在電路板上熔接。在打線接合方法中，半導體晶片的電極部分電性連接至具有金屬打線的板。 In the flip-chip method, bumps are formed on the lower surface of the semiconductor wafer, and the semiconductor wafer is welded to the circuit board via the bumps. In the wire bonding method, the electrode portion of the semiconductor wafer is electrically connected to a board with metal wire bonding.

如圖3所示，根據本發明實施例的半導體封裝可包括至少兩個相同種類的半導體晶片。如圖4所示，根據本發明實施例的半導體封裝可包括兩種不同的半導體晶片。 As shown in FIG. 3, a semiconductor package according to an embodiment of the present invention may include at least two semiconductor wafers of the same kind. As shown in FIG. 4, a semiconductor package according to an embodiment of the present invention may include two different semiconductor wafers.

包封層100可保護半導體晶片200a及/或半導體晶片200b免於外部環境，且可形成自上述根據本發明實施例的膜式半導體包封構件。為了避免重複，將省略其詳細說明。 The encapsulation layer 100 can protect the semiconductor wafer 200a and/or the semiconductor wafer 200b from the external environment, and can be formed from the above-described film-type semiconductor encapsulation member according to an embodiment of the present invention. In order to avoid repetition, detailed descriptions thereof will be omitted.

外部端子400可在板300的下表面上形成，所述表面為板300的其上有半導體晶片200a或半導體晶片200b安裝的相對表面。外部端子400用於板300至外部供給電源的電性連接。可不受限制地使用此技術領域中已知的各種外部端子，例如引線、球狀柵格陣列等。 The external terminal 400 may be formed on the lower surface of the board 300, which is the opposite surface of the board 300 on which the semiconductor wafer 200 a or the semiconductor wafer 200 b is mounted. The external terminal 400 is used to electrically connect the board 300 to an external power supply. Various external terminals known in this technical field can be used without limitation, such as leads, a ball grid array, and the like.

在例示性實施例中，根據本發明實施例的半導體封裝可包括：包括重佈線層的板、至少一個配置於重佈線層上的半導體晶片、包封半導體晶片的包封層以及形成在板的下表面上的外部端子。包封層可由根據本發明實施例的膜式包封層製備。 In an exemplary embodiment, a semiconductor package according to an embodiment of the present invention may include: a board including a redistribution layer, at least one semiconductor wafer disposed on the redistribution layer, an encapsulation layer encapsulating the semiconductor wafer, and a substrate formed on the board External terminals on the lower surface. The encapsulation layer may be prepared by a film-type encapsulation layer according to an embodiment of the present invention.

雖然本發明已以實施例揭露如上，然其並非用以限定本 發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾。 Although the present invention has been disclosed as above with examples, it is not intended to limit the The invention, any person with ordinary knowledge in the technical field to which he belongs, can make some changes and modifications without departing from the spirit and scope of the present invention.

10:第一層 10: first floor

12:玻璃纖維 12: Fiberglass

20:第二層 20: Second floor

22:第一無機填料 22: The first inorganic filler

24:第一環氧樹脂 24: First epoxy resin

30:第三層 30: third floor

32:第二無機填料 32: Second inorganic filler

34:第二環氧樹脂 34: Second epoxy resin

Claims (13)

一種膜式半導體包封構件，包括：第一層，包括玻璃織物；第二層，形成在所述第一層上，所述第二層包括第一環氧樹脂及第一無機填料；以及第三層，形成在所述第一層的下表面上，所述第三層包括第二環氧樹脂及第二無機填料，其中所述第三層比所述第二層厚，其中所述第一無機填料的最長直徑不大於所述玻璃織物的孔洞區域的一半。 A film-type semiconductor encapsulating member, including: a first layer including a glass fabric; a second layer formed on the first layer, the second layer including a first epoxy resin and a first inorganic filler; and Three layers, formed on the lower surface of the first layer, the third layer includes a second epoxy resin and a second inorganic filler, wherein the third layer is thicker than the second layer, wherein the first The longest diameter of an inorganic filler is no more than half of the hole area of the glass fabric. 如申請專利範圍第1項所述的膜式半導體包封構件，其中所述第三層為所述第二層的至少兩倍厚。 The film-type semiconductor encapsulating member as described in item 1 of the patent application range, wherein the third layer is at least twice as thick as the second layer. 如申請專利範圍第1項所述的膜式半導體包封構件，其中所述第二無機填料的最長直徑不大於所述第三層的厚度的一半。 The film-type semiconductor encapsulating member as described in item 1 of the patent application range, wherein the longest diameter of the second inorganic filler is not greater than half the thickness of the third layer. 如申請專利範圍第1項所述的膜式半導體包封構件，其中所述第二無機填料的最長直徑與所述第一無機填料的最長直徑相同或不同。 The film-type semiconductor encapsulating member as described in item 1 of the patent application range, wherein the longest diameter of the second inorganic filler is the same as or different from the longest diameter of the first inorganic filler. 如申請專利範圍第1項所述的膜式半導體包封構件，其中所述第三層包括各具有不同最長直徑的兩種無機填料。 The film-type semiconductor encapsulating member as described in item 1 of the patent application range, wherein the third layer includes two kinds of inorganic fillers each having a different longest diameter. 如申請專利範圍第5項所述的膜式半導體包封構件，其中所述第三層包括第一區域以及第二區域，所述第一區域包括具 有第一最長直徑的無機填料，以及所述第二區域包括具有第二最長直徑的無機填料，其中所述第一最長直徑大於所述第二最長直徑。 The film-type semiconductor encapsulating member as described in item 5 of the patent application range, wherein the third layer includes a first region and a second region, and the first region includes a There is a first longest diameter inorganic filler, and the second region includes an inorganic filler having a second longest diameter, wherein the first longest diameter is greater than the second longest diameter. 一種半導體封裝的製造方法，包括使用如申請專利範圍第1項至第6項中任一項所述的膜式半導體包封構件的半導體裝置的包封。 A method for manufacturing a semiconductor package includes encapsulation of a semiconductor device using the film-type semiconductor encapsulation member as described in any one of claims 1 to 6. 如申請專利範圍第7項所述的半導體封裝的製造方法，其中所述包封以壓縮模製或層壓模製進行。 The method of manufacturing a semiconductor package as described in item 7 of the patent application range, wherein the encapsulation is performed by compression molding or laminate molding. 如申請專利範圍第7項所述的半導體封裝的製造方法，包括：製備載體構件，所述載體構件具有貼附至所述載體構件的一個表面上的暫時固定構件；在所述暫時固定構件上排列多個半導體晶片；使用所述膜式半導體包封構件在所述多個半導體晶片上形成包封層；自所述暫時固定構件分離所述包封層；在所述多個半導體晶片上形成包括重佈線層的板；在所述板的下表面上形成外部端子；以及經由切割製程形成單獨的半導體封裝。 The method for manufacturing a semiconductor package as described in item 7 of the patent application scope includes: preparing a carrier member having a temporary fixing member attached to one surface of the carrier member; on the temporary fixing member Arranging a plurality of semiconductor wafers; forming an encapsulation layer on the plurality of semiconductor wafers using the film-type semiconductor encapsulation member; separating the encapsulation layer from the temporary fixing member; forming on the plurality of semiconductor wafers A board including a redistribution layer; forming external terminals on the lower surface of the board; and forming a separate semiconductor package via a dicing process. 一種半導體封裝，以如申請專利範圍第1項至第6項中任一項所述的膜式半導體包封構件進行包封。 A semiconductor package is encapsulated with the film-type semiconductor encapsulating member as described in any one of the patent application items 1 to 6. 如申請專利範圍第10項所述的半導體封裝，包括以倒裝晶片方法安裝的半導體晶片、以打線接合方法安裝的半導體晶片或其組合。 The semiconductor package as described in item 10 of the patent application scope includes a semiconductor wafer mounted by a flip-chip method, a semiconductor wafer mounted by a wire bonding method, or a combination thereof. 如申請專利範圍第10項所述的半導體封裝，包括至少兩種不同的半導體晶片。 The semiconductor package as described in item 10 of the patent application scope includes at least two different semiconductor wafers. 如申請專利範圍第10項所述的半導體封裝，包括：板，包括重佈線層；至少一個半導體晶片，配置於所述重佈線層上；包封層，以如申請專利範圍第1項至第6項中任一項所述的膜式半導體包封構件包封所述半導體晶片；以及外部端子，在所述板的下表面上形成。 The semiconductor package as described in item 10 of the patent application scope includes: a board including a redistribution layer; at least one semiconductor wafer disposed on the redistribution layer; an encapsulation layer, as described in the patent application range of items 1 to The film-type semiconductor encapsulating member according to any one of items 6 encapsulates the semiconductor wafer; and external terminals are formed on the lower surface of the board.
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Publication number Priority date Publication date Assignee Title
TW201334644A (en) * 2011-12-02 2013-08-16 Samsung Electro Mech Prepreg and printed circuit board comprising the same
US20130319749A1 (en) * 2007-11-22 2013-12-05 Shinko Electric Industries Co., Ltd. Production method of multilayer printed wiring board and multilayer printed wiring board
JP2015179769A (en) * 2014-03-19 2015-10-08 信越化学工業株式会社 Sealant with substrate for semiconductor encapsulation, semiconductor apparatus, and manufacturing method of semiconductor apparatus
TW201618196A (en) * 2014-08-07 2016-05-16 史達晶片有限公司 Semiconductor device and method of forming double-sided fan-out wafer level package

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000124363A (en) * 1998-10-12 2000-04-28 Citizen Electronics Co Ltd Semiconductor package
JP2000294692A (en) * 1999-04-06 2000-10-20 Hitachi Ltd Resin-sealing type electronic device and manufacture of the same, ignition coil for internal combustion engine using the same device
JP5200405B2 (en) 2007-04-03 2013-06-05 住友ベークライト株式会社 Multilayer wiring board and semiconductor package
TWI407546B (en) * 2010-02-24 2013-09-01 Advanced Optoelectronic Tech Side emitting type semiconductor package
US8502367B2 (en) * 2010-09-29 2013-08-06 Stmicroelectronics Pte Ltd. Wafer-level packaging method using composite material as a base
CN104037138B (en) * 2013-03-06 2019-03-19 新科金朋有限公司 Form the semiconductor devices and method of ultra high density embedded semiconductor die package
WO2015020859A2 (en) * 2013-08-05 2015-02-12 Corning Incorporated Luminescent coatings and devices
KR20160005873A (en) * 2014-07-07 2016-01-18 삼성에스디아이 주식회사 Composition for filling agent for encapsulating organic light emitting diode, film comprising the same and organic light emitting diode display comprising the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130319749A1 (en) * 2007-11-22 2013-12-05 Shinko Electric Industries Co., Ltd. Production method of multilayer printed wiring board and multilayer printed wiring board
TW201334644A (en) * 2011-12-02 2013-08-16 Samsung Electro Mech Prepreg and printed circuit board comprising the same
JP2015179769A (en) * 2014-03-19 2015-10-08 信越化学工業株式会社 Sealant with substrate for semiconductor encapsulation, semiconductor apparatus, and manufacturing method of semiconductor apparatus
TW201618196A (en) * 2014-08-07 2016-05-16 史達晶片有限公司 Semiconductor device and method of forming double-sided fan-out wafer level package

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