WO2018040491A1 - 一种双边阵列基板行驱动电路、液晶显示面板、驱动方法 - Google Patents

一种双边阵列基板行驱动电路、液晶显示面板、驱动方法 Download PDF

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Publication number
WO2018040491A1
WO2018040491A1 PCT/CN2017/071627 CN2017071627W WO2018040491A1 WO 2018040491 A1 WO2018040491 A1 WO 2018040491A1 CN 2017071627 W CN2017071627 W CN 2017071627W WO 2018040491 A1 WO2018040491 A1 WO 2018040491A1
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Prior art keywords
pull
circuit
array substrate
substrate row
row
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English (en)
French (fr)
Inventor
曾勉
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/500,156 priority Critical patent/US10417985B2/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystal technology, and in particular, to a bilateral array substrate row driving circuit, a driving method, and a liquid crystal display panel suitable for a narrow bezel design.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the array substrate row driving technology is a technique for forming a gate driving circuit row scanning driving signal circuit on an array substrate of a liquid crystal display panel to realize a driving method of progressively scanning the gate driving circuit.
  • a gate driving circuit integrated on an array substrate using such an array substrate row driving technique is referred to as an array substrate row driving (GOA) gate driving circuit or an array substrate row driving circuit.
  • Existing GOA circuits typically include a plurality of cascaded GOA units, each stage of which corresponds to driving a level one horizontal scan line.
  • the main structure of the GOA unit includes a pull-up part, a pull-up control part, a transfer part, a key pull-down part, and a pull-down sustain circuit ( Pull-down Holding Part), and the bootstrap capacitor responsible for potential lift.
  • the pull-up circuit is mainly responsible for outputting the clock signal (Clock) as the gate signal;
  • the pull-up control circuit is responsible for controlling the opening time of the pull-up circuit, generally connecting the downlink signal or the Gate signal transmitted by the GOA circuit of the previous stage;
  • the pull-down circuit is responsible for The first time, the Gate is pulled low to the low level, that is, the Gate signal is turned off;
  • the pull-down sustain circuit is responsible for maintaining the Gate output signal and the Gate signal of the pull-up circuit (commonly referred to as the Q point) in the off state (ie, the negative potential).
  • the bootstrap capacitor (Cboast) is responsible for the secondary rise of the Q point, which is beneficial to the G(N) output of the pull-up circuit.
  • Figure 1 shows a schematic diagram of a prior art GOA circuit.
  • the N-th horizontal scanning line G(N) is charged according to the N-th stage GOA unit, and the N-th stage GOA unit includes a pull-up control circuit 100, a pull-up circuit 200, a downlink circuit 300, a pull-down circuit 500, and The capacitor 400, the first pull-down sustain circuit 600, and the second pull-down sustain circuit 700 are lifted.
  • the pull-up control circuit 100 includes a thin film transistor T11 whose gate is input with a down signal ST(N-1) from the N-1th stage GOA unit, and the drain and the source are respectively connected to the N-1th horizontal scanning line G ( N-1) and the gate signal point Q(N).
  • the pull-up circuit 200 includes a thin film transistor T21 having a gate connected to the gate signal point Q(N), a drain and a source inputting a clock signal CK and a n-th horizontal scanning line G(N), respectively.
  • the down circuit 300 includes a thin film transistor T22 whose gate is connected to the gate signal point Q(N), and the drain and source respectively input the clock signal CK and the output down signal ST(N).
  • the pull-down circuit 500 includes a thin film transistor T31 whose gate is connected to the N+1th horizontal scanning line G(N+1), and the drain and the source are respectively connected to the Nth horizontal scanning line G(N) and the input DC low voltage.
  • VSS a thin film transistor T41 whose gate is connected to the N+1th horizontal scanning line G(N+1), the drain and the source are respectively connected to the gate signal point Q(N) and the DC low voltage VSS is input.
  • the pull-down sustain circuit includes two mirrored pull-down sustain circuits, a first pull-down sustain circuit 600 and a second pull-down sustain circuit 700.
  • the frequencies of the first clock signal LC1 and the second clock signal LC2 are lower than the clock signal CK input to the pull-up circuit 200, and the first circuit point P(N) and the second circuit point K(N) are alternately placed.
  • the high potential allows the two pull-down sustain circuits to work in turn to mitigate the adverse effects of their transistors in the DCStress state for long periods of time.
  • each GOA circuit unit includes two pull-down maintaining circuits.
  • the “narrow bezel” of the TV means that there is no obvious frame gland on the display panel of the display, which makes the appearance of the TV look simple and bright and stylish.
  • the narrow framed TV set has become the trend of LCD TV development with its simple and stylish appearance.
  • the bilateral drive design of the GOA circuit unit with two pull-down sustain circuits will not meet the requirements of the design of the narrow bezel display panel because of the large size of the GOA circuit unit. Therefore, the requirements of the GOA drive requirements are met. Under the circumstance, it is an urgent problem to reduce the size of the structure as much as possible.
  • the present invention is to solve the existing bilateral drive design of a GOA circuit unit having two pull-down sustain circuits.
  • the structure size of the GOA circuit unit is large, which is not enough to better meet the problem of the design of the narrow bezel display panel.
  • a double-sided array substrate row driving circuit wherein two rows of array substrate row driving units in the same row share a set of pull-down maintaining circuits.
  • the clock signal of the pull-down sustain circuit is a high frequency CK or an XCK signal inverted from CK, and the odd-numbered rows on the left side are the same as the clock signal potentials of the even-numbered-row pull-down sustain circuits on the right side, and the odd-numbered rows and even-numbered rows are pulled down to maintain the clock of the circuit.
  • the signal potential is reversed.
  • the multi-level array substrate row driving units having the same structure are respectively disposed on the left and right sides, and each row of the array substrate row driving unit includes a pull-up control circuit, a pull-up circuit, a downlink circuit, a bootstrap capacitor, a pull-down circuit, and a pull-down sustain circuit. .
  • the switching element T72 is further included, and the switching element T72 and the pull-down maintaining circuit simultaneously pull down the Gate output signal of the first-stage array substrate row driving unit.
  • the switching element is a metal oxide field effect transistor.
  • liquid crystal display panel comprising the bilateral array substrate row driving circuit of any of the above preferred embodiments is provided.
  • a display comprising the above liquid crystal display panel.
  • a method for driving a double-sided array substrate row includes: setting a multi-level array substrate row driving unit with the same structure on the left and right sides, and setting a pull-down maintaining circuit for each row of the array substrate driving unit.
  • the row-array driving units of the two-sided array substrate in the same row share a set of pull-down sustain circuits, and the potentials of the clock signals of the pull-down sustain circuits on both sides of the same row are complementary; the odd-numbered row clock signals and the even-numbered row clocks of the pull-down sustain circuits on the same side
  • the potentials of the signals are complementary.
  • the clock signal of the pull-down sustain circuit is a high frequency CK or an XCK signal inverted from CK.
  • the switching element T72 is used in cooperation with the pull-down maintaining circuit to jointly pull down the Gate output signal of the first-order array substrate row driving unit.
  • Each stage of the GOA driving circuit of the invention saves a pull-down maintaining circuit, and shares a set of pull-down maintaining circuits with the GOA driving circuit of the opposite side, and controls the working state by setting the potential of the clock signal to complete the pull-down maintaining function.
  • the scale of the circuit layout can be shortened to a large extent. Inch, so that the required border of the panel is narrower, which is conducive to the design of the narrow bezel.
  • FIG. 1 is a circuit schematic diagram of a prior art array substrate row drive (GOA) driving unit
  • FIG. 2 is a layout view of a bilateral array substrate row drive (GOA) driven display
  • FIG. 3 is a schematic circuit diagram of an array substrate row driving (GOA) driving unit (right side) according to Embodiment 1 of the present invention
  • FIG. 4 is a schematic circuit diagram of an array substrate row drive (GOA) driving unit (left side) according to Embodiment 1 of the present invention
  • FIG. 5 is a schematic circuit diagram of an array substrate row drive (GOA) driving unit (right side) according to a second embodiment of the present invention
  • FIG. 6 is a schematic circuit diagram of an array substrate row drive (GOA) driving unit (left side) according to a second embodiment of the present invention
  • FIG. 7 is a waveform diagram of an array substrate row drive (GOA) drive circuit signal.
  • the present invention proposes a small-sized array substrate row drive (GOA) drive circuit and a liquid crystal display panel fabricated using the array substrate row drive (GOA) drive circuit.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • FIG 3 and 4 are schematic diagrams showing the principle of an array substrate row drive (GOA) driving circuit in the first embodiment.
  • GAA array substrate row drive
  • the double-sided array substrate row driving circuit is used for manufacturing a narrow-border liquid crystal display panel.
  • the middle of the narrow-border liquid crystal display panel is an AA display area, and the left side is provided with a multi-level array substrate row driving (GOA) driving unit (left side) 2
  • FIG. 3 shows The schematic diagram of the N-th row, right-hand array substrate row drive (GOA) drive unit; the right side is provided with a multi-level array substrate row drive (GOA) drive unit (right) 1
  • Figure 4 shows the Nth stage, Array on the left
  • a circuit schematic diagram of a column substrate row driving (GOA) driving unit which has the same structure and performs driving together.
  • Each stage array substrate row driving (GOA) driving unit includes a pull-up control circuit 100, a pull-up circuit 200, and a down-transmission circuit 300.
  • the pull-up circuit 200 includes a switching element T21 whose gate is connected to the gate signal point Q(N), the drain and the source respectively input a clock signal CK and is connected to the Nth horizontal scanning line G(N), and is mainly responsible for the clock
  • the signal (Clock) output is the gate signal.
  • the pull-up control circuit 100 includes a switching element T11 whose gate input is a downlink signal ST(N-1) from the same N-1th stage substrate row driving (GOA) driving unit, and the drain and the source are respectively connected
  • the side N-1 horizontal scanning line G(N-1) and the gate signal point Q(N) are responsible for controlling the opening time of the pull-up circuit 200, and are connected to the front-stage array substrate row driving (GOA) circuit.
  • Down signal or Gate signal is responsible for controlling the opening time of the pull-up circuit 200, and are connected to the front-stage array substrate row driving (GOA) circuit.
  • the pull-down circuit 500 includes a switching element T31 whose gate is connected to the N+1th horizontal scanning line G(N+1), and the drain and the source are respectively connected to the Nth horizontal scanning line G(N) and the input DC low voltage. VSS; switching element T41 whose gate is connected to the N+1th horizontal scanning line G(N+1), the drain and the source are respectively connected to the gate signal point Q(N) and the DC low voltage VSS is input.
  • the pull-down circuit 500 is responsible for pulling the Gate low to the low level at the first time, that is, turning off the Gate signal.
  • the down circuit 300 includes a switching element T22 whose gate is connected to the gate signal point Q(N), and the drain and source respectively input the clock signal CK and the output down signal ST(N).
  • the bootstrap capacitor 400 is the capacitor Cb in the figure.
  • the pull-down sustain circuit 600 of both sides of the same row is mirrored;
  • the frequencies of the first clock signal LC3 and the second clock signal LC4 are lower than the clock signal CK input to the pull-up circuit, and the first circuit point K(N) and the second circuit point P(N) are alternately high. Potential, so that the two pull-down sustain circuits work in turn;
  • the pull-down sustain circuit includes a switching element T32, a switching element T42, a switching element T51, a switching element T52, a switching element T53, and a switching element T54;
  • the drain and the source of the switching element T42 are respectively connected to the gate signal point Q(N) and the DC low voltage VSS is input, the gate of the switching element T42 is connected to the gate of the switching element T32, the source of the switching element T53, and the switch.
  • the drain and the source of the switching element T32 are respectively connected to the Nth horizontal scanning line G(N) and the input DC low voltage VSS;
  • the drain of the switching element T53 is connected to the first clock signal LC3 or the second clock signal LC4; the gate of the switching element T53 is connected to the source of the switching element T51 and the drain of the switching element T52;
  • the drain and the gate of the switching element T51 are connected to the first clock signal LC3 or the second clock signal LC4;
  • the gate of the switching element T52 is connected to the gate signal point Q(N), and the source of the switching element T52 is connected to the input DC low voltage VSS;
  • the gate of the switching element T54 is connected to the gate signal point Q(N), and the source of the switching element T54 is connected to the input DC low voltage VSS.
  • the two pull-down sustain circuits 600 of the left and right sides are a group, and the set of pull-down maintaining circuits 600 is responsible for maintaining the Gate output signal and the Gate signal of the pull-up circuit (generally called Q point) in the off state (ie, negative). Potential), the two pull-down sustain circuits 600 alternate; the bootstrap capacitor (Cboast) is responsible for the secondary rise of the Q point, which is beneficial to the G(N) output of the pull-up circuit.
  • each stage array substrate row drive (GOA) drive circuit retains only one pull-down sustain circuit 600, in order to ensure the array substrate row drive.
  • the pull-down maintenance function of the (GOA) drive circuit changes the drive signal of the pull-down sustain circuit 600 to CK of high frequency or XCK signal of reverse of CK.
  • the two-sided array substrate row drive (GOA) drive circuit of the same row shares a set of pull-down sustain circuits 600, that is, if the left-hand array substrate row drive (GOA) drive circuit of the odd rows uses the CK signal to drive the pull-down sustain circuit 600 of its stage, Similarly, the right array substrate row drive (GOA) drive circuit of the odd row uses another pull-down sustain circuit 600 driven by the XCK signal (potential complementary); the even-numbered row on the left side also uses the XCK signal (potential complementary) to drive its stage.
  • the circuit signal waveform diagram of the row array substrate row driving (GOA) driving circuit of the present embodiment is shown in FIG. 7.
  • the waveforms of the LC1 and the LC2 in the circuit of FIG. 1 mentioned in the background art are normally high level and constant low level.
  • Complementary, and CK and XCK of the present embodiment are not only potential complementary waveforms, but also high frequency square waves having a duty ratio of 1. That is, a set of pull-down sustain circuits of the peers inputs clock signals by pressing CK and XCK.
  • the bilateral array substrate row driving (GOA) driving circuit of the embodiment can bring the following beneficial effects:
  • Double-sided array substrate row drive (GOA) drive circuit can save one without affecting its circuit function
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • FIG 5 and 6 are schematic diagrams showing the principle of an array substrate row drive (GOA) driving circuit in the second embodiment.
  • GAA array substrate row drive
  • the double-sided array substrate row driving circuit is used for manufacturing a narrow-border liquid crystal display panel.
  • the middle of the narrow-border liquid crystal display panel is an AA display area, and the left side is provided with a multi-level array substrate row driving (GOA) driving unit (left side) 2, and FIG. 5 shows The schematic diagram of the N-th row, right-hand array substrate row drive (GOA) drive unit; the right side is provided with a multi-level array substrate row drive (GOA) drive unit (right) 1, Figure 6 shows the Nth stage, The schematic diagram of the array substrate row drive (GOA) driving unit on the left side, the two structures are the same, and the driving is completed together.
  • GOA multi-level array substrate row driving
  • Each stage array substrate row driving (GOA) driving unit includes a pull-up control circuit 100, a pull-up circuit 200, and a lower pass.
  • the pull-up circuit 200 includes a switching element T21 whose gate is connected to the gate signal point Q(N), the drain and the source respectively input a clock signal CK and is connected to the Nth horizontal scanning line G(N), and is mainly responsible for the clock
  • the signal (Clock) output is the gate signal.
  • the pull-up control circuit 100 includes a switching element T11 whose gate input is a downlink signal ST(N-1) from the same N-1th stage substrate row driving (GOA) driving unit, and the drain and the source are respectively connected
  • the side N-1 horizontal scanning line G(N-1) and the gate signal point Q(N) are responsible for controlling the opening time of the pull-up circuit 200, and are connected to the front-stage array substrate row driving (GOA) circuit.
  • Down signal or Gate signal is responsible for controlling the opening time of the pull-up circuit 200, and are connected to the front-stage array substrate row driving (GOA) circuit.
  • the pull-down circuit 500 includes a switching element T31 whose gate is connected to the N+1th horizontal scanning line G(N+1), and the drain and the source are respectively connected to the Nth horizontal scanning line G(N) and the input DC low voltage. VSS; switching element T41 whose gate is connected to the N+1th horizontal scanning line G(N+1), the drain and the source are respectively connected to the gate signal point Q(N) and the DC low voltage VSS is input.
  • the pull-down circuit 500 is responsible for pulling the Gate low to the low level at the first time, that is, turning off the Gate signal.
  • the down circuit 300 includes a switching element T22 whose gate is connected to the gate signal point Q(N), and the drain and source respectively input the clock signal CK and the output down signal ST(N).
  • the bootstrap capacitor 400 is the capacitor Cb in the figure.
  • the pull-down sustain circuit 600 of both sides of the same row is mirrored;
  • the frequencies of the first clock signal LC3 and the second clock signal LC4 are lower than the clock signal CK input to the pull-up circuit, and the first circuit point K(N) and the second circuit point P(N) are alternately high. Potential, so that the two pull-down sustain circuits work in turn;
  • the pull-down sustain circuit includes a switching element T32, a switching element T42, a switching element T51, a switching element T52, a switching element T53, and a switching element T54;
  • the drain and the source of the switching element T42 are respectively connected to the gate signal point Q(N) and the DC low voltage VSS is input, the gate of the switching element T42 is connected to the gate of the switching element T32, the source of the switching element T53, and the switch.
  • the drain and the source of the switching element T32 are respectively connected to the Nth horizontal scanning line G(N) and the input DC low voltage VSS;
  • the drain of the switching element T53 is connected to the first clock signal LC3 or the second clock signal LC4; the gate of the switching element T53 is connected to the source of the switching element T51 and the drain of the switching element T52;
  • the drain and the gate of the switching element T51 are connected to the first clock signal LC3 or the second clock signal LC4;
  • the gate of the switching element T52 is connected to the gate signal point Q(N), and the source of the switching element T52 is connected to the input DC low voltage VSS;
  • the gate of the switching element T54 is connected to the gate signal point Q(N), and the source of the switching element T54 is connected to the input DC low voltage VSS.
  • the two pull-down sustain circuits 600 of the left and right sides are a group, and the set of pull-down maintaining circuits 600 is responsible for maintaining the Gate output signal and the Gate signal of the pull-up circuit (generally called Q point) in the off state (ie, negative). Potential), the two pull-down sustain circuits 600 alternate; the bootstrap capacitor (Cboast) is responsible for the secondary rise of the Q point, which is beneficial to the G(N) output of the pull-up circuit.
  • each stage array substrate row drive (GOA) drive circuit retains only one pull-down sustain circuit 600, in order to ensure the array substrate row drive.
  • the pull-down maintenance function of the (GOA) drive circuit changes the drive signal of the pull-down sustain circuit 600 to CK of high frequency or XCK signal of reverse of CK.
  • the two-sided array substrate row drive (GOA) drive circuit of the same row shares a set of pull-down sustain circuits 600, that is, if the left-hand array substrate row drive (GOA) drive circuit of the odd rows uses the CK signal to drive the pull-down sustain circuit 600 of its stage, Similarly, the right array substrate row drive (GOA) drive circuit of the odd row uses another pull-down sustain circuit 600 driven by the XCK signal (potential complementary); the even-numbered row on the left side also uses the XCK signal (potential complementary) to drive its stage.
  • Array substrate row drive (GOA) drive The pull-down sustain circuit 600 of the circuit and the even-numbered row substrate row drive (GOA) drive circuit on the right side drive the pull-down sustain circuit 600 of the stage array substrate drive (GOA) drive circuit of the stage array using the CK signal.
  • the switching element T72 is added, and the drain and the source of the switching element T72 are respectively connected to the drain of the switching element T11 and the DC low voltage VSS is input.
  • the switching element T72 is used in cooperation with the pull-down sustaining circuit to pull down the Gate output signal of the upper-row array substrate row driving unit.
  • the circuit signal waveform diagram of the row array substrate row driving (GOA) driving circuit of the present embodiment is shown in FIG. 7.
  • the waveforms of the LC1 and the LC2 in the circuit of FIG. 1 mentioned in the background art are normally high level and constant low level.
  • Complementary, and CK and XCK of the present embodiment are not only potential complementary waveforms, but also high frequency square waves having a duty ratio of 1. That is, a set of pull-down sustain circuits of the peers inputs clock signals by pressing CK and XCK.
  • the bilateral array substrate row driving (GOA) driving circuit of the embodiment can bring the following beneficial effects:
  • the bilateral array substrate row drive (GOA) drive circuit can save space for one (two) pull-down sustain circuits 600 without affecting its circuit function, and each pull-down sustain circuit 600 contains a plurality of electronic components, visible,
  • the circuit of the embodiment effectively reduces the layout size thereof, thereby facilitating the design of the narrow bezel panel.

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Abstract

公开了一种双边阵列基板行驱动电路、液晶显示面板和驱动方法，属于液晶技术领域。该驱动电路的技术方案解决现有采用具有两个下拉维持电路的ＧＯＡ电路单元的双边驱动设计技术制作窄边框、大尺寸显示器时，因ＧＯＡ电路单元的结构尺寸大，不足以更好的满足窄边框显示器面板设计的问题。该驱动电路的方案为：处于同一行的两边阵列基板行驱动单元（1）共用一组下拉维持电路（600）。

Description

一种双边阵列基板行驱动电路、液晶显示面板、驱动方法
本申请要求享有2016年8月31日提交的名称为“一种双边阵列基板行驱动电路、液晶显示面板、驱动方法”的中国专利申请CN201610797442.2的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及液晶技术领域，尤其涉及一种适用于窄边框设计的双边阵列基板行驱动电路、驱动方法及液晶显示面板。
背景技术
目前，作为现有技术中主要的平板显示器的TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)已经成为现代IT产品和视讯产品的重要显示平台。液晶显示器被广泛使用在各种电子产品的应用中。在制造液晶显示器过程中有一项非常重要的技术就是阵列基板行驱动(Gate Driver On Array，简称GOA)技术。阵列基板行驱动技术是将栅极驱动电路行扫描驱动信号电路制作在液晶显示面板的阵列基板上，实现对栅极驱动电路逐行扫描的驱动方式的一项技术。利用这种阵列基板行驱动技术集成在阵列基板上的栅极驱动电路被称之为阵列基板行驱动(GOA)栅极驱动电路或者阵列基板行驱动电路。
现有的GOA电路通常包括级联的多个GOA单元，每一级GOA单元对应驱动一级水平扫描线。GOA单元的主要结构包括上拉电路(Pull-up part)、上拉控制电路(Pull-up control part)、下传电路(Transfer Part)、下拉电路(Key Pull-down Part)和下拉维持电路(Pull-down Holding Part)，以及负责电位抬升的自举(Boast)电容。
上拉电路主要负责将时钟信号(Clock)输出为栅极信号；上拉控制电路负责控制上拉电路的打开时间，一般连接前面级GOA电路传递过来的下传信号或者Gate信号；下拉电路负责在第一时间将Gate拉低为低电位，即关闭Gate信号；下拉维持电路则负责将Gate输出信号和上拉电路的Gate信号(通常称为Q点)维持(Holding)在关闭状态(即负电位)，通常有两个下拉维持模块交替作用；自举电容(Cboast)则负责Q点的二次抬升，这样有利于上拉电路的G(N)输出。
图1所示为现有技术的GOA电路示意图。按照第N级GOA单元控制对显示区域第N级水平扫描线G(N)充电，该第N级GOA单元包括上拉控制电路100、上拉电路200、下传电路300、下拉电路500、自举电容400、第一下拉维持电路600和第二下拉维持电路700。
上拉控制电路100包括薄膜晶体管T11，其栅极输入来自第N-1级GOA单元的下传信号ST(N-1)，漏极和源极分别连接第N-1级水平扫描线G(N-1)和该栅极信号点Q(N)。上拉电路200包括薄膜晶体管T21，其栅极连接该栅极信号点Q(N)，漏极和源极分别输入时钟信号CK和连接第n级水平扫描线G(N)。下传电路300包括薄膜晶体管T22，其栅极连接栅极信号点Q(N)，漏极和源极分别输入时钟信号CK和输出下传信号ST(N)。下拉电路500包括：薄膜晶体管T31，其栅极连接第N+1级水平扫描线G(N+1)，漏极和源极分别连接第N级水平扫描线G(N)和输入直流低电压VSS；薄膜晶体管T41，其栅极连接第N+1级水平扫描线G(N+1)，漏极和源极分别连接该栅极信号点Q(N)和输入该直流低电压VSS。
下拉维持电路包括两个镜像的下拉维持电路，第一下拉维持电路600和第二下拉维持电路700。
工作时，第一时钟信号LC1和第二时钟信号LC2的频率低于输入该上拉电路200的时钟信号CK，并且使第一电路点P(N)和第二电路点K(N)交替处于高电位，可以使得两个下拉维持电路轮流工作，以减轻其晶体管长期处于DCStress状态时的不良影响。
针对大尺寸的液晶面板，由于其RC loading(RC负载)较大，一般会采用双边驱动的设计，其示意结构如图2所示，在AA显示区两边均设计有GOA电路，由两边同时向Gate Line输入Gate驱动信号。现有设计的双边GOA驱动电路原理图如图1所示，每个GOA电路单元均包括两个下拉维持电路。
电视“窄边框”是指显示器的显示面板上无明显框架压盖，使电视外观看起来简单明快、时尚大气。窄边框化的电视机，以其简约时尚的外观成为液晶电视发展的趋势。
而采用具有两个下拉维持电路的GOA电路单元的双边驱动设计，会因GOA电路单元的结构尺寸大，不足以更好的满足窄边框显示器面板设计的要求，因此，在满足GOA驱动要求的前提下，尽可能缩小其结构尺寸是亟需解决的问题。
发明内容
本发明是为了解决现有采用具有两个下拉维持电路的GOA电路单元的双边驱动设计 技术制作窄边框、大尺寸显示器时，因GOA电路单元的结构尺寸大，不足以更好的满足窄边框显示器面板设计的问题。
一种双边阵列基板行驱动电路，处于同一行的两边阵列基板行驱动单元共用一组下拉维持电路。
优选地，下拉维持电路的时钟信号为高频CK或者与CK反向的XCK信号，左边奇数行与右边偶数行下拉维持电路的时钟信号电位相同，同边奇数行和偶数行下拉维持电路的时钟信号电位相反。
优选地，结构相同的多级阵列基板行驱动单元分别设置在左右两边，每级阵列基板行驱动单元包括上拉控制电路、上拉电路、下传电路、自举电容、下拉电路和下拉维持电路。
优选地，还包括开关元件T72，开关元件T72与下拉维持电路同时下拉上一级阵列基板行驱动单元的Gate输出信号。
优选地，所述开关元件为金属氧化物场效应晶体管。
根据本发明的另一个方面，提供了一种液晶显示面板，包括上述优选地任一项所述的双边阵列基板行驱动电路。
根据本发明的另一个方面，提供了一种显示器，包括上述的液晶显示面板。
根据本发明的另一个方面，提供了一种双边阵列基板行驱动方法，该方法为：左右两边设置结构相同的多级阵列基板行驱动单元，每级阵列基板行驱动单元设置一个下拉维持电路，处于同一行的两边阵列基板行驱动单元共用一组下拉维持电路，同一行的两边所述下拉维持电路的时钟信号的电位互补；同边的所述下拉维持电路的奇数行时钟信号和偶数行时钟信号的电位互补。
优选地，下拉维持电路的时钟信号为高频CK或者与CK反向的XCK信号。
优选地，利用开关元件T72与下拉维持电路配合，共同下拉上一级阵列基板行驱动单元的Gate输出信号。
与现有技术相比，上述方案中的具有以下优点或者有益效果：
本发明每级GOA驱动电路均节省一个下拉维持电路，与对边同行的GOA驱动电路共用一组下拉维持电路，通过设定时钟信号的电位来控制其工作状态，完成下拉维持功能。
在不影响双边阵列基板行驱动电路功能的同时，可较大程度上缩短其电路版图的尺 寸，从而使其面板所需的边框更窄，有利于窄边框的设计。
上述技术特征可以各种适合的方式组合或由等效的技术特征来替代，只要能够达到本发明的目的。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1为现有技术的阵列基板行驱动(GOA)驱动单元的电路原理图；
图2为双边阵列基板行驱动(GOA)驱动显示器的布局图；
图3为本发明实施例一的阵列基板行驱动(GOA)驱动单元(右边)电路原理图；
图4为本发明实施例一的阵列基板行驱动(GOA)驱动单元(左边)电路原理图；
图5为本发明实施例二的阵列基板行驱动(GOA)驱动单元(右边)电路原理图；
图6为本发明实施例二的阵列基板行驱动(GOA)驱动单元(左边)电路原理图；
图7为阵列基板行驱动(GOA)驱动电路信号波形图。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例。
具体实施方式
下面将结合附图对本发明作进一步说明。
在现有技术中，针对窄边框显示器面板的阵列基板行驱动(GOA)驱动电路进行设计时，通常采用双边驱动，但由于现有阵列基板行驱动(GOA)电路单元的结构尺寸大，显示器存在边框不够窄的缺陷，本发明提出了一种小尺寸的阵列基板行驱动(GOA)驱动电路及利用该阵列基板行驱动(GOA)驱动电路制成的液晶显示面板。
实施例一：
图3和图4显示实施例一中阵列基板行驱动(GOA)驱动电路的原理示意图。
该双边阵列基板行驱动电路用于窄边框液晶显示面板的制作，窄边框液晶显示面板中间为AA显示区，左边设置一个多级阵列基板行驱动(GOA)驱动单元(左边)2，图3显示的是第N级、右边的阵列基板行驱动(GOA)驱动单元的电路原理图；右边设置一个多级阵列基板行驱动(GOA)驱动单元(右边)1，图4显示的是第N级、左边的阵 列基板行驱动(GOA)驱动单元的电路原理图，二者结构相同，共同完成驱动，每级阵列基板行驱动(GOA)驱动单元包括上拉控制电路100、上拉电路200、下传电路300、自举电容400、下拉电路500和下拉维持电路600。
上拉电路200包括开关元件T21，其栅极连接该栅极信号点Q(N)，漏极和源极分别输入时钟信号CK和连接第N级水平扫描线G(N)，主要负责将时钟信号(Clock)输出为栅极信号。
上拉控制电路100包括开关元件T11，其栅极输入来自同侧第N-1级阵列基板行驱动(GOA)驱动单元的下传信号ST(N-1)，漏极和源极分别连接同侧第N-1级水平扫描线G(N-1)和该栅极信号点Q(N)，负责控制上拉电路200的打开时间，连接前面级阵列基板行驱动(GOA)电路传递过来的下传信号或者Gate信号。
下拉电路500包括：开关元件T31，其栅极连接第N+1级水平扫描线G(N+1)，漏极和源极分别连接第N级水平扫描线G(N)和输入直流低电压VSS；开关元件T41，其栅极连接第N+1级水平扫描线G(N+1)，漏极和源极分别连接该栅极信号点Q(N)和输入该直流低电压VSS。下拉电路500负责在第一时间将Gate拉低为低电位，即关闭Gate信号。
下传电路300包括开关元件T22，其栅极连接栅极信号点Q(N)，漏极和源极分别输入时钟信号CK和输出下传信号ST(N)。
自举电容400为图中电容Cb。
同一行的两边下拉维持电路600镜像设置；
左边下拉维持电路输入时钟信号LC3，右边下拉维持电路输入时钟信号LC4，
工作时，第一时钟信号LC3和第二时钟信号LC4的频率低于输入该上拉电路的时钟信号CK，并且使第一电路点K(N)和第二电路点P(N)交替处于高电位，使得两个下拉维持电路轮流工作；
下拉维持电路包括开关元件T32、开关元件T42、开关元件T51、开关元件T52、开关元件T53和开关元件T54；
开关元件T42的漏极和源极分别连接该栅极信号点Q(N)和输入该直流低电压VSS，开关元件T42的栅极连接开关元件T32的栅极、开关元件T53的源极和开关元件T54的漏极；
开关元件T32的漏极和源极分别连接第N级水平扫描线G(N)和输入直流低电压 VSS；
开关元件T53的漏极连接第一时钟信号LC3或第二时钟信号LC4；开关元件T53的栅极连接开关元件T51的源极和开关元件T52的漏极；
开关元件T51的漏极和栅极连接第一时钟信号LC3或第二时钟信号LC4；
开关元件T52的栅极连接该栅极信号点Q(N)，开关元件T52的源极连接输入直流低电压VSS；
开关元件T54的栅极连接该栅极信号点Q(N)，开关元件T54的源极连接输入直流低电压VSS。
左右两边同行的两个下拉维持电路600为一组，该组下拉维持电路600则负责将Gate输出信号和上拉电路的Gate信号(通常称为Q点)维持(Holding)在关闭状态(即负电位)，两个下拉维持电路600交替作用；自举电容(Cboast)则负责Q点的二次抬升，这样有利于上拉电路的G(N)输出。
在现有技术阵列基板行驱动(GOA)电路的基础上，为了减少结构尺寸，本实施例中每级阵列基板行驱动(GOA)驱动电路只保留一个下拉维持电路600，为了保证阵列基板行驱动(GOA)驱动电路的下拉维持功能，将下拉维持电路600的驱动信号改为高频的CK或者与CK反向的XCK信号。同一行的两边阵列基板行驱动(GOA)驱动电路共用一组下拉维持电路600，即若是奇数行的左边阵列基板行驱动(GOA)驱动电路采用CK信号驱动其所在级的下拉维持电路600，则同样奇数行的右边阵列基板行驱动(GOA)驱动电路则采用XCK信号(电位互补)驱动的另一下拉维持电路600；与其相同左边的偶数行也同样采用XCK信号(电位互补)驱动其所在级阵列基板行驱动(GOA)驱动电路的下拉维持电路600，右边的偶数行阵列基板行驱动(GOA)驱动电路则采用CK信号驱动其所在级阵列基板行驱动(GOA)驱动电路的下拉维持电路600。
采用本实施例行阵列基板行驱动(GOA)驱动电路的电路信号波形图如图7所示，背景技术提及的图1电路中的LC1、LC2波形为常高电平、常低电平的互补，而本实施例的CK、XCK不但电位互补波形，且均为占空比为1的高频方波。即同行的一组下拉维持电路按CK、XCK输入时钟信号。
基于上述分析，可见本实施例双边阵列基板行驱动(GOA)驱动电路可带来如下有益效果：
双边阵列基板行驱动(GOA)驱动电路即可在不影响其电路功能的情况下，节省一 组(两个)下拉维持电路600的空间，每个下拉维持电路600含有多个电子元件，可见，本实施例电路有效的减小了其版图尺寸，从而更有利于窄边框面板的设计。
实施例二：
图5和图6显示实施例二中阵列基板行驱动(GOA)驱动电路的原理示意图。
该双边阵列基板行驱动电路用于窄边框液晶显示面板的制作，窄边框液晶显示面板中间为AA显示区，左边设置一个多级阵列基板行驱动(GOA)驱动单元(左边)2，图5显示的是第N级、右边的阵列基板行驱动(GOA)驱动单元的电路原理图；右边设置一个多级阵列基板行驱动(GOA)驱动单元(右边)1，图6显示的是第N级、左边的阵列基板行驱动(GOA)驱动单元的电路原理图，二者结构相同，共同完成驱动，每级阵列基板行驱动(GOA)驱动单元包括上拉控制电路100、上拉电路200、下传电路300、自举电容400、下拉电路500、下拉维持电路600和开关元件T72。
上拉电路200包括开关元件T21，其栅极连接该栅极信号点Q(N)，漏极和源极分别输入时钟信号CK和连接第N级水平扫描线G(N)，主要负责将时钟信号(Clock)输出为栅极信号。
上拉控制电路100包括开关元件T11，其栅极输入来自同侧第N-1级阵列基板行驱动(GOA)驱动单元的下传信号ST(N-1)，漏极和源极分别连接同侧第N-1级水平扫描线G(N-1)和该栅极信号点Q(N)，负责控制上拉电路200的打开时间，连接前面级阵列基板行驱动(GOA)电路传递过来的下传信号或者Gate信号。
下拉电路500包括：开关元件T31，其栅极连接第N+1级水平扫描线G(N+1)，漏极和源极分别连接第N级水平扫描线G(N)和输入直流低电压VSS；开关元件T41，其栅极连接第N+1级水平扫描线G(N+1)，漏极和源极分别连接该栅极信号点Q(N)和输入该直流低电压VSS。下拉电路500负责在第一时间将Gate拉低为低电位，即关闭Gate信号。
下传电路300包括开关元件T22，其栅极连接栅极信号点Q(N)，漏极和源极分别输入时钟信号CK和输出下传信号ST(N)。
自举电容400为图中电容Cb。
同一行的两边下拉维持电路600镜像设置；
左边下拉维持电路输入时钟信号LC3，右边下拉维持电路输入时钟信号LC4，
工作时，第一时钟信号LC3和第二时钟信号LC4的频率低于输入该上拉电路的时钟信号CK，并且使第一电路点K(N)和第二电路点P(N)交替处于高电位，使得两个下拉维持电路轮流工作；
下拉维持电路包括开关元件T32、开关元件T42、开关元件T51、开关元件T52、开关元件T53和开关元件T54；
开关元件T42的漏极和源极分别连接该栅极信号点Q(N)和输入该直流低电压VSS，开关元件T42的栅极连接开关元件T32的栅极、开关元件T53的源极和开关元件T54的漏极；
开关元件T32的漏极和源极分别连接第N级水平扫描线G(N)和输入直流低电压VSS；
开关元件T53的漏极连接第一时钟信号LC3或第二时钟信号LC4；开关元件T53的栅极连接开关元件T51的源极和开关元件T52的漏极；
开关元件T51的漏极和栅极连接第一时钟信号LC3或第二时钟信号LC4；
开关元件T52的栅极连接该栅极信号点Q(N)，开关元件T52的源极连接输入直流低电压VSS；
开关元件T54的栅极连接该栅极信号点Q(N)，开关元件T54的源极连接输入直流低电压VSS。
左右两边同行的两个下拉维持电路600为一组，该组下拉维持电路600则负责将Gate输出信号和上拉电路的Gate信号(通常称为Q点)维持(Holding)在关闭状态(即负电位)，两个下拉维持电路600交替作用；自举电容(Cboast)则负责Q点的二次抬升，这样有利于上拉电路的G(N)输出。
在现有技术阵列基板行驱动(GOA)电路的基础上，为了减少结构尺寸，本实施例中每级阵列基板行驱动(GOA)驱动电路只保留一个下拉维持电路600，为了保证阵列基板行驱动(GOA)驱动电路的下拉维持功能，将下拉维持电路600的驱动信号改为高频的CK或者与CK反向的XCK信号。同一行的两边阵列基板行驱动(GOA)驱动电路共用一组下拉维持电路600，即若是奇数行的左边阵列基板行驱动(GOA)驱动电路采用CK信号驱动其所在级的下拉维持电路600，则同样奇数行的右边阵列基板行驱动(GOA)驱动电路则采用XCK信号(电位互补)驱动的另一下拉维持电路600；与其相同左边的偶数行也同样采用XCK信号(电位互补)驱动其所在级阵列基板行驱动(GOA)驱动电 路的下拉维持电路600，右边的偶数行阵列基板行驱动(GOA)驱动电路则采用CK信号驱动其所在级阵列基板行驱动(GOA)驱动电路的下拉维持电路600。
本实施例相对于实施例一而言，增加了开关元件T72，开关元件T72的漏极和源极分别连接开关元件T11的漏极和输入该直流低电压VSS。
利用开关元件T72与下拉维持电路配合，共同下拉上一级阵列基板行驱动单元的Gate输出信号。
采用本实施例行阵列基板行驱动(GOA)驱动电路的电路信号波形图如图7所示，背景技术提及的图1电路中的LC1、LC2波形为常高电平、常低电平的互补，而本实施例的CK、XCK不但电位互补波形，且均为占空比为1的高频方波。即同行的一组下拉维持电路按CK、XCK输入时钟信号。
基于上述分析，可见本实施例双边阵列基板行驱动(GOA)驱动电路可带来如下有益效果：
双边阵列基板行驱动(GOA)驱动电路即可在不影响其电路功能的情况下，节省一组(两个)下拉维持电路600的空间，每个下拉维持电路600含有多个电子元件，可见，本实施例电路有效的减小了其版图尺寸，从而更有利于窄边框面板的设计。
在实施例一的基础上只增加一个下拉晶体管，在不增加版图尺寸的同时，更好的保证下拉效果。
虽然在本文中参照了特定的实施方式来描述本发明，但是应该理解的是，这些实施例仅仅是本发明的原理和应用的示例。因此应该理解的是，可以对示例性的实施例进行许多修改，并且可以设计出其他的布置，只要不偏离所附权利要求所限定的本发明的精神和范围。应该理解的是，可以通过不同于原始权利要求所描述的方式来结合不同的从属权利要求和本文中所述的特征。还可以理解的是，结合单独实施例所描述的特征可以使用在其他所述实施例中。

Claims (13)

  1. 一种双边阵列基板行驱动电路，处于同一行的两边阵列基板行驱动单元共用一组下拉维持电路。
  2. 根据权利要求1所述的双边阵列基板行驱动电路，其中，下拉维持电路的时钟信号为高频CK或者与CK反向的XCK信号，左边奇数行与右边偶数行下拉维持电路的时钟信号电位相同，同边奇数行和偶数行下拉维持电路的时钟信号电位相反。
  3. 根据权利要求2所述的双边阵列基板行驱动电路，其中，结构相同的多级阵列基板行驱动单元分别设置在左右两边，每级阵列基板行驱动单元包括上拉控制电路、上拉电路、下传电路、自举电容、下拉电路和下拉维持电路。
  4. 根据权利要求3所述的双边阵列基板行驱动电路，其中，还包括开关元件T72，开关元件T72与下拉维持电路同时下拉上一级阵列基板行驱动单元的Gate输出信号。
  5. 根据权利要求4所述的双边阵列基板行驱动电路，其中，所述开关元件为金属氧化物场效应晶体管。
  6. 一种液晶显示面板，包括双边阵列基板行驱动电路；
    所述双边阵列基板行驱动电路，处于同一行的两边阵列基板行驱动单元共用一组下拉维持电路。
  7. 根据权利要求6所述的液晶显示面板，其中，下拉维持电路的时钟信号为高频CK或者与CK反向的XCK信号，左边奇数行与右边偶数行下拉维持电路的时钟信号电位相同，同边奇数行和偶数行下拉维持电路的时钟信号电位相反。
  8. 根据权利要求7所述的液晶显示面板，其中，结构相同的多级阵列基板行驱动单元分别设置在左右两边，每级阵列基板行驱动单元包括上拉控制电路、上拉电路、下传电路、自举电容、下拉电路和下拉维持电路。
  9. 根据权利要求8所述的液晶显示面板，其中，还包括开关元件T72，开关元件T72与下拉维持电路同时下拉上一级阵列基板行驱动单元的Gate输出信号。
  10. 根据权利要求9所述的液晶显示面板，其中，所述开关元件为金属氧化物场效应晶体管。
  11. 一种双边阵列基板行驱动方法，该方法为：左右两边设置结构相同的多级阵列基板行驱动单元，每级阵列基板行驱动单元设置一个下拉维持电路，处于同一行的两边阵列基板行驱动单元共用一组下拉维持电路，同一行的两边所述下拉维持电路的时钟信 号的电位互补；同边的所述下拉维持电路的奇数行时钟信号和偶数行时钟信号的电位互补。
  12. 根据权利要求11所述的双边阵列基板行驱动方法，其中，下拉维持电路的时钟信号为高频CK或者与CK反向的XCK信号。
  13. 根据权利要求11所述的双边阵列基板行驱动方法，其中，利用开关元件T72与下拉维持电路配合，共同下拉上一级阵列基板行驱动单元的Gate输出信号。
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