WO2018040482A1 - 一种基于ltps的coms器件及其制作方法 - Google Patents

一种基于ltps的coms器件及其制作方法 Download PDF

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WO2018040482A1
WO2018040482A1 PCT/CN2017/071286 CN2017071286W WO2018040482A1 WO 2018040482 A1 WO2018040482 A1 WO 2018040482A1 CN 2017071286 W CN2017071286 W CN 2017071286W WO 2018040482 A1 WO2018040482 A1 WO 2018040482A1
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channel
layer
ltps
type
nmos
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PCT/CN2017/071286
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English (en)
French (fr)
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石龙强
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深圳市华星光电技术有限公司
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Priority to US15/329,335 priority Critical patent/US10644161B2/en
Publication of WO2018040482A1 publication Critical patent/WO2018040482A1/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Definitions

  • the present invention belongs to the field of semiconductor technology, and in particular, to a LTPS-based COMS device and a method for fabricating the same.
  • LTPS Low Temperature Poly-silicon
  • CMOS Complementary Metal Oxide Semiconductor
  • One method for solving the above problems in the prior art is to make an LD LTPS device with an LDD (Lightly Doped Drain) structure, but since the introduction of N--Si doping, an additional process has been added, and the result is increased. production cost.
  • LDD Lightly Doped Drain
  • the present invention provides a LTPS-based COMS device and a manufacturing method thereof for reducing electron circulation speed and avoiding hot electron effects.
  • an LTPS-based COMS device including an NMOS type LTPS, wherein
  • a PN junction is provided in the channel of the NMOS type LTPS to reduce the velocity of electrons flowing in the channel to avoid the hot electron effect.
  • a P-type weight is provided at both ends of the channel of the NMOS type LTPS.
  • a P-type heavily doped region is disposed inside the channel of the NMOS type LTPS for forming a PN junction between the P-type heavily doped region and the channel of the NMOS type LTPS.
  • the P-type heavily doped region is located in the middle of the channel of the NMOS type LTPS.
  • the NMOS type LTPS further includes:
  • a buffer layer disposed under the channel layer where the channel of the NMOS type LTPS is located;
  • a gate insulating layer disposed on the channel layer where the channel of the NMOS type LTPS is located and the exposed buffer layer;
  • a gate layer disposed on the gate insulating layer
  • a dielectric layer disposed on the gate layer and the exposed gate insulating layer
  • the source drain is disposed on the dielectric layer and communicates with the both ends of the channel of the NMOS type LTPS through the via.
  • the NMOS type LTPS further includes:
  • a buffer layer disposed under the channel layer where the channel of the NMOS type LTPS is located;
  • a gate insulating layer disposed on the channel layer where the channel of the NMOS type LTPS is located and the exposed buffer layer;
  • a gate layer disposed on the gate insulating layer
  • a dielectric layer disposed on the gate layer and the exposed gate insulating layer
  • the source drain is disposed on the dielectric layer and communicates with the both ends of the channel of the NMOS type LTPS through the via.
  • the device further includes a PMOS type LTPS, wherein the PMOS type LTPS comprises:
  • a gate insulating layer disposed on the channel layer of the PMOS type LTPS and the exposed buffer layer;
  • a gate layer disposed on the gate insulating layer
  • a dielectric layer disposed on the gate layer and the exposed gate insulating layer
  • the source drain is disposed on the dielectric layer and communicates with both ends of the channel of the PMOS type LTPS through the via.
  • a method for fabricating an LTPS-based COMS device comprising:
  • a source drain of the COMS device is formed on the dielectric layer, and the source drain communicates with a corresponding P-type heavily doped processing region through the via.
  • a step of performing an N-type heavily doping process on both ends of a channel of an NMOS type LTPS channel layer, and a P-type at both ends of a channel of a PMOS type LTPS channel layer of a PMOS region are performed.
  • the order of the steps of the heavy doping treatment is interchanged.
  • the present invention is directed to the problem of the complicated LDD process, by setting a PN junction in the NMOS type LTPS channel, thereby reducing the electron circulation speed and avoiding the hot electron effect.
  • FIG. 1a is a schematic structural diagram of a device corresponding to a PMOS LTPS fabrication step according to an embodiment of the present invention
  • FIG. 1b is a schematic structural diagram of a device corresponding to an NMOS LTPS fabrication step according to an embodiment of the present invention
  • 1c is a schematic structural view of a device corresponding to a P-type heavily doped step according to an embodiment of the present invention
  • FIG. 1d is a schematic structural view of a device corresponding to a gate insulating layer fabrication step according to an embodiment of the invention
  • 1e is a schematic structural view of a device corresponding to a gate layer fabrication step according to an embodiment of the present invention
  • 1f is a schematic structural view of a device corresponding to a dielectric layer fabrication step according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view of a device corresponding to a source/drain fabrication step according to an embodiment of the invention
  • FIG. 3a is a schematic structural diagram of a device corresponding to a PMOS LTPS fabrication step according to an embodiment of the present invention
  • 3b is a schematic structural view of a device corresponding to a channel P-type heavily doped step according to an embodiment of the present invention
  • FIG. 3c is a schematic structural diagram of a device corresponding to an NMOS LTPS fabrication step according to an embodiment of the present invention
  • FIG. 3d is a schematic structural diagram of a device corresponding to an NMOS communication N-type light doping step according to an embodiment of the present invention.
  • 3e is a schematic structural view of a device corresponding to an N-type heavily doping step according to an embodiment of the present invention
  • FIG. 3f is a schematic structural view of a device corresponding to a P-type heavily doped step according to an embodiment of the present invention.
  • FIG. 4 is a block diagram showing the structure of a device corresponding to a source/drain fabrication step in accordance with an embodiment of the present invention.
  • the present invention proposes a COMS device that solves the hot carrier effect of the NMOS type LTPS.
  • the COMS device includes an NMOS type LTPS in which a PN junction useful for reducing the velocity of electrons in the channel is provided in the channel of the NMOS type LTPS to avoid the effect of hot electrons.
  • FIG. 2 is a schematic diagram showing the structure of an NMOS type LTPS according to an embodiment of the present invention.
  • the NMOS type LTPS includes, in order from bottom to top, a buffer layer disposed on the glass substrate GLA, the buffer layer including a silicon nitride SiNx layer disposed on the glass substrate GLA and an oxide disposed on the SiNx layer.
  • a silicon SiOx layer a channel layer of an NMOS type LTPS disposed on the buffer layer, the channel layer including an N-type channel N-Si and a P-type heavily doped region P+- connected to the source and the drain at both ends of the channel a gate insulating layer GI disposed on the channel layer of the NMOS type LTPS and the exposed buffer layer; a gate layer disposed on the gate insulating layer GI for forming the gate pattern G; and being disposed on the gate layer and exposed a dielectric layer ILD on the gate insulating layer GI; a source S and a drain D disposed on the dielectric layer ILD and communicating with both ends of the channel of the NMOS type LTPS.
  • the region where the source drain is in contact with the NMOS type LTPS is set as the P-type heavily doped region P+-Si, instead of the N-type heavily doped region, which may be in the P-type heavily doped region.
  • a PN junction is formed between the channel of the NMOS type LTPS.
  • the channel region of the NMOS type LTPS forms a structure of a P+NP+ type transistor.
  • P+ represents P-type heavy doping
  • N+ represents N-type heavy doping.
  • Zener diodes form a Zener diode.
  • the benefit of Zener diodes is the formation of small depletion zones where electrons slow down through the depletion zone. Electrons can pass through the depletion zone, but do not damage the device like an avalanche diode. This not only solves the hot electron effect caused by too much electron velocity, but also solves the problem of source-drain and LTPS contact, and eliminates the two N-type heavily doped N+ and N-type lightly doped N- when forming an LDD structure. Road mask.
  • FIG. 4 is a schematic diagram showing the structure of an NMOS type LTPS according to another embodiment of the present invention.
  • a P-type heavily doped region is disposed inside the channel region of the NMOS type LTPS for forming a PN junction in the P-type heavily doped region and the channel region of the NMOS-type LTPS.
  • P-type heavily doping is performed in the middle of the channel of the NMOS type LTPS to form an NP+N triode structure.
  • This structure can compare the P+ type LTPS to the railing, and the electrons need to lose a certain speed across the railing, thereby avoiding the hot electron effect and eliminating the mask required for the N-type lightly doped N-.
  • the other structure of the channel region of the NMOS type LTPS is the same as that of FIG. 2 and will not be described in detail herein.
  • the LTPS-based COMS device further includes a PMOS type LTPS.
  • the PMOS type LTPS and the NMOS type LTPS form a complete COMS device.
  • the PMOS type LTPS includes, in order from bottom to top, a buffer layer disposed on the glass substrate GLA, the buffer layer including a SiNx layer disposed on the glass substrate GLA and an SiOx layer disposed on the SiNx layer.
  • a channel layer of a PMOS type LTPS disposed on the buffer layer, the channel layer including a P-type channel P-Si and a channel region, and a source-drain connection P-type heavily doped region P+-Si; a gate insulating layer GI on the channel layer of the PMOS type LTPS and the exposed buffer layer; a gate layer disposed on the gate insulating layer GI for forming the gate pattern G; and a gate layer and a bare gate insulating layer a dielectric layer ILD on the layer GI; a source S and a drain D disposed on the dielectric layer ILD and communicating with both ends of the channel of the PMOS type LTPS.
  • a method for fabricating an LTPS-based COMS device specifically comprising the following steps:
  • a buffer layer is formed on the glass substrate GLA.
  • a CVD (Chemical Vapor Deposition) film formation technique is employed to form a SiNx layer on the substrate GLA, and then an SiOx layer is formed on the SiNx layer.
  • the PMOS type LTPS channel layer includes a P-type channel P-Si and a P-type heavily doped region P+-Si connected to the source and the drain at both ends of the channel;
  • the NMOS type LTPS channel layer includes an N-type channel N-Si And a P-type heavily doped region P+-Si connected to the source and the drain at both ends of the channel.
  • an amorphous silicon a-Si film is first formed on the buffer layer by a CVD film forming technique, and then exposed and etched to form a.
  • the -Si silicon island pattern is then crystallized by ELA to form a P-type LTPS, as shown in Figure 1a.
  • photoresist coating and exposure are performed, N-type light doping treatment is performed on the LTPS of the NMOS region, and then photoresist stripping is performed to form an NMOS type LTPS pattern (NMOS type LTPS channel layer) as shown in FIG. 1b.
  • a gate insulating layer GI is formed on the channel layer of the NMOS type LTPS and the channel layer of the PMOS type LTPS and the exposed buffer layer by a CVD film formation technique, as shown in FIG. 1d.
  • a gate layer is formed on the gate insulating layer GI.
  • a metal film is formed on the gate insulating layer GI by PVD technology, and then exposed and developed to form a gate electrode, as shown in FIG. 1e.
  • a dielectric layer ILD is formed on the gate layer and the exposed gate insulating layer, and a P-type heavily doped processing region and a PMOS-type LTPS trench at both ends of the channel connecting the NMOS-type LTPS channel layer are etched on the dielectric layer ILD. Vias in the P-type heavily doped processing region at both ends of the channel of the via layer.
  • the dielectric layer is formed by a CVD film forming technique, and then an IDL layer pattern is formed by exposure and dry etching, as shown in FIG. 1f.
  • the source and drain of the COMS device are formed on the dielectric layer IDL, and the source and drain are connected to the respective P-type heavily doped processing regions through the via holes.
  • a metal film is formed by a PVD film forming technique, and a source and drain pattern is formed by exposure and development processing.
  • the source drain communicates with the source and drain regions corresponding to the NMOS type LTPS and the PMOS type LTPS through via holes, as shown in FIG. 2 .
  • a buffer layer is formed on the glass substrate GLA.
  • a SiNx layer is formed on the substrate GLA by a CVD film forming technique, and then an SiOx layer is formed on the SiNx layer.
  • a PMOS type LTPS channel layer is formed on both the corresponding PMOS region and the NMOS region on the buffer layer, as shown in FIG. 3a.
  • a P-type heavily doping process is performed on a region inside the channel of the PMOS type LTPS channel layer of the NMOS region to obtain a P-type heavily doped region P+-Si, as shown in FIG. 3b.
  • a photoresist PR is coated on the PMOS type LTPS channel layer, and a semi-shield mask is used to illuminate a region inside the channel of the PMOS type LTPS channel layer of the NMOS region, preferably a channel intermediate region, thereby lighting the portion. Block removal.
  • the portion where the photoresist is removed is heavily doped with P-type, thereby obtaining a P-type heavily doped LTPS.
  • the photoresist corresponding to the NMOS is etched away, and the photoresist of the PMOS is retained, as shown in FIG. 3c.
  • an N-type light doping treatment is performed on the LTPS channel of the NMOS region, and then photoresist stripping is performed to form an NMOS type LTPS pattern (NMOS type LTPS channel layer) as shown in FIG. 3d.
  • N-type heavily doping treatment is performed on both ends of the LTPS a-Si silicon island pattern of the NMOS region, and then the photoresist is peeled off to form an N+-Si pattern, as shown in FIG. 3e. Shown.
  • a gate insulating layer GI is formed on the channel layer of the NMOS type LTPS channel layer and the PMOS type LTPS and the exposed buffer layer by a CVD film formation technique.
  • a gate layer is formed on the gate insulating layer GI.
  • a metal layer is formed on the gate insulating layer GI by a PVD technique, and then a gate is formed by exposure and development processing.
  • a dielectric layer ILD is formed on the gate layer and the exposed gate insulating layer, and a P-type heavily doped processing region and a PMOS type LTPS both ends of the channel connecting the NMOS type LTPS channel layer are etched on the dielectric layer ILD. Vias of the P-type heavily doped processing region at both ends of the channel of the channel layer.
  • the dielectric layer is formed by a CVD film forming technique, and then an IDL layer pattern is formed by exposure and dry etching.
  • the source and drain of the COMS device are formed on the dielectric layer, and the source and drain are connected to the respective P-type heavily doped processing regions through the via holes.
  • a metal film is formed by a PVD film forming technique, and a source and drain pattern is formed by exposure and development processing.
  • the source drain is connected to the source and drain regions corresponding to the NMOS type LTPS and the PMOS type LTPS through via holes, as shown in FIG.
  • the two steps may be interchanged in the step of forming an N+-Si pattern by N-type heavy doping and the step of forming a P+-Si pattern by P-type heavy doping.

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Abstract

一种基于LTPS的CMOS器件及其制作方法，该器件包括NMOS型LTPS，其中，在NMOS型LTPS的沟道内设置有用以降低电子在沟道内流通速度的PN结，用以避免热电子效应。可以降低电子流通速度，避免热电子效应。

Description

一种基于LTPS的COMS器件及其制作方法
相关申请的交叉引用
本申请要求享有2016年08月31日提交的名称为“一种基于LTPS的COMS器件及其制作方法”的中国专利申请CN201610794123.6的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明属于半导体技术领域，具体地说，尤其涉及一种基于LTPS的COMS器件及其制作方法。
背景技术
LTPS(Low Temperature Poly-silicon，低温多晶硅)由于具有高迁移率，并且能用来制作CMOS器件，因而得到了广泛研究。
CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)由一个NMOS和PMOS组成。其中，由于NMOS器件中电子的迁移率太高，在强电场下容易产生热电子效应，从而将器件损坏。
现有技术中一种解决以上问题的方法是做LDD(Lightly Doped Drain，轻掺杂漏结构)结构的NMOS LTPS器件，但是由于引入了N--Si掺杂，多了一道工艺，结果增加了制作成本。
发明内容
为解决以上问题，本发明提供了一种基于LTPS的COMS器件及其制作方法，用以降低电子流通速度，避免热电子效应。
根据本发明的一个方面，提供了一种基于LTPS的COMS器件，包括NMOS型LTPS，其中，
在NMOS型LTPS的沟道内设置有用以降低电子在沟道内流通速度的PN结，以避免热电子效应。
根据本发明的一个实施例，在NMOS型LTPS的沟道两端均设置有P型重 掺杂区，用以在P型重掺杂区和NMOS型LTPS的沟道之间形成PN结。
根据本发明的一个实施例，在NMOS型LTPS的沟道内部设置有一P型重掺杂区，用以在P型重掺杂区和NMOS型LTPS的沟道之间形成PN结。
根据本发明的一个实施例，所述P型重掺杂区位于NMOS型LTPS的沟道的中间。
根据本发明的一个实施例，所述NMOS型LTPS还包括：
缓冲层，设置于NMOS型LTPS的沟道所在的沟道层下；
栅绝缘层，设置于NMOS型LTPS的沟道所在的沟道层和裸露的缓冲层上；
栅极层，设置于所述栅绝缘层上；
介质层，设置于所述栅极层及裸露的栅绝缘层上；
源漏极，设置于所述介质层上并与NMOS型LTPS的沟道两端通过过孔连通。
根据本发明的一个实施例，所述NMOS型LTPS还包括：
缓冲层，设置于NMOS型LTPS的沟道所在的沟道层下；
栅绝缘层，设置于NMOS型LTPS的沟道所在的沟道层和裸露的缓冲层上；
栅极层，设置于所述栅绝缘层上；
介质层，设置于所述栅极层及裸露的栅绝缘层上；
源漏极，设置于所述介质层上并与NMOS型LTPS的沟道两端通过过孔连通。
根据本发明的一个实施例，所述器件还包括一PMOS型LTPS，其中，所述PMOS型LTPS包括：
缓冲层，设置于玻璃基板上；
沟道层，设置于所述缓冲层上；
栅绝缘层，设置于PMOS型LTPS的沟道层和裸露的缓冲层上；
栅极层，设置于所述栅绝缘层上；
介质层，设置于所述栅极层及裸露的栅绝缘层上；
源漏极，设置于所述介质层上并与PMOS型LTPS的沟道两端通过过孔连通。
根据本发明的另一个方面，还提供了一种用于制作基于LTPS的COMS器件的方法，包括：
在玻璃基板上形成缓冲层；
在所述缓冲层上对应PMOS区域和NMOS区域均形成PMOS型LTPS沟道 层；
对NMOS区域的PMOS型LTPS沟道层进行N型轻掺杂处理，以形成NMOS型LTPS沟道层；
对所述NMOS型LTPS沟道层的沟道两端和PMOS区域的PMOS型LTPS沟道层的沟道两端进行P型重掺杂处理；
在所述NMOS型LTPS沟道层、所述PMOS型LTPS沟道层和裸露的缓冲层上形成栅绝缘层；
在所述栅绝缘层上形成栅极层；
在所述栅极层及裸露的栅绝缘层上形成介质层，并在所述介质层上蚀刻连通NMOS型LTPS沟道层的沟道两端的P型重掺杂处理区域和PMOS型LTPS沟道层的沟道两端的P型重掺杂处理区域的过孔；
在所述介质层上形成所述COMS器件的源漏极，所述源漏极通过所述过孔与各自对应的P型重掺杂处理区域连通。
根据本发明的另一个方面，还提供了另一种用于制作基于LTPS的COMS器件的方法，包括：
在玻璃基板上形成缓冲层；
在所述缓冲层上对应PMOS区域和NMOS区域均形成PMOS型LTPS沟道层；
对NMOS区域的PMOS型LTPS沟道层的沟道中间区域进行P型重掺杂处理；
对NMOS区域的PMOS型LTPS沟道层的沟道进行N型轻掺杂处理以形成NMOS型LTPS沟道层；
对NMOS型LTPS沟道层的沟道两端进行N型重掺杂处理；
对PMOS区域的PMOS型LTPS沟道层的沟道两端进行P型重掺杂处理；
在所述NMOS型LTPS沟道层、所述PMOS型LTPS沟道层和裸露的缓冲层上形成栅绝缘层；
在所述栅绝缘层上形成栅极层；
在所述栅极层及裸露的栅绝缘层上形成介质层，并在所述介质层上蚀刻连通NMOS型LTPS沟道层的沟道两端的P型重掺杂处理区域和PMOS型LTPS沟道层的沟道两端的P型重掺杂处理区域的过孔；
在所述介质层上形成所述COMS器件的源漏极，所述源漏极通过所述过孔 与各自对应的P型重掺杂处理区域连通。
根据本发明的一个实施例，在对NMOS型LTPS沟道层的沟道两端进行N型重掺杂处理的步骤，与对PMOS区域的PMOS型LTPS沟道层的沟道两端进行P型重掺杂处理的步骤的顺序互换。
本发明的有益效果：
本发明针对现有LDD工艺复杂的问题，通过在NMOS型LTPS沟道内设置PN结，从而降低电子流通速度，避免热电子效应。
本发明的其他优点、目标，和特征在某种程度上将在随后的说明书中进行阐述，并且在某种程度上，基于对下文的考察研究对本领域技术人员而言将是显而易见的，或者可以从本发明的实践中得到教导。本发明的目标和其他优点可以通过下面的说明书，权利要求书，以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请的技术方案或现有技术的进一步理解，并且构成说明书的一部分。其中，表达本申请实施例的附图与本申请的实施例一起用于解释本申请的技术方案，但并不构成对本申请技术方案的限制。
图1a是根据本发明的一个实施例的PMOS LTPS制作步骤对应的器件结构示意图；
图1b根据本发明的一个实施例的NMOS LTPS制作步骤对应的器件结构示意图；
图1c是根据本发明的一个实施例的P型重掺杂步骤对应的器件结构示意图；
图1d是根据本发明的一个实施例的栅绝缘层制作步骤对应的器件结构示意图；
图1e是根据本发明的一个实施例的栅极层制作步骤对应的器件结构示意图；
图1f是根据本发明的一个实施例的介质层制作步骤对应的器件结构示意图；
图2是根据本发明的一个实施例的源漏极制作步骤对应的器件结构示意图；
图3a是根据本发明的一个实施例的PMOS LTPS制作步骤对应的器件结构示意图；
图3b是根据本发明的一个实施例的沟道P型重掺杂步骤对应的器件结构示意图；
图3c根据本发明的一个实施例的NMOS LTPS制作步骤对应的器件结构示意图；
图3d根据本发明的一个实施例的NMOS沟通N型轻掺杂步骤对应的器件结构示意图；
图3e是根据本发明的一个实施例的N型重掺杂步骤对应的器件结构示意图；
图3f是根据本发明的一个实施例的P型重掺杂步骤对应的器件结构示意图；
图4是根据本发明的一个实施例的源漏极制作步骤对应的器件结构示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成相应技术效果的实现过程能充分理解并据以实施。本申请实施例以及实施例中的各个特征，在不相冲突前提下可以相互结合，所形成的技术方案均在本发明的保护范围之内。
为解决现有技术中LDD工艺复杂的问题，本发明提出了一种解决NMOS型LTPS热载流子效应的COMS器件。
该COMS器件包括NMOS型LTPS，其中，在NMOS型LTPS的沟道内设置有用以降低电子在沟道流通速度的PN结，用以避免热电子效应。
如图2所示为根据本发明的一个实施例的NMOS型LTPS结构示意图。如图2所示，该NMOS型LTPS由下至上依次包括：设置于玻璃基板GLA上的缓冲层，该缓冲层包括设置于玻璃基板GLA上的氮化硅SiNx层以及设置于SiNx层上的氧化硅SiOx层；设置于缓冲层上的NMOS型LTPS的沟道层，该沟道层包括N型沟道N-Si以及沟道两端、与源漏极连通的P型重掺杂区P+-Si；设置于NMOS型LTPS的沟道层和裸露的缓冲层上的栅绝缘层GI；设置于栅绝缘层GI上的栅极层，用于形成栅极图案G；设置于栅极层及裸露的栅绝缘层GI上的介质层ILD；设置于介质层ILD上并与NMOS型LTPS的沟道两端连通的源极S和漏极D。
具体的，如图2所示，在源漏极与NMOS型LTPS接触的区域设置为P型重掺杂区P+-Si，而不是设置N型重掺杂区，可以在P型重掺杂区和NMOS型LTPS的沟道之间形成PN结。这样，NMOS型LTPS的沟道区会形成P+NP+型的三极管的结构。其中P+表示P型重掺杂，N+表示N型重掺杂。当有电流从漏 极D端移动向源极S端的时候，P+N形成的二极管正向导通，电流畅通无阻。但是，NP+形成了一个齐纳二极管。齐纳二极管的好处是形成很小的空乏区，电子穿过空乏区会减速。电子可以穿过空乏区，但不会像雪崩二极管那样将器件损伤。这样既解决了电子速度太大造成的热电子效应，并且解决了源漏极和LTPS接触的问题，省去了形成LDD结构时对应N型重掺杂N+和N型轻掺杂N-的两道光罩。
如图4所示为根据本发明的另一个实施例的NMOS型LTPS结构示意图。如图4所示，在NMOS型LTPS的沟道区内部设置有一P型重掺杂区，用以在P型重掺杂区和NMOS型LTPS的沟道区形成PN结。在NMOS型LTPS的沟道中间进行P型重掺杂，形成NP+N三极管结构。该结构可以将P+型的LTPS比作栏杆，电子跨过栏杆需要损耗一定的速度，从而避免了热电子效应，并省却了N型轻掺杂N-所需的光罩。该NMOS型LTPS的沟道区的其他结构与图2相同，此处不再详述。
在本发明的一个实施例中，该基于LTPS的COMS器件还包括一PMOS型LTPS。该PMOS型LTPS与NMOS型LTPS构成一个完整的COMS器件。如图2和4所示，该PMOS型LTPS由下至上依次包括：设置于玻璃基板GLA上的缓冲层，该缓冲层包括设置于玻璃基板GLA上的SiNx层以及设置于SiNx层上的SiOx层；设置于缓冲层上的PMOS型LTPS的沟道层，该沟道层包括P型沟道P-Si以及沟道区两端、与源漏极连通P型重掺杂区P+-Si；设置于PMOS型LTPS的沟道层和裸露的缓冲层上的栅绝缘层GI；设置于栅绝缘层GI上的栅极层，用于形成栅极图案G；设置于栅极层及裸露的栅绝缘层GI上的介质层ILD；设置于介质层ILD上并与PMOS型LTPS的沟道两端连通的源极S和漏极D。
根据本发明的另一个方面，还提供了一种用于制作基于LTPS的COMS器件的方法，具体包括以下几个步骤：
首先，在玻璃基板GLA上形成缓冲层。具体的，采用CVD(Chemical Vapor Deposition，化学气相沉积)成膜技术，在基板GLA上形成SiNx层，然后在SiNx层上形成SiOx层。
接着，在缓冲层上形成PMOS型LTPS沟道层和NMOS型LTPS沟道层。PMOS型LTPS沟道层包括P型沟道P-Si以及沟道两端、与源漏极连通的P型重掺杂区P+-Si；NMOS型LTPS沟道层包括N型沟道N-Si以及沟道两端、与源漏极连通的P型重掺杂区P+-Si。
具体的，在形成PMOS型LTPS沟道层和NMOS型LTPS沟道层时，首先在缓冲层上采用CVD成膜技术形成一层非晶硅a-Si膜，然后经曝光、刻蚀后形成a-Si硅岛图案，然后经ELA结晶形成P型LTPS，如图1a所示。然后，进行光阻涂布、曝光，对NMOS区域的LTPS进行N型轻掺杂处理，然后进行光阻剥离，形成NMOS型LTPS图案(NMOS型LTPS沟道层)，如图1b所示。接着，继续进行光阻涂布、曝光，对PMOS型LTPS沟道层的沟道两端和NMOS型LTPS沟道层的沟道两端进行P型重掺杂处理，即对a-Si硅岛图案的两端进行P型重掺杂，接着进行光阻剥离，从而形成P+-Si图案，如图1c所示。
接下来，采用CVD成膜技术在NMOS型LTPS的沟道层和PMOS型LTPS的沟道层和裸露的缓冲层上形成栅绝缘层GI，如图1d所示。
接下来，在栅绝缘层GI上形成栅极层。具体的，在栅绝缘层GI上采用PVD技术形成一金属膜，然后经曝光、显影处理形成栅极，如图1e所示。
接下来，在栅极层及裸露的栅绝缘层上形成介质层ILD，并在介质层ILD上蚀刻连通NMOS型LTPS沟道层的沟道两端的P型重掺杂处理区域和PMOS型LTPS沟道层的沟道两端的P型重掺杂处理区域的过孔。具体的，采用CVD成膜技术形成介质层，然后经曝光、干法蚀刻形成IDL层图案，如图1f所示。
最后，在介质层IDL上形成COMS器件的源漏极，源漏极通过过孔与各自对应的P型重掺杂处理区域连通。具体的，采用PVD成膜技术形成一层金属膜，并经曝光、显影处理形成源漏极图案。其中，源漏极通过过孔与NMOS型LTPS和PMOS型LTPS对应的源漏极区域连通，如图2所示。
根据本发明的另一个方面，还提供了另外一种用于制作基于LTPS的COMS器件的方法，具体包括以下几个步骤：
首先，在玻璃基板GLA上形成缓冲层。具体的，采用CVD成膜技术，在基板GLA上形成SiNx层，然后在SiNx层上形成SiOx层。
接下来，在缓冲层上对应PMOS区域和NMOS区域均形成PMOS型LTPS沟道层，如图3a所示。
接下来，对NMOS区域的PMOS型LTPS沟道层的沟道内部一区域进行P型重掺杂处理，得到P型重掺杂区域P+-Si，如图3b所示。具体的，在PMOS型LTPS沟道层上涂布光阻PR，采用半遮光光罩照射NMOS区域的PMOS型LTPS沟道层的沟道内部一区域，优选沟道中间区域，从而将该部位光阻去除。接着，对该去除光阻的部位进行P型重掺杂，从而得到P型重掺杂的LTPS。
接下来，采用干刻蚀法，将NMOS对应的光阻刻蚀掉，PMOS的光阻保留，如图3c所示。
接下来，对NMOS区域的LTPS沟道进行N型轻掺杂处理，然后进行光阻剥离，形成NMOS型LTPS图案(NMOS型LTPS沟道层)，如图3d所示。
接下来，继续进行光阻涂布、曝光，对NMOS区域的LTPS的a-Si硅岛图案的两端进行N型重掺杂处理，接着光阻剥离，从而形成N+-Si图案，如图3e所示。
接下来，继续进行光阻涂布、曝光，对PMOS区域的LTPS的a-Si硅岛图案的两端进行P型重掺杂处理，接着光柱剥离，从而形成P+-Si图案，如图3f所示。
接下来，采用CVD成膜技术在NMOS型LTPS沟道层和PMOS型LTPS的沟道层和裸露的缓冲层上形成栅绝缘层GI。
接下来，在栅绝缘层GI上形成栅极层。具体的，在栅绝缘层GI上采用PVD技术形成一金属层，然后经曝光、显影处理形成栅极。
接下来，在栅极层及裸露的栅绝缘层上形成介质层ILD，并在所介质层ILD上蚀刻连通NMOS型LTPS沟道层的沟道两端的P型重掺杂处理区域和PMOS型LTPS沟道层的沟道两端的P型重掺杂处理区域的过孔。具体的，采用CVD成膜技术形成介质层，然后经曝光、干法蚀刻形成IDL层图案。
最后，在介质层上形成COMS器件的源漏极，源漏极通过过孔与各自对应的P型重掺杂处理区域连通。具体的，采用PVD成膜技术形成一层金属膜，并经曝光、显影处理形成源漏极图案。其中，源漏极通过过孔与NMOS型LTPS和PMOS型LTPS对应的源漏极区域连通，如图4所示。
在通过N型重掺杂形成N+-Si图案的步骤和通过P型重掺杂形成P+-Si图案的步骤，这两个步骤可以互换。
虽然本发明所揭露的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (10)

  1. 一种基于LTPS的COMS器件，包括NMOS型LTPS，其中，
    在NMOS型LTPS的沟道内设置有用以降低电子在沟道内流通速度的PN结，以避免热电子效应。
  2. 根据权利要求1所述的器件，其中，在NMOS型LTPS的沟道两端均设置有P型重掺杂区，用以在P型重掺杂区和NMOS型LTPS的沟道之间形成PN结。
  3. 根据权利要求1所述的器件，其中，在NMOS型LTPS的沟道内部设置有一P型重掺杂区，用以在P型重掺杂区和NMOS型LTPS的沟道之间形成PN结。
  4. 根据权利要求3所述的器件，其中，所述P型重掺杂区位于NMOS型LTPS的沟道的中间。
  5. 根据权利要求2所述的器件，其中，所述NMOS型LTPS还包括：
    缓冲层，设置于NMOS型LTPS的沟道所在的沟道层下；
    栅绝缘层，设置于NMOS型LTPS的沟道所在的沟道层和裸露的缓冲层上；
    栅极层，设置于所述栅绝缘层上；
    介质层，设置于所述栅极层及裸露的栅绝缘层上；
    源漏极，设置于所述介质层上并与NMOS型LTPS的沟道两端通过过孔连通。
  6. 根据权利要求4所述的器件，其中，所述NMOS型LTPS还包括：
    缓冲层，设置于NMOS型LTPS的沟道所在的沟道层下；
    栅绝缘层，设置于NMOS型LTPS的沟道所在的沟道层和裸露的缓冲层上；
    栅极层，设置于所述栅绝缘层上；
    介质层，设置于所述栅极层及裸露的栅绝缘层上；
    源漏极，设置于所述介质层上并与NMOS型LTPS的沟道两端通过过孔连通。
  7. 根据权利要求1所述的器件，其中，所述器件还包括一PMOS型LTPS，其中，所述PMOS型LTPS包括：
    缓冲层，设置于玻璃基板上；
    沟道层，设置于所述缓冲层上；
    栅绝缘层，设置于PMOS型LTPS的沟道层和裸露的缓冲层上；
    栅极层，设置于所述栅绝缘层上；
    介质层，设置于所述栅极层及裸露的栅绝缘层上；
    源漏极，设置于所述介质层上并与PMOS型LTPS的沟道两端通过过孔连通。
  8. 一种用于制作基于LTPS的COMS器件的方法，包括：
    在玻璃基板上形成缓冲层；
    在所述缓冲层上对应PMOS区域和NMOS区域均形成PMOS型LTPS沟道层；
    对NMOS区域的PMOS型LTPS沟道层进行N型轻掺杂处理，以形成NMOS型LTPS沟道层；
    对所述NMOS型LTPS沟道层的沟道两端和PMOS区域的PMOS型LTPS沟道层的沟道两端进行P型重掺杂处理；
    在所述NMOS型LTPS沟道层、所述PMOS型LTPS沟道层和裸露的缓冲层上形成栅绝缘层；
    在所述栅绝缘层上形成栅极层；
    在所述栅极层及裸露的栅绝缘层上形成介质层，并在所述介质层上蚀刻连通NMOS型LTPS沟道层的沟道两端的P型重掺杂处理区域和PMOS型LTPS沟道层的沟道两端的P型重掺杂处理区域的过孔；
    在所述介质层上形成所述COMS器件的源漏极，所述源漏极通过所述过孔与各自对应的P型重掺杂处理区域连通。
  9. 一种用于制作基于LTPS的COMS器件的方法，包括：
    在玻璃基板上形成缓冲层；
    在所述缓冲层上对应PMOS区域和NMOS区域均形成PMOS型LTPS沟道层；
    对NMOS区域的PMOS型LTPS沟道层的沟道中间区域进行P型重掺杂处理；
    对NMOS区域的PMOS型LTPS沟道层的沟道进行N型轻掺杂处理以形成NMOS型LTPS沟道层；
    对NMOS型LTPS沟道层的沟道两端进行N型重掺杂处理；
    对PMOS区域的PMOS型LTPS沟道层的沟道两端进行P型重掺杂处理；
    在所述NMOS型LTPS沟道层、所述PMOS型LTPS沟道层和裸露的缓冲层上形成栅绝缘层；
    在所述栅绝缘层上形成栅极层；
    在所述栅极层及裸露的栅绝缘层上形成介质层，并在所述介质层上蚀刻连通NMOS型LTPS沟道层的沟道两端的P型重掺杂处理区域和PMOS型LTPS沟道层的沟道两端的P型重掺杂处理区域的过孔；
    在所述介质层上形成所述COMS器件的源漏极，所述源漏极通过所述过孔与各自对应的P型重掺杂处理区域连通。
  10. 根据权利要求9所述的方法，其中，在对NMOS型LTPS沟道层的沟道两端进行N型重掺杂处理的步骤，与对PMOS区域的PMOS型LTPS沟道层的沟道两端进行P型重掺杂处理的步骤的顺序互换。
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