WO2018039236A1 - Hétérostructure semi-conductrice avec incorporation réduite d'impuretés de calcium non intentionnelles - Google Patents

Hétérostructure semi-conductrice avec incorporation réduite d'impuretés de calcium non intentionnelles Download PDF

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WO2018039236A1
WO2018039236A1 PCT/US2017/048026 US2017048026W WO2018039236A1 WO 2018039236 A1 WO2018039236 A1 WO 2018039236A1 US 2017048026 W US2017048026 W US 2017048026W WO 2018039236 A1 WO2018039236 A1 WO 2018039236A1
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iii
nitride
deposited
layers
high temperature
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Erin C. Young
James S. Speck
Nicolas Grandjean
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The Regents Of The University Of California
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/10—Heating of the reaction chamber or the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/22—Sandwich processes
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present invention is related to a semiconductor heterostructure with reduced calcium impurity incorporation. 2. Description of the Related Art.
  • III-nitride materials has been well established for the fabrication of high-efficiency visible light-emitting devices, where the term“III-nitrides” refers to any alloy composition of the (Ga,Al,In,B)N semiconductors having the formula
  • GaN and InGaN alloy based thin films and light emitting diode (LED) heterostructures grown by the technique of molecular beam epitaxy (MBE) have high (10 15 -10 18 /cm 3 ) concentrations of unintentional Calcium (Ca) impurities that come from the growth environment or the surface of the starting substrate.
  • Ca impurities have previously been reported for growth of Silicon (Si) based
  • GaAs Gallium Arsenide
  • the high concentration of Ca impurity atoms is likely the source of a mechanism for non-radiative recombination known as Shockley-Read-Hall (SRH) recombination.
  • Shockley-Read-Hall (SRH) recombination Dreyer et al. have predicted that defect concentrations of the order of 10 16 /cm 3 are already sufficient to cause extremely high non-radiative recombination rates and result in low device efficiency [4].
  • the present invention discloses a device and a method for fabrication of the device.
  • the device comprises a III-nitride semiconductor heterostructure with at least one Calcium impurity reduction structure, deposited on or above a substrate, that reduces unintentional Calcium impurity incorporation in subsequent layers of the III-nitride semiconductor heterostructure to a concentration of about 1 x 10 14 /cm 3 or less.
  • the Calcium impurity reduction structure is comprised of at least one low temperature III-nitride layer deposited at a lower temperature, and is sandwiched between a plurality of high temperature III-nitride layers deposited at a higher temperature, to reduce the Calcium at a surface of the low temperature III-nitride layer by forcing the Calcium’s incorporation into the low temperature III-nitride layer.
  • the substrate comprises a sapphire substrate with a III-nitride template layer deposited thereon.
  • a first one of the plurality of high temperature III-nitride layers is deposited on the sapphire substrate with the III-nitride template layer and the Calcium impurity reduction structure is deposited on the first one of the plurality of high temperature III- nitride layers.
  • a second one of the plurality of high temperature III-nitride layers is deposited on the Calcium impurity reduction structure and the subsequent layers of the III-nitride semiconductor heterostructure are deposited on the second one of the plurality of high temperature III-nitride layers.
  • the Calcium impurity reduction structure may be a multilayer superlattice with alternating ones of the low temperature and high temperature III-nitride layers deposited at the lower and higher temperatures, respectively.
  • the low temperature III-nitride layer comprises a low temperature Gallium Nitride (GaN) layer grown at the lower temperature of about 550oC to 700oC.
  • GaN Gallium Nitride
  • the high temperature III-nitride layer comprises a high temperature GaN layer grown at the higher temperature of greater than about 700oC.
  • the subsequent layers of the semiconductor heterostructure form an
  • FIG.1 is a graph of SIMS (Secondary Ion Mass Spectrometry) data showing the Ca concentration in a heterostructure of a LED grown by MBE.
  • FIG.2 is a graph of SIMS data showing the Ca concentration in a GaN superlattice (SL) with layers grown alternating at high and low growth temperature.
  • FIG.3 is a schematic of an LED structure with a 15 period Ca impurity reduction superlattice grown prior to the LED device structure.
  • FIG.4 is a graph of electroluminescence (EL) data for two LED devices, with and without the Ca impurity reduction structure as shown in FIG.3.
  • FIG.5 is a flowchart that illustrates the process for fabricating a III-nitride semiconductor heterostructure with a Ca impurity reduction structure, according to one embodiment.
  • the Ca incorporation in a heterostructure of interest can be reduced by introducing a Ca impurity reduction structure into the heterostructure that includes at least one III-nitride layer grown at a lower temperature of about 550oC to 700oC to trap the Ca, wherein the III-nitride layer grown at the lower temperature is sandwiched by a plurality of III-nitride layers grown at a higher temperature of greater than about 700oC.
  • the Ca impurity reduction structure reduces the unintentional Ca concentration in subsequent layers of the heterostructure.
  • the invention described herein improves III-nitride semiconductor device performance by reducing non-radiative losses associated with unintentional Ca defects.
  • the invention disclosed is a III-nitride semiconductor heterostructure with an underlying Ca impurity reduction structure comprised of a single III-nitride layer or multiple III- nitride layers that reduce the unintentional Ca concentration to concentrations to about 1 x 10 14 /cm 3 or less in subsequent layers of the heterostructure.
  • the single III-nitride layer is grown at the lower temperature, and the multiple III-nitride layers are a superlattice with the III-nitride layers grown alternating at the higher and lower temperatures.
  • the Ca impurity reduction structure is sandwiched by a plurality of III-nitride layers grown at the higher temperature.
  • Subsequent layers of the heterostructure could be an optoelectronic device based on a p-n junction, such as a light emitting diode, a laser diode, a solar cell, or a photodetector, or another electronic device such as a transistor.
  • FIG.1 is a graph of SIMS data showing the Ca, In and Si concentrations in an InGaN-based LED heterostructure grown by MBE, wherein the x-axis is time (minutes, mn), the left-hand y-axis is intensity (counts/second, c/s), the right-hand y-axis is concentration (atom/cm 3 ), and the lines are labeled as Ca, In and Si.
  • the Ca concentration peaks at about 1 x 10 18 /cm 3 in the InGaN quantum well layers which are grown at a low temperature of about 600oC.
  • the background Ca concentration is about 1 x 10 16 /cm 3 for layers grown at a high temperature of about 820oC.
  • the Ca impurity can be reduced by depositing a Ca impurity reduction structure, comprised of at least one low temperature (LT) GaN layer grown at a lower temperature, and sandwiched between a plurality of high temperature (HT) GaN layers grown at a higher temperature, to trap the Ca impurity in the LT GaN layer at a growth condition where it incorporates more readily.
  • a Ca impurity reduction structure comprised of at least one low temperature (LT) GaN layer grown at a lower temperature, and sandwiched between a plurality of high temperature (HT) GaN layers grown at a higher temperature, to trap the Ca impurity in the LT GaN layer at a growth condition where it incorporates more readily.
  • FIG.2 is a graph of SIMS data showing the Ca, Ga and In concentrations for a heterostructure including the multilayer superlattice, wherein the x-axis is depth (nanometers, nm), the left-hand y-axis is intensity (counts/second, c/s), the right-hand y-axis is concentration (atom/cm 3 ), and the lines are labeled as Ca, Ga and In. From right-to-left in the graph, the Ca
  • concentrations are shown at a regrowth interface, in a 100 nm GaN buffer layer grown at a temperature of about 820oC, in a 10x HT/LT GaN SL with an Indium (In) surfactant, and a 120 nm GaN cap layer grown at a temperature of about 820oC. It can be seen that, after the 10x HT/LT GaN SL with layers grown alternating at the higher and lower temperatures, the Ca concentration in the top layer is reduced to about 1 x 10 14 /cm 3 or less.
  • FIG.3 is a schematic of an LED structure fabricated with a Ca impurity reduction structure comprised of a 15 period multilayer superlattice grown prior to the LED device layers.
  • the LED structure 300 is fabricated on a sapphire substrate 302 having an n-GaN template deposited thereon, and includes a 100 nm HT GaN buffer layer 304 grown at a higher temperature of about 820o, a Ca impurity reduction structure 306 that is a superlattice comprised of 15 periods of a 5 nm LT n-type GaN:Si layer 308 grown at a lower temperature of about 600°C, followed by a 20 nm HT n-type GaN:Si layer 310 grown at a higher temperature of about 820°C (with the layers 308, 310 repeated 15 times within the superlattice), a 100 nm HT n-type GaN:Si layer 312 grown at a higher temperature of about 820°C, a multiple quantum well (MQW)
  • FIG.4 is a graph of EL data for two LED devices, with and without the Ca impurity reduction structure 306 shown in FIG.3, wherein the x-axis is wavelength (nanometers, nm), the y-axis is intensity (arbitrary units, au), and the lines are labeled as LED with Ca reduction and Reference LED.
  • the LED with Ca reduction shows higher EL efficiency than the Reference LED with no Ca reduction.
  • the output power of the LED with Ca reduction was 10 times higher at low (20 mA) current density than the Reference LED with no Ca reduction.
  • the Ca impurity reduction structure 306 comprises a single low temperature III-nitride layer deposited at a lower temperature, i.e., a thicker version of layer 308, but not layer 310.
  • the single low temperature III-nitride layer comprises at least 50 nm of an LT n-type GaN:Si layer 308 grown at a lower temperature of about 600°C.
  • FIG.5 is a flowchart that illustrates the process for fabricating a III-nitride semiconductor heterostructure with a Ca impurity reduction structure using MBE, according to one embodiment.
  • Block 500 represents the step of providing a substrate, wherein the substrate is a sapphire substrate having a III-nitride template layer deposited thereon in one embodiment.
  • Block 502 represents the step of depositing a high temperature III-nitride layer on or above the substrate, wherein the high temperature III-nitride layer is a high temperature GaN buffer layer that is grown at a higher temperature of greater than about 700o.
  • Block 504 represents the step of creating a Ca impurity reduction structure on or above the high temperature III-nitride layer of step 502, wherein the Ca impurity reduction structure reduces unintentional Ca impurity incorporation in subsequent layers of the III-nitride semiconductor heterostructure to a concentration of about 1 x 10 14 /cm 3 or less.
  • Block 506 represents the step of depositing a high temperature III-nitride layer on or above the Ca impurity reduction structure, wherein the high temperature III-nitride layer is an n-type GaN layer that is grown at a higher temperature of greater than about 700o.
  • the Ca impurity reduction structure is comprised of at least one low temperature III-nitride layer deposited at a lower temperature of about 550oC to 700oC, and is sandwiched between a plurality of high temperature III-nitride layers deposited at a higher temperature of greater than about 700oC (i.e., the III-nitride layers deposited in Blocks 502 and 506), to reduce the Ca at a surface of the low temperature III-nitride layer by forcing the Ca’s incorporation into the low temperature III-nitride layer.
  • the Ca impurity reduction structure comprises a single low temperature III-nitride layer deposited at a lower temperature, wherein the single low temperature III-nitride layer comprises at least 50 nm of an LT n-type GaN:Si layer grown at a lower temperature of about 550oC to 700oC.
  • the Ca impurity reduction structure is a superlattice with alternating ones of the low temperature and high temperature III-nitride layers deposited at the lower and higher temperatures, respectively, wherein the low temperature III- nitride layer comprises an LT n-type GaN:Si layer grown at a lower temperature of about 550oC to 700oC, and the high temperature III-nitride layer comprises an HT n-type GaN:Si layer grown at a higher temperature of greater than about 700oC.
  • Block 506 represents the step of depositing subsequent III-nitride layers of the semiconductor heterostructure on or above the Ca impurity reduction structure to form an optoelectronic device based on a p-n junction or a transistor.
  • This invention could potentially improve the performance (for example, efficiency and output power) of semiconductor devices such as LEDs, lasers, and transistors. It could also enable the use of the MBE growth technique for prototype and commercial production of GaN based light emitting devices. References

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Abstract

Cette invention concerne une hétérostructure semi-conductrice ayant une concentration réduite d'impuretés de Calcium (Ca) non intentionnelles, d'environ 1 x 1014/cm3 ou moins. Une structure de réduction d'impuretés de Calcium peut comprendre une seule couche à basse température ou un super-réseau multicouche avec des couches alternées à basse température et à haute température, la structure de réduction d'impuretés de Calcium étant prise en sandwich entre des couches à haute température. L'hétérostructure semi-conductrice est constituée d'un alliage de nitrure du groupe III.
PCT/US2017/048026 2016-08-22 2017-08-22 Hétérostructure semi-conductrice avec incorporation réduite d'impuretés de calcium non intentionnelles WO2018039236A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109860340A (zh) * 2018-10-29 2019-06-07 华灿光电（浙江）有限公司 一种发光二极管外延片的生长方法
EP3951025A4 (fr) * 2019-03-29 2022-06-01 Mitsubishi Chemical Corporation Tranche de substrat de nitrure de gallium et procédé de fabrication de tranche de substrat de nitrure de gallium

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140235005A1 (en) * 2013-02-15 2014-08-21 Samsung Electronics Co., Ltd. Method of producing p-type nitride semiconductor and method of manufacturing nitride semiconductor light emitting device therewith
US20140339686A1 (en) * 2011-09-21 2014-11-20 International Rectifier Corporation Group III-V Device with a Selectively Modified Impurity Concentration
US20160104816A1 (en) * 2013-05-22 2016-04-14 Seoul Viosys Co., Ltd. Light emitting device and method for preparing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140339686A1 (en) * 2011-09-21 2014-11-20 International Rectifier Corporation Group III-V Device with a Selectively Modified Impurity Concentration
US20140235005A1 (en) * 2013-02-15 2014-08-21 Samsung Electronics Co., Ltd. Method of producing p-type nitride semiconductor and method of manufacturing nitride semiconductor light emitting device therewith
US20160104816A1 (en) * 2013-05-22 2016-04-14 Seoul Viosys Co., Ltd. Light emitting device and method for preparing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109860340A (zh) * 2018-10-29 2019-06-07 华灿光电（浙江）有限公司 一种发光二极管外延片的生长方法
CN109860340B (zh) * 2018-10-29 2020-07-07 华灿光电（浙江）有限公司 一种发光二极管外延片的生长方法
EP3951025A4 (fr) * 2019-03-29 2022-06-01 Mitsubishi Chemical Corporation Tranche de substrat de nitrure de gallium et procédé de fabrication de tranche de substrat de nitrure de gallium

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