WO2018018875A1 - 可扩展的多端口存储器的数据处理方法及数据处理系统 - Google Patents

可扩展的多端口存储器的数据处理方法及数据处理系统 Download PDF

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WO2018018875A1
WO2018018875A1 PCT/CN2017/073644 CN2017073644W WO2018018875A1 WO 2018018875 A1 WO2018018875 A1 WO 2018018875A1 CN 2017073644 W CN2017073644 W CN 2017073644W WO 2018018875 A1 WO2018018875 A1 WO 2018018875A1
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data
memory
read
write
port
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PCT/CN2017/073644
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English (en)
French (fr)
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许俊
蒋震
郑晓阳
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盛科网络（苏州）有限公司
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Priority to US16/318,356 priority Critical patent/US10818325B2/en
Publication of WO2018018875A1 publication Critical patent/WO2018018875A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9078—Intermediate storage in different physical parts of a node or terminal using an external memory or storage device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the field of network communication technologies, and in particular, to a data processing method and a data processing system for an expandable multi-port memory.
  • vendors typically provide only one read or write memory, one read write memory, and two read or write memories. Thus, the designer can only build memory for multiple ports based on the basic memory unit described above.
  • Message buffering is a special type of multi-port memory whose writing is controllable, that is, sequential writing, but reading is random.
  • the usual method is to divide the entire chip into multiple independent message forwarding and processing units for parallel processing.
  • the English name of the message forwarding and processing unit is Slice, for example, divided into 4 slices for parallel processing.
  • the bandwidth of the data that each slice needs to process is reduced, and the core frequency requirement is also reduced to 1/4 of the original core frequency.
  • multi-port memory not only needs to consider the portability of the design, but also needs to consider the scalability of the design.
  • the designed memory architecture can be easily extended from 4 slices to 6 or 8 or more slice architectures.
  • custom design such as: modify the storage unit, and algorithm design to increase the SRAM The number of ports.
  • Custom design cycles are generally long, need to do spice simulation, and provide a memory compiler to generate different sizes and types of SRAM. For suppliers, it usually takes 6-9 months to provide a new type.
  • the type of SRAM, and such custom design is strongly related to the specific process (such as GlobalFoundries 14nm, 28nm or TSMC 28nm, 16nm), once the process changes, the custom designed SRAM library needs to be redesigned.
  • the algorithm design is based on the off-the-shelf SRAM type provided by the manufacturer.
  • the algorithm realizes multi-port memory. The biggest advantage is to avoid custom design and shorten the time. At the same time, the design is independent of the manufacturer library and can be easily transplanted between different manufacturers. .
  • a four-read and four-write memory architecture supporting four slice accesses is designed by means of algorithm design.
  • a large-capacity 2R2W SRAM is designed using 1R1W SRAM2D, which is logically total.
  • the area of 18M bytes 4 read 4 write SRAM occupies 213.248 squares. Cm, the total power consumption is 55.296Watts, the overhead of inserting Decap and DFT and place and route has not been considered here.
  • the multi-port SRAM designed by this algorithm design has a huge footprint and total power consumption.
  • another algorithm design method uses a 2R2W SRAM as a basic unit to implement packet buffering of multiple ports through spatial segmentation, and a message buffer architecture of four slices is used. For example, each X? Y?
  • CCE it is a CCE
  • the English full name is Criss-Cross Element
  • the Chinese translation is: vertical and horizontal memory unit
  • the horizontal two CCEs constitute a CCHG
  • the English full name of the CCHG is: Criss-Cross Horizontal Group
  • the Chinese translation is: vertical and horizontal memory Horizontal grouping
  • two vertical CCEs form a CCVG
  • the English name of the CCVG is: Criss-Cross Vertical Group
  • the Chinese translation is: vertical and horizontal memory vertical grouping.
  • S0, S1, S2, and S3 represent 4 slices, and each slice includes, for example, six 100GE ports.
  • the message input from slice0 or slice1 to slice0 or slice1 is stored in X0Y0, and input from slice0 or slice1.
  • the message to slice2 or slice3 is stored in X1Y0
  • the message input from slice2 or slice3 to slice0 or slice1 is stored in X0Y1
  • the message input from slice2 or slice3 to slice2 or slice3 is stored in X1Y1; for multicast message
  • the multicast message from Slice0 or Slice1 is simultaneously stored in X0Y0 and X1Y0.
  • slice0 or slice1 will read the message from X0Y0 or X0Y1, and slice2 or slice3 will be from X1Y0 or The message is read in X1Y1.
  • each CCE is also a 2R2W SRAM logic block, the size is 4.5M bytes, and there are a total of (8/2) 2 , a total of 16 such SRAM logic blocks.
  • the 8R8W SRAM is constructed, and the write and read data are similar to the above 4R4W memory, and will not be described in detail herein.
  • each CCE designed by the prior art algorithm an X? Y? Logically, four 16384 deep 2304 wide SRAMs are required.
  • an object of the present invention is to provide a data processing method and processing system for an expandable multi-port memory.
  • an embodiment of the present invention provides a data processing method for a scalable multi-port memory, wherein the multi-port memory is a 2-port n-write multi-port memory unit, and n is an even number;
  • the method includes:
  • the size of the data is less than or equal to the bit width of the 2R1W memory, the data is respectively written into different 2R1W memories;
  • the method further includes:
  • the read port selected in the multi-port memory unit of the 2 read n write is directly read out data
  • the second clock cycle is awaited, and when the second clock cycle arrives, the matched read port of the multi-port memory cell of the 2nd read n write is directly read out.
  • the method further includes:
  • the data is respectively written into different 2R1W memories according to the destination port of the data;
  • the method further includes:
  • the matched read port in the multi-port memory of n-read n-write is selected to directly read data
  • the second clock cycle is awaited, and when the second clock cycle comes, the matching read port in the multi-port memory of n-read n-write is selected to directly read the data.
  • the method further includes:
  • a 2m+1 block SRAM2P memory having the same depth and width is used to construct a hardware framework of the 2R1W memory, where m is a positive integer;
  • Each SRAM2P memory has M pointer addresses, wherein one of the plurality of SRAM2P memories is a secondary memory, and the rest are main memories;
  • the data in the main memory and the auxiliary memory are associated with each other according to the current pointer position of the data, and an exclusive OR operation is performed to complete the writing and reading of the data. .
  • an embodiment of the present invention provides a scalable multi-port memory data processing system, the multi-port memory being a 2-read n-write multi-port memory unit, n being an even number; Including: data building module, data processing module;
  • the data construction module is specifically configured to: assemble two 2R1W memories into one bank storage unit in parallel;
  • the data processing module is specifically configured to: when determining one clock cycle, data is written to the two-read n-write multi-port memory unit through n write ports;
  • the size of the data is less than or equal to the bit width of the 2R1W memory, the data is respectively written into different 2R1W memories;
  • the data processing module is further configured to:
  • the read port selected in the multi-port memory unit of the 2 read n write is directly read out data
  • the second clock cycle is awaited, and when the second clock cycle arrives, the matched read port of the multi-port memory cell of the 2nd read n write is directly read out.
  • the data construction module is further configured to: directly form a hardware framework of the n-read n-write memory based on n/2 the 2 read n-write multi-port memory units;
  • the data processing module is further configured to: when determining that the data is written to the n-read n-write multi-port memory through the n write ports under one clock cycle,
  • the data is respectively written into different 2R1W memories according to the destination port of the data;
  • the data processing module is further configured to:
  • the matched read port in the multi-port memory of n-read n-write is selected to directly read data
  • the second clock cycle is awaited, and when the second clock cycle comes, the matching read port in the multi-port memory of n-read n-write is selected to directly read the data.
  • the data construction module is further configured to: select a 2m+1 block SRAM2P memory having the same depth and width according to the depth and width of the 2R1W memory to construct a hardware framework of the 2R1W memory, where m is a positive integer ;
  • Each SRAM2P memory has M pointer addresses, wherein one of the plurality of SRAM2P memories is a secondary memory, and the rest are main memories;
  • the data processing module is further configured to: perform an exclusive OR operation on the data in the main memory and the auxiliary memory according to the current pointer position of the data. , complete the writing and reading of data.
  • the data processing method and processing system of the scalable multi-port memory of the present invention builds more port SRAMs by algorithm based on the existing SRAM type, and can be maximized with only minimal cost.
  • Limit support for multi-port SRAM in the implementation process, avoid complex control logic and additional multi-port SRAM or register array resources, take advantage of the speciality of message buffer, through spatial segmentation and time division, only need simple XOR The operation can realize the message buffering of multiple ports.
  • all the cache resources of the multi-port memory implemented by the present invention can be completely shared between any input ports, and logically, more CCEs can be used to construct multiple ports.
  • Memory, easy to implement port expansion, the invention has lower power consumption, faster processing speed, and saves more resources or area, the message cache architecture has better scalability, simple implementation, saving manpower and Material cost.
  • FIG. 1 is a schematic diagram of a message buffer logic unit of a 2R2W memory based on an algorithm design of a 1R1W memory in the prior art
  • FIG. 2 is a schematic diagram of a message buffer logic unit of a 4R4W memory implemented by an algorithm based on a 2R2W memory in the prior art;
  • FIG. 3A is a schematic diagram of a message buffering architecture of a 4R4W memory based on 2R2W memory using another algorithm design in the prior art
  • FIG. 3B is a schematic diagram of a message buffering architecture of an 8R8W memory based on 2R2W memory using another algorithm design in the prior art
  • FIG. 4 is a schematic diagram of a message buffer logic unit of one of the CCEs in FIG. 3;
  • FIG. 5 is a schematic diagram showing the relationship between the number of 2R2W memories and the number of CCEs when the 2R2W memory is designed to expand the memory port based on the 2R2W memory;
  • FIG. 6 is a schematic flow chart of a data processing method of a 2-read n-write scalable multi-port memory according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram showing the structure of a digital circuit of a 2R1W memory formed by a custom design in the first embodiment of the present invention
  • FIG. 8 is a schematic diagram of a 2R1W memory read/write time-sharing operation formed by a custom design according to a second embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a message buffer logic unit of a 2R1W memory formed by an algorithm design in a third embodiment of the present invention.
  • 10a is a schematic diagram of a message buffer logic unit of a 2R1W memory formed by an algorithm design in a fourth embodiment of the present invention
  • FIG. 10b is a schematic structural diagram of a memory block number mapping table corresponding to FIG. 10a;
  • FIG. 10b is a schematic structural diagram of a memory block number mapping table corresponding to FIG. 10a;
  • FIG. 11 is a schematic flowchart of a data processing method of a 2R1W memory provided in a fifth embodiment of the present invention.
  • FIG. 12 is a schematic diagram of a message buffer logic unit of a 2R1W memory provided in a fifth embodiment of the present invention.
  • FIG. 13 is a schematic diagram of a message buffering architecture of two banks according to an embodiment of the present invention.
  • FIG. 14 is a flow chart showing a data processing method of an n-read n-write scalable multi-port memory according to an embodiment of the present invention
  • 15A is a schematic diagram of a message buffering architecture of a 4R4W memory in an embodiment of the present invention.
  • 15B is a schematic diagram of a message buffering architecture of an 8R8W memory in an embodiment of the present invention.
  • 16 is a schematic diagram showing the relationship between the number of 2 read n write memories and the number of CCEs when the memory expands the memory port based on 2 read n writes in the specific embodiment of the present invention
  • 17 is a block diagram of a data processing system of an expandable multi-port memory provided in an embodiment of the present invention.
  • a data processing method for an expandable multi-port memory according to an embodiment of the present invention, wherein the multi-port memory is a 2-port n-write multi-port memory unit, and n is an even number.
  • the method includes:
  • the size of the data is less than or equal to the bit width of the 2R1W memory, the data is respectively written into different 2R1W memories;
  • the read port selected in the multi-port memory unit of the 2 read n write is directly read out data
  • the second clock cycle is awaited, and when the second clock cycle arrives, the matched read port of the multi-port memory cell of the 2nd read n write is directly read out.
  • one word line is divided into two left and right, so that two read ports can be simultaneously operated or one write port, so that the MOS from the left side
  • the data read by the tube and the data read by the right MOS tube can be simultaneously performed.
  • the data read by the right MOS tube needs to be inverted before being used, and in order not to affect the speed of data reading, the readout is performed.
  • a sense amplifier requires a pseudo differential amplifier.
  • the 6T SRAM area is unchanged, the only cost is to double the word line, thus ensuring that the overall storage density is basically unchanged.
  • FIG. 8 in the second embodiment, a 2R1W memory read/write operation flow diagram formed by a custom design is shown;
  • FIG. 9 a schematic diagram of a 2R1W memory read/write operation process formed by an algorithm in an embodiment of the present invention in a third embodiment
  • an SRAM of 2R1W is constructed based on SRAM2P, which is an SRAM type capable of supporting 1 read and 1 read/write, that is, 2 read operations or 1 read can be simultaneously performed on SRAM2P. And 1 write operation.
  • a 2R1W SRAM is constructed based on SRAM2P by copying one SRAM; in this example, the right SRAM2P_1 is a copy of the left SRAM2P_0, and when the specific operation is performed, two SRAM2Ps are used as one read and one write memory. ;When writing data, write data to the left and right SRAM2P at the same time. When reading data, A is fixedly read from SRAM2P_0, and data B is fixedly read from SRAM2P_1, so that one write operation and two reads can be realized. The operation proceeds concurrently.
  • a logically monolithic 16384-depth SRAM is divided into logically four 4096-depth SRAM2Ps, numbered sequentially as 0, 1, 2, and 3, and an additional 4096-depth SRAM is added, numbered as 4, as a solution to read and write conflicts, for read data A and read data B, always ensure that these two read operations can be performed concurrently, when the address of two read operations is in different SRAM2P, because any one SRAM2P can Configured as 1R1W type, so there is no conflict between reading and writing; when the addresses of 2 read operations are in the same block of SRAM2P, for example, they are all in SRAM2P_0, since the same SRAM2P can only provide 2 ports at the same time, at this time Its port is occupied by 2 read operations. If there is exactly one write operation to write to SRAM2P_0, then this data is written into the fourth block of memory SRAM2P_4.
  • a memory block mapping table is required to record which memory block stores valid data.
  • the depth of the memory block mapping table is the same as the depth of one memory block, that is, 4096 depths, each In an entry, the number of each memory block is sequentially stored after initialization, from 0 to 4.
  • SRAM2P_0 since SRAM2P_0 has read and write conflicts when writing data, the data is actually written to SRAM2P_4.
  • the read operation also reads the corresponding content in the memory map, the original content is ⁇ 0, 1, 2, 3, 4 ⁇ , and after modification, it becomes ⁇ 4, 1, 2, 3, 0 ⁇ , the first block
  • the number and the 4th block number are reversed, indicating that the data is actually written to SRAM2P_4, and SRAM2P_0 becomes a backup entry.
  • the memory block number mapping table address is first read.
  • the memory block number map is required to provide 1 read and 1 write ports.
  • the memory block number map is required to provide 2 read ports, so that a total of memory block number maps are required to provide 3 reads. Port and 1 write port, and these 4 access operations must be performed simultaneously.
  • a method for constructing a 2R1W memory includes:
  • the plurality of SRAM2P memories are sequentially SRAM2P(0), SRAM2P(1), ..., SRAM2P(2m), and each SRAM2P memory has M pointer addresses, wherein one of the plurality of SRAM2P memories For the auxiliary memory, the rest are the main memory;
  • each SRAM 2P memory (2R1W memory depth and width product) / 2m.
  • the plurality of SRAM2P memories are sequentially SRAM2P(0), SRAM2P(1), SRAM2P(2), SRAM2P(3), SRAM2P(4), wherein SRAM2P(0), SRAM2P(1), SRAM2P(2), SRAM2P(3) are the main memories, and SRAM2P(4) is the auxiliary memory.
  • the depth and width of each SRAM2P memory are 4096 and 128 respectively.
  • each SRAM2P memory has 4096. Pointer address; if the address of each SRAM2P memory is independently identified, the address of each SRAM2P memory is 0 ⁇ 4095. If all the addresses of the main memory are arranged in order, all the pointer addresses are: 0 to 16383.
  • SRAM2P(4) is used to resolve port conflicts, and in this embodiment, there is no need to add a memory block number mapping table to meet the demand.
  • the method further includes:
  • the data in the main memory and the auxiliary memory are associated with each other according to the current pointer position of the data, and an exclusive OR operation is performed to complete the writing and reading of the data. .
  • the data writing process is as follows:
  • the write address of the current data is W(x, y), and x represents the arrangement position of the SRAM2P memory where the write data is located, 0 ⁇ x ⁇ 2m, and y represents the specific pointer in the SRAM2P memory where the write data is located. Address, 0 ⁇ y ⁇ M;
  • the data in the remaining main memory having the same pointer address as the write address is obtained, and it is XORed with the current write data at the same time, and the XOR operation result is written into the same pointer address of the auxiliary memory.
  • a 128-bit all-one "1" is written to the pointer address "5" in the SRAM2P(0), that is, the write address of the current data.
  • W(0,5) in the process of writing data, in addition to directly writing 128 bits of data to all "1" Specifying the pointer address "5" in the position SRAM2P(0), and reading the data of the remaining main memory at the same pointer address, assuming that the data read from the pointer address "5" in the SRAM2P(1) is 128 bits.
  • the data reading process is as follows:
  • the read addresses of the two read data are respectively obtained as R1 (x1, y1), R2 (x2, y2), and x1 and y1 represent the arrangement positions of the SRAM2P memory in which the read data is located, 0 ⁇ x1 ⁇ 2 m, 0. ⁇ x2 ⁇ 2m, y1, y2 represent the specific pointer address in the SRAM2P memory in which the read data is located, 0 ⁇ y1 ⁇ M, 0 ⁇ y2 ⁇ M;
  • reading data stored in one of the read addresses R1 (x1, y1) reads the currently stored data directly from the current designated read address;
  • the remaining main memory having the same pointer address as the other read address, and the data stored in the auxiliary memory are acquired, and exclusive-ORed are performed, and the result of the exclusive OR operation is output as the stored data of the other read address.
  • the read data is two, and the pointer addresses are the pointer address "2" in the SRAM2P(0) and the pointer address "5" in the SRAM2P(0). , that is, the current data read address is R (0, 2) and R (0, 5);
  • the present invention solves the problem of simultaneously reading data by two read ports by using an exclusive OR operation.
  • the data is output and outputted by the above process, and the result is completely identical with the data stored in the pointer address "5" in the SRAM2P(0), thus, according to the current pointer position of the data, associated with the main memory and the auxiliary memory
  • the data is XORed to complete the writing and reading of the data.
  • the read addresses of the two current read data are in different SRAM2P memories, the data directly acquiring the corresponding pointer addresses in the different SRAM2P memories are independently output.
  • the read data is two, and the pointer addresses are the pointer address "5" in the SRAM2P(0) and the pointer address "10" in the SRAM2P(1). , that is, the current data read address is R (0, 5) and R (1, 10);
  • each SRAM2P is logically further divided, for example, into 4m SRAM2Ps having the same depth
  • the above 2R1W type SRAM can be constructed by adding only 1/4m of the memory area; correspondingly, Physically, the number of blocks of SRAM is also increased by nearly 2 times, which occupies a lot of area overhead in actual layout and routing; of course, the present invention is not limited to the above specific embodiments, and other uses XOR operation to expand the memory port.
  • the solution is also included in the scope of protection of the present invention and will not be described in detail herein.
  • the bandwidth requirement can be satisfied; thus, the write data of the two slices is respectively written to one.
  • the write data of the other two slices are respectively written into the two 2R1W memories of the other other banks, so that the write data does not collide.
  • the bandwidth requirement can be satisfied; that is, the data of each slice needs to occupy the entire bank; For each slice, only two clock cycles are required, and ping-pong operation can be used to meet the demand.
  • two of the data are written into two banks, and the second cycle arrives.
  • the other two data are respectively written into two banks; wherein, two 2R1W memories in each bank respectively store the high and bottom bits of any data larger than 144 bytes, and no detailed description is made here. Narration. As such, there is no conflict in writing data.
  • the reading process is similar to the writing process, in which only two data readings are supported per clock cycle;
  • the read data is stored in the same 2R1W memory of the same bank, since each 2R1W memory of the present invention can simultaneously support Two read requests, so data can be read directly from the specified port regardless of the circumstances.
  • the read data is stored in the same bank, similar to the writing process, only needs to use ping pong in two clock cycles.
  • the operation can satisfy the read request, and will not be described in detail here.
  • n-read n-write memory is constructed based on the above-described 2-read n-write memory cells.
  • the method includes:
  • the data is respectively written into different 2R1W memories according to the destination port of the data;
  • the matched read port in the multi-port memory of n-read n-write is selected to directly read data
  • the second clock cycle is awaited, and when the second clock cycle comes, the matching read port in the multi-port memory of n-read n-write is selected to directly read the data.
  • the data writing and reading process of the n-read n-write multi-port memory is similar to the writing and reading process of the 2-read n-write multi-port memory cell, and the difference is only in the process of writing data.
  • the write port is matched according to the write port of the write data, and others are not described in detail.
  • n 4
  • the structures of X0Y0 and X1Y1 are the same as those shown in FIG. 13, and the data writing and reading process are performed according to the same.
  • the corresponding forwarding port is stored.
  • the data of S0 and S1 can only be written into X0Y0
  • the data of S2 and S3 can only be written into X1Y1.
  • the writing process is not described in detail.
  • n 8
  • the structures of X0Y0, X1Y1, X2Y2, and X3Y3 are similar to the structure shown in FIG. 13, and the difference is that Based on the structure shown in Figure 13, two more banks are added to form the 2R8W memory. During the data writing and reading process, it needs to be stored according to its corresponding forwarding port. For example, the data of S0 and S1 can only be written to X0Y0.
  • the data of S2 and S3 can only be written into X1Y1, the data of S4 and S5 can only be written into X2Y2, and the data of S6 and S7 can only be written into X3Y3, and the writing process is not described in detail.
  • the hardware framework of the n-read n-write memory can be realized based on only n/2 2-read n-write multi-port memory cells. Compared with the traditional 2R2W memory-based memory expansion method, it is easy to implement More extensions to Slice.
  • the 4R4W memory and the 14nm integrated circuit process are taken as an example for description.
  • a data processing system for an expandable multi-port memory wherein the multi-port memory is a 2-port n-write multi-port memory unit, and n is an even number.
  • the system includes: a data construction module 100, a data processing module 200;
  • the data construction module 100 is specifically configured to: assemble two 2R1W memories into one bank storage unit in parallel;
  • the data processing module 200 is specifically configured to: when determining one clock cycle, data is written to the two-read n-write multi-port memory unit through n write ports;
  • the size of the data is less than or equal to the bit width of the 2R1W memory, the data is respectively written into different 2R1W memories;
  • the data processing module 200 is further configured to: when it is determined that one clock period, data is read from two read ports of the multi-port memory unit of the 2 read n write,
  • the read port selected in the multi-port memory unit of the 2 read n write is directly read out data
  • the second clock cycle is awaited, and when the second clock cycle arrives, the matched read port of the multi-port memory cell of the 2nd read n write is directly read out.
  • the data construction module 100 establishes the 2R1W memory in five ways.
  • the data construction module 100 divides a word line into two left and right sides, so that two read ports can be simultaneously operated or one write port can be used.
  • the data read from the left MOS transistor and the data read from the right MOS transistor can be simultaneously performed.
  • the data read by the right MOS transistor needs to be inverted before being used, and in order not to affect the speed of data reading.
  • the sense amplifier that is read out requires a pseudo differential amplifier.
  • the 6T SRAM area is unchanged, the only cost is to double the word line, thus ensuring that the overall storage density is basically unchanged.
  • the data construction module 100 can increase the port of the SRAM by custom design, and cut one word line into two word lines, and increase the read port to two;
  • the technique of operation that is, the read operation is performed on the rising edge of the clock, and the write operation is completed on the falling edge of the clock.
  • This also expands a basic 1-read or 1-write SRAM into a 1-read and 1-write SRAM type, ie One read and one write can be performed simultaneously, and the storage density is basically unchanged.
  • an SRAM of 2R1W is constructed based on SRAM2P, which is an SRAM type capable of supporting 1 read and 1 read/write, that is, SRAM2P can be simultaneously performed 2 One read operation, or one read and one write operation.
  • the data construction module 100 constructs a 2R1W SRAM based on the SRAM2P by copying a copy of the SRAM; in this example, the SRAM2P_1 on the right is a copy of the left SRAM2P_0, and in the specific operation, the two SRAM2Ps are read as 1 and 1 Write memory to use; in which, when writing data, write data to the left and right SRAM2P at the same time.
  • A is fixed to read from SRAM2P_0
  • data B is fixedly read from SRAM2P_1, so that one write operation can be realized. And two read operations are performed concurrently.
  • the data construction module 100 divides the logically monolithic 16384-depth SRAM into logically four 4096-depth SRAM2Ps, which are numbered 0, 1, and 2, respectively. 3, and then add a 4096-depth SRAM, numbered 4, as a solution to read and write conflicts, for read data A and read data B, always ensure that the two read operations can be performed concurrently, when the address of two read operations When it is in different SRAM2P, since any one of SRAM2P can be configured as 1R1W type, there will be no conflict between read and write; when the addresses of 2 read operations are in the same block In SRAM2P, for example, they are all in SRAM2P_0.
  • a memory block mapping table is required to record which memory block stores valid data.
  • the depth of the memory block mapping table is the same as the depth of one memory block, that is, 4096 depths, each In an entry, the number of each memory block is sequentially stored after initialization, from 0 to 4.
  • SRAM2P_0 since SRAM2P_0 has read and write conflicts when writing data, the data is actually written to SRAM2P_4.
  • the read operation also reads the corresponding content in the memory map, the original content is ⁇ 0, 1, 2, 3, 4 ⁇ , and after modification, it becomes ⁇ 4, 1, 2, 3, 0 ⁇ , the first block
  • the number and the 4th block number are reversed, indicating that the data is actually written to SRAM2P_4, and SRAM2P_0 becomes a backup entry.
  • the memory block number mapping table address is first read.
  • the memory block number map is required to provide 1 read and 1 write ports.
  • the memory block number map is required to provide 2 read ports, so that a total of memory block number maps are required to provide 3 reads. Port and 1 write port, and these 4 access operations must be performed simultaneously.
  • the data construction module 100 selects 2m+1 blocks of SRAM2P memory having the same depth and width according to the depth and width of the 2R1W memory to construct a 2R1W memory.
  • Hardware framework m is a positive integer
  • the plurality of SRAM2P memories are sequentially SRAM2P(0), SRAM2P(1), ..., SRAM2P(2m), and each SRAM2P memory has M pointer addresses, wherein one of the plurality of SRAM2P memories For the auxiliary memory, the rest are the main memory;
  • each SRAM2P memory (the product of the depth and width of the 2R1W memory) / 2m.
  • the plurality of SRAM2P memories are sequentially SRAM2P(0), SRAM2P(1), SRAM2P(2), SRAM2P(3), SRAM2P(4), wherein SRAM2P(0), SRAM2P(1), SRAM2P(2), SRAM2P(3) are the main memories, and SRAM2P(4) is the auxiliary memory.
  • the depth and width of each SRAM2P memory are 4096 and 128 respectively.
  • each SRAM2P memory has 4096. Pointer address; if the address of each SRAM2P memory is independently identified, the address of each SRAM2P memory is 0 ⁇ 4095. If all the addresses of the main memory are arranged in order, all the pointer addresses are: 0 to 16383.
  • SRAM2P(4) is used to resolve port conflicts, and in this embodiment, there is no need to add a memory block number mapping table to meet the demand.
  • the data processing module 200 when data is written to and/or read from the 2R1W memory, the data processing module 200 is specifically configured to: associate the main memory and the auxiliary memory according to the current pointer position of the data. The data is XORed and the data is written and read.
  • the data writing process is as follows:
  • the write address of the current data is W(x, y), and x represents the arrangement position of the SRAM2P memory where the write data is located, 0 ⁇ x ⁇ 2m, and y represents the specific pointer in the SRAM2P memory where the write data is located. Address, 0 ⁇ y ⁇ M;
  • the data in the remaining main memory having the same pointer address as the write address is obtained, and it is XORed with the current write data at the same time, and the XOR operation result is written into the same pointer address of the auxiliary memory.
  • the data processing module 200 reads out the data as follows:
  • the data processing module 200 is specifically configured to: respectively acquire the read addresses of the two read data as R1 (x1, y1), R2 (x2, y2), and x1 and y1 respectively indicate the arrangement position of the SRAM2P memory in which the read data is located.
  • 0 ⁇ x1 ⁇ 2m, 0 ⁇ x2 ⁇ 2m, y1, y2 each represent a specific pointer address in the SRAM2P memory in which the read data is located, 0 ⁇ y1 ⁇ M, 0 ⁇ y2 ⁇ M;
  • the data processing module 200 is specifically configured to: select the read data stored in one of the read addresses R1 (x1, y1), and directly read the currently stored data from the current designated read address;
  • the data processing module 200 is specifically configured to: acquire the remaining main memory having the same pointer address as another read address, and store the auxiliary memory The stored data is subjected to an exclusive OR operation, and the result of the exclusive OR operation is output as the stored data of another read address.
  • the data processing module 200 directly obtains data corresponding to the pointer addresses in the different SRAM2P memories and outputs them independently.
  • each SRAM2P is logically further divided, for example, into 4m SRAM2Ps having the same depth
  • the above 2R1W type SRAM can be constructed by adding only 1/4m of the memory area; correspondingly, Physically, the number of blocks of SRAM is also increased by nearly 2 times, which occupies a lot of area overhead in actual layout and routing; of course, the present invention is not limited to the above specific embodiments, and other uses XOR operation to expand the memory port.
  • the solution is also included in the scope of protection of the present invention and will not be described in detail herein.
  • the data construction module 100 constructs a hardware architecture of n-read n-write memory based on the above-mentioned 2-read n-write memory unit.
  • the data construction module 100 directly forms a hardware framework of n-read n-write memory based on n/2 of the 2 read n-write multi-port memory units;
  • the data processing module 200 is further configured to: when it is determined that one clock cycle is written to the n-read n-write multi-port memory through the n write ports,
  • the data is respectively written into different 2R1W memories according to the destination port of the data;
  • the data processing module 200 is further configured to: when it is determined that one clock period is read, when data is read from two read ports of the n-write multi-port memory
  • the matched read port in the multi-port memory of n-read n-write is selected to directly read data
  • the second clock cycle is awaited, and when the second clock cycle comes, the matching read port in the multi-port memory of n-read n-write is selected to directly read the data.
  • the data writing and reading process of the n-read n-write multi-port memory is similar to the writing and reading process of the 2-read n-write multi-port memory cell, and the difference is only in the process of writing data.
  • the write port is matched according to the write port of the write data, and others are not described in detail.
  • n 4
  • the structures of X0Y0 and X1Y1 are the same as those shown in FIG. 13, and the data writing and reading process are performed according to the same.
  • the corresponding forwarding port is stored.
  • the data of S0 and S1 can only be written into X0Y0
  • the data of S2 and S3 can only be written into X1Y1.
  • the writing process is not described in detail.
  • n 8
  • the structures of X0Y0, X1Y1, X2Y2, and X3Y3 are similar to the structure shown in FIG. 13, and the difference is that Based on the structure shown in Figure 13, two more banks are added to form the 2R8W memory. During the data writing and reading process, it needs to be stored according to its corresponding forwarding port. For example, the data of S0 and S1 can only be written to X0Y0.
  • the data of S2 and S3 can only be written into X1Y1, the data of S4 and S5 can only be written into X2Y2, and the data of S6 and S7 can only be written into X3Y3, and the writing process is not described in detail.
  • the hardware framework of the n-read n-write memory can be realized based on only n/2 2-read n-write multi-port memory cells. Compared with the traditional method of expanding the port of the memory based on the 2R2W memory, it is convenient to implement more Slice extension.
  • the data processing method and processing system of the scalable multi-port memory of the present invention constructs more port SRAMs by means of an algorithm, and can maximize the maximum cost.
  • Support multi-port SRAM in the implementation process, avoid using complex control logic and additional multi-port SRAM or register array resources, using the speciality of message buffer, through spatial segmentation and time division, only need simple XOR operation
  • the message cache of multiple ports can be implemented.
  • all the cache resources of the multi-port memory implemented by the present invention can be completely shared between any input ports, and logically, a CCE can be used to construct a multi-port memory.
  • Easy to implement port expansion the invention has lower power consumption, faster processing speed, and saves more resources or area, and the message buffer architecture has better scalability, simple implementation, saving manpower and material cost. .
  • the device embodiments described above are merely illustrative, wherein the modules described as separate components may or may not be physically separate, and the components displayed as modules may or may not be physical modules, ie may be located A place, or it can be distributed to multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. Those of ordinary skill in the art can understand and implement without any creative effort.

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Abstract

一种可扩展的多端口存储器的数据处理方法及处理系统，所述多端口存储器为2读n写的多端口存储器单元，n为偶数；所述方法包括：将2个2R1W存储器并行拼装为一个Bank存储单元；将n/2个Bank存储单元在深度上拼装为一个2读n写的多端口存储器单元的硬件框架；一个时钟周期下，当数据通过n个写端口写入到2读n写的多端口存储器单元时，若数据的大小小于等于所述2R1W存储器的位宽，则将数据分别写入不同的2R1W存储器中；若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，将写入数据的高低位分别写入到一个Bank存储单元的2个2R1W存储器中。上述数据处理方法及处理系统具有更低的功耗，能节省更多的资源或面积，并具有更好的扩展性。

Description

可扩展的多端口存储器的数据处理方法及数据处理系统
本申请要求了申请日为2016年07月28日，申请号为201610605711.0，发明名称为“可扩展的多端口存储器的数据处理方法及数据处理系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及网络通信技术领域，尤其涉及一种可扩展的多端口存储器的数据处理方法及数据处理系统。
背景技术
在设计以太网交换芯片时，通常需要使用大容量的多端口存储器，例如2读1写(同时支持2个读端口和1个写端口)存储器、1读2写存储器、2读2写存储器或者更多端口的存储器。
通常情况下，供应商一般只提供1个读或者写存储器、1读1写存储器和2个读或者写存储器，如此，设计者仅能基于上述基本存储器单元构建多个端口的存储器。
报文缓存是一类特殊的多端口存储器，其写入是可控的，亦即，顺序写入，但是读出却是随机的。用户的其中一种需求中，单向交换容量为2.4Tbps的以太网交换芯片，为了做到线速写入和读出，每个最小报文(64字节)花费的时间只有280ps，需要核心频率高达3.571GHz，该种需求目前在现有的半导体工艺上无法实现。为了实现上述目标，通常的做法是，把整个芯片分割成多个独立的报文转发和处理单元并行进行处理，报文转发和处理单元的英文名称为Slice，例如分割成4个Slice并行处理，每个Slice需要处理的数据带宽就降低，对核心频率的要求也会降低到原核心频率的1/4。相应的，实现该方案过程中，对于报文缓存需要同时提供8个端口供4个Slice访问，其中4个是读端口，4个是写端口。
另外，多端口存储器不仅要考虑到设计的移植性，还需要考虑到设计的可扩展性，设计的存储架构能够很方便的从4个slice扩展到6个，8个或者更多slice的架构。
一般的，在SRAM的端口类型为1个读或者写，2个读或者写，以及1写或者2读的基础上，通过定制设计，例如：修改存储单元的办法，以及算法设计来增加SRAM的端口数量。
定制设计的周期一般比较长，需要做spice仿真，还要提供存储器编译器，以生成不同大小和类型的SRAM，对于供应商来说，一般需要6～9个月的时间，才能提供一个新型的SRAM的类型，而且这样的定制设计是与具体的工艺(例如GlobalFoundries 14nm，28nm还是TSMC的28nm，16nm)强相关的，工艺一旦改变，定制设计的SRAM库需要重新设计。
算法设计是基于厂家提供的现成的SRAM类型，通过算法来实现多端口存储器，最大的好处是避免定制设计，缩短时间，同时设计与厂家库无关，可以很容易的在不同的厂家库之间移植。
如图1所示，一种通过算法设计的方式，设计一个支持4个slice访问的4读4写的存储架构，该实施方式中，采用1R1W的SRAM2D设计大容量的2R2W的SRAM，逻辑上总共需要4块65536深度2304宽度大小的SRAM2D，由于单个物理SRAM2D的容量无法满足上述需求，需要把1块65536深度2304宽度的逻辑SRAM切割成多块物理SRAM，例如：可以切割成32块16384深度288宽度的物理块，这样总共需要32x4＝128块物理块；以上述2R2W SRAM为基本单元，搭建18M字节大小的4R4W SRAM。
结合图2所示，逻辑上总共需要4块65536深度2304宽度大小的2R2W的SRAM，即：需要SRAM2D(16384深度288宽度)的物理块的个数为512块；根据现有数据可知：14nm工艺条件下，一块16384深度288宽度大小SRAM2D物理块的大小是0.4165平方厘米，功耗是0.108Watts(核心电压＝0.9V，结温＝125摄氏度，工艺条件是最快)；上述采用厂家库提供的基本单元SRAM复制多份拷贝，构建更多端口SRAM的方法，虽然设计原理上显而易见，但是面积开销非常大，以上述方案为例，单单18M字节4读4写SRAM的面积就占用了213.248平方厘米，总的功耗为55.296Watts，这里还没有考虑到插入Decap和DFT以及布局布线的开销，通过此种算法设计方式设计出的多端口SRAM，其占用面积以及总功耗均十分庞大；
同时这样的设计扩展性很差，如果要支持例如8个slice的架构，需要有16个端口，其中8个读端口和8个写端口，SRAM需要做成8读8写，SRAM所占用的面积和功耗是成倍的增长。
如图3A所示，现有技术中，另外一种算法设计方式，以2R2W的SRAM为基本单元，通过空间上的分割实现多个端口的报文缓存，以4个slices的报文缓存架构为例，每个X？Y？是一个CCE，其英文全称为Criss-Cross Element，中文译文为：纵横内存单元；横向的2个CCE构成一个CCHG，所述CCHG的英文全称为：Criss-Cross Horizontal Group，中文译文为：纵横内存水平分组；纵向的2个CCE构成一个CCVG，所述CCVG的英文全称为：Criss-Cross Vertical Group，中文译文为：纵横内存垂直分组。
现有算法设计中，每个CCE均为2R2W的SRAM逻辑块，大小是4.5M字节，总共有4块这样的SRAM逻辑块，构成4R4W SRAM，大小是18M字节(4.5Mx4＝18M)。
其中，S0、S1、S2、S3代表4个slice，每个slice举例来说包含有6个100GE端口，从slice0或者slice1输入去往slice0或者slice1的报文存入X0Y0，从slice0或者slice1输入去往slice2或者slice3的报文存入X1Y0，从slice2或者slice3输入去往slice0或者slice1的报文存入X0Y1，从slice2或者slice3输入去往slice2或者slice3的报文存入X1Y1；对于组播报文，从Slice0或者Slice1来的组播报文同时存入X0Y0和X1Y0中；进一步的，读取报文的时候，slice0或者slice1将从X0Y0或者X0Y1中读取报文，slice2或者slice3将从X1Y0或者X1Y1中读取报文。
结合图3B所示，基于2R2W构建8R8W存储器时，每个CCE同样均为2R2W的SRAM逻辑块，大小是4.5M字节，总共有(8/2)2，共16块这样的SRAM逻辑块，构成8R8W SRAM，其写入及读出数据与上述4R4W存储器相类似，在此不做详细赘述。
结合图4所示，现有技术中算法设计的每一个CCE的架构图，一个X？Y？逻辑上需要4块16384深度2304宽度的SRAM，每一个逻辑上16384深度和2304宽度的SRAM可以切割成8块16384深度和288宽度的物理SRAM2D；这样一个18M字节的报文缓存总共需要4x4x8＝128块16384深度和288宽度的物理SRAM2D，总的面积为51.312平方厘米，总的功耗是13.824Watts(核心电压＝0.9V，结温＝125摄氏度，工艺条件是最快)
上述第二种算法设计的面积和功耗开销只有上述第一种算法设计的1/4，然而，其扩展性却仍然得不到很好的满足。
结合图5所示，基于2R2W SRAM设计多端口的报文缓存存在可扩展性问题，基于2R2W存储器实现的CCE个数＝(Slice个数/2)^2，即CCE的个数是slice个数除以2再做2的平方得到，随着slice的个数增加，CCE的个数将多到无法实现，对于6个slice、8个slice以及更多的端口扩展，CCE的个数逐级增长，导致系统难以负荷。
发明内容
为解决上述技术问题，本发明的目的在于提供一种可扩展的多端口存储器的数据处理方法及处理系统。
为实现上述发明目的之一，本发明一实施方式提供的可扩展的多端口存储器的数据处理方法，所述多端口存储器为2读n写的多端口存储器单元，n为偶数；
所述方法包括：
将2个2R1W存储器并行拼装为一个Bank存储单元；
将n/2个Bank存储单元在深度上拼装为一个2读n写的多端口存储器单元的硬件框架；
一个时钟周期下，当数据通过n个写端口写入到2读n写的多端口存储器单元时，
若数据的大小小于等于所述2R1W存储器的位宽，则将数据分别写入不同的2R1W存储器中；
若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，将写入数据的高低位分别写入到一个Bank存储单元的2个2R1W存储器中。
作为本发明一实施方式的进一步改进，所述方法还包括：
一个时钟周期下，当数据从2读n写的多端口存储器单元的其中2个读端口读出时，
若数据的大小小于等于所述2R1W存储器的位宽，则选择2读n写的多端口存储器单元中匹配的读端口直接读出数据；
若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，选择2读n写的多端口存储器单元中匹配的读端口直接读出数据。
作为本发明一实施方式的进一步改进，所述方法还包括：
基于n/2个所述2读n写的多端口存储器单元直接形成n读n写存储器的硬件框架；
一个时钟周期下，当数据通过n个写端口写入到n读n写的多端口存储器时，
若数据的大小小于等于所述2R1W存储器的位宽，则根据数据的目的端口将数据分别写入不同的2R1W存储器中；
若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，根据数据的目的端口将写入数据的高低位分别写入到一个Bank存储单元的2个2R1W存储器中。
作为本发明一实施方式的进一步改进，所述方法还包括：
一个时钟周期下，当数据从n读n写的多端口存储器的其中2个读端口读出时，
若数据的大小小于等于所述2R1W存储器的位宽，则选择n读n写的多端口存储器中匹配的读端口直接读出数据；
若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，选择n读n写的多端口存储器中匹配的读端口直接读出数据。
作为本发明一实施方式的进一步改进，所述方法还包括：
根据2R1W存储器的深度和宽度选择2m+1块具有相同深度及宽度的SRAM2P存储器构建2R1W存储器的硬件框架，m为正整数；
每个SRAM2P存储器均具有M个指针地址，其中，多个所述SRAM2P存储器中的一个为辅助存储器，其余均为主存储器；
当数据写入2R1W存储器和/或从所述2R1W存储器读出时，根据数据的当前指针位置，关联主存储器以及辅助存储器中的数据，对其做异或运算，完成数据的写入和读出。
为了实现上述发明目的之一，本发明一实施方式提供一种可扩展的多端口存储器的数据处理系统，所述多端口存储器为2读n写的多端口存储器单元，n为偶数；所述系统包括：数据构建模块，数据处理模块；
所述数据构建模块具体用于：将2个2R1W存储器并行拼装为一个Bank存储单元；
将n/2个Bank存储单元在深度上拼装为一个2读n写的多端口存储器单元的硬件框架；
所述数据处理模块具体用于：当确定一个时钟周期下，数据通过n个写端口写入到2读n写的多端口存储器单元时；
若数据的大小小于等于所述2R1W存储器的位宽，则将数据分别写入不同的2R1W存储器中；
若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，将写入数据的高低位分别写入到一个Bank存储单元的2个2R1W存储器中。
作为本发明一实施方式的进一步改进，所述数据处理模块还用于：
当确定一个时钟周期下，数据从2读n写的多端口存储器单元的其中2个读端口读出时，
若数据的大小小于等于所述2R1W存储器的位宽，则选择2读n写的多端口存储器单元中匹配的读端口直接读出数据；
若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，选择2读n写的多端口存储器单元中匹配的读端口直接读出数据。
作为本发明一实施方式的进一步改进，所述数据构建模块还用于：基于n/2个所述2读n写的多端口存储器单元直接形成n读n写存储器的硬件框架；
所述数据处理模块还用于：当确定一个时钟周期下，数据通过n个写端口写入到n读n写的多端口存储器时，
若数据的大小小于等于所述2R1W存储器的位宽，则根据数据的目的端口将数据分别写入不同的2R1W存储器中；
若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，根据数据的目的端口将写入数据的高低位分别写入到一个Bank存储单元的2个2R1W存储器中。
作为本发明一实施方式的进一步改进，所述数据处理模块还用于：
当确定一个时钟周期下，数据从n读n写的多端口存储器的其中2个读端口读出时，
若数据的大小小于等于所述2R1W存储器的位宽，则选择n读n写的多端口存储器中匹配的读端口直接读出数据；
若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，选择n读n写的多端口存储器中匹配的读端口直接读出数据。
作为本发明一实施方式的进一步改进，所述数据构建模块还用于：根据2R1W存储器的深度和宽度选择2m+1块具有相同深度及宽度的SRAM2P存储器构建2R1W存储器的硬件框架，m为正整数；
每个SRAM2P存储器均具有M个指针地址，其中，多个所述SRAM2P存储器中的一个为辅助存储器，其余均为主存储器；
当数据写入2R1W存储器和/或从所述2R1W存储器读出时，所述数据处理模块还用于：根据数据的当前指针位置，关联主存储器以及辅助存储器中的数据，对其做异或运算，完成数据的写入和读出。
与现有技术相比，本发明的可扩展的多端口存储器的数据处理方法及处理系统，基于现有的SRAM类型，通过算法的方式搭建更多端口的SRAM，仅仅用最小的代价便可以最大限度的支持多端口SRAM；其实现过程中，避免采用复杂的控制逻辑和额外的多端口SRAM或者寄存器阵列资源，利用报文缓存的特殊性，通过空间分割和时间分割，仅需要简单的异或运算就可实现多个端口的报文缓存，同时，通过本发明实现的多端口存储器，其所有缓存资源可以在任意输入端口之间实现完全共享，逻辑上采用更少的CCE即可以构建多端口存储器，容易实现端口的扩展，本发明具有更低的功耗，更快的处理速度，以及节省更多的资源或面积，其报文缓存架构具有更好的扩展性，实现简单，节约人力及物质成本。
附图说明
图1是现有技术中，基于1R1W存储器采用算法设计实现的2R2W存储器的报文缓存逻辑单元示意图；
图2是现有技术中，基于2R2W存储器采用算法设计实现的4R4W存储器的报文缓存逻辑单元示意图；
图3A是现有技术中，基于2R2W存储器采用另一种算法设计实现的4R4W存储器的报文缓存架构示意图；
图3B是现有技术中，基于2R2W存储器采用另一种算法设计实现的8R8W存储器的报文缓存架构示意图；
图4是图3中其中一个CCE的报文缓存逻辑单元示意图；
图5是现有技术中，基于2R2W存储器采用算法设计扩展存储器端口时，2R2W存储器与CCE数量对比关系示意图；
图6是本发明一实施方式中2读n写的可扩展的多端口存储器的数据处理方法的流程示意图；
图7是本发明第一实施方式中，通过定制设计形成的2R1W存储器的数字电路结构示意图；
图8是本发明第二实施方式的，通过定制设计形成的2R1W存储器读写分时操作示意图；
图9是本发明第三实施方式中，采用算法设计形成的2R1W存储器的报文缓存逻辑单元示意图；
图10a是本发明第四实施方式中，采用算法设计形成的2R1W存储器的报文缓存逻辑单元示意图；
图10b是对应图10a存储器块编号映射表的结构示意图；
图11是本发明第五实施方式中，提供的2R1W存储器的数据处理方法的流程示意图；
图12是本发明第五实施方式中，提供的2R1W存储器的的报文缓存逻辑单元示意图；
图13是本发明是一具体实施方式中，2个Bank的报文缓存架构示意图；
图14是本发明一实施方式中n读n写的可扩展的多端口存储器的数据处理方法的流程示意图；
图15A是本发明是一具体实施方式中，4R4W存储器的报文缓存架构示意图；
图15B是本发明是一具体实施方式中，8R8W存储器的报文缓存架构示意图；
图16是本发明是具体实施方式中，基于2读n写的存储器扩展存储器端口时，2读n写存储器与CCE数量对比关系示意图；
图17是本发明一实施方式中提供的可扩展的多端口存储器的数据处理系统的模块示意图。
具体实施方式
以下将结合附图所示的各实施方式对本发明进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
结合图6所示，本发明一实施方式提供的可扩展的多端口存储器的数据处理方法，该实施方式中，所述多端口存储器为2读n写的多端口存储器单元，n为偶数。
所述方法包括：
将2个2R1W存储器并行拼装为一个Bank存储单元；
将n/2个Bank存储单元在深度上拼装为一个2读n写的多端口存储器单元的硬件框架；
一个时钟周期下，当数据通过n个写端口写入到2读n写的多端口存储器单元时，
若数据的大小小于等于所述2R1W存储器的位宽，则将数据分别写入不同的2R1W存储器中；
若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，将写入数据的高低位分别写入到一个Bank存储单元的2个2R1W存储器中。
一个时钟周期下，当数据从2读n写的多端口存储器单元的其中2个读端口读出时，
若数据的大小小于等于所述2R1W存储器的位宽，则选择2读n写的多端口存储器单元中匹配的读端口直接读出数据；
若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，选择2读n写的多端口存储器单元中匹配的读端口直接读出数据。
本发明优选实施方式中，建立所述2R1W存储器有五种方法。
如图7所示，第一种实施方式中，在6T SRAM的基础，把一根字线分割成左右两个，这样可以做成2个读端口同时操作或者1个写端口，这样从左边MOS管读出的数据和右边MOS管读出的数据可以同时进行，需要注意的是，右边MOS管读出的数据需要反相之后才可以用，同时为了不影响数据读取的速度，读出的感应放大器需要用伪差分放大器。这样，6T SRAM面积不变，唯一的代价是增加一倍的字线，从而保证总体的存储密度基本不变。
如图8所示，第二种实施方式中，通过定制设计形成的2R1W存储器读写操作流程示意图；
通过定制设计可以增加SRAM的端口，把一个字线切割成2个字线，将读端口增加到2个；还可以通过分时操作的技术，即读操作在时钟的上升沿进行，而写操作在时钟的下降沿完成，这样也可以把一个基本的1读或者1写的SRAM扩展成1读和1写的SRAM类型，即1个读和1个写操作可以同时进行，存储密度基本不变。
如图9所示，第三种实施方式中本发明一实施方式中采用算法设计形成的2R1W存储器读写操作流程示意图；
本实施方式中，以SRAM2P为基础构建2R1W的SRAM为例，所述SRAM2P是一种能够支持1读和1读/写的SRAM类型，即可以对SRAM2P同时进行2个读操作，或者1个读和1个写操作。
本实施方式中，通过复制一份SRAM以SRAM2P为基础构建2R1W的SRAM；该示例中，右边的SRAM2P_1是左边SRAM2P_0的拷贝，具体操作的时候，把两块SRAM2P作为1读和1写存储器来使用；其中，写入数据时，同时往左右两个SRAM2P写入数据，读出数据时，A固定从SRAM2P_0读取，数据B固定从SRAM2P_1读取，这样就可以实现1个写操作和2个读操作并发进行。
如图10a、10b所示，第四种实施方式中，为另一实施方式中采用算法设计形成的2R1W存储器读写操作流程示 意图；
该实施方式中，把逻辑上一整块的16384深度的SRAM分割成逻辑上4块4096深度的SRAM2P，编号依次为为0、1、2、3，再额外增加一块4096深度的SRAM，编号为4，作为解决读写冲突用，对于读数据A和读数据B，永远保证这2个读操作可以并发进行，当2个读操作的地址是处于不同的SRAM2P中时，因为任何一个SRAM2P都可以配置成1R1W类型，所以读写不会有冲突；当2个读操作的地址处于同一块SRAM2P中时，例如：均处于SRAM2P_0中，由于同一个SRAM2P最多只能提供2个端口同时操作，此时，其端口被2个读操作占用，如果恰好有一个写操作要写入SRAM2P_0，那么这时就把这个数据写入存储器第4块SRAM2P_4中。
该种实施方式中，需要有一个存储器块映射表记录哪一个存储器块存放有效数据，如图10b所示，存储器块映射表的深度和一个存储器块的深度相同，即都是4096个深度，每一个条目中在初始化后依次存放每个存储器块的编号，从0到4，图10a示例中，由于SRAM2P_0在写入数据的时候发生读写冲突，数据实际上是写入到SRAM2P_4中，此时，读操作同时会读取存储器映射表中对应的内容，原始内容为{0，1，2，3，4}，修改之后变成{4，1，2，3，0}，第一个块编号和第4个块编号对调，表示数据实际写入到SRAM2P_4中，同时SRAM2P_0变成了备份条目。
当读取数据的时候，需要首先读对应地址的存储器块编号映射表，查看有效数据存放在哪一个存储器块中，例如当要读取地址5123的数据，那么首先读取存储块编号映射表地址1027(5123-4096＝1027)存放的内容，根据第二列的数字编号去读取对应存储块的地址1027的内容。
对于写数据操作，需要存储器块编号映射表提供1读和1写端口，对于2个读数据操作，需要存储器块编号映射表提供2个读端口，这样总共需要存储器块编号映射表提供3个读端口和1个写端口，而且这4个访问操作必须是同时进行。
如图11所示，第五种实施方式，即本发明的优选实施方式中，2R1W存储器的构建方法包括：
根据所述2R1W存储器的深度和宽度选择2m+1块具有相同深度及宽度的SRAM2P存储器构建2R1W存储器的硬件框架，m为正整数；
多个所述SRAM2P存储器按照排列顺序依次为SRAM2P(0)、SRAM2P(1)……、SRAM2P(2m)，每个SRAM2P存储器均具有M个指针地址，其中，多个所述SRAM2P存储器中的一个为辅助存储器，其余均为主存储器；
该发明的优选实施方式中，每块SRAM2P存储器的深度与宽度的乘积＝(2R1W存储器的深度与宽度乘积)/2m。
以下为了描述方便，对m取值为2、2R1W存储器为16384深度、128宽度的SRAM存储器进行详细描述。
则在该具体示例中，多个所述SRAM2P存储器按照排列顺序依次为SRAM2P(0)、SRAM2P(1)、SRAM2P(2)、SRAM2P(3)、SRAM2P(4)，其中，SRAM2P(0)、SRAM2P(1)、SRAM2P(2)、SRAM2P(3)为主存储器，SRAM2P(4)为辅助存储器，每个SRAM2P存储器的深度和宽度分别为4096和128，相应的，每个SRAM2P存储器均具有4096个指针地址；如果对每个SRAM2P存储器的指针地址均独立标识，则每个SRAM2P存储器的指针地址均为0～4095，若将全部的主存储器的地址依次排列，则全部的指针地址范围为:0～16383。该示例中，SRAM2P(4)用于解决端口冲突，且在该实施方式中，无需增加存储器块编号映射表即可以满足需求。
进一步的，在上述硬件框架基础上，所述方法还包括：
当数据写入2R1W存储器和/或从所述2R1W存储器读出时，根据数据的当前指针位置，关联主存储器以及辅助存储器中的数据，对其做异或运算，完成数据的写入和读出。
本发明优选实施方式中，其数据写入过程如下：
获取当前数据的写入地址为W(x，y)，x表示写入数据所处于的SRAM2P存储器的排列位置，0≤x＜2m，y表示写入数据所处于的SRAM2P存储器中的具体的指针地址，0≤y≤M；
获取与写入地址具有相同指针地址的其余主存储器中的数据，将其同时与当前写入数据做异或运算，并将异或运算结果写入到辅助存储器的相同指针地址中。
结合图12所示，本发明一具体示例中，本发明一具体示例中，将数据128比特全“1”写入到SRAM2P(0)中的指针地址“5”，即当前数据的写入地址为W(0,5)，在写入数据过程中，除了直接将数据128比特全“1”写入到 指定位置SRAM2P(0)中的指针地址“5”外，同时，需要读取其余主存储器在相同指针地址的数据，假设从SRAM2P(1)中的指针地址“5”读出的数据为128比特全“1”，从SRAM2P(2)中的指针地址“5”读出的数据为128比特全“0”，从SRAM2P(3)中的指针地址“5”读出的数据为128比特全“1”，则将数据128比特全“1”、128比特全“0”、128比特全“1”、128比特全“1”做异或运算，并将其异或运算的结果“1”同时写入到SRAM2P(4)中的指针地址“5”。如此，以保证2R1W存储器的2个读端口和1个写端口同时操作。
进一步的，本发明优选实施方式中，其数据读出过程如下：
若当前两个读出数据的读出地址处于相同的SRAM2P存储器中，则
分别获取两个读出数据的读出地址为R1(x1，y1)，R2(x2，y2)，x1、y1均表示读出数据所处于的SRAM2P存储器的排列位置，0≤x1＜2m，0≤x2＜2m，y1、y2均表示读出数据所处于的SRAM2P存储器中的具体的指针地址，0≤y1≤M，0≤y2≤M；
任选其中一个读出地址R1(x1，y1)中存储的读出数据，从当前的指定读出地址中直接读出当前存储的数据；
获取与另一个读出地址具有相同指针地址的其余主存储器、以及辅助存储器中存储的数据，并对其做异或运算，将异或运算结果作为另一个读出地址的存储数据进行输出。
接续图12所示，本发明一具体示例中，读出的数据为2个，其指针地址分别为SRAM2P(0)中的指针地址“2”，以及SRAM2P(0)中的指针地址“5”，即当前数据的读出地址为R(0，2)和R(0，5)；
在从2R1W存储器读出数据过程中，由于每一个SRAM2P只能保证1个读端口和1个写端口同时操作，读端口直接从SRAM2P(0)中的指针地址“2”中读取数据，但是另一读端口的请求无法满足。相应的，本发明采用异或运算的方式解决两个读端口同时读出数据的问题。
对于R(0，5)中的数据，分别读取其他三个主存储器以及辅助存储器的指针地址“5”的数据并对其做异或运算，接续上例，从SRAM2P(1)中的指针地址“5”读出的数据为“1”，从SRAM2P(2)中的指针地址“5”读出的数据为“0”，从SRAM2P(3)中的指针地址“5”读出的数据为128比特全“1”，从SRAM2P(4)中的指针地址“5”读出的数据为128比特全“1”，将数据128比特全“1”、128比特全“1”、128比特全“0”、128比特全“1”做异或运算，得到128比特“1”，并将其异或运算的结果128比特全“1”作为SRAM2P(0)中的指针地址“5”的存储数据进行输出，通过上述过程得到的数据，其结果与SRAM2P(0)中的指针地址“5”中存储的数据完全一致，如此，根据数据的当前指针位置，关联主存储器以及辅助存储器中的数据，对其做异或运算，完成数据的写入和读出。
本发明一实施方式中，若当前两个读出数据的读出地址处于不同的SRAM2P存储器中，则直接获取不同SRAM2P存储器中对应指针地址的数据分别独立进行输出。
接续图12所示，本发明一具体示例中，读出的数据为2个，其指针地址分别为SRAM2P(0)中的指针地址“5”，以及SRAM2P(1)中的指针地址“10”，即当前数据的读出地址为R(0，5)和R(1，10)；
在从2R1W存储器读出数据过程中，由于每一个SRAM2P均能保证1个读端口和1个写端口同时操作，故，读出数据过程中，直接从SRAM2P(0)中的指针地址“5”读取数据，以及直接从SRAM2P(1)中的指针地址“10”读出数据，如此，以保证2R1W存储器的2个读端口和1个写端口同时操作，在此不做详细赘述。
需要说明的是，如果逻辑上把每一个SRAM2P进一步切分，比如切分成4m个具有相同深度的SRAM2P，那么只需要增加额外1/4m的存储器面积就可以构建上述2R1W类型的SRAM；相应的，物理上SRAM的块数也增加了近2倍，在实际的布局布线中会占用不少的面积开销；当然，本发明并不以上述具体实施方式为限，其它采用异或运算以扩展存储器端口的方案也包括在本发明的保护范围内，在此不做详细赘述。
结合图13所示，对于本发明的2读n写的多端口存储器单元，以下为了描述方便，接续上述示例，对n取值为4进行详细描述。该示例中，以2个16384深度和1152宽度的2R1W类型的SRAM并行拼装成一个Bank，一个Bank的容量大小是4.5M字节，总共有2个bank组成一个9M字节的2R4W多端口存储器单元。
该示例中，数据写入2读n写的多端口存储器单元过程中，需要同时支持4个slice的同时写入，假设，每个slice 的数据总线位宽是1152bits，同时每个slice支持6个100GE端口线速转发；在数据通道上最差的情况，对于小于等于144字节长度的报文数据，需要核心时钟频率跑到892.9MHz，对于大于144字节长度的报文，需要核心时钟频率跑到909.1MHz。
一个时钟周期下，若写入数据的位宽小于等于144字节，同时，需要满足4个Slice同时写入，才能满足带宽需求；如此，通过2个Slice的写入数据分别写入到1个Bank的2个2R1W存储器中，另外2个Slice的写入数据分别写入到其余另一个Bank的2个2R1W存储器中，如此，写入数据不会发生冲突。
一个时钟周期下，若写入数据的位宽大于144字节，同时，需要满足4个Slice同时写入，才能满足带宽需求；即：通过每个Slice的数据均需要占用整个Bank；如此，对于每个Slice而言，只需要在2个时钟周期下，采用乒乓操作即可以满足需求，例如：一个时钟周期下，将其中的两个数据分别写入到2个Bank中，第二个周期到来时，将另外两个数据分别写入到2个Bank中；其中，每个Bank中的两个2R1W存储器，分别对应存储任一个大于144字节的数据的高位和底位，在此不做详细赘述。如此，写入数据不会发生冲突。
其读取过程与写入过程相类似，该示例中，每个时钟周期下，仅支持两个数据的读出；
一个时钟周期下，若读出数据的位宽小于等于144字节，最坏情况下，读出数据存储于同一个Bank的同一个2R1W存储器中，由于本发明的每个2R1W存储器均可以同时支持两个读出请求，故无论在什么情况下，数据均可以从指定端口直接读出。
一个时钟周期下，若读出数据的位宽大于144字节，最坏情况下，读出数据存储于同一个Bank中，与写入过程相类似，仅需要在两个时钟周期下，采用乒乓操作，即可以满足读出请求，在此不做详细赘述。
进一步的，结合图14所示，本发明一优选实施方式中，基于上述2读n写的存储器单元构建n读n写的存储器的硬件架构。
本发明一具体实施方式中，所述方法包括：
基于n/2个所述2读n写的多端口存储器单元直接形成n读n写存储器的硬件框架；
一个时钟周期下，当数据通过n个写端口写入到n读n写的多端口存储器时，
若数据的大小小于等于所述2R1W存储器的位宽，则根据数据的目的端口将数据分别写入不同的2R1W存储器中；
若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，根据数据的目的端口将写入数据的高低位分别写入到一个Bank存储单元的2个2R1W存储器中。
一个时钟周期下，当数据从n读n写的多端口存储器的其中2个读端口读出时，
若数据的大小小于等于所述2R1W存储器的位宽，则选择n读n写的多端口存储器中匹配的读端口直接读出数据；
若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，选择n读n写的多端口存储器中匹配的读端口直接读出数据。
上述n读n写的多端口存储器的数据写入及读出过程均与2读n写的多端口存储器单元的写入及读出过程相类似，其区别仅在于，写入数据过程中，需根据写入数据的转发端口匹配其写入位置，其他不在详细赘述。
结合图15A所示，本发明一具体示例中，n的取值为4，该具体示例中，X0Y0以及X1Y1的结构均与图13所示相同，数据写入及读出过程中，需根据其对应的转发端口进行存储，例如：S0、S1的数据仅能写入到X0Y0中，而S2、S3的数据仅能写入到X1Y1中，其写入过程不在具体赘述。
结合图15B所示，本发明一具体示例中，n的取值为8，该具体示例中，X0Y0、X1Y1、X2Y2以及X3Y3的结构均与图13所示结构相类似相同，其区别在于，在图13所示结构基础上再增加2个Bank以构成2R8W存储器，数据写入及读出过程中，需根据其对应的转发端口进行存储，例如：S0、S1的数据仅能写入到X0Y0中，S2、S3的数据仅能写入到X1Y1中，S4、S5的数据仅能写入到X2Y2中，而S6、S7的数据仅能写入到X3Y3中，其写入过程不在具体赘述。
结合图16所示，本实施方式中，当需要对存储器的端口进行扩展时，仅基于n/2个2读n写的多端口存储器单元即可以实现n读n写的存储器的硬件框架，相较于传统的基于2R2W存储器对存储器的端口进行扩展的方法，便于实现 更多Slice的扩展。
另外，以4R4W存储器和14nm集成电路工艺为例进行说明，采用本发明获得的4R4W存储器，其逻辑上总共个需要40个4096深度1152宽度的SRAM2P，总共占用面积22.115平方厘米，总的功耗为13.503Watts(核心电压＝0.9V,结温＝125摄氏度,工艺条件是最快)，同时，不需要复杂的控制逻辑，只需要简单的异或运算就可实现多个读端口的操作；另外，也不需要额外的存储器块映射表和控制逻辑。
结合图17所示，本发明一实施方式提供的可扩展的多端口存储器的数据处理系统，该实施方式中，所述多端口存储器为2读n写的多端口存储器单元，n为偶数。
所述系统包括：数据构建模块100，数据处理模块200；
所述数据构建模块100具体用于：将2个2R1W存储器并行拼装为一个Bank存储单元；
将n/2个Bank存储单元在深度上拼装为一个2读n写的多端口存储器单元的硬件框架；
所述数据处理模块200具体用于：当确定一个时钟周期下，数据通过n个写端口写入到2读n写的多端口存储器单元时；
若数据的大小小于等于所述2R1W存储器的位宽，则将数据分别写入不同的2R1W存储器中；
若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，将写入数据的高低位分别写入到一个Bank存储单元的2个2R1W存储器中。
所述数据处理模块200还用于：当确定一个时钟周期下，数据从2读n写的多端口存储器单元的其中2个读端口读出时，
若数据的大小小于等于所述2R1W存储器的位宽，则选择2读n写的多端口存储器单元中匹配的读端口直接读出数据；
若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，选择2读n写的多端口存储器单元中匹配的读端口直接读出数据。
本发明优选实施方式中，数据构建模块100采用5种方式建立所述2R1W存储器。
如图7所示，第一种实施方式中，在6T SRAM的基础，数据构建模块100把一根字线分割成左右两个，这样可以做成2个读端口同时操作或者1个写端口，这样从左边MOS管读出的数据和右边MOS管读出的数据可以同时进行，需要注意的是，右边MOS管读出的数据需要反相之后才可以用，同时为了不影响数据读取的速度，读出的感应放大器需要用伪差分放大器。这样，6T SRAM面积不变，唯一的代价是增加一倍的字线，从而保证总体的存储密度基本不变。
如图8所示，第二种实施方式中，数据构建模块100通过定制设计可以增加SRAM的端口，把一个字线切割成2个字线，将读端口增加到2个；还可以通过分时操作的技术，即读操作在时钟的上升沿进行，而写操作在时钟的下降沿完成，这样也可以把一个基本的1读或者1写的SRAM扩展成1读和1写的SRAM类型，即1个读和1个写操作可以同时进行，存储密度基本不变。
如图9所示，第三种实施方式中，以SRAM2P为基础构建2R1W的SRAM为例，所述SRAM2P是一种能够支持1读和1读/写的SRAM类型，即可以对SRAM2P同时进行2个读操作，或者1个读和1个写操作。
本实施方式中，数据构建模块100通过复制一份SRAM以SRAM2P为基础构建2R1W的SRAM；该示例中，右边的SRAM2P_1是左边SRAM2P_0的拷贝，具体操作的时候，把两块SRAM2P作为1读和1写存储器来使用；其中，写入数据时，同时往左右两个SRAM2P写入数据，读出数据时，A固定从SRAM2P_0读取，数据B固定从SRAM2P_1读取，这样就可以实现1个写操作和2个读操作并发进行。
如图10a、10b所示，第四种实施方式中，数据构建模块100把逻辑上一整块的16384深度的SRAM分割成逻辑上4块4096深度的SRAM2P，编号依次为为0、1、2、3，再额外增加一块4096深度的SRAM，编号为4，作为解决读写冲突用，对于读数据A和读数据B，永远保证这2个读操作可以并发进行，当2个读操作的地址是处于不同的SRAM2P中时，因为任何一个SRAM2P都可以配置成1R1W类型，所以读写不会有冲突；当2个读操作的地址处于同一块 SRAM2P中时，例如：均处于SRAM2P_0中，由于同一个SRAM2P最多只能提供2个端口同时操作，此时，其端口被2个读操作占用，如果恰好有一个写操作要写入SRAM2P_0，那么这时就把这个数据写入存储器第4块SRAM2P_4中。
该种实施方式中，需要有一个存储器块映射表记录哪一个存储器块存放有效数据，如图10b所示，存储器块映射表的深度和一个存储器块的深度相同，即都是4096个深度，每一个条目中在初始化后依次存放每个存储器块的编号，从0到4，图10a示例中，由于SRAM2P_0在写入数据的时候发生读写冲突，数据实际上是写入到SRAM2P_4中，此时，读操作同时会读取存储器映射表中对应的内容，原始内容为{0，1，2，3，4}，修改之后变成{4，1，2，3，0}，第一个块编号和第4个块编号对调，表示数据实际写入到SRAM2P_4中，同时SRAM2P_0变成了备份条目。
当读取数据的时候，需要首先读对应地址的存储器块编号映射表，查看有效数据存放在哪一个存储器块中，例如当要读取地址5123的数据，那么首先读取存储块编号映射表地址1027(5123-4096＝1027)存放的内容，根据第二列的数字编号去读取对应存储块的地址1027的内容。
对于写数据操作，需要存储器块编号映射表提供1读和1写端口，对于2个读数据操作，需要存储器块编号映射表提供2个读端口，这样总共需要存储器块编号映射表提供3个读端口和1个写端口，而且这4个访问操作必须是同时进行。
如图11所示，第五种实施方式，即本发明的优选实施方式中，数据构建模块100根据所述2R1W存储器的深度和宽度选择2m+1块具有相同深度及宽度的SRAM2P存储器构建2R1W存储器的硬件框架，m为正整数；
多个所述SRAM2P存储器按照排列顺序依次为SRAM2P(0)、SRAM2P(1)……、SRAM2P(2m)，每个SRAM2P存储器均具有M个指针地址，其中，多个所述SRAM2P存储器中的一个为辅助存储器，其余均为主存储器；
每块SRAM2P存储器的深度与宽度的乘积＝(2R1W存储器的深度与宽度乘积)/2m。
以下为了描述方便，对m取值为2、2R1W存储器为16384深度、128宽度的SRAM存储器进行详细描述。
则在该具体示例中，多个所述SRAM2P存储器按照排列顺序依次为SRAM2P(0)、SRAM2P(1)、SRAM2P(2)、SRAM2P(3)、SRAM2P(4)，其中，SRAM2P(0)、SRAM2P(1)、SRAM2P(2)、SRAM2P(3)为主存储器，SRAM2P(4)为辅助存储器，每个SRAM2P存储器的深度和宽度分别为4096和128，相应的，每个SRAM2P存储器均具有4096个指针地址；如果对每个SRAM2P存储器的指针地址均独立标识，则每个SRAM2P存储器的指针地址均为0～4095，若将全部的主存储器的地址依次排列，则全部的指针地址范围为:0～16383。该示例中，SRAM2P(4)用于解决端口冲突，且在该实施方式中，无需增加存储器块编号映射表即可以满足需求。
进一步的，在上述硬件框架基础上，当数据写入2R1W存储器和/或从所述2R1W存储器读出时，数据处理模块200具体用于：根据数据的当前指针位置，关联主存储器以及辅助存储器中的数据，对其做异或运算，完成数据的写入和读出。
本发明优选实施方式中，其数据写入过程如下：
获取当前数据的写入地址为W(x，y)，x表示写入数据所处于的SRAM2P存储器的排列位置，0≤x＜2m，y表示写入数据所处于的SRAM2P存储器中的具体的指针地址，0≤y≤M；
获取与写入地址具有相同指针地址的其余主存储器中的数据，将其同时与当前写入数据做异或运算，并将异或运算结果写入到辅助存储器的相同指针地址中。
进一步的，本发明优选实施方式中，数据处理模块200读出数据过程如下：
若当前两个读出数据的读出地址处于相同的SRAM2P存储器中，则
数据处理模块200具体用于：分别获取两个读出数据的读出地址为R1(x1，y1)，R2(x2，y2)，x1、y1均表示读出数据所处于的SRAM2P存储器的排列位置，0≤x1＜2m，0≤x2＜2m，y1、y2均表示读出数据所处于的SRAM2P存储器中的具体的指针地址，0≤y1≤M，0≤y2≤M；
数据处理模块200具体用于：任选其中一个读出地址R1(x1，y1)中存储的读出数据，从当前的指定读出地址中直接读出当前存储的数据；
数据处理模块200具体用于：获取与另一个读出地址具有相同指针地址的其余主存储器、以及辅助存储器中存 储的数据，并对其做异或运算，将异或运算结果作为另一个读出地址的存储数据进行输出。
本发明一实施方式中，若当前两个读出数据的读出地址处于不同的SRAM2P存储器中，数据处理模块200则直接获取不同SRAM2P存储器中对应指针地址的数据分别独立进行输出。
需要说明的是，如果逻辑上把每一个SRAM2P进一步切分，比如切分成4m个具有相同深度的SRAM2P，那么只需要增加额外1/4m的存储器面积就可以构建上述2R1W类型的SRAM；相应的，物理上SRAM的块数也增加了近2倍，在实际的布局布线中会占用不少的面积开销；当然，本发明并不以上述具体实施方式为限，其它采用异或运算以扩展存储器端口的方案也包括在本发明的保护范围内，在此不做详细赘述。
进一步的，本发明一优选实施方式中，所述数据构建模块100基于上述2读n写的存储器单元构建n读n写的存储器的硬件架构。
本发明一具体实施方式中，所述数据构建模块100基于n/2个所述2读n写的多端口存储器单元直接形成n读n写存储器的硬件框架；
所述数据处理模块200还用于：当确定一个时钟周期下，数据通过n个写端口写入到n读n写的多端口存储器时，
若数据的大小小于等于所述2R1W存储器的位宽，则根据数据的目的端口将数据分别写入不同的2R1W存储器中；
若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，根据数据的目的端口将写入数据的高低位分别写入到一个Bank存储单元的2个2R1W存储器中。
所述数据处理模块200还用于：当确定一个时钟周期下，数据从n读n写的多端口存储器的其中2个读端口读出时，
若数据的大小小于等于所述2R1W存储器的位宽，则选择n读n写的多端口存储器中匹配的读端口直接读出数据；
若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，选择n读n写的多端口存储器中匹配的读端口直接读出数据。
上述n读n写的多端口存储器的数据写入及读出过程均与2读n写的多端口存储器单元的写入及读出过程相类似，其区别仅在于，写入数据过程中，需根据写入数据的转发端口匹配其写入位置，其他不在详细赘述。
结合图15A所示，本发明一具体示例中，n的取值为4，该具体示例中，X0Y0以及X1Y1的结构均与图13所示相同，数据写入及读出过程中，需根据其对应的转发端口进行存储，例如：S0、S1的数据仅能写入到X0Y0中，而S2、S3的数据仅能写入到X1Y1中，其写入过程不在具体赘述。
结合图15B所示，本发明一具体示例中，n的取值为8，该具体示例中，X0Y0、X1Y1、X2Y2以及X3Y3的结构均与图13所示结构相类似相同，其区别在于，在图13所示结构基础上再增加2个Bank以构成2R8W存储器，数据写入及读出过程中，需根据其对应的转发端口进行存储，例如：S0、S1的数据仅能写入到X0Y0中，S2、S3的数据仅能写入到X1Y1中，S4、S5的数据仅能写入到X2Y2中，而S6、S7的数据仅能写入到X3Y3中，其写入过程不在具体赘述。
结合图16所示，本实施方式中，当需要对存储器的端口进行扩展时，仅基于n/2个2读n写的多端口存储器单元即可以实现n读n写的存储器的硬件框架，相较于传统的基于2R2W存储器对存储器的端口进行扩展的方法，便于实现更多Slice的扩展。
综上所述，本发明的可扩展的多端口存储器的数据处理方法及处理系统，基于现有的SRAM类型，通过算法的方式搭建更多端口的SRAM，仅仅用最小的代价便可以最大限度的支持多端口SRAM；其实现过程中，避免采用复杂的控制逻辑和额外的多端口SRAM或者寄存器阵列资源，利用报文缓存的特殊性，通过空间分割和时间分割，仅需要简单的异或运算就可实现多个端口的报文缓存，同时，通过本发明实现的多端口存储器，其所有缓存资源可以在任意输入端口之间实现完全共享，逻辑上采用更少的CCE即可以构建多端口存储器，容易实现端口的扩展，本发明具有更低的功耗，更快的处理速度，以及节省更多的资源或面积，其报文缓存架构具有更好的扩展性，实现简单，节约人力及物质成本。
为了描述的方便，描述以上装置时以功能分为各种模块分别描述。当然，在实施本发明时可以把各模块的功能在同一个或多个软件和/或硬件中实现。
以上所描述的装置实施方式仅仅是示意性的，其中所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施方式方案的目的。本领域普通技术人员在不付出创造性劳动的情况下，即可以理解并实施。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，它们并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种可扩展的多端口存储器的数据处理方法，其特征在于，所述多端口存储器为2读n写的多端口存储器单元，n为偶数；
    所述方法包括：
    将2个2R1W存储器并行拼装为一个Bank存储单元；
    将n/2个Bank存储单元在深度上拼装为一个2读n写的多端口存储器单元的硬件框架；
    一个时钟周期下，当数据通过n个写端口写入到2读n写的多端口存储器单元时，
    若数据的大小小于等于所述2R1W存储器的位宽，则将数据分别写入不同的2R1W存储器中；
    若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，将写入数据的高低位分别写入到一个Bank存储单元的2个2R1W存储器中。
  2. 根据权利要求1所述的可扩展的多端口存储器的数据处理方法，其特征在于，所述方法还包括：
    一个时钟周期下，当数据从2读n写的多端口存储器单元的其中2个读端口读出时，
    若数据的大小小于等于所述2R1W存储器的位宽，则选择2读n写的多端口存储器单元中匹配的读端口直接读出数据；
    若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，选择2读n写的多端口存储器单元中匹配的读端口直接读出数据。
  3. 根据权利要求2所述的可扩展的多端口存储器的数据处理方法，其特征在于，所述方法还包括：
    基于n/2个所述2读n写的多端口存储器单元直接形成n读n写存储器的硬件框架；
    一个时钟周期下，当数据通过n个写端口写入到n读n写的多端口存储器时，
    若数据的大小小于等于所述2R1W存储器的位宽，则根据数据的目的端口将数据分别写入不同的2R1W存储器中；
    若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，根据数据的目的端口将写入数据的高低位分别写入到一个Bank存储单元的2个2R1W存储器中。
  4. 根据权利要求3所述的可扩展的多端口存储器的数据处理方法，其特征在于，所述方法还包括：
    一个时钟周期下，当数据从n读n写的多端口存储器的其中2个读端口读出时，
    若数据的大小小于等于所述2R1W存储器的位宽，则选择n读n写的多端口存储器中匹配的读端口直接读出数据；
    若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，选择n读n写的多端口存储器中匹配的读端口直接读出数据。
  5. 根据权利要求1至4任一项所述的可扩展的多端口存储器的数据处理方法，其特征在于，所述方法还包括：
    根据2R1W存储器的深度和宽度选择2m+1块具有相同深度及宽度的SRAM2P存储器构建2R1W存储器的硬件框架，m为正整数；
    每个SRAM2P存储器均具有M个指针地址，其中，多个所述SRAM2P存储器中的一个为辅助存储器，其余均为主存储器；
    当数据写入2R1W存储器和/或从所述2R1W存储器读出时，根据数据的当前指针位置，关联主存储器以及辅助存储器中的数据，对其做异或运算，完成数据的写入和读出。
  6. 一种可扩展的多端口存储器的数据处理系统，其特征在于，所述多端口存储器为2读n写的多端口存储器单元，n为偶数；
    所述系统包括：数据构建模块，数据处理模块；
    所述数据构建模块具体用于：将2个2R1W存储器并行拼装为一个Bank存储单元；
    将n/2个Bank存储单元在深度上拼装为一个2读n写的多端口存储器单元的硬件框架；
    所述数据处理模块具体用于：当确定一个时钟周期下，数据通过n个写端口写入到2读n写的多端口存储器单元时；
    若数据的大小小于等于所述2R1W存储器的位宽，则将数据分别写入不同的2R1W存储器中；
    若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，将写入数据的高低位分别写入到一个Bank存储单元的2个2R1W存储器中。
  7. 根据权利要求6所述的可扩展的多端口存储器的数据处理系统，其特征在于，
    所述数据处理模块还用于：
    当确定一个时钟周期下，数据从2读n写的多端口存储器单元的其中2个读端口读出时，
    若数据的大小小于等于所述2R1W存储器的位宽，则选择2读n写的多端口存储器单元中匹配的读端口直接读出数据；
    若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，选择2读n写的多端口存储器单元中匹配的读端口直接读出数据。
  8. 根据权利要求7所述的可扩展的多端口存储器的数据处理系统，其特征在于，
    所述数据构建模块还用于：基于n/2个所述2读n写的多端口存储器单元直接形成n读n写存储器的硬件框架；
    所述数据处理模块还用于：当确定一个时钟周期下，数据通过n个写端口写入到n读n写的多端口存储器时，
    若数据的大小小于等于所述2R1W存储器的位宽，则根据数据的目的端口将数据分别写入不同的2R1W存储器中；
    若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，根据数据的目的端口将写入数据的高低位分别写入到一个Bank存储单元的2个2R1W存储器中。
  9. 根据权利要求8所述的可扩展的多端口存储器的数据处理系统，其特征在于，
    所述数据处理模块还用于：
    当确定一个时钟周期下，数据从n读n写的多端口存储器的其中2个读端口读出时，
    若数据的大小小于等于所述2R1W存储器的位宽，则选择n读n写的多端口存储器中匹配的读端口直接读出数据；
    若数据的大小大于所述2R1W存储器的位宽，则等待第二个时钟周期，当第二个时钟周期到来时，选择n读n写的多端口存储器中匹配的读端口直接读出数据。
  10. 根据权利要求6至9任一项所述的可扩展的多端口存储器的数据处理系统，其特征在于，
    所述数据构建模块还用于：根据2R1W存储器的深度和宽度选择2m+1块具有相同深度及宽度的SRAM2P存储器构建2R1W存储器的硬件框架，m为正整数；
    每个SRAM2P存储器均具有M个指针地址，其中，多个所述SRAM2P存储器中的一个为辅助存储器，其余均为主存储器；
    当数据写入2R1W存储器和/或从所述2R1W存储器读出时，所述数据处理模块还用于：根据数据的当前指针位置，关联主存储器以及辅助存储器中的数据，对其做异或运算，完成数据的写入和读出。
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CN113227984B (zh) * 2018-12-22 2023-12-15 华为技术有限公司 一种处理芯片、方法及相关设备

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