WO2018016162A1

WO2018016162A1 - Semiconductor device

Info

Publication number: WO2018016162A1
Application number: PCT/JP2017/018437
Authority: WO
Inventors: 湯河　潤一
Original assignee: パナソニックＩｐマネジメント株式会社
Priority date: 2016-07-19
Filing date: 2017-05-17
Publication date: 2018-01-25
Also published as: JP2018014356A; CN109478540A

Abstract

This semiconductor device which accurately detects the temperature of a semiconductor element is provided with first and second substrates. The first and second substrates are facing each other by having a predetermined gap therebetween. A plurality of semiconductor elements are mounted on a first substrate surface facing the second substrate. A plurality of temperature detection elements are mounted on a second substrate surface facing the first substrate, and are thermally in contact with the semiconductor elements.

Description

Semiconductor device

This disclosure relates to a semiconductor device.

Conventionally, a semiconductor device including a semiconductor element is known. For example, Patent Document 1 discloses a semiconductor device including a semiconductor element mounted on a substrate and a temperature detection element that is disposed between the substrate and the semiconductor element and detects the temperature of the semiconductor element. . Specifically, in the semiconductor device of Patent Document 1, an inverter circuit (semiconductor element) is configured by a substantially rectangular inverter circuit portion (main body portion) and a plurality of terminals, and the plurality of terminals of the inverter circuit are formed by soldering the substrate. It is electrically connected to the wiring pattern. And the temperature detection element is mounted in the board | substrate (board | substrate with which the inverter circuit was mounted) so that it may be located between an inverter circuit part and a board | substrate.

JP 2006-135167 A

This disclosure is intended to provide a semiconductor device capable of accurately detecting the temperature of a semiconductor element in a temperature detection element.

A semiconductor device according to the present disclosure includes a first substrate, a second substrate facing the first substrate at a predetermined interval, and at least one semiconductor element mounted on a surface of the first substrate facing the second substrate. And at least one temperature detecting element mounted on a surface of the second substrate facing the first substrate and in thermal contact with at least one semiconductor element.

According to this disclosure, the temperature of the semiconductor element can be accurately detected by the temperature detection element.

FIG. 3 is a schematic cross-sectional view showing a configuration example of the semiconductor device according to the embodiment. FIG. 10 is a circuit diagram for describing a specific example of a semiconductor device. FIG. 6 is a schematic plan view for explaining a specific example of the semiconductor device. FIG. 9 is a schematic cross-sectional view showing Modification 1 of the semiconductor device according to the embodiment. FIG. 9 is a schematic cross-sectional view showing Modification Example 2 of the semiconductor device according to the embodiment.

Prior to the description of the embodiment of the present disclosure, problems in the conventional semiconductor device will be briefly described. In the semiconductor device of Patent Document 1, the heat of the main body of the semiconductor element is transmitted to the substrate on which the temperature detection element is mounted via the terminal of the semiconductor element. That is, in the semiconductor device of Patent Document 1, not only the original heat transfer path from the main body of the semiconductor element to the temperature detection element (specifically, the heat transfer path not passing through the terminal of the semiconductor element), Another heat transfer path from the main body portion to the temperature detection element via the terminal of the semiconductor element is also formed. For this reason, thermal crosstalk in the temperature detection element (here, defined as a phenomenon in which heat transferred via another heat transfer path is mixed with heat transferred via another heat transfer path). Therefore, it is difficult for the temperature detecting element to accurately detect the temperature of the semiconductor element.

Hereinafter, embodiments will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Semiconductor device)
FIG. 1 shows a configuration example of a semiconductor device 10 according to the embodiment. The semiconductor device 10 includes a housing 11, a control board 15, a first board 20, and a second board 30. The first substrate 20 is provided with a plurality of semiconductor elements 40, the second substrate 30 is provided with a plurality of temperature detection elements 50, and between the plurality of semiconductor elements 40 and the plurality of temperature detection elements 50. A plurality of heat conductors 60 are provided. In this example, the semiconductor device 10 constitutes a switching power supply device as shown in FIG. A specific example (switching power supply device) of the semiconductor device 10 will be described in detail later.

<Case>
The housing 11 houses the control board 15, the first board 20, and the second board 30. In this example, the casing 11 is made of a metal material (for example, aluminum) and is formed in a hollow rectangular parallelepiped shape, and a support column 12 is provided therein. The support column 12 is erected on the bottom of the housing 11 and supports the control board 15.

<Control board>
The control board 15 is formed in a flat plate shape. A control circuit 16 is mounted on one surface of the control board 15 (the upper surface in FIG. 1). Specifically, the control board 15 is made of an insulating material (for example, epoxy resin) and formed in a flat plate shape, and a control board 15 is made of a conductive material (for example, copper) and is one of the insulating base materials. A wiring pattern (conductive layer, not shown) provided in the direction is provided, and the control circuit 16 is electrically connected to the wiring pattern.

In this example, the control board 15 is supported by the support column 12 and faces the bottom of the housing 11 with a predetermined interval. A connector 17 is mounted on the other surface (the lower surface in FIG. 1) of the control board 15. Specifically, a wiring pattern (conductive layer, not shown) is also provided on the other surface of the insulating base of the control board 15, and the connector 17 is electrically connected to the wiring pattern. The wiring pattern provided on the other surface of the control board 15 is electrically connected to the wiring pattern provided on the one surface of the control board 15 via vias (not shown) provided on the insulating base material. ing. That is, the connector 17 is electrically connected to the control circuit 16 via the wiring pattern on the other side of the control board 15 and the wiring pattern on the one side.

<First substrate>
The first substrate 20 is formed in a flat plate shape. In this example, the first substrate 20 is a power substrate on which a power element such as a field effect transistor (FET) is mounted, and the rigidity of the first substrate 20 is higher than the rigidity of the control substrate 15. Specifically, the first substrate 20 includes an insulating layer 21, a conductive layer 22, and a heat dissipation layer 23.

The insulating layer 21 is made of an insulating material (for example, epoxy resin) and is formed in a flat plate shape.

The conductive layer 22 is made of a conductive material (for example, copper or the like), is provided on one surface (the upper surface in FIG. 1) of the insulating layer 21, and is formed in a foil shape. A wiring pattern is formed on the conductive layer 22. In the example of FIG. 1, the wiring pattern includes one or more power supply wirings WP, one or more grounding wirings WG (not shown), and one or more output wirings WO. In the conductive layer 22, the power supply wiring WP, the ground wiring WG, and the output wiring WO are separated so as not to short-circuit each other. The power supply wiring WP, the ground wiring WG, and the output wiring WO will be described in detail later.

The heat dissipation layer 23 is made of a heat conductive material (for example, aluminum) and is provided on the other surface (the lower surface in FIG. 1) of the insulating layer 21. A cooling member (not shown) configured to be cooled by water cooling (cooling with cooling water) or oil cooling (cooling with cooling oil) may be connected to the heat radiation layer 23.

In this example, the thickness of the insulating layer 21 is thinner than the thickness of each of the conductive layer 22 and the heat dissipation layer 23. The thickness of the heat dissipation layer 23 is greater than the thickness of the conductive layer 22. For example, the thickness of the insulating layer 21 may be set to about 100 μm, the thickness of the conductive layer 22 may be set to about 200 μm, and the thickness of the heat dissipation layer 23 may be set to about 1 to 3 mm. The thermal conductivity of the insulating layer 21 is lower than that of each of the conductive layer 22 and the heat dissipation layer 23. The thermal conductivity of the conductive layer 22 is higher than the thermal conductivity of the heat dissipation layer 23.

In this example, the first substrate 20 is placed on the bottom of the housing 11, and the heat dissipation layer 23 is in contact with the bottom of the housing 11. The first substrate 20 faces the control substrate 15 supported by the support column 12 with a predetermined interval.

<Second substrate>
The second substrate 30 is an independent substrate different from the first substrate 20 and is formed in a flat plate shape. The second substrate 30 is provided to face the first substrate 20 with a predetermined interval. In this example, the rigidity of the second substrate 30 is lower than the rigidity of the first substrate 20. Specifically, the second substrate 30 is composed of a flexible substrate 31 having flexibility.

The flexible substrate 31 is a substrate different from the control substrate 15 and is formed in a flat plate shape. And the flexible substrate 31 is arrange | positioned between the 1st board | substrate 20 and the control board 15 so that the 1st board | substrate 20 may be opposed with a predetermined space | interval, The part (one end in this example) is a control board. It is connected and fixed to the other surface of 15 (the lower surface in FIG. 1). The rigidity of the flexible substrate 31 is lower than the rigidity of the control substrate 15. Specifically, the flexible substrate 31 is made of an insulating material (for example, polyimide resin) and formed into a flat plate shape (a flexible insulating base material), and a conductive material (for example, copper). And a wiring pattern (conductive layer, not shown) provided on one surface (the lower surface in FIG. 1) of the flexible substrate. One end of the flexible board 31 is fitted into the connector 17 and fixed, and the wiring pattern of the flexible board 31 is electrically connected to the wiring pattern provided on the other surface of the control board 15 via the connector 17.

<Semiconductor element>
The plurality of semiconductor elements 40 are mounted on the surface of the first substrate 20 facing the second substrate 30 (upper surface in FIG. 1). Specifically, the semiconductor element 40 is electrically connected to a wiring pattern (conductive layer 22) provided on one surface (the upper surface in FIG. 1) of the first substrate 20.

In this example, the semiconductor element 40 is composed of a surface mount type field effect transistor (FET). The semiconductor element 40 may be constituted by other parts (for example, a diode) that are not surface mount type field effect transistors (FETs).

<Temperature detection element>
The plurality of temperature detection elements 50 are mounted on the surface (the lower surface in FIG. 1) of the second substrate 30 that faces the first substrate 20. Specifically, the plurality of temperature detecting elements 50 are electrically connected to a wiring pattern (not shown) provided on one surface (the lower surface in FIG. 1) of the second substrate 30 (in this example, the flexible substrate 31). ing. The wiring pattern on one side of the flexible substrate 31 is electrically connected to a wiring pattern (not shown) provided on the other surface (the lower surface in FIG. 1) of the control board 15 via the connector 17. Then, the wiring pattern on the other surface side (the lower surface side in FIG. 1) of the control board 15 is electrically connected to the wiring pattern (not shown) on the one surface side (the upper surface side in FIG. 1) of the control board 15, and is controlled. A control circuit 16 is electrically connected to the wiring pattern on one side of the substrate 15. Accordingly, the plurality of temperature detection elements 50 are electrically connected to the control circuit 16 via the wiring pattern of the flexible substrate 31, the connector 17, the wiring pattern on the other surface side of the control substrate 15, and the wiring pattern on the one surface side of the control substrate 15. Connected.

Further, the plurality of temperature detection elements 50 are in thermal contact with the plurality of semiconductor elements 40. In this example, the number of temperature detection elements 50 is the same as the number of semiconductor elements 40, and the plurality of temperature detection elements 50 are in thermal contact with the plurality of semiconductor elements 40 on a one-to-one basis. The temperature detecting element 50 is opposed to the semiconductor element 40 so that part or all of the temperature detecting element 50 overlaps part or all of the semiconductor element 40 (the semiconductor element 40 corresponding to the temperature detecting element 50) in plan view. Yes.

Further, the temperature detecting element 50 is configured to detect the temperature of the semiconductor element 40 that is in thermal contact. Specifically, the temperature detection element 50 is configured to output an electrical signal corresponding to the temperature of the installation location. The electrical signal output from the temperature detection element 50 (the electrical signal corresponding to the temperature detected by the temperature detection element 50) is controlled by the wiring pattern on the flexible substrate 31, the wiring pattern on the other surface side of the connector 17 and the control substrate 15, and the control. The signal is transmitted to the control circuit 16 via the wiring pattern on one side of the substrate 15. In this example, the temperature detection element 50 is configured by a thermistor. Note that the temperature detection element 50 may be composed of other parts (for example, a thermocouple) different from the thermistor.

<Heat conductor>
The heat conductor 60 is interposed between the plurality of semiconductor elements 40 and the plurality of temperature detection elements 50. In this example, the number of thermal conductors 60 is the same as the number of temperature detection elements 50. That is, in this example, the number of the semiconductor elements 40, the number of the temperature detecting elements 50, and the number of the heat conductors 60 are the same. The plurality of thermal conductors 60 are interposed between the plurality of semiconductor elements 40 and the plurality of temperature detection elements 50, respectively. In this example, the heat conductor 60 is composed of heat conductive grease or a heat conductive adhesive. In addition, the heat conductor 60 may be comprised by other members (for example, heat conductive rubber etc.) different from heat conductive grease or a heat conductive adhesive.

<Specific examples of semiconductor devices: switching power supply devices>
As described above, in this example, the semiconductor device 10 constitutes a switching power supply device as shown in FIG. The switching power supply device (semiconductor device 10) converts the power supplied from the power supply (DC power supply P in this example) into output power by a switching operation, and supplies the output power to the drive target (motor M in this example). It is configured. In the example of FIG. 2, the switching power supply device (semiconductor device 10) constitutes an inverter that converts DC power into three-phase AC power.

As shown in FIG. 2, the switching power supply device (semiconductor device 10) includes a power supply line LP, a ground line LG, one or more output lines LO, one or more switching units SW, and a capacitor unit CP. And. In this example, the power supply line LP is connected to one end (positive electrode) of the DC power supply P, and the ground line LG is connected to the other end (negative electrode) of the DC power supply P. Further, the switching power supply device (semiconductor device 10) is provided with three output lines LO and three switching units SW, and the three switching units SW pass through the three output lines LO and the three phases (U, V, W).

The switching unit SW is connected between the power supply line LP and the ground line LG. The intermediate node of the switching unit SW is connected to the motor M via the output line LO. The switching unit SW includes a first switching element 71 and a second switching element 72. Note that the free-wheeling diode connected in parallel to the first switching element 71 (or the second switching element 72) in the drawing corresponds to a parasitic diode parasitic on the first switching element 71 (or the second switching element 72). The first switching element 71 is composed of one or more (three in this example) semiconductor elements 40, and the second switching element 72 is composed of one or more (three in this example) semiconductor elements 40. Has been. The configuration of the first and

second switching elements

71 and 72 will be described in detail later.

The capacitor part CP is connected between the power supply line LP and the ground line LG. The capacitor part CP has a capacitor 80. The capacitor portion CP is provided with a connection line LC that connects the capacitor 80 and the power supply line LP.

<Structure of switching power supply>
Next, the structure of the switching power supply device (semiconductor device 10) will be described with reference to FIG. FIG. 3 is a schematic plan view of the first substrate 20 viewed from the second substrate 30 side.

In the example of FIG. 3, the conductive layer 22 has three power supply wirings WP, three grounding wirings WG, and three output wirings WO, and one power supply wiring WP, one grounding wiring WG, and one output wiring WO are one. One wiring set is configured, and the three wiring sets are arranged in the first direction (left-right direction in FIG. 3). As shown in FIG. 2, the switching power supply device (semiconductor device 10) includes three first switching elements 71 and three second switching elements 72, and one first switching element 71 and one second switching element. 72 constitutes one switching unit SW. As shown in FIG. 3, the three switching units SW correspond to the three wiring sets, respectively. In the example of FIG. 3, three semiconductor elements 40 are connected in parallel to form one first switching element 71, and three semiconductor elements 40 are connected in parallel to form one second switching element 72. is doing. Therefore, there are 18 semiconductor elements 40 in the example of FIG. Hereinafter, each part of the switching power supply device (semiconductor device 10) will be described focusing on one wiring set and one switching unit SW.

<Power supply wiring, ground wiring, and output wiring>
The power supply wiring WP constitutes a part of the power supply line LP shown in FIG. 2, the ground wiring WG constitutes a part of the ground line LG shown in FIG. 2, and the output wiring WO is shown in FIG. It constitutes a part of the output line LO.

Further, the power supply wiring WP, the ground wiring WG, and the output wiring WO are formed in parallel to each other. The output wiring WO is disposed between the power supply wiring WP and the ground wiring WG. In the example of FIG. 3, each of the power supply wiring WP, the ground wiring WG, and the output wiring WO is formed in a plate shape extending in a second direction (vertical direction in FIG. 3) orthogonal to the first direction.

<First switching element>
As described above, in the example of FIG. 3, the first switching element 71 is configured by the three semiconductor elements 40. The three semiconductor elements 40 constituting the first switching element 71 are arranged along the extending direction of the power supply wiring WP, and each is surface-mounted on the power supply wiring WP and connected to the output wiring WO. Specifically, the semiconductor element 40 constituting the first switching element 71 is placed on the power supply wiring WP, one end (drain / heat radiation surface) thereof is joined to the surface of the power supply wiring WP by soldering, and the other end (source) ) Is connected to the output wiring WO by a wiring member such as a bonding wire, and its gate is connected to the first gate wiring (not shown) by the wiring member.

<Second switching element>
As described above, in the example of FIG. 3, the second switching element 72 is configured by the three semiconductor elements 40. The three semiconductor elements 40 constituting the second switching element 72 are arranged along the extending direction of the output wiring WO, and each is surface-mounted on the output wiring WO and connected to the ground wiring WG. Specifically, the semiconductor element 40 constituting the second switching element 72 is placed on the output wiring WO, one end (drain / heat radiation surface) thereof is joined to the surface of the output wiring WO by soldering, and the other end (source) ) Is connected to the ground wiring WG by a wiring material such as a bonding wire, and its gate is connected to a second gate wiring (not shown) by a wiring member.

<Capacitor and connection wiring>
Further, the switching power supply device (semiconductor device 10) includes a capacitor 80 and a connection wiring 85. Capacitor 80 is mounted on ground wiring WG and electrically connected to power supply wiring WP. The connection wiring 85 constitutes the connection line LC shown in FIG. 2 and electrically connects the capacitor 80 and the power supply wiring WP. Specifically, the capacitor 80 is placed on the ground wiring WG, one end (negative electrode) thereof is joined to the ground wiring WG by solder, and the other end (positive electrode) is electrically connected to the power supply wiring WP by the connection wiring 85. Has been.

In the example of FIG. 3, the capacitor 80 is configured by nine divided capacitors 81. Further, the connection wiring 85 is configured by nine divided wirings 86. Three divided capacitors 81 and three divided wires 86 are arranged in each of the three ground wires WG.

The three divided capacitors 81 arranged in one ground wiring WG are arranged along the extending direction of the ground wiring WG, are surface-mounted on the ground wiring WG, and are connected to the power supply wiring WP (specifically, the ground wiring WG). The power supply wiring WP belonging to the same wiring set as the wiring WG) is electrically connected. In the example of FIG. 3, the divided capacitor 81 is disposed inside the outer edge of the ground wiring WG in a plan view. That is, in this example, the divided capacitor 81 does not protrude from the ground wiring WG in plan view. The split capacitor 81 may be constituted by, for example, a surface mount type electrolytic capacitor, or may be constituted by a surface mount type film capacitor.

Three divided wirings 86 arranged in one ground wiring WG include three divided capacitors 81 arranged in the ground wiring WG and a power supply wiring WP (specifically, power supply wirings belonging to the same wiring set as the ground wiring WG). WP) are electrically connected to each other. In the example of FIG. 3, the divided wiring 86 is formed in an elongated plate shape extending along the first direction (the left-right direction in FIG. 3). Note that the divided wiring 86 may be configured by, for example, a bus bar, may be configured by a jumper, or may be configured by another wiring member.

In the example of FIG. 3, one of the three semiconductor elements 40 constituting the first switching element 71, one of the three semiconductor elements 40 constituting the second switching element 72, and the split capacitor 81 are in the first direction (FIG. 3). 3 are arranged in a straight line.

<Arrangement of each part in plan view>
In the example of FIG. 3, the 18 semiconductor elements 40 are arranged in a matrix of 3 rows and 6 columns in plan view. Similarly, 18

temperature detection elements

50 and 18 heat conductors 60 (not shown) are arranged in a matrix of 3 rows and 6 columns in plan view and face 18 semiconductor elements 40, respectively. ing. In the example of FIG. 3, the temperature detection element 50 and the heat conductor 60 (not shown) are arranged so as to be positioned at the center of the semiconductor element 40 in plan view.

<Effects of the embodiment>
As described above, by mounting the temperature detection element 50 on the second substrate 30 different from the first substrate 20 on which the semiconductor element 40 is mounted, the heat of the semiconductor element 40 is transferred to the original heat transfer path (in this example, It is prevented (or suppressed) from being transmitted to the temperature detection element 50 via a different heat transfer path from the semiconductor element 40 via the heat conductor 60 to the temperature detection element 50). be able to. Thereby, thermal crosstalk can be suppressed in the temperature detection element 50, and the temperature of the semiconductor element 40 can be accurately detected in the temperature detection element 50.

Further, since the rigidity of the second substrate 30 (in this example, the flexible substrate 31) is lower than the rigidity of the first substrate 20, the flexibility of the second substrate 30 can be improved compared to the first substrate 20. Therefore, the opposing distance between the semiconductor element 40 mounted on the first substrate 20 and the temperature detection element 50 mounted on the second substrate 30 can be adjusted by deforming the second substrate 30. As a result, the facing distance between the semiconductor element 40 and the temperature detection element 50 can be shortened and heat transfer from the semiconductor element 40 to the temperature detection element 50 can be promoted. The temperature can be detected more accurately. In addition, variation in the facing distance between the temperature detecting element 50 and the semiconductor element 40 (the facing distance between the semiconductor element 40 varies among the plurality of temperature detecting elements 50) can be suppressed. For example, even if the mounting height varies among the plurality of semiconductor elements 40, the second substrate 30 can be flexibly deformed, so that the variation in the facing distance between the temperature detecting element 50 and the semiconductor element 40 is varied. Can be suppressed. As a result, variations in the detection value of the temperature detection element 50 due to variations in the facing distance between the temperature detection element 50 and the semiconductor element 40 (the detection values corresponding to the temperature vary among the plurality of temperature detection elements 50). ) Can be suppressed.

Further, by mounting a plurality of temperature detection elements 50 on a substrate (in this example, flexible substrate 31) different from the control substrate 15, the first substrate 20 on which the plurality of semiconductor elements 40 are mounted and the plurality of temperature detection elements 50 are mounted. It is possible to arbitrarily adjust the facing distance from the substrate (second substrate 30) on which is mounted. Thereby, since the facing distance between the temperature detection element 50 and the semiconductor element 40 can be easily adjusted, the shortening of the facing distance between the semiconductor element 40 and the temperature detection element 50 or the temperature detection element 50 and the semiconductor can be performed. It is possible to easily suppress variations in the facing distance from the element 40.

Further, the plurality of semiconductor elements 40 and the plurality of temperature detection elements 50 are brought into thermal contact with each other in a one-to-one manner, so that the plurality of semiconductor elements 40 and the plurality of temperature detection elements 50 are brought into thermal contact with each other in one to one. The temperature of the plurality of semiconductor elements 40 can be individually detected more accurately than when there is no (for example, when one temperature detection element 50 is in thermal contact with the plurality of semiconductor elements 40).

Further, by interposing the thermal conductor 60 between the semiconductor element 40 and the temperature detecting element 50, the semiconductor is more effective than the case where the thermal conductor 60 is not interposed between the semiconductor element 40 and the temperature detecting element 50. Heat transfer from the element 40 to the temperature detection element 50 can be promoted. Thereby, the temperature of the semiconductor element 40 can be detected more accurately in the temperature detection element 50. In addition, variation in heat transfer from the semiconductor element 40 to the temperature detection element 50 (easiness of heat transfer to the temperature detection element 50 varies among a plurality of semiconductor elements) can be suppressed. Variation in the detection value of the temperature detection element 50 due to variation in heat transfer from 40 to the temperature detection element 50 can be suppressed.

Further, by configuring the heat conductor 60 with heat conductive grease or a heat conductive adhesive, the facing distance between the semiconductor element 40 and the temperature detecting element 50 is greater than when the heat conductor 60 is formed with heat conductive rubber. Can be shortened. Thereby, since heat transfer from the semiconductor element 40 to the temperature detection element 50 can be promoted, the temperature of the semiconductor element 40 can be detected more accurately in the temperature detection element 50.

Further, by configuring the temperature detection element 50 with a thermistor, the sensitivity of the temperature detection element 50 can be improved as compared with the case where the temperature detection element 50 is configured with a thermocouple.

Further, by detecting the temperature of the semiconductor element 40 accurately by the temperature detection element 50, the temperature abnormality of the semiconductor element 40 can be detected accurately. Thereby, the abnormality of the semiconductor device 10 can be accurately detected based on the temperature abnormality of the semiconductor element 40. For example, one (or two) semiconductor elements 40 out of three semiconductor elements 40 (three semiconductor elements 40 connected in parallel) constituting one first switching element 71 (or second switching element 72). Becomes impossible to drive (conducting failure), the remaining two (or one) semiconductor elements 40 will bear the load of the semiconductor element 40 that has become impossible to drive. Therefore, the current flowing through the remaining two (or one) semiconductor elements 40 increases, and as a result, the temperature of the remaining two (or one) semiconductor elements 40 tends to increase. Therefore, by accurately detecting and comparing the temperatures of the three semiconductor elements 40 constituting one first switching element 71 (or second switching element 72), the three semiconductor elements 40 cannot be driven ( It can be determined whether or not there is a semiconductor element 40 that is in a conduction failure state.

(Modification 1 of embodiment)
As shown in FIG. 4, in the semiconductor device 10, the second substrate 30 may be configured by a sensor substrate 32. The sensor substrate 32 is a substrate different from the control substrate 15 and is formed in a flat plate shape. The sensor substrate 32 is provided between the first substrate 20 and the control substrate 15 so as to face the first substrate 20 with a predetermined interval. Note that the rigidity of the sensor substrate 32 is lower than that of the first substrate 20 and is equal to the rigidity of the control substrate 15. Specifically, the sensor substrate 32 is made of an insulating material (for example, epoxy resin) and formed in a flat plate shape, and is formed of a conductive material (for example, copper) and is one side of the insulating substrate. And a wiring pattern (conductive layer, not shown) provided on (the lower surface in FIG. 4). Thus, the sensor substrate 32 has the same configuration as the control substrate 15. A wiring pattern provided on one surface of the sensor substrate 32 is electrically connected to a wiring pattern (not shown) on one surface side (the upper surface side in FIG. 4) of the control substrate 15 via one or a plurality of lead wires 18. Connected.

In the example of FIG. 4, the plurality of temperature detection elements 50 are mounted on one surface of the sensor substrate 32 (the surface facing the first substrate 20). Specifically, the plurality of temperature detection elements 50 are electrically connected to a wiring pattern provided on one surface of the sensor substrate 32. The plurality of temperature detection elements 50 are electrically connected to the control circuit 16 via the wiring pattern on one side of the sensor substrate 32, the lead wire 18, and the wiring pattern on the one surface side of the control board 15. .

Even when configured as described above, since the temperature detection element 50 is mounted on the sensor substrate 32 different from the first substrate 20 on which the semiconductor element 40 is mounted, thermal crosstalk is suppressed in the temperature detection element 50. The temperature of the semiconductor element 40 can be accurately detected by the temperature detecting element 50.

Further, since the rigidity of the sensor substrate 32 is lower than the rigidity of the first substrate 20, the flexibility of the sensor substrate 32 can be improved compared to the first substrate 20. Therefore, the opposing distance between the semiconductor element 40 mounted on the first substrate 20 and the temperature detection element 50 mounted on the sensor substrate 32 can be adjusted by bending the sensor substrate 32. As a result, the facing distance between the semiconductor element 40 and the temperature detection element 50 can be shortened and heat transfer from the semiconductor element 40 to the temperature detection element 50 can be promoted. The temperature can be detected more accurately. In addition, variation in the detection value of the temperature detection element 50 due to variation in the facing distance between the temperature detection element 50 and the semiconductor element 40 can be suppressed.

Further, by mounting a plurality of temperature detection elements 50 on a substrate different from the control substrate 15 (in this example, the sensor substrate 32), the first substrate 20 on which the plurality of semiconductor elements 40 are mounted and the plurality of temperature detection elements 50 are mounted. It is possible to arbitrarily adjust the facing distance from the substrate (second substrate 30) on which is mounted. Thereby, since the facing distance between the temperature detection element 50 and the semiconductor element 40 can be easily adjusted, the shortening of the facing distance between the semiconductor element 40 and the temperature detection element 50 or the temperature detection element 50 and the semiconductor can be performed. It is possible to easily suppress variations in the facing distance from the element 40.

In addition, when the 2nd board | substrate 30 is comprised with the sensor board | substrate 32, it is preferable to comprise the heat conductor 60 with heat conductive grease or a heat conductive adhesive. With this configuration, even when the mounting height varies among the plurality of semiconductor elements 40 and the opposing distance between the semiconductor element 40 and the temperature detecting element 50 varies, the heat conduction grease or the heat conduction adhesion is achieved. The thermal contact between the semiconductor element 40 and the temperature detection element 50 can be ensured by the adhesiveness of the agent. Thereby, variation in heat transfer from the semiconductor element 40 to the temperature detection element 50 can be suppressed. As a result, detection of the temperature detection element 50 due to variation in heat transfer from the semiconductor element 40 to the temperature detection element 50 can be performed. Variation in values can be suppressed.

(Modification 2 of embodiment)
As shown in FIG. 5, in the semiconductor device 10, the second substrate 30 may be configured by a control substrate 15. The control board 15 is provided to face the first board 20 with a predetermined interval. The rigidity of the control board 15 is lower than that of the first board 20.

In the example of FIG. 5, the plurality of temperature detection elements 50 are mounted on the other surface of the control substrate 15 (the surface facing the first substrate 20). Specifically, the plurality of temperature detection elements 50 are electrically connected to a wiring pattern (not shown) on the other surface side (the lower surface side in FIG. 5) of the control board 15. The plurality of temperature detection elements 50 are connected to the control circuit 16 via a wiring pattern on the other side of the control board 15 and a wiring pattern (not shown) on one side (the upper surface side in FIG. 5) of the control board 15. Electrically connected.

Even when configured as described above, since the temperature detection element 50 is mounted on the control substrate 15 different from the first substrate 20 on which the semiconductor element 40 is mounted, thermal crosstalk is suppressed in the temperature detection element 50. The temperature of the semiconductor element 40 can be accurately detected by the temperature detecting element 50.

Further, since the rigidity of the control board 15 is lower than the rigidity of the first board 20, the flexibility of the control board 15 can be improved as compared with the first board 20. Therefore, the facing distance between the semiconductor element 40 mounted on the first substrate 20 and the temperature detection element 50 mounted on the control board 15 can be adjusted by bending the control board 15. As a result, the facing distance between the semiconductor element 40 and the temperature detection element 50 can be shortened and heat transfer from the semiconductor element 40 to the temperature detection element 50 can be promoted. The temperature can be detected more accurately. In addition, variation in the detection value of the temperature detection element 50 due to variation in the facing distance between the temperature detection element 50 and the semiconductor element 40 can be suppressed.

In addition, by mounting the plurality of temperature detection elements 50 on the other surface of the control board 15 (the surface facing the first substrate 20), the plurality of temperature detection elements 50 are mounted on another board different from the control board 15. The electrical connection between the plurality of temperature detection elements 50 and the control circuit 16 can be made easier than in the case.

In addition, when the 2nd board | substrate 30 is comprised by the control board | substrate 15, it is preferable to comprise the heat conductor 60 with heat conductive grease or a heat conductive adhesive. With this configuration, even when the mounting height varies among the plurality of semiconductor elements 40 and the opposing distance between the semiconductor element 40 and the temperature detecting element 50 varies, the heat conduction grease or the heat conduction adhesion is achieved. The thermal contact between the semiconductor element 40 and the temperature detection element 50 can be ensured by the adhesiveness of the agent. Thereby, variation in heat transfer from the semiconductor element 40 to the temperature detection element 50 can be suppressed. As a result, detection of the temperature detection element 50 due to variation in heat transfer from the semiconductor element 40 to the temperature detection element 50 can be performed. Variation in values can be suppressed.

(Other embodiments)
In the above description, the case where the number of the temperature detection elements 50 is the same as the number of the semiconductor elements 40 is taken as an example, but the number of the temperature detection elements 50 is different from the number of the semiconductor elements 40. Also good. Similarly, the number of thermal conductors 60 may be the same as or different from the number of temperature detection elements 50 and the number of semiconductor elements 40. For example, three semiconductor elements 40 and three temperature detecting elements 50 constituting one first switching element 71 (or second switching element 72) have a one-to-one correspondence, and the three semiconductor elements 40 and the three switching elements One thermal conductor 60 formed in a flat plate shape may be interposed between the temperature detection element. Alternatively, three semiconductor elements 40 constituting one first switching element 71 (or second switching element 72) correspond to one temperature detection element, and the three semiconductor elements 40 and one temperature detection element Between them, one heat conductor 60 formed in a flat plate shape may be interposed.

In the above description, the case where the plurality of thermal conductors 60 are interposed between the plurality of semiconductor elements 40 and the plurality of temperature detection elements 50 is described as an example. One thermal conductor 60 formed in a flat plate shape may be interposed between the temperature detecting elements 50.

In the above description, the case where one or a plurality of thermal conductors 60 are interposed between the plurality of semiconductor elements 40 and the plurality of temperature detection elements 50 is described as an example. The plurality of semiconductor elements 40 and the plurality of temperature detection elements 50 may be in direct contact with each other without interposing the heat conductor 60 between the plurality of temperature detection elements 50.

In the above description, the number of semiconductor elements 40 constituting the first switching element 71 is not limited to three, but may be two or less, or may be four or more. Similarly, the same applies to the number of semiconductor elements 40 constituting the second switching element 72, the number of divided capacitors 81 constituting the capacitor 80, and the number of divided wirings 86 constituting the connection wiring 85. Further, the number of semiconductor elements 40 constituting the first switching element 71 may be the same as or different from the number of semiconductor elements 40 constituting the second switching element 72. Further, the number of the divided wirings 86 constituting the connection wiring 85 may be the same as the number of the divided capacitors 81 constituting the capacitor 80 or may be increased.

In the above description, the case where the capacitor 80 is configured by a plurality of divided capacitors 81 has been described as an example, but the capacitor 80 may be configured by one divided capacitor 81. For example, the capacitor 80 may be composed of one surface-mount electrolytic capacitor (or one surface-mount film capacitor or the like).

In the above description, the case where the connection wiring 85 is configured by a plurality of connection wirings 85 is described as an example, but the connection wiring 85 may be configured by one divided wiring 86. For example, the connection wiring 85 may be configured by one bus bar (or one jumper, one wiring member, or the like).

In the above description, the case where the capacitor 80 is electrically connected to the power supply wiring WP by the connection wiring 85 is described as an example. However, the capacitor 80 is electrically connected to the output wiring WO by the connection wiring 85. It may be. Specific examples will be described later in detail.

Further, the switching power supply device (semiconductor device 10) may constitute an inverter that converts DC power (or AC power) into AC power by switching operation, and DC power (or AC power) is switched by switching operation. You may comprise the converter which converts into direct-current power. For example, the switching power supply device (semiconductor device 10) may constitute a DC / DC converter (a converter that converts input DC power into output DC power having a voltage value different from the input DC power by a switching operation). The DC / DC converter includes a step-down converter, a step-up converter, and a bidirectional DC / DC converter.

When the switching power supply device (semiconductor device 10) constitutes a step-down converter, the capacitor 80 has one end connected to the ground wiring WG and the other end electrically connected to the output wiring WO via an inductor. .

When the switching power supply device (semiconductor device 10) forms a boost converter, the capacitor 80 has one end connected to the ground wiring WG and the other end connected to the power supply wiring WP. In the boost converter, the output wiring WO is on the power supply side and the power supply wiring WP is on the output side in consideration of the direction of current flow. Here, the wiring WO is referred to as “output wiring WO even if the wiring WO is on the power supply side. The wiring WP is defined as “power supply wiring WP” even if the wiring WP is on the output side.

When the switching power supply (semiconductor device 10) constitutes a bidirectional DC / DC converter, the switching power supply (semiconductor device 10) is provided with two capacitors 80. One capacitor 80 has one end connected to the ground wiring WG and the other end connected to the output wiring WO. The other capacitor 80 has one end connected to the ground wiring WG and the other end connected to the power supply wiring WP.

As described above, in the switching power supply device (semiconductor device 10), the capacitor 80 is surface-mounted on the ground wiring WG and electrically connected to the power supply wiring WP or the output wiring WO. Further, when the capacitor 80 is constituted by a plurality of divided capacitors 81, a connection wiring 85 for electrically connecting the capacitor 80 and the power supply wiring WP or the output wiring WO is provided as a plurality of divided capacitors 81 and the power supply wiring WP or the output. You may comprise by the some division | segmentation wiring 86 which each electrically connects with the wiring WO.

Also, the above embodiments and modifications may be combined as appropriate. The above embodiments and modifications are essentially preferable examples, and are not intended to limit the scope of this disclosure, its application, or its use.

As described above, the semiconductor device described above is useful as a switching power supply device or the like.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Housing | casing 12 Support | pillar 15 Control board 16 Control circuit 17 Connector 18 Lead wire 20 1st board | substrate 21 Insulating layer 22 Conductive layer 23 Heat dissipation layer 30 2nd board | substrate 31 Flexible board 32 Sensor board 40 Semiconductor element 50 Temperature detection element 60 Thermal conductor 71 First switching element 72 Second switching element 80 Capacitor 81 Split capacitor 85 Connection wiring 86 Split wiring WP Power supply wiring WG Ground wiring WO Output wiring SW Switching section CP Capacitance section

Claims

A first substrate;
A second substrate facing the first substrate at a predetermined interval;
At least one semiconductor element mounted on a surface of the first substrate facing the second substrate;
A semiconductor device comprising: at least one temperature detection element mounted on a surface of the second substrate facing the first substrate and in thermal contact with the at least one semiconductor element.
In claim 1,
The semiconductor device wherein the rigidity of the second substrate is lower than the rigidity of the first substrate.
In claim 2,
The second substrate is a semiconductor device configured by a flexible substrate having flexibility.
In claim 2,
A control board on which the control circuit is mounted;
The control substrate is a semiconductor device configured by a substrate different from the first substrate and the second substrate.
In claim 2,
The second substrate is a semiconductor device configured by a control substrate on which a control circuit is mounted.
In claim 1,
The number of the temperature detection elements is the same as the number of the semiconductor elements,
The temperature detection element is a semiconductor device in one-to-one thermal contact with the semiconductor element.
In claim 1,
A semiconductor device further comprising at least one heat conductor interposed between the at least one semiconductor element and the at least one temperature detection element.
In claim 6,
A semiconductor device comprising a heat conductor interposed between the semiconductor element and the temperature detection element.
In claim 7 or 8,
The said heat conductor is a semiconductor device comprised by the heat conductive grease or the heat conductive adhesive.
In claim 1,
The semiconductor device in which the at least one temperature detection element is configured by a thermistor.